1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 /* 3 * Copyright (c) 2016 Amlogic, Inc. 4 * Author: Michael Turquette <mturquette@baylibre.com> 5 * 6 * Copyright (c) 2018 Amlogic, inc. 7 * Author: Qiufang Dai <qiufang.dai@amlogic.com> 8 * Author: Jian Hu <jian.hu@amlogic.com> 9 * 10 */ 11 #ifndef __G12A_H 12 #define __G12A_H 13 14 /* 15 * Clock controller register offsets 16 * 17 * Register offsets from the data sheet must be multiplied by 4 before 18 * adding them to the base address to get the right value. 19 */ 20 #define HHI_MIPI_CNTL0 0x000 21 #define HHI_MIPI_CNTL1 0x004 22 #define HHI_MIPI_CNTL2 0x008 23 #define HHI_MIPI_STS 0x00C 24 #define HHI_GP0_PLL_CNTL0 0x040 25 #define HHI_GP0_PLL_CNTL1 0x044 26 #define HHI_GP0_PLL_CNTL2 0x048 27 #define HHI_GP0_PLL_CNTL3 0x04C 28 #define HHI_GP0_PLL_CNTL4 0x050 29 #define HHI_GP0_PLL_CNTL5 0x054 30 #define HHI_GP0_PLL_CNTL6 0x058 31 #define HHI_GP0_PLL_STS 0x05C 32 #define HHI_PCIE_PLL_CNTL0 0x098 33 #define HHI_PCIE_PLL_CNTL1 0x09C 34 #define HHI_PCIE_PLL_CNTL2 0x0A0 35 #define HHI_PCIE_PLL_CNTL3 0x0A4 36 #define HHI_PCIE_PLL_CNTL4 0x0A8 37 #define HHI_PCIE_PLL_CNTL5 0x0AC 38 #define HHI_PCIE_PLL_STS 0x0B8 39 #define HHI_HIFI_PLL_CNTL0 0x0D8 40 #define HHI_HIFI_PLL_CNTL1 0x0DC 41 #define HHI_HIFI_PLL_CNTL2 0x0E0 42 #define HHI_HIFI_PLL_CNTL3 0x0E4 43 #define HHI_HIFI_PLL_CNTL4 0x0E8 44 #define HHI_HIFI_PLL_CNTL5 0x0EC 45 #define HHI_HIFI_PLL_CNTL6 0x0F0 46 #define HHI_VIID_CLK_DIV 0x128 47 #define HHI_VIID_CLK_CNTL 0x12C 48 #define HHI_GCLK_MPEG0 0x140 49 #define HHI_GCLK_MPEG1 0x144 50 #define HHI_GCLK_MPEG2 0x148 51 #define HHI_GCLK_OTHER 0x150 52 #define HHI_GCLK_OTHER2 0x154 53 #define HHI_SYS_CPU_CLK_CNTL1 0x15c 54 #define HHI_VID_CLK_DIV 0x164 55 #define HHI_MPEG_CLK_CNTL 0x174 56 #define HHI_AUD_CLK_CNTL 0x178 57 #define HHI_VID_CLK_CNTL 0x17c 58 #define HHI_TS_CLK_CNTL 0x190 59 #define HHI_VID_CLK_CNTL2 0x194 60 #define HHI_SYS_CPU_CLK_CNTL0 0x19c 61 #define HHI_VID_PLL_CLK_DIV 0x1A0 62 #define HHI_MALI_CLK_CNTL 0x1b0 63 #define HHI_VPU_CLKC_CNTL 0x1b4 64 #define HHI_VPU_CLK_CNTL 0x1bC 65 #define HHI_HDMI_CLK_CNTL 0x1CC 66 #define HHI_VDEC_CLK_CNTL 0x1E0 67 #define HHI_VDEC2_CLK_CNTL 0x1E4 68 #define HHI_VDEC3_CLK_CNTL 0x1E8 69 #define HHI_VDEC4_CLK_CNTL 0x1EC 70 #define HHI_HDCP22_CLK_CNTL 0x1F0 71 #define HHI_VAPBCLK_CNTL 0x1F4 72 #define HHI_VPU_CLKB_CNTL 0x20C 73 #define HHI_GEN_CLK_CNTL 0x228 74 #define HHI_VDIN_MEAS_CLK_CNTL 0x250 75 #define HHI_MIPIDSI_PHY_CLK_CNTL 0x254 76 #define HHI_NAND_CLK_CNTL 0x25C 77 #define HHI_SD_EMMC_CLK_CNTL 0x264 78 #define HHI_MPLL_CNTL0 0x278 79 #define HHI_MPLL_CNTL1 0x27C 80 #define HHI_MPLL_CNTL2 0x280 81 #define HHI_MPLL_CNTL3 0x284 82 #define HHI_MPLL_CNTL4 0x288 83 #define HHI_MPLL_CNTL5 0x28c 84 #define HHI_MPLL_CNTL6 0x290 85 #define HHI_MPLL_CNTL7 0x294 86 #define HHI_MPLL_CNTL8 0x298 87 #define HHI_FIX_PLL_CNTL0 0x2A0 88 #define HHI_FIX_PLL_CNTL1 0x2A4 89 #define HHI_FIX_PLL_CNTL3 0x2AC 90 #define HHI_SYS_PLL_CNTL0 0x2f4 91 #define HHI_SYS_PLL_CNTL1 0x2f8 92 #define HHI_SYS_PLL_CNTL2 0x2fc 93 #define HHI_SYS_PLL_CNTL3 0x300 94 #define HHI_SYS_PLL_CNTL4 0x304 95 #define HHI_SYS_PLL_CNTL5 0x308 96 #define HHI_SYS_PLL_CNTL6 0x30c 97 #define HHI_HDMI_PLL_CNTL0 0x320 98 #define HHI_HDMI_PLL_CNTL1 0x324 99 #define HHI_HDMI_PLL_CNTL2 0x328 100 #define HHI_HDMI_PLL_CNTL3 0x32c 101 #define HHI_HDMI_PLL_CNTL4 0x330 102 #define HHI_HDMI_PLL_CNTL5 0x334 103 #define HHI_HDMI_PLL_CNTL6 0x338 104 #define HHI_SPICC_CLK_CNTL 0x3dc 105 106 /* 107 * CLKID index values 108 * 109 * These indices are entirely contrived and do not map onto the hardware. 110 * It has now been decided to expose everything by default in the DT header: 111 * include/dt-bindings/clock/g12a-clkc.h. Only the clocks ids we don't want 112 * to expose, such as the internal muxes and dividers of composite clocks, 113 * will remain defined here. 114 */ 115 #define CLKID_MPEG_SEL 8 116 #define CLKID_MPEG_DIV 9 117 #define CLKID_SD_EMMC_A_CLK0_SEL 63 118 #define CLKID_SD_EMMC_A_CLK0_DIV 64 119 #define CLKID_SD_EMMC_B_CLK0_SEL 65 120 #define CLKID_SD_EMMC_B_CLK0_DIV 66 121 #define CLKID_SD_EMMC_C_CLK0_SEL 67 122 #define CLKID_SD_EMMC_C_CLK0_DIV 68 123 #define CLKID_MPLL0_DIV 69 124 #define CLKID_MPLL1_DIV 70 125 #define CLKID_MPLL2_DIV 71 126 #define CLKID_MPLL3_DIV 72 127 #define CLKID_MPLL_PREDIV 73 128 #define CLKID_FCLK_DIV2_DIV 75 129 #define CLKID_FCLK_DIV3_DIV 76 130 #define CLKID_FCLK_DIV4_DIV 77 131 #define CLKID_FCLK_DIV5_DIV 78 132 #define CLKID_FCLK_DIV7_DIV 79 133 #define CLKID_FCLK_DIV2P5_DIV 100 134 #define CLKID_FIXED_PLL_DCO 101 135 #define CLKID_SYS_PLL_DCO 102 136 #define CLKID_GP0_PLL_DCO 103 137 #define CLKID_HIFI_PLL_DCO 104 138 #define CLKID_VPU_0_DIV 111 139 #define CLKID_VPU_1_DIV 114 140 #define CLKID_VAPB_0_DIV 118 141 #define CLKID_VAPB_1_DIV 121 142 #define CLKID_HDMI_PLL_DCO 125 143 #define CLKID_HDMI_PLL_OD 126 144 #define CLKID_HDMI_PLL_OD2 127 145 #define CLKID_VID_PLL_SEL 130 146 #define CLKID_VID_PLL_DIV 131 147 #define CLKID_VCLK_SEL 132 148 #define CLKID_VCLK2_SEL 133 149 #define CLKID_VCLK_INPUT 134 150 #define CLKID_VCLK2_INPUT 135 151 #define CLKID_VCLK_DIV 136 152 #define CLKID_VCLK2_DIV 137 153 #define CLKID_VCLK_DIV2_EN 140 154 #define CLKID_VCLK_DIV4_EN 141 155 #define CLKID_VCLK_DIV6_EN 142 156 #define CLKID_VCLK_DIV12_EN 143 157 #define CLKID_VCLK2_DIV2_EN 144 158 #define CLKID_VCLK2_DIV4_EN 145 159 #define CLKID_VCLK2_DIV6_EN 146 160 #define CLKID_VCLK2_DIV12_EN 147 161 #define CLKID_CTS_ENCI_SEL 158 162 #define CLKID_CTS_ENCP_SEL 159 163 #define CLKID_CTS_VDAC_SEL 160 164 #define CLKID_HDMI_TX_SEL 161 165 #define CLKID_HDMI_SEL 166 166 #define CLKID_HDMI_DIV 167 167 #define CLKID_MALI_0_DIV 170 168 #define CLKID_MALI_1_DIV 173 169 #define CLKID_MPLL_5OM_DIV 176 170 #define CLKID_SYS_PLL_DIV16_EN 178 171 #define CLKID_SYS_PLL_DIV16 179 172 #define CLKID_CPU_CLK_DYN0_SEL 180 173 #define CLKID_CPU_CLK_DYN0_DIV 181 174 #define CLKID_CPU_CLK_DYN0 182 175 #define CLKID_CPU_CLK_DYN1_SEL 183 176 #define CLKID_CPU_CLK_DYN1_DIV 184 177 #define CLKID_CPU_CLK_DYN1 185 178 #define CLKID_CPU_CLK_DYN 186 179 #define CLKID_CPU_CLK_DIV16_EN 188 180 #define CLKID_CPU_CLK_DIV16 189 181 #define CLKID_CPU_CLK_APB_DIV 190 182 #define CLKID_CPU_CLK_APB 191 183 #define CLKID_CPU_CLK_ATB_DIV 192 184 #define CLKID_CPU_CLK_ATB 193 185 #define CLKID_CPU_CLK_AXI_DIV 194 186 #define CLKID_CPU_CLK_AXI 195 187 #define CLKID_CPU_CLK_TRACE_DIV 196 188 #define CLKID_CPU_CLK_TRACE 197 189 #define CLKID_PCIE_PLL_DCO 198 190 #define CLKID_PCIE_PLL_DCO_DIV2 199 191 #define CLKID_PCIE_PLL_OD 200 192 #define CLKID_VDEC_1_SEL 202 193 #define CLKID_VDEC_1_DIV 203 194 #define CLKID_VDEC_HEVC_SEL 205 195 #define CLKID_VDEC_HEVC_DIV 206 196 #define CLKID_VDEC_HEVCF_SEL 208 197 #define CLKID_VDEC_HEVCF_DIV 209 198 199 #define NR_CLKS 211 200 201 /* include the CLKIDs that have been made part of the DT binding */ 202 #include <dt-bindings/clock/g12a-clkc.h> 203 204 #endif /* __G12A_H */ 205