10b9f1c2cSBiju Das // SPDX-License-Identifier: GPL-2.0
20b9f1c2cSBiju Das /*
30b9f1c2cSBiju Das * r8a774b1 Clock Pulse Generator / Module Standby and Software Reset
40b9f1c2cSBiju Das *
50b9f1c2cSBiju Das * Copyright (C) 2019 Renesas Electronics Corp.
60b9f1c2cSBiju Das *
70b9f1c2cSBiju Das * Based on r8a7796-cpg-mssr.c
80b9f1c2cSBiju Das *
90b9f1c2cSBiju Das * Copyright (C) 2016 Glider bvba
100b9f1c2cSBiju Das */
110b9f1c2cSBiju Das
120b9f1c2cSBiju Das #include <linux/device.h>
130b9f1c2cSBiju Das #include <linux/init.h>
140b9f1c2cSBiju Das #include <linux/kernel.h>
150b9f1c2cSBiju Das #include <linux/soc/renesas/rcar-rst.h>
160b9f1c2cSBiju Das
170b9f1c2cSBiju Das #include <dt-bindings/clock/r8a774b1-cpg-mssr.h>
180b9f1c2cSBiju Das
190b9f1c2cSBiju Das #include "renesas-cpg-mssr.h"
200b9f1c2cSBiju Das #include "rcar-gen3-cpg.h"
210b9f1c2cSBiju Das
220b9f1c2cSBiju Das enum clk_ids {
230b9f1c2cSBiju Das /* Core Clock Outputs exported to DT */
240b9f1c2cSBiju Das LAST_DT_CORE_CLK = R8A774B1_CLK_CANFD,
250b9f1c2cSBiju Das
260b9f1c2cSBiju Das /* External Input Clocks */
270b9f1c2cSBiju Das CLK_EXTAL,
280b9f1c2cSBiju Das CLK_EXTALR,
290b9f1c2cSBiju Das
300b9f1c2cSBiju Das /* Internal Core Clocks */
310b9f1c2cSBiju Das CLK_MAIN,
320b9f1c2cSBiju Das CLK_PLL0,
330b9f1c2cSBiju Das CLK_PLL1,
340b9f1c2cSBiju Das CLK_PLL3,
350b9f1c2cSBiju Das CLK_PLL4,
360b9f1c2cSBiju Das CLK_PLL1_DIV2,
370b9f1c2cSBiju Das CLK_PLL1_DIV4,
380b9f1c2cSBiju Das CLK_S0,
390b9f1c2cSBiju Das CLK_S1,
400b9f1c2cSBiju Das CLK_S2,
410b9f1c2cSBiju Das CLK_S3,
420b9f1c2cSBiju Das CLK_SDSRC,
43fb9805c5SBiju Das CLK_RPCSRC,
440b9f1c2cSBiju Das CLK_RINT,
450b9f1c2cSBiju Das
460b9f1c2cSBiju Das /* Module Clocks */
470b9f1c2cSBiju Das MOD_CLK_BASE
480b9f1c2cSBiju Das };
490b9f1c2cSBiju Das
500b9f1c2cSBiju Das static const struct cpg_core_clk r8a774b1_core_clks[] __initconst = {
510b9f1c2cSBiju Das /* External Clock Inputs */
520b9f1c2cSBiju Das DEF_INPUT("extal", CLK_EXTAL),
530b9f1c2cSBiju Das DEF_INPUT("extalr", CLK_EXTALR),
540b9f1c2cSBiju Das
550b9f1c2cSBiju Das /* Internal Core Clocks */
560b9f1c2cSBiju Das DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
570b9f1c2cSBiju Das DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
580b9f1c2cSBiju Das DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
590b9f1c2cSBiju Das DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
600b9f1c2cSBiju Das DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
610b9f1c2cSBiju Das
620b9f1c2cSBiju Das DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
630b9f1c2cSBiju Das DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
640b9f1c2cSBiju Das DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
650b9f1c2cSBiju Das DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
660b9f1c2cSBiju Das DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
670b9f1c2cSBiju Das DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
680b9f1c2cSBiju Das DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
69fb9805c5SBiju Das
70880c3fa3SGeert Uytterhoeven DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
710b9f1c2cSBiju Das
720b9f1c2cSBiju Das DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
730b9f1c2cSBiju Das
740b9f1c2cSBiju Das /* Core Clock Outputs */
750b9f1c2cSBiju Das DEF_GEN3_Z("z", R8A774B1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
76adf6b916SAdam Ford DEF_GEN3_Z("zg", R8A774B1_CLK_ZG, CLK_TYPE_GEN3_ZG, CLK_PLL4, 4, 24),
770b9f1c2cSBiju Das DEF_FIXED("ztr", R8A774B1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
780b9f1c2cSBiju Das DEF_FIXED("ztrd2", R8A774B1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
790b9f1c2cSBiju Das DEF_FIXED("zt", R8A774B1_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
800b9f1c2cSBiju Das DEF_FIXED("zx", R8A774B1_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
810b9f1c2cSBiju Das DEF_FIXED("s0d1", R8A774B1_CLK_S0D1, CLK_S0, 1, 1),
820b9f1c2cSBiju Das DEF_FIXED("s0d2", R8A774B1_CLK_S0D2, CLK_S0, 2, 1),
830b9f1c2cSBiju Das DEF_FIXED("s0d3", R8A774B1_CLK_S0D3, CLK_S0, 3, 1),
840b9f1c2cSBiju Das DEF_FIXED("s0d4", R8A774B1_CLK_S0D4, CLK_S0, 4, 1),
850b9f1c2cSBiju Das DEF_FIXED("s0d6", R8A774B1_CLK_S0D6, CLK_S0, 6, 1),
860b9f1c2cSBiju Das DEF_FIXED("s0d8", R8A774B1_CLK_S0D8, CLK_S0, 8, 1),
870b9f1c2cSBiju Das DEF_FIXED("s0d12", R8A774B1_CLK_S0D12, CLK_S0, 12, 1),
880b9f1c2cSBiju Das DEF_FIXED("s1d2", R8A774B1_CLK_S1D2, CLK_S1, 2, 1),
890b9f1c2cSBiju Das DEF_FIXED("s1d4", R8A774B1_CLK_S1D4, CLK_S1, 4, 1),
900b9f1c2cSBiju Das DEF_FIXED("s2d1", R8A774B1_CLK_S2D1, CLK_S2, 1, 1),
910b9f1c2cSBiju Das DEF_FIXED("s2d2", R8A774B1_CLK_S2D2, CLK_S2, 2, 1),
920b9f1c2cSBiju Das DEF_FIXED("s2d4", R8A774B1_CLK_S2D4, CLK_S2, 4, 1),
930b9f1c2cSBiju Das DEF_FIXED("s3d1", R8A774B1_CLK_S3D1, CLK_S3, 1, 1),
940b9f1c2cSBiju Das DEF_FIXED("s3d2", R8A774B1_CLK_S3D2, CLK_S3, 2, 1),
950b9f1c2cSBiju Das DEF_FIXED("s3d4", R8A774B1_CLK_S3D4, CLK_S3, 4, 1),
960b9f1c2cSBiju Das
971abd0448SWolfram Sang DEF_GEN3_SDH("sd0h", R8A774B1_CLK_SD0H, CLK_SDSRC, 0x074),
981abd0448SWolfram Sang DEF_GEN3_SDH("sd1h", R8A774B1_CLK_SD1H, CLK_SDSRC, 0x078),
991abd0448SWolfram Sang DEF_GEN3_SDH("sd2h", R8A774B1_CLK_SD2H, CLK_SDSRC, 0x268),
1001abd0448SWolfram Sang DEF_GEN3_SDH("sd3h", R8A774B1_CLK_SD3H, CLK_SDSRC, 0x26c),
1011abd0448SWolfram Sang DEF_GEN3_SD("sd0", R8A774B1_CLK_SD0, R8A774B1_CLK_SD0H, 0x074),
1021abd0448SWolfram Sang DEF_GEN3_SD("sd1", R8A774B1_CLK_SD1, R8A774B1_CLK_SD1H, 0x078),
1031abd0448SWolfram Sang DEF_GEN3_SD("sd2", R8A774B1_CLK_SD2, R8A774B1_CLK_SD2H, 0x268),
1041abd0448SWolfram Sang DEF_GEN3_SD("sd3", R8A774B1_CLK_SD3, R8A774B1_CLK_SD3H, 0x26c),
1050b9f1c2cSBiju Das
106880c3fa3SGeert Uytterhoeven DEF_BASE("rpc", R8A774B1_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC),
107880c3fa3SGeert Uytterhoeven DEF_BASE("rpcd2", R8A774B1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A774B1_CLK_RPC),
108880c3fa3SGeert Uytterhoeven
1090b9f1c2cSBiju Das DEF_FIXED("cl", R8A774B1_CLK_CL, CLK_PLL1_DIV2, 48, 1),
1100b9f1c2cSBiju Das DEF_FIXED("cp", R8A774B1_CLK_CP, CLK_EXTAL, 2, 1),
1110b9f1c2cSBiju Das DEF_FIXED("cpex", R8A774B1_CLK_CPEX, CLK_EXTAL, 2, 1),
1120b9f1c2cSBiju Das
1130b9f1c2cSBiju Das DEF_DIV6P1("canfd", R8A774B1_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
1140b9f1c2cSBiju Das DEF_DIV6P1("csi0", R8A774B1_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
1150b9f1c2cSBiju Das DEF_DIV6P1("mso", R8A774B1_CLK_MSO, CLK_PLL1_DIV4, 0x014),
1160b9f1c2cSBiju Das DEF_DIV6P1("hdmi", R8A774B1_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
1170b9f1c2cSBiju Das
1180b9f1c2cSBiju Das DEF_GEN3_OSC("osc", R8A774B1_CLK_OSC, CLK_EXTAL, 8),
1190b9f1c2cSBiju Das
1200b9f1c2cSBiju Das DEF_BASE("r", R8A774B1_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
1210b9f1c2cSBiju Das };
1220b9f1c2cSBiju Das
1230b9f1c2cSBiju Das static const struct mssr_mod_clk r8a774b1_mod_clks[] __initconst = {
124adf6b916SAdam Ford DEF_MOD("3dge", 112, R8A774B1_CLK_ZG),
12556278c8fSBiju Das DEF_MOD("tmu4", 121, R8A774B1_CLK_S0D6),
12656278c8fSBiju Das DEF_MOD("tmu3", 122, R8A774B1_CLK_S3D2),
12756278c8fSBiju Das DEF_MOD("tmu2", 123, R8A774B1_CLK_S3D2),
12856278c8fSBiju Das DEF_MOD("tmu1", 124, R8A774B1_CLK_S3D2),
12956278c8fSBiju Das DEF_MOD("tmu0", 125, R8A774B1_CLK_CP),
1300b9f1c2cSBiju Das DEF_MOD("fdp1-0", 119, R8A774B1_CLK_S0D1),
1310b9f1c2cSBiju Das DEF_MOD("scif5", 202, R8A774B1_CLK_S3D4),
1320b9f1c2cSBiju Das DEF_MOD("scif4", 203, R8A774B1_CLK_S3D4),
1330b9f1c2cSBiju Das DEF_MOD("scif3", 204, R8A774B1_CLK_S3D4),
1340b9f1c2cSBiju Das DEF_MOD("scif1", 206, R8A774B1_CLK_S3D4),
1350b9f1c2cSBiju Das DEF_MOD("scif0", 207, R8A774B1_CLK_S3D4),
1360b9f1c2cSBiju Das DEF_MOD("msiof3", 208, R8A774B1_CLK_MSO),
1370b9f1c2cSBiju Das DEF_MOD("msiof2", 209, R8A774B1_CLK_MSO),
1380b9f1c2cSBiju Das DEF_MOD("msiof1", 210, R8A774B1_CLK_MSO),
1390b9f1c2cSBiju Das DEF_MOD("msiof0", 211, R8A774B1_CLK_MSO),
1400b9f1c2cSBiju Das DEF_MOD("sys-dmac2", 217, R8A774B1_CLK_S3D1),
1410b9f1c2cSBiju Das DEF_MOD("sys-dmac1", 218, R8A774B1_CLK_S3D1),
1420b9f1c2cSBiju Das DEF_MOD("sys-dmac0", 219, R8A774B1_CLK_S0D3),
1430b9f1c2cSBiju Das DEF_MOD("cmt3", 300, R8A774B1_CLK_R),
1440b9f1c2cSBiju Das DEF_MOD("cmt2", 301, R8A774B1_CLK_R),
1450b9f1c2cSBiju Das DEF_MOD("cmt1", 302, R8A774B1_CLK_R),
1460b9f1c2cSBiju Das DEF_MOD("cmt0", 303, R8A774B1_CLK_R),
1470b9f1c2cSBiju Das DEF_MOD("tpu0", 304, R8A774B1_CLK_S3D4),
1480b9f1c2cSBiju Das DEF_MOD("scif2", 310, R8A774B1_CLK_S3D4),
1490b9f1c2cSBiju Das DEF_MOD("sdif3", 311, R8A774B1_CLK_SD3),
1500b9f1c2cSBiju Das DEF_MOD("sdif2", 312, R8A774B1_CLK_SD2),
1510b9f1c2cSBiju Das DEF_MOD("sdif1", 313, R8A774B1_CLK_SD1),
1520b9f1c2cSBiju Das DEF_MOD("sdif0", 314, R8A774B1_CLK_SD0),
1530b9f1c2cSBiju Das DEF_MOD("pcie1", 318, R8A774B1_CLK_S3D1),
1540b9f1c2cSBiju Das DEF_MOD("pcie0", 319, R8A774B1_CLK_S3D1),
1550b9f1c2cSBiju Das DEF_MOD("usb3-if0", 328, R8A774B1_CLK_S3D1),
1560b9f1c2cSBiju Das DEF_MOD("usb-dmac0", 330, R8A774B1_CLK_S3D1),
1570b9f1c2cSBiju Das DEF_MOD("usb-dmac1", 331, R8A774B1_CLK_S3D1),
1580b9f1c2cSBiju Das DEF_MOD("rwdt", 402, R8A774B1_CLK_R),
1590b9f1c2cSBiju Das DEF_MOD("intc-ex", 407, R8A774B1_CLK_CP),
1600b9f1c2cSBiju Das DEF_MOD("intc-ap", 408, R8A774B1_CLK_S0D3),
1610b9f1c2cSBiju Das DEF_MOD("audmac1", 501, R8A774B1_CLK_S1D2),
1620b9f1c2cSBiju Das DEF_MOD("audmac0", 502, R8A774B1_CLK_S1D2),
1630b9f1c2cSBiju Das DEF_MOD("hscif4", 516, R8A774B1_CLK_S3D1),
1640b9f1c2cSBiju Das DEF_MOD("hscif3", 517, R8A774B1_CLK_S3D1),
1650b9f1c2cSBiju Das DEF_MOD("hscif2", 518, R8A774B1_CLK_S3D1),
1660b9f1c2cSBiju Das DEF_MOD("hscif1", 519, R8A774B1_CLK_S3D1),
1670b9f1c2cSBiju Das DEF_MOD("hscif0", 520, R8A774B1_CLK_S3D1),
1680b9f1c2cSBiju Das DEF_MOD("thermal", 522, R8A774B1_CLK_CP),
1690b9f1c2cSBiju Das DEF_MOD("pwm", 523, R8A774B1_CLK_S0D12),
1700b9f1c2cSBiju Das DEF_MOD("fcpvd1", 602, R8A774B1_CLK_S0D2),
1710b9f1c2cSBiju Das DEF_MOD("fcpvd0", 603, R8A774B1_CLK_S0D2),
1720b9f1c2cSBiju Das DEF_MOD("fcpvb0", 607, R8A774B1_CLK_S0D1),
1730b9f1c2cSBiju Das DEF_MOD("fcpvi0", 611, R8A774B1_CLK_S0D1),
1740b9f1c2cSBiju Das DEF_MOD("fcpf0", 615, R8A774B1_CLK_S0D1),
1750b9f1c2cSBiju Das DEF_MOD("fcpcs", 619, R8A774B1_CLK_S0D2),
1760b9f1c2cSBiju Das DEF_MOD("vspd1", 622, R8A774B1_CLK_S0D2),
1770b9f1c2cSBiju Das DEF_MOD("vspd0", 623, R8A774B1_CLK_S0D2),
1780b9f1c2cSBiju Das DEF_MOD("vspb", 626, R8A774B1_CLK_S0D1),
1790b9f1c2cSBiju Das DEF_MOD("vspi0", 631, R8A774B1_CLK_S0D1),
1800b9f1c2cSBiju Das DEF_MOD("ehci1", 702, R8A774B1_CLK_S3D2),
1810b9f1c2cSBiju Das DEF_MOD("ehci0", 703, R8A774B1_CLK_S3D2),
1820b9f1c2cSBiju Das DEF_MOD("hsusb", 704, R8A774B1_CLK_S3D2),
1830b9f1c2cSBiju Das DEF_MOD("csi20", 714, R8A774B1_CLK_CSI0),
1840b9f1c2cSBiju Das DEF_MOD("csi40", 716, R8A774B1_CLK_CSI0),
1850b9f1c2cSBiju Das DEF_MOD("du3", 721, R8A774B1_CLK_S2D1),
1860b9f1c2cSBiju Das DEF_MOD("du1", 723, R8A774B1_CLK_S2D1),
1870b9f1c2cSBiju Das DEF_MOD("du0", 724, R8A774B1_CLK_S2D1),
1880b9f1c2cSBiju Das DEF_MOD("lvds", 727, R8A774B1_CLK_S2D1),
1890b9f1c2cSBiju Das DEF_MOD("hdmi0", 729, R8A774B1_CLK_HDMI),
1900b9f1c2cSBiju Das DEF_MOD("vin7", 804, R8A774B1_CLK_S0D2),
1910b9f1c2cSBiju Das DEF_MOD("vin6", 805, R8A774B1_CLK_S0D2),
1920b9f1c2cSBiju Das DEF_MOD("vin5", 806, R8A774B1_CLK_S0D2),
1930b9f1c2cSBiju Das DEF_MOD("vin4", 807, R8A774B1_CLK_S0D2),
1940b9f1c2cSBiju Das DEF_MOD("vin3", 808, R8A774B1_CLK_S0D2),
1950b9f1c2cSBiju Das DEF_MOD("vin2", 809, R8A774B1_CLK_S0D2),
1960b9f1c2cSBiju Das DEF_MOD("vin1", 810, R8A774B1_CLK_S0D2),
1970b9f1c2cSBiju Das DEF_MOD("vin0", 811, R8A774B1_CLK_S0D2),
1980b9f1c2cSBiju Das DEF_MOD("etheravb", 812, R8A774B1_CLK_S0D6),
1990b9f1c2cSBiju Das DEF_MOD("sata0", 815, R8A774B1_CLK_S3D2),
2000b9f1c2cSBiju Das DEF_MOD("gpio7", 905, R8A774B1_CLK_S3D4),
2010b9f1c2cSBiju Das DEF_MOD("gpio6", 906, R8A774B1_CLK_S3D4),
2020b9f1c2cSBiju Das DEF_MOD("gpio5", 907, R8A774B1_CLK_S3D4),
2030b9f1c2cSBiju Das DEF_MOD("gpio4", 908, R8A774B1_CLK_S3D4),
2040b9f1c2cSBiju Das DEF_MOD("gpio3", 909, R8A774B1_CLK_S3D4),
2050b9f1c2cSBiju Das DEF_MOD("gpio2", 910, R8A774B1_CLK_S3D4),
2060b9f1c2cSBiju Das DEF_MOD("gpio1", 911, R8A774B1_CLK_S3D4),
2070b9f1c2cSBiju Das DEF_MOD("gpio0", 912, R8A774B1_CLK_S3D4),
2080b9f1c2cSBiju Das DEF_MOD("can-fd", 914, R8A774B1_CLK_S3D2),
2090b9f1c2cSBiju Das DEF_MOD("can-if1", 915, R8A774B1_CLK_S3D4),
2100b9f1c2cSBiju Das DEF_MOD("can-if0", 916, R8A774B1_CLK_S3D4),
211fb9805c5SBiju Das DEF_MOD("rpc-if", 917, R8A774B1_CLK_RPCD2),
2120b9f1c2cSBiju Das DEF_MOD("i2c6", 918, R8A774B1_CLK_S0D6),
2130b9f1c2cSBiju Das DEF_MOD("i2c5", 919, R8A774B1_CLK_S0D6),
214*708cb698SKuninori Morimoto DEF_MOD("adg", 922, R8A774B1_CLK_S0D4),
215d23fcff1SGeert Uytterhoeven DEF_MOD("iic-pmic", 926, R8A774B1_CLK_CP),
2160b9f1c2cSBiju Das DEF_MOD("i2c4", 927, R8A774B1_CLK_S0D6),
2170b9f1c2cSBiju Das DEF_MOD("i2c3", 928, R8A774B1_CLK_S0D6),
2180b9f1c2cSBiju Das DEF_MOD("i2c2", 929, R8A774B1_CLK_S3D2),
2190b9f1c2cSBiju Das DEF_MOD("i2c1", 930, R8A774B1_CLK_S3D2),
2200b9f1c2cSBiju Das DEF_MOD("i2c0", 931, R8A774B1_CLK_S3D2),
2210b9f1c2cSBiju Das DEF_MOD("ssi-all", 1005, R8A774B1_CLK_S3D4),
2220b9f1c2cSBiju Das DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
2230b9f1c2cSBiju Das DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
2240b9f1c2cSBiju Das DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
2250b9f1c2cSBiju Das DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
2260b9f1c2cSBiju Das DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
2270b9f1c2cSBiju Das DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
2280b9f1c2cSBiju Das DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
2290b9f1c2cSBiju Das DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
2300b9f1c2cSBiju Das DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
2310b9f1c2cSBiju Das DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
2320b9f1c2cSBiju Das DEF_MOD("scu-all", 1017, R8A774B1_CLK_S3D4),
2330b9f1c2cSBiju Das DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
2340b9f1c2cSBiju Das DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
2350b9f1c2cSBiju Das DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
2360b9f1c2cSBiju Das DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
2370b9f1c2cSBiju Das DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
2380b9f1c2cSBiju Das DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
2390b9f1c2cSBiju Das DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
2400b9f1c2cSBiju Das DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
2410b9f1c2cSBiju Das DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
2420b9f1c2cSBiju Das DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
2430b9f1c2cSBiju Das DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
2440b9f1c2cSBiju Das DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
2450b9f1c2cSBiju Das DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
2460b9f1c2cSBiju Das DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
2470b9f1c2cSBiju Das };
2480b9f1c2cSBiju Das
2490b9f1c2cSBiju Das static const unsigned int r8a774b1_crit_mod_clks[] __initconst = {
25052bc5ea6SUlrich Hecht MOD_CLK_ID(402), /* RWDT */
2510b9f1c2cSBiju Das MOD_CLK_ID(408), /* INTC-AP (GIC) */
2520b9f1c2cSBiju Das };
2530b9f1c2cSBiju Das
2540b9f1c2cSBiju Das /*
2550b9f1c2cSBiju Das * CPG Clock Data
2560b9f1c2cSBiju Das */
2570b9f1c2cSBiju Das
2580b9f1c2cSBiju Das /*
2590b9f1c2cSBiju Das * MD EXTAL PLL0 PLL1 PLL3 PLL4 OSC
2600b9f1c2cSBiju Das * 14 13 19 17 (MHz)
2610b9f1c2cSBiju Das *-----------------------------------------------------------------
2620b9f1c2cSBiju Das * 0 0 0 0 16.66 x 1 x180 x192 x192 x144 /16
2630b9f1c2cSBiju Das * 0 0 0 1 16.66 x 1 x180 x192 x128 x144 /16
2640b9f1c2cSBiju Das * 0 0 1 0 Prohibited setting
2650b9f1c2cSBiju Das * 0 0 1 1 16.66 x 1 x180 x192 x192 x144 /16
2660b9f1c2cSBiju Das * 0 1 0 0 20 x 1 x150 x160 x160 x120 /19
2670b9f1c2cSBiju Das * 0 1 0 1 20 x 1 x150 x160 x106 x120 /19
2680b9f1c2cSBiju Das * 0 1 1 0 Prohibited setting
2690b9f1c2cSBiju Das * 0 1 1 1 20 x 1 x150 x160 x160 x120 /19
2700b9f1c2cSBiju Das * 1 0 0 0 25 x 1 x120 x128 x128 x96 /24
2710b9f1c2cSBiju Das * 1 0 0 1 25 x 1 x120 x128 x84 x96 /24
2720b9f1c2cSBiju Das * 1 0 1 0 Prohibited setting
2730b9f1c2cSBiju Das * 1 0 1 1 25 x 1 x120 x128 x128 x96 /24
2740b9f1c2cSBiju Das * 1 1 0 0 33.33 / 2 x180 x192 x192 x144 /32
2750b9f1c2cSBiju Das * 1 1 0 1 33.33 / 2 x180 x192 x128 x144 /32
2760b9f1c2cSBiju Das * 1 1 1 0 Prohibited setting
2770b9f1c2cSBiju Das * 1 1 1 1 33.33 / 2 x180 x192 x192 x144 /32
2780b9f1c2cSBiju Das */
2790b9f1c2cSBiju Das #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
2800b9f1c2cSBiju Das (((md) & BIT(13)) >> 11) | \
2810b9f1c2cSBiju Das (((md) & BIT(19)) >> 18) | \
2820b9f1c2cSBiju Das (((md) & BIT(17)) >> 17))
2830b9f1c2cSBiju Das
2840b9f1c2cSBiju Das static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
2850b9f1c2cSBiju Das /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
2860b9f1c2cSBiju Das { 1, 192, 1, 192, 1, 16, },
2870b9f1c2cSBiju Das { 1, 192, 1, 128, 1, 16, },
2880b9f1c2cSBiju Das { 0, /* Prohibited setting */ },
2890b9f1c2cSBiju Das { 1, 192, 1, 192, 1, 16, },
2900b9f1c2cSBiju Das { 1, 160, 1, 160, 1, 19, },
2910b9f1c2cSBiju Das { 1, 160, 1, 106, 1, 19, },
2920b9f1c2cSBiju Das { 0, /* Prohibited setting */ },
2930b9f1c2cSBiju Das { 1, 160, 1, 160, 1, 19, },
2940b9f1c2cSBiju Das { 1, 128, 1, 128, 1, 24, },
2950b9f1c2cSBiju Das { 1, 128, 1, 84, 1, 24, },
2960b9f1c2cSBiju Das { 0, /* Prohibited setting */ },
2970b9f1c2cSBiju Das { 1, 128, 1, 128, 1, 24, },
2980b9f1c2cSBiju Das { 2, 192, 1, 192, 1, 32, },
2990b9f1c2cSBiju Das { 2, 192, 1, 128, 1, 32, },
3000b9f1c2cSBiju Das { 0, /* Prohibited setting */ },
3010b9f1c2cSBiju Das { 2, 192, 1, 192, 1, 32, },
3020b9f1c2cSBiju Das };
3030b9f1c2cSBiju Das
r8a774b1_cpg_mssr_init(struct device * dev)3040b9f1c2cSBiju Das static int __init r8a774b1_cpg_mssr_init(struct device *dev)
3050b9f1c2cSBiju Das {
3060b9f1c2cSBiju Das const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
3070b9f1c2cSBiju Das u32 cpg_mode;
3080b9f1c2cSBiju Das int error;
3090b9f1c2cSBiju Das
3100b9f1c2cSBiju Das error = rcar_rst_read_mode_pins(&cpg_mode);
3110b9f1c2cSBiju Das if (error)
3120b9f1c2cSBiju Das return error;
3130b9f1c2cSBiju Das
3140b9f1c2cSBiju Das cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
3150b9f1c2cSBiju Das if (!cpg_pll_config->extal_div) {
3160b9f1c2cSBiju Das dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode);
3170b9f1c2cSBiju Das return -EINVAL;
3180b9f1c2cSBiju Das }
3190b9f1c2cSBiju Das
3200b9f1c2cSBiju Das return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
3210b9f1c2cSBiju Das }
3220b9f1c2cSBiju Das
3230b9f1c2cSBiju Das const struct cpg_mssr_info r8a774b1_cpg_mssr_info __initconst = {
3240b9f1c2cSBiju Das /* Core Clocks */
3250b9f1c2cSBiju Das .core_clks = r8a774b1_core_clks,
3260b9f1c2cSBiju Das .num_core_clks = ARRAY_SIZE(r8a774b1_core_clks),
3270b9f1c2cSBiju Das .last_dt_core_clk = LAST_DT_CORE_CLK,
3280b9f1c2cSBiju Das .num_total_core_clks = MOD_CLK_BASE,
3290b9f1c2cSBiju Das
3300b9f1c2cSBiju Das /* Module Clocks */
3310b9f1c2cSBiju Das .mod_clks = r8a774b1_mod_clks,
3320b9f1c2cSBiju Das .num_mod_clks = ARRAY_SIZE(r8a774b1_mod_clks),
3330b9f1c2cSBiju Das .num_hw_mod_clks = 12 * 32,
3340b9f1c2cSBiju Das
3350b9f1c2cSBiju Das /* Critical Module Clocks */
3360b9f1c2cSBiju Das .crit_mod_clks = r8a774b1_crit_mod_clks,
3370b9f1c2cSBiju Das .num_crit_mod_clks = ARRAY_SIZE(r8a774b1_crit_mod_clks),
3380b9f1c2cSBiju Das
3390b9f1c2cSBiju Das /* Callbacks */
3400b9f1c2cSBiju Das .init = r8a774b1_cpg_mssr_init,
3410b9f1c2cSBiju Das .cpg_clk_register = rcar_gen3_cpg_clk_register,
3420b9f1c2cSBiju Das };
343