1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 4 * Author: Chanwoo Choi <cw00.choi@samsung.com> 5 * 6 * Common Clock Framework support for Exynos5433 SoC. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/clk-provider.h> 11 #include <linux/of.h> 12 #include <linux/of_address.h> 13 #include <linux/of_device.h> 14 #include <linux/platform_device.h> 15 #include <linux/pm_runtime.h> 16 17 #include <dt-bindings/clock/exynos5433.h> 18 19 #include "clk.h" 20 #include "clk-cpu.h" 21 #include "clk-pll.h" 22 23 /* 24 * Register offset definitions for CMU_TOP 25 */ 26 #define ISP_PLL_LOCK 0x0000 27 #define AUD_PLL_LOCK 0x0004 28 #define ISP_PLL_CON0 0x0100 29 #define ISP_PLL_CON1 0x0104 30 #define ISP_PLL_FREQ_DET 0x0108 31 #define AUD_PLL_CON0 0x0110 32 #define AUD_PLL_CON1 0x0114 33 #define AUD_PLL_CON2 0x0118 34 #define AUD_PLL_FREQ_DET 0x011c 35 #define MUX_SEL_TOP0 0x0200 36 #define MUX_SEL_TOP1 0x0204 37 #define MUX_SEL_TOP2 0x0208 38 #define MUX_SEL_TOP3 0x020c 39 #define MUX_SEL_TOP4 0x0210 40 #define MUX_SEL_TOP_MSCL 0x0220 41 #define MUX_SEL_TOP_CAM1 0x0224 42 #define MUX_SEL_TOP_DISP 0x0228 43 #define MUX_SEL_TOP_FSYS0 0x0230 44 #define MUX_SEL_TOP_FSYS1 0x0234 45 #define MUX_SEL_TOP_PERIC0 0x0238 46 #define MUX_SEL_TOP_PERIC1 0x023c 47 #define MUX_ENABLE_TOP0 0x0300 48 #define MUX_ENABLE_TOP1 0x0304 49 #define MUX_ENABLE_TOP2 0x0308 50 #define MUX_ENABLE_TOP3 0x030c 51 #define MUX_ENABLE_TOP4 0x0310 52 #define MUX_ENABLE_TOP_MSCL 0x0320 53 #define MUX_ENABLE_TOP_CAM1 0x0324 54 #define MUX_ENABLE_TOP_DISP 0x0328 55 #define MUX_ENABLE_TOP_FSYS0 0x0330 56 #define MUX_ENABLE_TOP_FSYS1 0x0334 57 #define MUX_ENABLE_TOP_PERIC0 0x0338 58 #define MUX_ENABLE_TOP_PERIC1 0x033c 59 #define MUX_STAT_TOP0 0x0400 60 #define MUX_STAT_TOP1 0x0404 61 #define MUX_STAT_TOP2 0x0408 62 #define MUX_STAT_TOP3 0x040c 63 #define MUX_STAT_TOP4 0x0410 64 #define MUX_STAT_TOP_MSCL 0x0420 65 #define MUX_STAT_TOP_CAM1 0x0424 66 #define MUX_STAT_TOP_FSYS0 0x0430 67 #define MUX_STAT_TOP_FSYS1 0x0434 68 #define MUX_STAT_TOP_PERIC0 0x0438 69 #define MUX_STAT_TOP_PERIC1 0x043c 70 #define DIV_TOP0 0x0600 71 #define DIV_TOP1 0x0604 72 #define DIV_TOP2 0x0608 73 #define DIV_TOP3 0x060c 74 #define DIV_TOP4 0x0610 75 #define DIV_TOP_MSCL 0x0618 76 #define DIV_TOP_CAM10 0x061c 77 #define DIV_TOP_CAM11 0x0620 78 #define DIV_TOP_FSYS0 0x062c 79 #define DIV_TOP_FSYS1 0x0630 80 #define DIV_TOP_FSYS2 0x0634 81 #define DIV_TOP_PERIC0 0x0638 82 #define DIV_TOP_PERIC1 0x063c 83 #define DIV_TOP_PERIC2 0x0640 84 #define DIV_TOP_PERIC3 0x0644 85 #define DIV_TOP_PERIC4 0x0648 86 #define DIV_TOP_PLL_FREQ_DET 0x064c 87 #define DIV_STAT_TOP0 0x0700 88 #define DIV_STAT_TOP1 0x0704 89 #define DIV_STAT_TOP2 0x0708 90 #define DIV_STAT_TOP3 0x070c 91 #define DIV_STAT_TOP4 0x0710 92 #define DIV_STAT_TOP_MSCL 0x0718 93 #define DIV_STAT_TOP_CAM10 0x071c 94 #define DIV_STAT_TOP_CAM11 0x0720 95 #define DIV_STAT_TOP_FSYS0 0x072c 96 #define DIV_STAT_TOP_FSYS1 0x0730 97 #define DIV_STAT_TOP_FSYS2 0x0734 98 #define DIV_STAT_TOP_PERIC0 0x0738 99 #define DIV_STAT_TOP_PERIC1 0x073c 100 #define DIV_STAT_TOP_PERIC2 0x0740 101 #define DIV_STAT_TOP_PERIC3 0x0744 102 #define DIV_STAT_TOP_PLL_FREQ_DET 0x074c 103 #define ENABLE_ACLK_TOP 0x0800 104 #define ENABLE_SCLK_TOP 0x0a00 105 #define ENABLE_SCLK_TOP_MSCL 0x0a04 106 #define ENABLE_SCLK_TOP_CAM1 0x0a08 107 #define ENABLE_SCLK_TOP_DISP 0x0a0c 108 #define ENABLE_SCLK_TOP_FSYS 0x0a10 109 #define ENABLE_SCLK_TOP_PERIC 0x0a14 110 #define ENABLE_IP_TOP 0x0b00 111 #define ENABLE_CMU_TOP 0x0c00 112 #define ENABLE_CMU_TOP_DIV_STAT 0x0c04 113 114 static const unsigned long top_clk_regs[] __initconst = { 115 ISP_PLL_LOCK, 116 AUD_PLL_LOCK, 117 ISP_PLL_CON0, 118 ISP_PLL_CON1, 119 ISP_PLL_FREQ_DET, 120 AUD_PLL_CON0, 121 AUD_PLL_CON1, 122 AUD_PLL_CON2, 123 AUD_PLL_FREQ_DET, 124 MUX_SEL_TOP0, 125 MUX_SEL_TOP1, 126 MUX_SEL_TOP2, 127 MUX_SEL_TOP3, 128 MUX_SEL_TOP4, 129 MUX_SEL_TOP_MSCL, 130 MUX_SEL_TOP_CAM1, 131 MUX_SEL_TOP_DISP, 132 MUX_SEL_TOP_FSYS0, 133 MUX_SEL_TOP_FSYS1, 134 MUX_SEL_TOP_PERIC0, 135 MUX_SEL_TOP_PERIC1, 136 MUX_ENABLE_TOP0, 137 MUX_ENABLE_TOP1, 138 MUX_ENABLE_TOP2, 139 MUX_ENABLE_TOP3, 140 MUX_ENABLE_TOP4, 141 MUX_ENABLE_TOP_MSCL, 142 MUX_ENABLE_TOP_CAM1, 143 MUX_ENABLE_TOP_DISP, 144 MUX_ENABLE_TOP_FSYS0, 145 MUX_ENABLE_TOP_FSYS1, 146 MUX_ENABLE_TOP_PERIC0, 147 MUX_ENABLE_TOP_PERIC1, 148 DIV_TOP0, 149 DIV_TOP1, 150 DIV_TOP2, 151 DIV_TOP3, 152 DIV_TOP4, 153 DIV_TOP_MSCL, 154 DIV_TOP_CAM10, 155 DIV_TOP_CAM11, 156 DIV_TOP_FSYS0, 157 DIV_TOP_FSYS1, 158 DIV_TOP_FSYS2, 159 DIV_TOP_PERIC0, 160 DIV_TOP_PERIC1, 161 DIV_TOP_PERIC2, 162 DIV_TOP_PERIC3, 163 DIV_TOP_PERIC4, 164 DIV_TOP_PLL_FREQ_DET, 165 ENABLE_ACLK_TOP, 166 ENABLE_SCLK_TOP, 167 ENABLE_SCLK_TOP_MSCL, 168 ENABLE_SCLK_TOP_CAM1, 169 ENABLE_SCLK_TOP_DISP, 170 ENABLE_SCLK_TOP_FSYS, 171 ENABLE_SCLK_TOP_PERIC, 172 ENABLE_IP_TOP, 173 ENABLE_CMU_TOP, 174 ENABLE_CMU_TOP_DIV_STAT, 175 }; 176 177 static const struct samsung_clk_reg_dump top_suspend_regs[] = { 178 /* force all aclk clocks enabled */ 179 { ENABLE_ACLK_TOP, 0x67ecffed }, 180 /* force all sclk_uart clocks enabled */ 181 { ENABLE_SCLK_TOP_PERIC, 0x38 }, 182 /* ISP PLL has to be enabled for suspend: reset value + ENABLE bit */ 183 { ISP_PLL_CON0, 0x85cc0502 }, 184 /* ISP PLL has to be enabled for suspend: reset value + ENABLE bit */ 185 { AUD_PLL_CON0, 0x84830202 }, 186 }; 187 188 /* list of all parent clock list */ 189 PNAME(mout_aud_pll_p) = { "oscclk", "fout_aud_pll", }; 190 PNAME(mout_isp_pll_p) = { "oscclk", "fout_isp_pll", }; 191 PNAME(mout_aud_pll_user_p) = { "oscclk", "mout_aud_pll", }; 192 PNAME(mout_mphy_pll_user_p) = { "oscclk", "sclk_mphy_pll", }; 193 PNAME(mout_mfc_pll_user_p) = { "oscclk", "sclk_mfc_pll", }; 194 PNAME(mout_bus_pll_user_p) = { "oscclk", "sclk_bus_pll", }; 195 PNAME(mout_bus_pll_user_t_p) = { "oscclk", "mout_bus_pll_user", }; 196 PNAME(mout_mphy_pll_user_t_p) = { "oscclk", "mout_mphy_pll_user", }; 197 198 PNAME(mout_bus_mfc_pll_user_p) = { "mout_bus_pll_user", "mout_mfc_pll_user",}; 199 PNAME(mout_mfc_bus_pll_user_p) = { "mout_mfc_pll_user", "mout_bus_pll_user",}; 200 PNAME(mout_aclk_cam1_552_b_p) = { "mout_aclk_cam1_552_a", 201 "mout_mfc_pll_user", }; 202 PNAME(mout_aclk_cam1_552_a_p) = { "mout_isp_pll", "mout_bus_pll_user", }; 203 204 PNAME(mout_aclk_mfc_400_c_p) = { "mout_aclk_mfc_400_b", 205 "mout_mphy_pll_user", }; 206 PNAME(mout_aclk_mfc_400_b_p) = { "mout_aclk_mfc_400_a", 207 "mout_bus_pll_user", }; 208 PNAME(mout_aclk_mfc_400_a_p) = { "mout_mfc_pll_user", "mout_isp_pll", }; 209 210 PNAME(mout_bus_mphy_pll_user_p) = { "mout_bus_pll_user", 211 "mout_mphy_pll_user", }; 212 PNAME(mout_aclk_mscl_b_p) = { "mout_aclk_mscl_400_a", 213 "mout_mphy_pll_user", }; 214 PNAME(mout_aclk_g2d_400_b_p) = { "mout_aclk_g2d_400_a", 215 "mout_mphy_pll_user", }; 216 217 PNAME(mout_sclk_jpeg_c_p) = { "mout_sclk_jpeg_b", "mout_mphy_pll_user",}; 218 PNAME(mout_sclk_jpeg_b_p) = { "mout_sclk_jpeg_a", "mout_mfc_pll_user", }; 219 220 PNAME(mout_sclk_mmc2_b_p) = { "mout_sclk_mmc2_a", "mout_mfc_pll_user",}; 221 PNAME(mout_sclk_mmc1_b_p) = { "mout_sclk_mmc1_a", "mout_mfc_pll_user",}; 222 PNAME(mout_sclk_mmc0_d_p) = { "mout_sclk_mmc0_c", "mout_isp_pll", }; 223 PNAME(mout_sclk_mmc0_c_p) = { "mout_sclk_mmc0_b", "mout_mphy_pll_user",}; 224 PNAME(mout_sclk_mmc0_b_p) = { "mout_sclk_mmc0_a", "mout_mfc_pll_user", }; 225 226 PNAME(mout_sclk_spdif_p) = { "sclk_audio0", "sclk_audio1", 227 "oscclk", "ioclk_spdif_extclk", }; 228 PNAME(mout_sclk_audio1_p) = { "ioclk_audiocdclk1", "oscclk", 229 "mout_aud_pll_user_t",}; 230 PNAME(mout_sclk_audio0_p) = { "ioclk_audiocdclk0", "oscclk", 231 "mout_aud_pll_user_t",}; 232 233 PNAME(mout_sclk_hdmi_spdif_p) = { "sclk_audio1", "ioclk_spdif_extclk", }; 234 235 static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initconst = { 236 FFACTOR(0, "oscclk_efuse_common", "oscclk", 1, 1, 0), 237 }; 238 239 static const struct samsung_fixed_rate_clock top_fixed_clks[] __initconst = { 240 /* Xi2s{0|1}CDCLK input clock for I2S/PCM */ 241 FRATE(0, "ioclk_audiocdclk1", NULL, 0, 100000000), 242 FRATE(0, "ioclk_audiocdclk0", NULL, 0, 100000000), 243 /* Xi2s1SDI input clock for SPDIF */ 244 FRATE(0, "ioclk_spdif_extclk", NULL, 0, 100000000), 245 /* XspiCLK[4:0] input clock for SPI */ 246 FRATE(0, "ioclk_spi4_clk_in", NULL, 0, 50000000), 247 FRATE(0, "ioclk_spi3_clk_in", NULL, 0, 50000000), 248 FRATE(0, "ioclk_spi2_clk_in", NULL, 0, 50000000), 249 FRATE(0, "ioclk_spi1_clk_in", NULL, 0, 50000000), 250 FRATE(0, "ioclk_spi0_clk_in", NULL, 0, 50000000), 251 /* Xi2s1SCLK input clock for I2S1_BCLK */ 252 FRATE(0, "ioclk_i2s1_bclk_in", NULL, 0, 12288000), 253 }; 254 255 static const struct samsung_mux_clock top_mux_clks[] __initconst = { 256 /* MUX_SEL_TOP0 */ 257 MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p, MUX_SEL_TOP0, 258 4, 1), 259 MUX(CLK_MOUT_ISP_PLL, "mout_isp_pll", mout_isp_pll_p, MUX_SEL_TOP0, 260 0, 1), 261 262 /* MUX_SEL_TOP1 */ 263 MUX(CLK_MOUT_AUD_PLL_USER_T, "mout_aud_pll_user_t", 264 mout_aud_pll_user_p, MUX_SEL_TOP1, 12, 1), 265 MUX(CLK_MOUT_MPHY_PLL_USER, "mout_mphy_pll_user", mout_mphy_pll_user_p, 266 MUX_SEL_TOP1, 8, 1), 267 MUX(CLK_MOUT_MFC_PLL_USER, "mout_mfc_pll_user", mout_mfc_pll_user_p, 268 MUX_SEL_TOP1, 4, 1), 269 MUX(CLK_MOUT_BUS_PLL_USER, "mout_bus_pll_user", mout_bus_pll_user_p, 270 MUX_SEL_TOP1, 0, 1), 271 272 /* MUX_SEL_TOP2 */ 273 MUX(CLK_MOUT_ACLK_HEVC_400, "mout_aclk_hevc_400", 274 mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 28, 1), 275 MUX(CLK_MOUT_ACLK_CAM1_333, "mout_aclk_cam1_333", 276 mout_mfc_bus_pll_user_p, MUX_SEL_TOP2, 16, 1), 277 MUX(CLK_MOUT_ACLK_CAM1_552_B, "mout_aclk_cam1_552_b", 278 mout_aclk_cam1_552_b_p, MUX_SEL_TOP2, 12, 1), 279 MUX(CLK_MOUT_ACLK_CAM1_552_A, "mout_aclk_cam1_552_a", 280 mout_aclk_cam1_552_a_p, MUX_SEL_TOP2, 8, 1), 281 MUX(CLK_MOUT_ACLK_ISP_DIS_400, "mout_aclk_isp_dis_400", 282 mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 4, 1), 283 MUX(CLK_MOUT_ACLK_ISP_400, "mout_aclk_isp_400", 284 mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 0, 1), 285 286 /* MUX_SEL_TOP3 */ 287 MUX(CLK_MOUT_ACLK_BUS0_400, "mout_aclk_bus0_400", 288 mout_bus_mphy_pll_user_p, MUX_SEL_TOP3, 20, 1), 289 MUX(CLK_MOUT_ACLK_MSCL_400_B, "mout_aclk_mscl_400_b", 290 mout_aclk_mscl_b_p, MUX_SEL_TOP3, 16, 1), 291 MUX(CLK_MOUT_ACLK_MSCL_400_A, "mout_aclk_mscl_400_a", 292 mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 12, 1), 293 MUX(CLK_MOUT_ACLK_GSCL_333, "mout_aclk_gscl_333", 294 mout_mfc_bus_pll_user_p, MUX_SEL_TOP3, 8, 1), 295 MUX(CLK_MOUT_ACLK_G2D_400_B, "mout_aclk_g2d_400_b", 296 mout_aclk_g2d_400_b_p, MUX_SEL_TOP3, 4, 1), 297 MUX(CLK_MOUT_ACLK_G2D_400_A, "mout_aclk_g2d_400_a", 298 mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 0, 1), 299 300 /* MUX_SEL_TOP4 */ 301 MUX(CLK_MOUT_ACLK_MFC_400_C, "mout_aclk_mfc_400_c", 302 mout_aclk_mfc_400_c_p, MUX_SEL_TOP4, 8, 1), 303 MUX(CLK_MOUT_ACLK_MFC_400_B, "mout_aclk_mfc_400_b", 304 mout_aclk_mfc_400_b_p, MUX_SEL_TOP4, 4, 1), 305 MUX(CLK_MOUT_ACLK_MFC_400_A, "mout_aclk_mfc_400_a", 306 mout_aclk_mfc_400_a_p, MUX_SEL_TOP4, 0, 1), 307 308 /* MUX_SEL_TOP_MSCL */ 309 MUX(CLK_MOUT_SCLK_JPEG_C, "mout_sclk_jpeg_c", mout_sclk_jpeg_c_p, 310 MUX_SEL_TOP_MSCL, 8, 1), 311 MUX(CLK_MOUT_SCLK_JPEG_B, "mout_sclk_jpeg_b", mout_sclk_jpeg_b_p, 312 MUX_SEL_TOP_MSCL, 4, 1), 313 MUX(CLK_MOUT_SCLK_JPEG_A, "mout_sclk_jpeg_a", mout_bus_pll_user_t_p, 314 MUX_SEL_TOP_MSCL, 0, 1), 315 316 /* MUX_SEL_TOP_CAM1 */ 317 MUX(CLK_MOUT_SCLK_ISP_SENSOR2, "mout_sclk_isp_sensor2", 318 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 24, 1), 319 MUX(CLK_MOUT_SCLK_ISP_SENSOR1, "mout_sclk_isp_sensor1", 320 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 20, 1), 321 MUX(CLK_MOUT_SCLK_ISP_SENSOR0, "mout_sclk_isp_sensor0", 322 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 16, 1), 323 MUX(CLK_MOUT_SCLK_ISP_UART, "mout_sclk_isp_uart", 324 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 8, 1), 325 MUX(CLK_MOUT_SCLK_ISP_SPI1, "mout_sclk_isp_spi1", 326 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 4, 1), 327 MUX(CLK_MOUT_SCLK_ISP_SPI0, "mout_sclk_isp_spi0", 328 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 0, 1), 329 330 /* MUX_SEL_TOP_FSYS0 */ 331 MUX(CLK_MOUT_SCLK_MMC2_B, "mout_sclk_mmc2_b", mout_sclk_mmc2_b_p, 332 MUX_SEL_TOP_FSYS0, 28, 1), 333 MUX(CLK_MOUT_SCLK_MMC2_A, "mout_sclk_mmc2_a", mout_bus_pll_user_t_p, 334 MUX_SEL_TOP_FSYS0, 24, 1), 335 MUX(CLK_MOUT_SCLK_MMC1_B, "mout_sclk_mmc1_b", mout_sclk_mmc1_b_p, 336 MUX_SEL_TOP_FSYS0, 20, 1), 337 MUX(CLK_MOUT_SCLK_MMC1_A, "mout_sclk_mmc1_a", mout_bus_pll_user_t_p, 338 MUX_SEL_TOP_FSYS0, 16, 1), 339 MUX(CLK_MOUT_SCLK_MMC0_D, "mout_sclk_mmc0_d", mout_sclk_mmc0_d_p, 340 MUX_SEL_TOP_FSYS0, 12, 1), 341 MUX(CLK_MOUT_SCLK_MMC0_C, "mout_sclk_mmc0_c", mout_sclk_mmc0_c_p, 342 MUX_SEL_TOP_FSYS0, 8, 1), 343 MUX(CLK_MOUT_SCLK_MMC0_B, "mout_sclk_mmc0_b", mout_sclk_mmc0_b_p, 344 MUX_SEL_TOP_FSYS0, 4, 1), 345 MUX(CLK_MOUT_SCLK_MMC0_A, "mout_sclk_mmc0_a", mout_bus_pll_user_t_p, 346 MUX_SEL_TOP_FSYS0, 0, 1), 347 348 /* MUX_SEL_TOP_FSYS1 */ 349 MUX(CLK_MOUT_SCLK_PCIE_100, "mout_sclk_pcie_100", mout_bus_pll_user_t_p, 350 MUX_SEL_TOP_FSYS1, 12, 1), 351 MUX(CLK_MOUT_SCLK_UFSUNIPRO, "mout_sclk_ufsunipro", 352 mout_mphy_pll_user_t_p, MUX_SEL_TOP_FSYS1, 8, 1), 353 MUX(CLK_MOUT_SCLK_USBHOST30, "mout_sclk_usbhost30", 354 mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 4, 1), 355 MUX(CLK_MOUT_SCLK_USBDRD30, "mout_sclk_usbdrd30", 356 mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 0, 1), 357 358 /* MUX_SEL_TOP_PERIC0 */ 359 MUX(CLK_MOUT_SCLK_SPI4, "mout_sclk_spi4", mout_bus_pll_user_t_p, 360 MUX_SEL_TOP_PERIC0, 28, 1), 361 MUX(CLK_MOUT_SCLK_SPI3, "mout_sclk_spi3", mout_bus_pll_user_t_p, 362 MUX_SEL_TOP_PERIC0, 24, 1), 363 MUX(CLK_MOUT_SCLK_UART2, "mout_sclk_uart2", mout_bus_pll_user_t_p, 364 MUX_SEL_TOP_PERIC0, 20, 1), 365 MUX(CLK_MOUT_SCLK_UART1, "mout_sclk_uart1", mout_bus_pll_user_t_p, 366 MUX_SEL_TOP_PERIC0, 16, 1), 367 MUX(CLK_MOUT_SCLK_UART0, "mout_sclk_uart0", mout_bus_pll_user_t_p, 368 MUX_SEL_TOP_PERIC0, 12, 1), 369 MUX(CLK_MOUT_SCLK_SPI2, "mout_sclk_spi2", mout_bus_pll_user_t_p, 370 MUX_SEL_TOP_PERIC0, 8, 1), 371 MUX(CLK_MOUT_SCLK_SPI1, "mout_sclk_spi1", mout_bus_pll_user_t_p, 372 MUX_SEL_TOP_PERIC0, 4, 1), 373 MUX(CLK_MOUT_SCLK_SPI0, "mout_sclk_spi0", mout_bus_pll_user_t_p, 374 MUX_SEL_TOP_PERIC0, 0, 1), 375 376 /* MUX_SEL_TOP_PERIC1 */ 377 MUX(CLK_MOUT_SCLK_SLIMBUS, "mout_sclk_slimbus", mout_aud_pll_user_p, 378 MUX_SEL_TOP_PERIC1, 16, 1), 379 MUX(CLK_MOUT_SCLK_SPDIF, "mout_sclk_spdif", mout_sclk_spdif_p, 380 MUX_SEL_TOP_PERIC1, 12, 2), 381 MUX(CLK_MOUT_SCLK_AUDIO1, "mout_sclk_audio1", mout_sclk_audio1_p, 382 MUX_SEL_TOP_PERIC1, 4, 2), 383 MUX(CLK_MOUT_SCLK_AUDIO0, "mout_sclk_audio0", mout_sclk_audio0_p, 384 MUX_SEL_TOP_PERIC1, 0, 2), 385 386 /* MUX_SEL_TOP_DISP */ 387 MUX(CLK_MOUT_SCLK_HDMI_SPDIF, "mout_sclk_hdmi_spdif", 388 mout_sclk_hdmi_spdif_p, MUX_SEL_TOP_DISP, 0, 1), 389 }; 390 391 static const struct samsung_div_clock top_div_clks[] __initconst = { 392 /* DIV_TOP0 */ 393 DIV(CLK_DIV_ACLK_CAM1_333, "div_aclk_cam1_333", "mout_aclk_cam1_333", 394 DIV_TOP0, 28, 3), 395 DIV(CLK_DIV_ACLK_CAM1_400, "div_aclk_cam1_400", "mout_bus_pll_user", 396 DIV_TOP0, 24, 3), 397 DIV(CLK_DIV_ACLK_CAM1_552, "div_aclk_cam1_552", "mout_aclk_cam1_552_b", 398 DIV_TOP0, 20, 3), 399 DIV(CLK_DIV_ACLK_CAM0_333, "div_aclk_cam0_333", "mout_mfc_pll_user", 400 DIV_TOP0, 16, 3), 401 DIV(CLK_DIV_ACLK_CAM0_400, "div_aclk_cam0_400", "mout_bus_pll_user", 402 DIV_TOP0, 12, 3), 403 DIV(CLK_DIV_ACLK_CAM0_552, "div_aclk_cam0_552", "mout_isp_pll", 404 DIV_TOP0, 8, 3), 405 DIV(CLK_DIV_ACLK_ISP_DIS_400, "div_aclk_isp_dis_400", 406 "mout_aclk_isp_dis_400", DIV_TOP0, 4, 4), 407 DIV(CLK_DIV_ACLK_ISP_400, "div_aclk_isp_400", 408 "mout_aclk_isp_400", DIV_TOP0, 0, 4), 409 410 /* DIV_TOP1 */ 411 DIV(CLK_DIV_ACLK_GSCL_111, "div_aclk_gscl_111", "mout_aclk_gscl_333", 412 DIV_TOP1, 28, 3), 413 DIV(CLK_DIV_ACLK_GSCL_333, "div_aclk_gscl_333", "mout_aclk_gscl_333", 414 DIV_TOP1, 24, 3), 415 DIV(CLK_DIV_ACLK_HEVC_400, "div_aclk_hevc_400", "mout_aclk_hevc_400", 416 DIV_TOP1, 20, 3), 417 DIV(CLK_DIV_ACLK_MFC_400, "div_aclk_mfc_400", "mout_aclk_mfc_400_c", 418 DIV_TOP1, 12, 3), 419 DIV(CLK_DIV_ACLK_G2D_266, "div_aclk_g2d_266", "mout_bus_pll_user", 420 DIV_TOP1, 8, 3), 421 DIV(CLK_DIV_ACLK_G2D_400, "div_aclk_g2d_400", "mout_aclk_g2d_400_b", 422 DIV_TOP1, 0, 3), 423 424 /* DIV_TOP2 */ 425 DIV(CLK_DIV_ACLK_MSCL_400, "div_aclk_mscl_400", "mout_aclk_mscl_400_b", 426 DIV_TOP2, 4, 3), 427 DIV(CLK_DIV_ACLK_FSYS_200, "div_aclk_fsys_200", "mout_bus_pll_user", 428 DIV_TOP2, 0, 3), 429 430 /* DIV_TOP3 */ 431 DIV(CLK_DIV_ACLK_IMEM_SSSX_266, "div_aclk_imem_sssx_266", 432 "mout_bus_pll_user", DIV_TOP3, 24, 3), 433 DIV(CLK_DIV_ACLK_IMEM_200, "div_aclk_imem_200", 434 "mout_bus_pll_user", DIV_TOP3, 20, 3), 435 DIV(CLK_DIV_ACLK_IMEM_266, "div_aclk_imem_266", 436 "mout_bus_pll_user", DIV_TOP3, 16, 3), 437 DIV(CLK_DIV_ACLK_PERIC_66_B, "div_aclk_peric_66_b", 438 "div_aclk_peric_66_a", DIV_TOP3, 12, 3), 439 DIV(CLK_DIV_ACLK_PERIC_66_A, "div_aclk_peric_66_a", 440 "mout_bus_pll_user", DIV_TOP3, 8, 3), 441 DIV(CLK_DIV_ACLK_PERIS_66_B, "div_aclk_peris_66_b", 442 "div_aclk_peris_66_a", DIV_TOP3, 4, 3), 443 DIV(CLK_DIV_ACLK_PERIS_66_A, "div_aclk_peris_66_a", 444 "mout_bus_pll_user", DIV_TOP3, 0, 3), 445 446 /* DIV_TOP4 */ 447 DIV(CLK_DIV_ACLK_G3D_400, "div_aclk_g3d_400", "mout_bus_pll_user", 448 DIV_TOP4, 8, 3), 449 DIV(CLK_DIV_ACLK_BUS0_400, "div_aclk_bus0_400", "mout_aclk_bus0_400", 450 DIV_TOP4, 4, 3), 451 DIV(CLK_DIV_ACLK_BUS1_400, "div_aclk_bus1_400", "mout_bus_pll_user", 452 DIV_TOP4, 0, 3), 453 454 /* DIV_TOP_MSCL */ 455 DIV(CLK_DIV_SCLK_JPEG, "div_sclk_jpeg", "mout_sclk_jpeg_c", 456 DIV_TOP_MSCL, 0, 4), 457 458 /* DIV_TOP_CAM10 */ 459 DIV(CLK_DIV_SCLK_ISP_UART, "div_sclk_isp_uart", "mout_sclk_isp_uart", 460 DIV_TOP_CAM10, 24, 5), 461 DIV(CLK_DIV_SCLK_ISP_SPI1_B, "div_sclk_isp_spi1_b", 462 "div_sclk_isp_spi1_a", DIV_TOP_CAM10, 16, 8), 463 DIV(CLK_DIV_SCLK_ISP_SPI1_A, "div_sclk_isp_spi1_a", 464 "mout_sclk_isp_spi1", DIV_TOP_CAM10, 12, 4), 465 DIV(CLK_DIV_SCLK_ISP_SPI0_B, "div_sclk_isp_spi0_b", 466 "div_sclk_isp_spi0_a", DIV_TOP_CAM10, 4, 8), 467 DIV(CLK_DIV_SCLK_ISP_SPI0_A, "div_sclk_isp_spi0_a", 468 "mout_sclk_isp_spi0", DIV_TOP_CAM10, 0, 4), 469 470 /* DIV_TOP_CAM11 */ 471 DIV(CLK_DIV_SCLK_ISP_SENSOR2_B, "div_sclk_isp_sensor2_b", 472 "div_sclk_isp_sensor2_a", DIV_TOP_CAM11, 20, 4), 473 DIV(CLK_DIV_SCLK_ISP_SENSOR2_A, "div_sclk_isp_sensor2_a", 474 "mout_sclk_isp_sensor2", DIV_TOP_CAM11, 16, 4), 475 DIV(CLK_DIV_SCLK_ISP_SENSOR1_B, "div_sclk_isp_sensor1_b", 476 "div_sclk_isp_sensor1_a", DIV_TOP_CAM11, 12, 4), 477 DIV(CLK_DIV_SCLK_ISP_SENSOR1_A, "div_sclk_isp_sensor1_a", 478 "mout_sclk_isp_sensor1", DIV_TOP_CAM11, 8, 4), 479 DIV(CLK_DIV_SCLK_ISP_SENSOR0_B, "div_sclk_isp_sensor0_b", 480 "div_sclk_isp_sensor0_a", DIV_TOP_CAM11, 4, 4), 481 DIV(CLK_DIV_SCLK_ISP_SENSOR0_A, "div_sclk_isp_sensor0_a", 482 "mout_sclk_isp_sensor0", DIV_TOP_CAM11, 0, 4), 483 484 /* DIV_TOP_FSYS0 */ 485 DIV(CLK_DIV_SCLK_MMC1_B, "div_sclk_mmc1_b", "div_sclk_mmc1_a", 486 DIV_TOP_FSYS0, 16, 8), 487 DIV(CLK_DIV_SCLK_MMC1_A, "div_sclk_mmc1_a", "mout_sclk_mmc1_b", 488 DIV_TOP_FSYS0, 12, 4), 489 DIV_F(CLK_DIV_SCLK_MMC0_B, "div_sclk_mmc0_b", "div_sclk_mmc0_a", 490 DIV_TOP_FSYS0, 4, 8, CLK_SET_RATE_PARENT, 0), 491 DIV_F(CLK_DIV_SCLK_MMC0_A, "div_sclk_mmc0_a", "mout_sclk_mmc0_d", 492 DIV_TOP_FSYS0, 0, 4, CLK_SET_RATE_PARENT, 0), 493 494 /* DIV_TOP_FSYS1 */ 495 DIV(CLK_DIV_SCLK_MMC2_B, "div_sclk_mmc2_b", "div_sclk_mmc2_a", 496 DIV_TOP_FSYS1, 4, 8), 497 DIV(CLK_DIV_SCLK_MMC2_A, "div_sclk_mmc2_a", "mout_sclk_mmc2_b", 498 DIV_TOP_FSYS1, 0, 4), 499 500 /* DIV_TOP_FSYS2 */ 501 DIV(CLK_DIV_SCLK_PCIE_100, "div_sclk_pcie_100", "mout_sclk_pcie_100", 502 DIV_TOP_FSYS2, 12, 3), 503 DIV(CLK_DIV_SCLK_USBHOST30, "div_sclk_usbhost30", 504 "mout_sclk_usbhost30", DIV_TOP_FSYS2, 8, 4), 505 DIV(CLK_DIV_SCLK_UFSUNIPRO, "div_sclk_ufsunipro", 506 "mout_sclk_ufsunipro", DIV_TOP_FSYS2, 4, 4), 507 DIV(CLK_DIV_SCLK_USBDRD30, "div_sclk_usbdrd30", "mout_sclk_usbdrd30", 508 DIV_TOP_FSYS2, 0, 4), 509 510 /* DIV_TOP_PERIC0 */ 511 DIV(CLK_DIV_SCLK_SPI1_B, "div_sclk_spi1_b", "div_sclk_spi1_a", 512 DIV_TOP_PERIC0, 16, 8), 513 DIV(CLK_DIV_SCLK_SPI1_A, "div_sclk_spi1_a", "mout_sclk_spi1", 514 DIV_TOP_PERIC0, 12, 4), 515 DIV(CLK_DIV_SCLK_SPI0_B, "div_sclk_spi0_b", "div_sclk_spi0_a", 516 DIV_TOP_PERIC0, 4, 8), 517 DIV(CLK_DIV_SCLK_SPI0_A, "div_sclk_spi0_a", "mout_sclk_spi0", 518 DIV_TOP_PERIC0, 0, 4), 519 520 /* DIV_TOP_PERIC1 */ 521 DIV(CLK_DIV_SCLK_SPI2_B, "div_sclk_spi2_b", "div_sclk_spi2_a", 522 DIV_TOP_PERIC1, 4, 8), 523 DIV(CLK_DIV_SCLK_SPI2_A, "div_sclk_spi2_a", "mout_sclk_spi2", 524 DIV_TOP_PERIC1, 0, 4), 525 526 /* DIV_TOP_PERIC2 */ 527 DIV(CLK_DIV_SCLK_UART2, "div_sclk_uart2", "mout_sclk_uart2", 528 DIV_TOP_PERIC2, 8, 4), 529 DIV(CLK_DIV_SCLK_UART1, "div_sclk_uart1", "mout_sclk_uart0", 530 DIV_TOP_PERIC2, 4, 4), 531 DIV(CLK_DIV_SCLK_UART0, "div_sclk_uart0", "mout_sclk_uart1", 532 DIV_TOP_PERIC2, 0, 4), 533 534 /* DIV_TOP_PERIC3 */ 535 DIV(CLK_DIV_SCLK_I2S1, "div_sclk_i2s1", "sclk_audio1", 536 DIV_TOP_PERIC3, 16, 6), 537 DIV(CLK_DIV_SCLK_PCM1, "div_sclk_pcm1", "sclk_audio1", 538 DIV_TOP_PERIC3, 8, 8), 539 DIV(CLK_DIV_SCLK_AUDIO1, "div_sclk_audio1", "mout_sclk_audio1", 540 DIV_TOP_PERIC3, 4, 4), 541 DIV(CLK_DIV_SCLK_AUDIO0, "div_sclk_audio0", "mout_sclk_audio0", 542 DIV_TOP_PERIC3, 0, 4), 543 544 /* DIV_TOP_PERIC4 */ 545 DIV(CLK_DIV_SCLK_SPI4_B, "div_sclk_spi4_b", "div_sclk_spi4_a", 546 DIV_TOP_PERIC4, 16, 8), 547 DIV(CLK_DIV_SCLK_SPI4_A, "div_sclk_spi4_a", "mout_sclk_spi4", 548 DIV_TOP_PERIC4, 12, 4), 549 DIV(CLK_DIV_SCLK_SPI3_B, "div_sclk_spi3_b", "div_sclk_spi3_a", 550 DIV_TOP_PERIC4, 4, 8), 551 DIV(CLK_DIV_SCLK_SPI3_A, "div_sclk_spi3_a", "mout_sclk_spi3", 552 DIV_TOP_PERIC4, 0, 4), 553 }; 554 555 static const struct samsung_gate_clock top_gate_clks[] __initconst = { 556 /* ENABLE_ACLK_TOP */ 557 GATE(CLK_ACLK_G3D_400, "aclk_g3d_400", "div_aclk_g3d_400", 558 ENABLE_ACLK_TOP, 30, CLK_IS_CRITICAL, 0), 559 GATE(CLK_ACLK_IMEM_SSSX_266, "aclk_imem_sssx_266", 560 "div_aclk_imem_sssx_266", ENABLE_ACLK_TOP, 561 29, CLK_IGNORE_UNUSED, 0), 562 GATE(CLK_ACLK_BUS0_400, "aclk_bus0_400", "div_aclk_bus0_400", 563 ENABLE_ACLK_TOP, 26, 564 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), 565 GATE(CLK_ACLK_BUS1_400, "aclk_bus1_400", "div_aclk_bus1_400", 566 ENABLE_ACLK_TOP, 25, 567 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), 568 GATE(CLK_ACLK_IMEM_200, "aclk_imem_200", "div_aclk_imem_200", 569 ENABLE_ACLK_TOP, 24, 570 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), 571 GATE(CLK_ACLK_IMEM_266, "aclk_imem_266", "div_aclk_imem_266", 572 ENABLE_ACLK_TOP, 23, 573 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), 574 GATE(CLK_ACLK_PERIC_66, "aclk_peric_66", "div_aclk_peric_66_b", 575 ENABLE_ACLK_TOP, 22, 576 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), 577 GATE(CLK_ACLK_PERIS_66, "aclk_peris_66", "div_aclk_peris_66_b", 578 ENABLE_ACLK_TOP, 21, 579 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), 580 GATE(CLK_ACLK_MSCL_400, "aclk_mscl_400", "div_aclk_mscl_400", 581 ENABLE_ACLK_TOP, 19, 582 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), 583 GATE(CLK_ACLK_FSYS_200, "aclk_fsys_200", "div_aclk_fsys_200", 584 ENABLE_ACLK_TOP, 18, 585 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), 586 GATE(CLK_ACLK_GSCL_111, "aclk_gscl_111", "div_aclk_gscl_111", 587 ENABLE_ACLK_TOP, 15, 588 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), 589 GATE(CLK_ACLK_GSCL_333, "aclk_gscl_333", "div_aclk_gscl_333", 590 ENABLE_ACLK_TOP, 14, 591 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 592 GATE(CLK_ACLK_CAM1_333, "aclk_cam1_333", "div_aclk_cam1_333", 593 ENABLE_ACLK_TOP, 13, 594 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 595 GATE(CLK_ACLK_CAM1_400, "aclk_cam1_400", "div_aclk_cam1_400", 596 ENABLE_ACLK_TOP, 12, 597 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), 598 GATE(CLK_ACLK_CAM1_552, "aclk_cam1_552", "div_aclk_cam1_552", 599 ENABLE_ACLK_TOP, 11, 600 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 601 GATE(CLK_ACLK_CAM0_333, "aclk_cam0_333", "div_aclk_cam0_333", 602 ENABLE_ACLK_TOP, 10, 603 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 604 GATE(CLK_ACLK_CAM0_400, "aclk_cam0_400", "div_aclk_cam0_400", 605 ENABLE_ACLK_TOP, 9, 606 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), 607 GATE(CLK_ACLK_CAM0_552, "aclk_cam0_552", "div_aclk_cam0_552", 608 ENABLE_ACLK_TOP, 8, 609 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 610 GATE(CLK_ACLK_ISP_DIS_400, "aclk_isp_dis_400", "div_aclk_isp_dis_400", 611 ENABLE_ACLK_TOP, 7, 612 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 613 GATE(CLK_ACLK_ISP_400, "aclk_isp_400", "div_aclk_isp_400", 614 ENABLE_ACLK_TOP, 6, 615 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), 616 GATE(CLK_ACLK_HEVC_400, "aclk_hevc_400", "div_aclk_hevc_400", 617 ENABLE_ACLK_TOP, 5, 618 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), 619 GATE(CLK_ACLK_MFC_400, "aclk_mfc_400", "div_aclk_mfc_400", 620 ENABLE_ACLK_TOP, 3, 621 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), 622 GATE(CLK_ACLK_G2D_266, "aclk_g2d_266", "div_aclk_g2d_266", 623 ENABLE_ACLK_TOP, 2, 624 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 625 GATE(CLK_ACLK_G2D_400, "aclk_g2d_400", "div_aclk_g2d_400", 626 ENABLE_ACLK_TOP, 0, 627 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), 628 629 /* ENABLE_SCLK_TOP_MSCL */ 630 GATE(CLK_SCLK_JPEG_MSCL, "sclk_jpeg_mscl", "div_sclk_jpeg", 631 ENABLE_SCLK_TOP_MSCL, 0, CLK_SET_RATE_PARENT, 0), 632 633 /* ENABLE_SCLK_TOP_CAM1 */ 634 GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "div_sclk_isp_sensor2_b", 635 ENABLE_SCLK_TOP_CAM1, 7, 0, 0), 636 GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "div_sclk_isp_sensor1_b", 637 ENABLE_SCLK_TOP_CAM1, 6, 0, 0), 638 GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "div_sclk_isp_sensor0_b", 639 ENABLE_SCLK_TOP_CAM1, 5, 0, 0), 640 GATE(CLK_SCLK_ISP_MCTADC_CAM1, "sclk_isp_mctadc_cam1", "oscclk", 641 ENABLE_SCLK_TOP_CAM1, 4, 0, 0), 642 GATE(CLK_SCLK_ISP_UART_CAM1, "sclk_isp_uart_cam1", "div_sclk_isp_uart", 643 ENABLE_SCLK_TOP_CAM1, 2, 0, 0), 644 GATE(CLK_SCLK_ISP_SPI1_CAM1, "sclk_isp_spi1_cam1", "div_sclk_isp_spi1_b", 645 ENABLE_SCLK_TOP_CAM1, 1, 0, 0), 646 GATE(CLK_SCLK_ISP_SPI0_CAM1, "sclk_isp_spi0_cam1", "div_sclk_isp_spi0_b", 647 ENABLE_SCLK_TOP_CAM1, 0, 0, 0), 648 649 /* ENABLE_SCLK_TOP_DISP */ 650 GATE(CLK_SCLK_HDMI_SPDIF_DISP, "sclk_hdmi_spdif_disp", 651 "mout_sclk_hdmi_spdif", ENABLE_SCLK_TOP_DISP, 0, 652 CLK_IGNORE_UNUSED, 0), 653 654 /* ENABLE_SCLK_TOP_FSYS */ 655 GATE(CLK_SCLK_PCIE_100_FSYS, "sclk_pcie_100_fsys", "div_sclk_pcie_100", 656 ENABLE_SCLK_TOP_FSYS, 7, CLK_IGNORE_UNUSED, 0), 657 GATE(CLK_SCLK_MMC2_FSYS, "sclk_mmc2_fsys", "div_sclk_mmc2_b", 658 ENABLE_SCLK_TOP_FSYS, 6, CLK_SET_RATE_PARENT, 0), 659 GATE(CLK_SCLK_MMC1_FSYS, "sclk_mmc1_fsys", "div_sclk_mmc1_b", 660 ENABLE_SCLK_TOP_FSYS, 5, CLK_SET_RATE_PARENT, 0), 661 GATE(CLK_SCLK_MMC0_FSYS, "sclk_mmc0_fsys", "div_sclk_mmc0_b", 662 ENABLE_SCLK_TOP_FSYS, 4, CLK_SET_RATE_PARENT, 0), 663 GATE(CLK_SCLK_UFSUNIPRO_FSYS, "sclk_ufsunipro_fsys", 664 "div_sclk_ufsunipro", ENABLE_SCLK_TOP_FSYS, 665 3, CLK_SET_RATE_PARENT, 0), 666 GATE(CLK_SCLK_USBHOST30_FSYS, "sclk_usbhost30_fsys", 667 "div_sclk_usbhost30", ENABLE_SCLK_TOP_FSYS, 668 1, CLK_SET_RATE_PARENT, 0), 669 GATE(CLK_SCLK_USBDRD30_FSYS, "sclk_usbdrd30_fsys", 670 "div_sclk_usbdrd30", ENABLE_SCLK_TOP_FSYS, 671 0, CLK_SET_RATE_PARENT, 0), 672 673 /* ENABLE_SCLK_TOP_PERIC */ 674 GATE(CLK_SCLK_SPI4_PERIC, "sclk_spi4_peric", "div_sclk_spi4_b", 675 ENABLE_SCLK_TOP_PERIC, 12, CLK_SET_RATE_PARENT, 0), 676 GATE(CLK_SCLK_SPI3_PERIC, "sclk_spi3_peric", "div_sclk_spi3_b", 677 ENABLE_SCLK_TOP_PERIC, 11, CLK_SET_RATE_PARENT, 0), 678 GATE(CLK_SCLK_SPDIF_PERIC, "sclk_spdif_peric", "mout_sclk_spdif", 679 ENABLE_SCLK_TOP_PERIC, 9, CLK_SET_RATE_PARENT, 0), 680 GATE(CLK_SCLK_I2S1_PERIC, "sclk_i2s1_peric", "div_sclk_i2s1", 681 ENABLE_SCLK_TOP_PERIC, 8, CLK_SET_RATE_PARENT, 0), 682 GATE(CLK_SCLK_PCM1_PERIC, "sclk_pcm1_peric", "div_sclk_pcm1", 683 ENABLE_SCLK_TOP_PERIC, 7, CLK_SET_RATE_PARENT, 0), 684 GATE(CLK_SCLK_UART2_PERIC, "sclk_uart2_peric", "div_sclk_uart2", 685 ENABLE_SCLK_TOP_PERIC, 5, CLK_SET_RATE_PARENT | 686 CLK_IGNORE_UNUSED, 0), 687 GATE(CLK_SCLK_UART1_PERIC, "sclk_uart1_peric", "div_sclk_uart1", 688 ENABLE_SCLK_TOP_PERIC, 4, CLK_SET_RATE_PARENT | 689 CLK_IGNORE_UNUSED, 0), 690 GATE(CLK_SCLK_UART0_PERIC, "sclk_uart0_peric", "div_sclk_uart0", 691 ENABLE_SCLK_TOP_PERIC, 3, CLK_SET_RATE_PARENT | 692 CLK_IGNORE_UNUSED, 0), 693 GATE(CLK_SCLK_SPI2_PERIC, "sclk_spi2_peric", "div_sclk_spi2_b", 694 ENABLE_SCLK_TOP_PERIC, 2, CLK_SET_RATE_PARENT, 0), 695 GATE(CLK_SCLK_SPI1_PERIC, "sclk_spi1_peric", "div_sclk_spi1_b", 696 ENABLE_SCLK_TOP_PERIC, 1, CLK_SET_RATE_PARENT, 0), 697 GATE(CLK_SCLK_SPI0_PERIC, "sclk_spi0_peric", "div_sclk_spi0_b", 698 ENABLE_SCLK_TOP_PERIC, 0, CLK_SET_RATE_PARENT, 0), 699 700 /* MUX_ENABLE_TOP_PERIC1 */ 701 GATE(CLK_SCLK_SLIMBUS, "sclk_slimbus", "mout_sclk_slimbus", 702 MUX_ENABLE_TOP_PERIC1, 16, 0, 0), 703 GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_sclk_audio1", 704 MUX_ENABLE_TOP_PERIC1, 4, 0, 0), 705 GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_sclk_audio0", 706 MUX_ENABLE_TOP_PERIC1, 0, 0, 0), 707 }; 708 709 /* 710 * ATLAS_PLL & APOLLO_PLL & MEM0_PLL & MEM1_PLL & BUS_PLL & MFC_PLL 711 * & MPHY_PLL & G3D_PLL & DISP_PLL & ISP_PLL 712 */ 713 static const struct samsung_pll_rate_table exynos5433_pll_rates[] __initconst = { 714 PLL_35XX_RATE(24 * MHZ, 2500000000U, 625, 6, 0), 715 PLL_35XX_RATE(24 * MHZ, 2400000000U, 500, 5, 0), 716 PLL_35XX_RATE(24 * MHZ, 2300000000U, 575, 6, 0), 717 PLL_35XX_RATE(24 * MHZ, 2200000000U, 550, 6, 0), 718 PLL_35XX_RATE(24 * MHZ, 2100000000U, 350, 4, 0), 719 PLL_35XX_RATE(24 * MHZ, 2000000000U, 500, 6, 0), 720 PLL_35XX_RATE(24 * MHZ, 1900000000U, 475, 6, 0), 721 PLL_35XX_RATE(24 * MHZ, 1800000000U, 375, 5, 0), 722 PLL_35XX_RATE(24 * MHZ, 1700000000U, 425, 6, 0), 723 PLL_35XX_RATE(24 * MHZ, 1600000000U, 400, 6, 0), 724 PLL_35XX_RATE(24 * MHZ, 1500000000U, 250, 4, 0), 725 PLL_35XX_RATE(24 * MHZ, 1400000000U, 350, 6, 0), 726 PLL_35XX_RATE(24 * MHZ, 1332000000U, 222, 4, 0), 727 PLL_35XX_RATE(24 * MHZ, 1300000000U, 325, 6, 0), 728 PLL_35XX_RATE(24 * MHZ, 1200000000U, 500, 5, 1), 729 PLL_35XX_RATE(24 * MHZ, 1100000000U, 550, 6, 1), 730 PLL_35XX_RATE(24 * MHZ, 1086000000U, 362, 4, 1), 731 PLL_35XX_RATE(24 * MHZ, 1066000000U, 533, 6, 1), 732 PLL_35XX_RATE(24 * MHZ, 1000000000U, 500, 6, 1), 733 PLL_35XX_RATE(24 * MHZ, 933000000U, 311, 4, 1), 734 PLL_35XX_RATE(24 * MHZ, 921000000U, 307, 4, 1), 735 PLL_35XX_RATE(24 * MHZ, 900000000U, 375, 5, 1), 736 PLL_35XX_RATE(24 * MHZ, 825000000U, 275, 4, 1), 737 PLL_35XX_RATE(24 * MHZ, 800000000U, 400, 6, 1), 738 PLL_35XX_RATE(24 * MHZ, 733000000U, 733, 12, 1), 739 PLL_35XX_RATE(24 * MHZ, 700000000U, 175, 3, 1), 740 PLL_35XX_RATE(24 * MHZ, 666000000U, 222, 4, 1), 741 PLL_35XX_RATE(24 * MHZ, 633000000U, 211, 4, 1), 742 PLL_35XX_RATE(24 * MHZ, 600000000U, 500, 5, 2), 743 PLL_35XX_RATE(24 * MHZ, 552000000U, 460, 5, 2), 744 PLL_35XX_RATE(24 * MHZ, 550000000U, 550, 6, 2), 745 PLL_35XX_RATE(24 * MHZ, 543000000U, 362, 4, 2), 746 PLL_35XX_RATE(24 * MHZ, 533000000U, 533, 6, 2), 747 PLL_35XX_RATE(24 * MHZ, 500000000U, 500, 6, 2), 748 PLL_35XX_RATE(24 * MHZ, 444000000U, 370, 5, 2), 749 PLL_35XX_RATE(24 * MHZ, 420000000U, 350, 5, 2), 750 PLL_35XX_RATE(24 * MHZ, 400000000U, 400, 6, 2), 751 PLL_35XX_RATE(24 * MHZ, 350000000U, 350, 6, 2), 752 PLL_35XX_RATE(24 * MHZ, 333000000U, 222, 4, 2), 753 PLL_35XX_RATE(24 * MHZ, 300000000U, 500, 5, 3), 754 PLL_35XX_RATE(24 * MHZ, 278000000U, 556, 6, 3), 755 PLL_35XX_RATE(24 * MHZ, 266000000U, 532, 6, 3), 756 PLL_35XX_RATE(24 * MHZ, 250000000U, 500, 6, 3), 757 PLL_35XX_RATE(24 * MHZ, 200000000U, 400, 6, 3), 758 PLL_35XX_RATE(24 * MHZ, 166000000U, 332, 6, 3), 759 PLL_35XX_RATE(24 * MHZ, 160000000U, 320, 6, 3), 760 PLL_35XX_RATE(24 * MHZ, 133000000U, 532, 6, 4), 761 PLL_35XX_RATE(24 * MHZ, 100000000U, 400, 6, 4), 762 { /* sentinel */ } 763 }; 764 765 /* AUD_PLL */ 766 static const struct samsung_pll_rate_table exynos5433_aud_pll_rates[] __initconst = { 767 PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0), 768 PLL_36XX_RATE(24 * MHZ, 393216003U, 197, 3, 2, -25690), 769 PLL_36XX_RATE(24 * MHZ, 384000000U, 128, 2, 2, 0), 770 PLL_36XX_RATE(24 * MHZ, 368639991U, 246, 4, 2, -15729), 771 PLL_36XX_RATE(24 * MHZ, 361507202U, 181, 3, 2, -16148), 772 PLL_36XX_RATE(24 * MHZ, 338687988U, 113, 2, 2, -6816), 773 PLL_36XX_RATE(24 * MHZ, 294912002U, 98, 1, 3, 19923), 774 PLL_36XX_RATE(24 * MHZ, 288000000U, 96, 1, 3, 0), 775 PLL_36XX_RATE(24 * MHZ, 252000000U, 84, 1, 3, 0), 776 PLL_36XX_RATE(24 * MHZ, 196608001U, 197, 3, 3, -25690), 777 { /* sentinel */ } 778 }; 779 780 static const struct samsung_pll_clock top_pll_clks[] __initconst = { 781 PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "oscclk", 782 ISP_PLL_LOCK, ISP_PLL_CON0, exynos5433_pll_rates), 783 PLL(pll_36xx, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk", 784 AUD_PLL_LOCK, AUD_PLL_CON0, exynos5433_aud_pll_rates), 785 }; 786 787 static const struct samsung_cmu_info top_cmu_info __initconst = { 788 .pll_clks = top_pll_clks, 789 .nr_pll_clks = ARRAY_SIZE(top_pll_clks), 790 .mux_clks = top_mux_clks, 791 .nr_mux_clks = ARRAY_SIZE(top_mux_clks), 792 .div_clks = top_div_clks, 793 .nr_div_clks = ARRAY_SIZE(top_div_clks), 794 .gate_clks = top_gate_clks, 795 .nr_gate_clks = ARRAY_SIZE(top_gate_clks), 796 .fixed_clks = top_fixed_clks, 797 .nr_fixed_clks = ARRAY_SIZE(top_fixed_clks), 798 .fixed_factor_clks = top_fixed_factor_clks, 799 .nr_fixed_factor_clks = ARRAY_SIZE(top_fixed_factor_clks), 800 .nr_clk_ids = TOP_NR_CLK, 801 .clk_regs = top_clk_regs, 802 .nr_clk_regs = ARRAY_SIZE(top_clk_regs), 803 .suspend_regs = top_suspend_regs, 804 .nr_suspend_regs = ARRAY_SIZE(top_suspend_regs), 805 }; 806 807 static void __init exynos5433_cmu_top_init(struct device_node *np) 808 { 809 samsung_cmu_register_one(np, &top_cmu_info); 810 } 811 CLK_OF_DECLARE(exynos5433_cmu_top, "samsung,exynos5433-cmu-top", 812 exynos5433_cmu_top_init); 813 814 /* 815 * Register offset definitions for CMU_CPIF 816 */ 817 #define MPHY_PLL_LOCK 0x0000 818 #define MPHY_PLL_CON0 0x0100 819 #define MPHY_PLL_CON1 0x0104 820 #define MPHY_PLL_FREQ_DET 0x010c 821 #define MUX_SEL_CPIF0 0x0200 822 #define DIV_CPIF 0x0600 823 #define ENABLE_SCLK_CPIF 0x0a00 824 825 static const unsigned long cpif_clk_regs[] __initconst = { 826 MPHY_PLL_LOCK, 827 MPHY_PLL_CON0, 828 MPHY_PLL_CON1, 829 MPHY_PLL_FREQ_DET, 830 MUX_SEL_CPIF0, 831 DIV_CPIF, 832 ENABLE_SCLK_CPIF, 833 }; 834 835 static const struct samsung_clk_reg_dump cpif_suspend_regs[] = { 836 /* force all sclk clocks enabled */ 837 { ENABLE_SCLK_CPIF, 0x3ff }, 838 /* MPHY PLL has to be enabled for suspend: reset value + ENABLE bit */ 839 { MPHY_PLL_CON0, 0x81c70601 }, 840 }; 841 842 /* list of all parent clock list */ 843 PNAME(mout_mphy_pll_p) = { "oscclk", "fout_mphy_pll", }; 844 845 static const struct samsung_pll_clock cpif_pll_clks[] __initconst = { 846 PLL(pll_35xx, CLK_FOUT_MPHY_PLL, "fout_mphy_pll", "oscclk", 847 MPHY_PLL_LOCK, MPHY_PLL_CON0, exynos5433_pll_rates), 848 }; 849 850 static const struct samsung_mux_clock cpif_mux_clks[] __initconst = { 851 /* MUX_SEL_CPIF0 */ 852 MUX(CLK_MOUT_MPHY_PLL, "mout_mphy_pll", mout_mphy_pll_p, MUX_SEL_CPIF0, 853 0, 1), 854 }; 855 856 static const struct samsung_div_clock cpif_div_clks[] __initconst = { 857 /* DIV_CPIF */ 858 DIV(CLK_DIV_SCLK_MPHY, "div_sclk_mphy", "mout_mphy_pll", DIV_CPIF, 859 0, 6), 860 }; 861 862 static const struct samsung_gate_clock cpif_gate_clks[] __initconst = { 863 /* ENABLE_SCLK_CPIF */ 864 GATE(CLK_SCLK_MPHY_PLL, "sclk_mphy_pll", "mout_mphy_pll", 865 ENABLE_SCLK_CPIF, 9, CLK_IGNORE_UNUSED, 0), 866 GATE(CLK_SCLK_UFS_MPHY, "sclk_ufs_mphy", "div_sclk_mphy", 867 ENABLE_SCLK_CPIF, 4, 0, 0), 868 }; 869 870 static const struct samsung_cmu_info cpif_cmu_info __initconst = { 871 .pll_clks = cpif_pll_clks, 872 .nr_pll_clks = ARRAY_SIZE(cpif_pll_clks), 873 .mux_clks = cpif_mux_clks, 874 .nr_mux_clks = ARRAY_SIZE(cpif_mux_clks), 875 .div_clks = cpif_div_clks, 876 .nr_div_clks = ARRAY_SIZE(cpif_div_clks), 877 .gate_clks = cpif_gate_clks, 878 .nr_gate_clks = ARRAY_SIZE(cpif_gate_clks), 879 .nr_clk_ids = CPIF_NR_CLK, 880 .clk_regs = cpif_clk_regs, 881 .nr_clk_regs = ARRAY_SIZE(cpif_clk_regs), 882 .suspend_regs = cpif_suspend_regs, 883 .nr_suspend_regs = ARRAY_SIZE(cpif_suspend_regs), 884 }; 885 886 static void __init exynos5433_cmu_cpif_init(struct device_node *np) 887 { 888 samsung_cmu_register_one(np, &cpif_cmu_info); 889 } 890 CLK_OF_DECLARE(exynos5433_cmu_cpif, "samsung,exynos5433-cmu-cpif", 891 exynos5433_cmu_cpif_init); 892 893 /* 894 * Register offset definitions for CMU_MIF 895 */ 896 #define MEM0_PLL_LOCK 0x0000 897 #define MEM1_PLL_LOCK 0x0004 898 #define BUS_PLL_LOCK 0x0008 899 #define MFC_PLL_LOCK 0x000c 900 #define MEM0_PLL_CON0 0x0100 901 #define MEM0_PLL_CON1 0x0104 902 #define MEM0_PLL_FREQ_DET 0x010c 903 #define MEM1_PLL_CON0 0x0110 904 #define MEM1_PLL_CON1 0x0114 905 #define MEM1_PLL_FREQ_DET 0x011c 906 #define BUS_PLL_CON0 0x0120 907 #define BUS_PLL_CON1 0x0124 908 #define BUS_PLL_FREQ_DET 0x012c 909 #define MFC_PLL_CON0 0x0130 910 #define MFC_PLL_CON1 0x0134 911 #define MFC_PLL_FREQ_DET 0x013c 912 #define MUX_SEL_MIF0 0x0200 913 #define MUX_SEL_MIF1 0x0204 914 #define MUX_SEL_MIF2 0x0208 915 #define MUX_SEL_MIF3 0x020c 916 #define MUX_SEL_MIF4 0x0210 917 #define MUX_SEL_MIF5 0x0214 918 #define MUX_SEL_MIF6 0x0218 919 #define MUX_SEL_MIF7 0x021c 920 #define MUX_ENABLE_MIF0 0x0300 921 #define MUX_ENABLE_MIF1 0x0304 922 #define MUX_ENABLE_MIF2 0x0308 923 #define MUX_ENABLE_MIF3 0x030c 924 #define MUX_ENABLE_MIF4 0x0310 925 #define MUX_ENABLE_MIF5 0x0314 926 #define MUX_ENABLE_MIF6 0x0318 927 #define MUX_ENABLE_MIF7 0x031c 928 #define MUX_STAT_MIF0 0x0400 929 #define MUX_STAT_MIF1 0x0404 930 #define MUX_STAT_MIF2 0x0408 931 #define MUX_STAT_MIF3 0x040c 932 #define MUX_STAT_MIF4 0x0410 933 #define MUX_STAT_MIF5 0x0414 934 #define MUX_STAT_MIF6 0x0418 935 #define MUX_STAT_MIF7 0x041c 936 #define DIV_MIF1 0x0604 937 #define DIV_MIF2 0x0608 938 #define DIV_MIF3 0x060c 939 #define DIV_MIF4 0x0610 940 #define DIV_MIF5 0x0614 941 #define DIV_MIF_PLL_FREQ_DET 0x0618 942 #define DIV_STAT_MIF1 0x0704 943 #define DIV_STAT_MIF2 0x0708 944 #define DIV_STAT_MIF3 0x070c 945 #define DIV_STAT_MIF4 0x0710 946 #define DIV_STAT_MIF5 0x0714 947 #define DIV_STAT_MIF_PLL_FREQ_DET 0x0718 948 #define ENABLE_ACLK_MIF0 0x0800 949 #define ENABLE_ACLK_MIF1 0x0804 950 #define ENABLE_ACLK_MIF2 0x0808 951 #define ENABLE_ACLK_MIF3 0x080c 952 #define ENABLE_PCLK_MIF 0x0900 953 #define ENABLE_PCLK_MIF_SECURE_DREX0_TZ 0x0904 954 #define ENABLE_PCLK_MIF_SECURE_DREX1_TZ 0x0908 955 #define ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT 0x090c 956 #define ENABLE_PCLK_MIF_SECURE_RTC 0x0910 957 #define ENABLE_SCLK_MIF 0x0a00 958 #define ENABLE_IP_MIF0 0x0b00 959 #define ENABLE_IP_MIF1 0x0b04 960 #define ENABLE_IP_MIF2 0x0b08 961 #define ENABLE_IP_MIF3 0x0b0c 962 #define ENABLE_IP_MIF_SECURE_DREX0_TZ 0x0b10 963 #define ENABLE_IP_MIF_SECURE_DREX1_TZ 0x0b14 964 #define ENABLE_IP_MIF_SECURE_MONOTONIC_CNT 0x0b18 965 #define ENABLE_IP_MIF_SECURE_RTC 0x0b1c 966 #define CLKOUT_CMU_MIF 0x0c00 967 #define CLKOUT_CMU_MIF_DIV_STAT 0x0c04 968 #define DREX_FREQ_CTRL0 0x1000 969 #define DREX_FREQ_CTRL1 0x1004 970 #define PAUSE 0x1008 971 #define DDRPHY_LOCK_CTRL 0x100c 972 973 static const unsigned long mif_clk_regs[] __initconst = { 974 MEM0_PLL_LOCK, 975 MEM1_PLL_LOCK, 976 BUS_PLL_LOCK, 977 MFC_PLL_LOCK, 978 MEM0_PLL_CON0, 979 MEM0_PLL_CON1, 980 MEM0_PLL_FREQ_DET, 981 MEM1_PLL_CON0, 982 MEM1_PLL_CON1, 983 MEM1_PLL_FREQ_DET, 984 BUS_PLL_CON0, 985 BUS_PLL_CON1, 986 BUS_PLL_FREQ_DET, 987 MFC_PLL_CON0, 988 MFC_PLL_CON1, 989 MFC_PLL_FREQ_DET, 990 MUX_SEL_MIF0, 991 MUX_SEL_MIF1, 992 MUX_SEL_MIF2, 993 MUX_SEL_MIF3, 994 MUX_SEL_MIF4, 995 MUX_SEL_MIF5, 996 MUX_SEL_MIF6, 997 MUX_SEL_MIF7, 998 MUX_ENABLE_MIF0, 999 MUX_ENABLE_MIF1, 1000 MUX_ENABLE_MIF2, 1001 MUX_ENABLE_MIF3, 1002 MUX_ENABLE_MIF4, 1003 MUX_ENABLE_MIF5, 1004 MUX_ENABLE_MIF6, 1005 MUX_ENABLE_MIF7, 1006 DIV_MIF1, 1007 DIV_MIF2, 1008 DIV_MIF3, 1009 DIV_MIF4, 1010 DIV_MIF5, 1011 DIV_MIF_PLL_FREQ_DET, 1012 ENABLE_ACLK_MIF0, 1013 ENABLE_ACLK_MIF1, 1014 ENABLE_ACLK_MIF2, 1015 ENABLE_ACLK_MIF3, 1016 ENABLE_PCLK_MIF, 1017 ENABLE_PCLK_MIF_SECURE_DREX0_TZ, 1018 ENABLE_PCLK_MIF_SECURE_DREX1_TZ, 1019 ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT, 1020 ENABLE_PCLK_MIF_SECURE_RTC, 1021 ENABLE_SCLK_MIF, 1022 ENABLE_IP_MIF0, 1023 ENABLE_IP_MIF1, 1024 ENABLE_IP_MIF2, 1025 ENABLE_IP_MIF3, 1026 ENABLE_IP_MIF_SECURE_DREX0_TZ, 1027 ENABLE_IP_MIF_SECURE_DREX1_TZ, 1028 ENABLE_IP_MIF_SECURE_MONOTONIC_CNT, 1029 ENABLE_IP_MIF_SECURE_RTC, 1030 CLKOUT_CMU_MIF, 1031 CLKOUT_CMU_MIF_DIV_STAT, 1032 DREX_FREQ_CTRL0, 1033 DREX_FREQ_CTRL1, 1034 PAUSE, 1035 DDRPHY_LOCK_CTRL, 1036 }; 1037 1038 static const struct samsung_pll_clock mif_pll_clks[] __initconst = { 1039 PLL(pll_35xx, CLK_FOUT_MEM0_PLL, "fout_mem0_pll", "oscclk", 1040 MEM0_PLL_LOCK, MEM0_PLL_CON0, exynos5433_pll_rates), 1041 PLL(pll_35xx, CLK_FOUT_MEM1_PLL, "fout_mem1_pll", "oscclk", 1042 MEM1_PLL_LOCK, MEM1_PLL_CON0, exynos5433_pll_rates), 1043 PLL(pll_35xx, CLK_FOUT_BUS_PLL, "fout_bus_pll", "oscclk", 1044 BUS_PLL_LOCK, BUS_PLL_CON0, exynos5433_pll_rates), 1045 PLL(pll_35xx, CLK_FOUT_MFC_PLL, "fout_mfc_pll", "oscclk", 1046 MFC_PLL_LOCK, MFC_PLL_CON0, exynos5433_pll_rates), 1047 }; 1048 1049 /* list of all parent clock list */ 1050 PNAME(mout_mfc_pll_div2_p) = { "mout_mfc_pll", "dout_mfc_pll", }; 1051 PNAME(mout_bus_pll_div2_p) = { "mout_bus_pll", "dout_bus_pll", }; 1052 PNAME(mout_mem1_pll_div2_p) = { "mout_mem1_pll", "dout_mem1_pll", }; 1053 PNAME(mout_mem0_pll_div2_p) = { "mout_mem0_pll", "dout_mem0_pll", }; 1054 PNAME(mout_mfc_pll_p) = { "oscclk", "fout_mfc_pll", }; 1055 PNAME(mout_bus_pll_p) = { "oscclk", "fout_bus_pll", }; 1056 PNAME(mout_mem1_pll_p) = { "oscclk", "fout_mem1_pll", }; 1057 PNAME(mout_mem0_pll_p) = { "oscclk", "fout_mem0_pll", }; 1058 1059 PNAME(mout_clk2x_phy_c_p) = { "mout_mem0_pll_div2", "mout_clkm_phy_b", }; 1060 PNAME(mout_clk2x_phy_b_p) = { "mout_bus_pll_div2", "mout_clkm_phy_a", }; 1061 PNAME(mout_clk2x_phy_a_p) = { "mout_bus_pll_div2", "mout_mfc_pll_div2", }; 1062 PNAME(mout_clkm_phy_b_p) = { "mout_mem1_pll_div2", "mout_clkm_phy_a", }; 1063 1064 PNAME(mout_aclk_mifnm_200_p) = { "mout_mem0_pll_div2", "div_mif_pre", }; 1065 PNAME(mout_aclk_mifnm_400_p) = { "mout_mem1_pll_div2", "mout_bus_pll_div2",}; 1066 1067 PNAME(mout_aclk_disp_333_b_p) = { "mout_aclk_disp_333_a", 1068 "mout_bus_pll_div2", }; 1069 PNAME(mout_aclk_disp_333_a_p) = { "mout_mfc_pll_div2", "sclk_mphy_pll", }; 1070 1071 PNAME(mout_sclk_decon_vclk_c_p) = { "mout_sclk_decon_vclk_b", 1072 "sclk_mphy_pll", }; 1073 PNAME(mout_sclk_decon_vclk_b_p) = { "mout_sclk_decon_vclk_a", 1074 "mout_mfc_pll_div2", }; 1075 PNAME(mout_sclk_decon_p) = { "oscclk", "mout_bus_pll_div2", }; 1076 PNAME(mout_sclk_decon_eclk_c_p) = { "mout_sclk_decon_eclk_b", 1077 "sclk_mphy_pll", }; 1078 PNAME(mout_sclk_decon_eclk_b_p) = { "mout_sclk_decon_eclk_a", 1079 "mout_mfc_pll_div2", }; 1080 1081 PNAME(mout_sclk_decon_tv_eclk_c_p) = { "mout_sclk_decon_tv_eclk_b", 1082 "sclk_mphy_pll", }; 1083 PNAME(mout_sclk_decon_tv_eclk_b_p) = { "mout_sclk_decon_tv_eclk_a", 1084 "mout_mfc_pll_div2", }; 1085 PNAME(mout_sclk_dsd_c_p) = { "mout_sclk_dsd_b", "mout_bus_pll_div2", }; 1086 PNAME(mout_sclk_dsd_b_p) = { "mout_sclk_dsd_a", "sclk_mphy_pll", }; 1087 PNAME(mout_sclk_dsd_a_p) = { "oscclk", "mout_mfc_pll_div2", }; 1088 1089 PNAME(mout_sclk_dsim0_c_p) = { "mout_sclk_dsim0_b", "sclk_mphy_pll", }; 1090 PNAME(mout_sclk_dsim0_b_p) = { "mout_sclk_dsim0_a", "mout_mfc_pll_div2" }; 1091 1092 PNAME(mout_sclk_decon_tv_vclk_c_p) = { "mout_sclk_decon_tv_vclk_b", 1093 "sclk_mphy_pll", }; 1094 PNAME(mout_sclk_decon_tv_vclk_b_p) = { "mout_sclk_decon_tv_vclk_a", 1095 "mout_mfc_pll_div2", }; 1096 PNAME(mout_sclk_dsim1_c_p) = { "mout_sclk_dsim1_b", "sclk_mphy_pll", }; 1097 PNAME(mout_sclk_dsim1_b_p) = { "mout_sclk_dsim1_a", "mout_mfc_pll_div2",}; 1098 1099 static const struct samsung_fixed_factor_clock mif_fixed_factor_clks[] __initconst = { 1100 /* dout_{mfc|bus|mem1|mem0}_pll is half fixed rate from parent mux */ 1101 FFACTOR(CLK_DOUT_MFC_PLL, "dout_mfc_pll", "mout_mfc_pll", 1, 1, 0), 1102 FFACTOR(CLK_DOUT_BUS_PLL, "dout_bus_pll", "mout_bus_pll", 1, 1, 0), 1103 FFACTOR(CLK_DOUT_MEM1_PLL, "dout_mem1_pll", "mout_mem1_pll", 1, 1, 0), 1104 FFACTOR(CLK_DOUT_MEM0_PLL, "dout_mem0_pll", "mout_mem0_pll", 1, 1, 0), 1105 }; 1106 1107 static const struct samsung_mux_clock mif_mux_clks[] __initconst = { 1108 /* MUX_SEL_MIF0 */ 1109 MUX(CLK_MOUT_MFC_PLL_DIV2, "mout_mfc_pll_div2", mout_mfc_pll_div2_p, 1110 MUX_SEL_MIF0, 28, 1), 1111 MUX(CLK_MOUT_BUS_PLL_DIV2, "mout_bus_pll_div2", mout_bus_pll_div2_p, 1112 MUX_SEL_MIF0, 24, 1), 1113 MUX(CLK_MOUT_MEM1_PLL_DIV2, "mout_mem1_pll_div2", mout_mem1_pll_div2_p, 1114 MUX_SEL_MIF0, 20, 1), 1115 MUX(CLK_MOUT_MEM0_PLL_DIV2, "mout_mem0_pll_div2", mout_mem0_pll_div2_p, 1116 MUX_SEL_MIF0, 16, 1), 1117 MUX(CLK_MOUT_MFC_PLL, "mout_mfc_pll", mout_mfc_pll_p, MUX_SEL_MIF0, 1118 12, 1), 1119 MUX(CLK_MOUT_BUS_PLL, "mout_bus_pll", mout_bus_pll_p, MUX_SEL_MIF0, 1120 8, 1), 1121 MUX(CLK_MOUT_MEM1_PLL, "mout_mem1_pll", mout_mem1_pll_p, MUX_SEL_MIF0, 1122 4, 1), 1123 MUX(CLK_MOUT_MEM0_PLL, "mout_mem0_pll", mout_mem0_pll_p, MUX_SEL_MIF0, 1124 0, 1), 1125 1126 /* MUX_SEL_MIF1 */ 1127 MUX(CLK_MOUT_CLK2X_PHY_C, "mout_clk2x_phy_c", mout_clk2x_phy_c_p, 1128 MUX_SEL_MIF1, 24, 1), 1129 MUX(CLK_MOUT_CLK2X_PHY_B, "mout_clk2x_phy_b", mout_clk2x_phy_b_p, 1130 MUX_SEL_MIF1, 20, 1), 1131 MUX(CLK_MOUT_CLK2X_PHY_A, "mout_clk2x_phy_a", mout_clk2x_phy_a_p, 1132 MUX_SEL_MIF1, 16, 1), 1133 MUX(CLK_MOUT_CLKM_PHY_C, "mout_clkm_phy_c", mout_clk2x_phy_c_p, 1134 MUX_SEL_MIF1, 12, 1), 1135 MUX(CLK_MOUT_CLKM_PHY_B, "mout_clkm_phy_b", mout_clkm_phy_b_p, 1136 MUX_SEL_MIF1, 8, 1), 1137 MUX(CLK_MOUT_CLKM_PHY_A, "mout_clkm_phy_a", mout_clk2x_phy_a_p, 1138 MUX_SEL_MIF1, 4, 1), 1139 1140 /* MUX_SEL_MIF2 */ 1141 MUX(CLK_MOUT_ACLK_MIFNM_200, "mout_aclk_mifnm_200", 1142 mout_aclk_mifnm_200_p, MUX_SEL_MIF2, 8, 1), 1143 MUX(CLK_MOUT_ACLK_MIFNM_400, "mout_aclk_mifnm_400", 1144 mout_aclk_mifnm_400_p, MUX_SEL_MIF2, 0, 1), 1145 1146 /* MUX_SEL_MIF3 */ 1147 MUX(CLK_MOUT_ACLK_DISP_333_B, "mout_aclk_disp_333_b", 1148 mout_aclk_disp_333_b_p, MUX_SEL_MIF3, 4, 1), 1149 MUX(CLK_MOUT_ACLK_DISP_333_A, "mout_aclk_disp_333_a", 1150 mout_aclk_disp_333_a_p, MUX_SEL_MIF3, 0, 1), 1151 1152 /* MUX_SEL_MIF4 */ 1153 MUX(CLK_MOUT_SCLK_DECON_VCLK_C, "mout_sclk_decon_vclk_c", 1154 mout_sclk_decon_vclk_c_p, MUX_SEL_MIF4, 24, 1), 1155 MUX(CLK_MOUT_SCLK_DECON_VCLK_B, "mout_sclk_decon_vclk_b", 1156 mout_sclk_decon_vclk_b_p, MUX_SEL_MIF4, 20, 1), 1157 MUX(CLK_MOUT_SCLK_DECON_VCLK_A, "mout_sclk_decon_vclk_a", 1158 mout_sclk_decon_p, MUX_SEL_MIF4, 16, 1), 1159 MUX(CLK_MOUT_SCLK_DECON_ECLK_C, "mout_sclk_decon_eclk_c", 1160 mout_sclk_decon_eclk_c_p, MUX_SEL_MIF4, 8, 1), 1161 MUX(CLK_MOUT_SCLK_DECON_ECLK_B, "mout_sclk_decon_eclk_b", 1162 mout_sclk_decon_eclk_b_p, MUX_SEL_MIF4, 4, 1), 1163 MUX(CLK_MOUT_SCLK_DECON_ECLK_A, "mout_sclk_decon_eclk_a", 1164 mout_sclk_decon_p, MUX_SEL_MIF4, 0, 1), 1165 1166 /* MUX_SEL_MIF5 */ 1167 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_C, "mout_sclk_decon_tv_eclk_c", 1168 mout_sclk_decon_tv_eclk_c_p, MUX_SEL_MIF5, 24, 1), 1169 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_B, "mout_sclk_decon_tv_eclk_b", 1170 mout_sclk_decon_tv_eclk_b_p, MUX_SEL_MIF5, 20, 1), 1171 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_A, "mout_sclk_decon_tv_eclk_a", 1172 mout_sclk_decon_p, MUX_SEL_MIF5, 16, 1), 1173 MUX(CLK_MOUT_SCLK_DSD_C, "mout_sclk_dsd_c", mout_sclk_dsd_c_p, 1174 MUX_SEL_MIF5, 8, 1), 1175 MUX(CLK_MOUT_SCLK_DSD_B, "mout_sclk_dsd_b", mout_sclk_dsd_b_p, 1176 MUX_SEL_MIF5, 4, 1), 1177 MUX(CLK_MOUT_SCLK_DSD_A, "mout_sclk_dsd_a", mout_sclk_dsd_a_p, 1178 MUX_SEL_MIF5, 0, 1), 1179 1180 /* MUX_SEL_MIF6 */ 1181 MUX(CLK_MOUT_SCLK_DSIM0_C, "mout_sclk_dsim0_c", mout_sclk_dsim0_c_p, 1182 MUX_SEL_MIF6, 8, 1), 1183 MUX(CLK_MOUT_SCLK_DSIM0_B, "mout_sclk_dsim0_b", mout_sclk_dsim0_b_p, 1184 MUX_SEL_MIF6, 4, 1), 1185 MUX(CLK_MOUT_SCLK_DSIM0_A, "mout_sclk_dsim0_a", mout_sclk_decon_p, 1186 MUX_SEL_MIF6, 0, 1), 1187 1188 /* MUX_SEL_MIF7 */ 1189 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C, "mout_sclk_decon_tv_vclk_c", 1190 mout_sclk_decon_tv_vclk_c_p, MUX_SEL_MIF7, 24, 1), 1191 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B, "mout_sclk_decon_tv_vclk_b", 1192 mout_sclk_decon_tv_vclk_b_p, MUX_SEL_MIF7, 20, 1), 1193 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A, "mout_sclk_decon_tv_vclk_a", 1194 mout_sclk_decon_p, MUX_SEL_MIF7, 16, 1), 1195 MUX(CLK_MOUT_SCLK_DSIM1_C, "mout_sclk_dsim1_c", mout_sclk_dsim1_c_p, 1196 MUX_SEL_MIF7, 8, 1), 1197 MUX(CLK_MOUT_SCLK_DSIM1_B, "mout_sclk_dsim1_b", mout_sclk_dsim1_b_p, 1198 MUX_SEL_MIF7, 4, 1), 1199 MUX(CLK_MOUT_SCLK_DSIM1_A, "mout_sclk_dsim1_a", mout_sclk_decon_p, 1200 MUX_SEL_MIF7, 0, 1), 1201 }; 1202 1203 static const struct samsung_div_clock mif_div_clks[] __initconst = { 1204 /* DIV_MIF1 */ 1205 DIV(CLK_DIV_SCLK_HPM_MIF, "div_sclk_hpm_mif", "div_clk2x_phy", 1206 DIV_MIF1, 16, 2), 1207 DIV(CLK_DIV_ACLK_DREX1, "div_aclk_drex1", "div_clk2x_phy", DIV_MIF1, 1208 12, 2), 1209 DIV(CLK_DIV_ACLK_DREX0, "div_aclk_drex0", "div_clk2x_phy", DIV_MIF1, 1210 8, 2), 1211 DIV(CLK_DIV_CLK2XPHY, "div_clk2x_phy", "mout_clk2x_phy_c", DIV_MIF1, 1212 4, 4), 1213 1214 /* DIV_MIF2 */ 1215 DIV(CLK_DIV_ACLK_MIF_266, "div_aclk_mif_266", "mout_bus_pll_div2", 1216 DIV_MIF2, 20, 3), 1217 DIV(CLK_DIV_ACLK_MIFND_133, "div_aclk_mifnd_133", "div_mif_pre", 1218 DIV_MIF2, 16, 4), 1219 DIV(CLK_DIV_ACLK_MIF_133, "div_aclk_mif_133", "div_mif_pre", 1220 DIV_MIF2, 12, 4), 1221 DIV(CLK_DIV_ACLK_MIFNM_200, "div_aclk_mifnm_200", 1222 "mout_aclk_mifnm_200", DIV_MIF2, 8, 3), 1223 DIV(CLK_DIV_ACLK_MIF_200, "div_aclk_mif_200", "div_aclk_mif_400", 1224 DIV_MIF2, 4, 2), 1225 DIV(CLK_DIV_ACLK_MIF_400, "div_aclk_mif_400", "mout_aclk_mifnm_400", 1226 DIV_MIF2, 0, 3), 1227 1228 /* DIV_MIF3 */ 1229 DIV(CLK_DIV_ACLK_BUS2_400, "div_aclk_bus2_400", "div_mif_pre", 1230 DIV_MIF3, 16, 4), 1231 DIV(CLK_DIV_ACLK_DISP_333, "div_aclk_disp_333", "mout_aclk_disp_333_b", 1232 DIV_MIF3, 4, 3), 1233 DIV(CLK_DIV_ACLK_CPIF_200, "div_aclk_cpif_200", "mout_aclk_mifnm_200", 1234 DIV_MIF3, 0, 3), 1235 1236 /* DIV_MIF4 */ 1237 DIV(CLK_DIV_SCLK_DSIM1, "div_sclk_dsim1", "mout_sclk_dsim1_c", 1238 DIV_MIF4, 24, 4), 1239 DIV(CLK_DIV_SCLK_DECON_TV_VCLK, "div_sclk_decon_tv_vclk", 1240 "mout_sclk_decon_tv_vclk_c", DIV_MIF4, 20, 4), 1241 DIV(CLK_DIV_SCLK_DSIM0, "div_sclk_dsim0", "mout_sclk_dsim0_c", 1242 DIV_MIF4, 16, 4), 1243 DIV(CLK_DIV_SCLK_DSD, "div_sclk_dsd", "mout_sclk_dsd_c", 1244 DIV_MIF4, 12, 4), 1245 DIV(CLK_DIV_SCLK_DECON_TV_ECLK, "div_sclk_decon_tv_eclk", 1246 "mout_sclk_decon_tv_eclk_c", DIV_MIF4, 8, 4), 1247 DIV(CLK_DIV_SCLK_DECON_VCLK, "div_sclk_decon_vclk", 1248 "mout_sclk_decon_vclk_c", DIV_MIF4, 4, 4), 1249 DIV(CLK_DIV_SCLK_DECON_ECLK, "div_sclk_decon_eclk", 1250 "mout_sclk_decon_eclk_c", DIV_MIF4, 0, 4), 1251 1252 /* DIV_MIF5 */ 1253 DIV(CLK_DIV_MIF_PRE, "div_mif_pre", "mout_bus_pll_div2", DIV_MIF5, 1254 0, 3), 1255 }; 1256 1257 static const struct samsung_gate_clock mif_gate_clks[] __initconst = { 1258 /* ENABLE_ACLK_MIF0 */ 1259 GATE(CLK_CLK2X_PHY1, "clk2k_phy1", "div_clk2x_phy", ENABLE_ACLK_MIF0, 1260 19, CLK_IGNORE_UNUSED, 0), 1261 GATE(CLK_CLK2X_PHY0, "clk2x_phy0", "div_clk2x_phy", ENABLE_ACLK_MIF0, 1262 18, CLK_IGNORE_UNUSED, 0), 1263 GATE(CLK_CLKM_PHY1, "clkm_phy1", "mout_clkm_phy_c", ENABLE_ACLK_MIF0, 1264 17, CLK_IGNORE_UNUSED, 0), 1265 GATE(CLK_CLKM_PHY0, "clkm_phy0", "mout_clkm_phy_c", ENABLE_ACLK_MIF0, 1266 16, CLK_IGNORE_UNUSED, 0), 1267 GATE(CLK_RCLK_DREX1, "rclk_drex1", "oscclk", ENABLE_ACLK_MIF0, 1268 15, CLK_IGNORE_UNUSED, 0), 1269 GATE(CLK_RCLK_DREX0, "rclk_drex0", "oscclk", ENABLE_ACLK_MIF0, 1270 14, CLK_IGNORE_UNUSED, 0), 1271 GATE(CLK_ACLK_DREX1_TZ, "aclk_drex1_tz", "div_aclk_drex1", 1272 ENABLE_ACLK_MIF0, 13, CLK_IGNORE_UNUSED, 0), 1273 GATE(CLK_ACLK_DREX0_TZ, "aclk_drex0_tz", "div_aclk_drex0", 1274 ENABLE_ACLK_MIF0, 12, CLK_IGNORE_UNUSED, 0), 1275 GATE(CLK_ACLK_DREX1_PEREV, "aclk_drex1_perev", "div_aclk_drex1", 1276 ENABLE_ACLK_MIF0, 11, CLK_IGNORE_UNUSED, 0), 1277 GATE(CLK_ACLK_DREX0_PEREV, "aclk_drex0_perev", "div_aclk_drex0", 1278 ENABLE_ACLK_MIF0, 10, CLK_IGNORE_UNUSED, 0), 1279 GATE(CLK_ACLK_DREX1_MEMIF, "aclk_drex1_memif", "div_aclk_drex1", 1280 ENABLE_ACLK_MIF0, 9, CLK_IGNORE_UNUSED, 0), 1281 GATE(CLK_ACLK_DREX0_MEMIF, "aclk_drex0_memif", "div_aclk_drex0", 1282 ENABLE_ACLK_MIF0, 8, CLK_IGNORE_UNUSED, 0), 1283 GATE(CLK_ACLK_DREX1_SCH, "aclk_drex1_sch", "div_aclk_drex1", 1284 ENABLE_ACLK_MIF0, 7, CLK_IGNORE_UNUSED, 0), 1285 GATE(CLK_ACLK_DREX0_SCH, "aclk_drex0_sch", "div_aclk_drex0", 1286 ENABLE_ACLK_MIF0, 6, CLK_IGNORE_UNUSED, 0), 1287 GATE(CLK_ACLK_DREX1_BUSIF, "aclk_drex1_busif", "div_aclk_drex1", 1288 ENABLE_ACLK_MIF0, 5, CLK_IGNORE_UNUSED, 0), 1289 GATE(CLK_ACLK_DREX0_BUSIF, "aclk_drex0_busif", "div_aclk_drex0", 1290 ENABLE_ACLK_MIF0, 4, CLK_IGNORE_UNUSED, 0), 1291 GATE(CLK_ACLK_DREX1_BUSIF_RD, "aclk_drex1_busif_rd", "div_aclk_drex1", 1292 ENABLE_ACLK_MIF0, 3, CLK_IGNORE_UNUSED, 0), 1293 GATE(CLK_ACLK_DREX0_BUSIF_RD, "aclk_drex0_busif_rd", "div_aclk_drex0", 1294 ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0), 1295 GATE(CLK_ACLK_DREX1, "aclk_drex1", "div_aclk_drex1", 1296 ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0), 1297 GATE(CLK_ACLK_DREX0, "aclk_drex0", "div_aclk_drex0", 1298 ENABLE_ACLK_MIF0, 1, CLK_IGNORE_UNUSED, 0), 1299 1300 /* ENABLE_ACLK_MIF1 */ 1301 GATE(CLK_ACLK_ASYNCAXIS_MIF_IMEM, "aclk_asyncaxis_mif_imem", 1302 "div_aclk_mif_200", ENABLE_ACLK_MIF1, 28, 1303 CLK_IGNORE_UNUSED, 0), 1304 GATE(CLK_ACLK_ASYNCAXIS_NOC_P_CCI, "aclk_asyncaxis_noc_p_cci", 1305 "div_aclk_mif_200", ENABLE_ACLK_MIF1, 1306 27, CLK_IGNORE_UNUSED, 0), 1307 GATE(CLK_ACLK_ASYNCAXIM_NOC_P_CCI, "aclk_asyncaxim_noc_p_cci", 1308 "div_aclk_mif_133", ENABLE_ACLK_MIF1, 1309 26, CLK_IGNORE_UNUSED, 0), 1310 GATE(CLK_ACLK_ASYNCAXIS_CP1, "aclk_asyncaxis_cp1", 1311 "div_aclk_mifnm_200", ENABLE_ACLK_MIF1, 1312 25, CLK_IGNORE_UNUSED, 0), 1313 GATE(CLK_ACLK_ASYNCAXIM_CP1, "aclk_asyncaxim_cp1", 1314 "div_aclk_drex1", ENABLE_ACLK_MIF1, 1315 24, CLK_IGNORE_UNUSED, 0), 1316 GATE(CLK_ACLK_ASYNCAXIS_CP0, "aclk_asyncaxis_cp0", 1317 "div_aclk_mifnm_200", ENABLE_ACLK_MIF1, 1318 23, CLK_IGNORE_UNUSED, 0), 1319 GATE(CLK_ACLK_ASYNCAXIM_CP0, "aclk_asyncaxim_cp0", 1320 "div_aclk_drex0", ENABLE_ACLK_MIF1, 1321 22, CLK_IGNORE_UNUSED, 0), 1322 GATE(CLK_ACLK_ASYNCAXIS_DREX1_3, "aclk_asyncaxis_drex1_3", 1323 "div_aclk_mif_133", ENABLE_ACLK_MIF1, 1324 21, CLK_IGNORE_UNUSED, 0), 1325 GATE(CLK_ACLK_ASYNCAXIM_DREX1_3, "aclk_asyncaxim_drex1_3", 1326 "div_aclk_drex1", ENABLE_ACLK_MIF1, 1327 20, CLK_IGNORE_UNUSED, 0), 1328 GATE(CLK_ACLK_ASYNCAXIS_DREX1_1, "aclk_asyncaxis_drex1_1", 1329 "div_aclk_mif_133", ENABLE_ACLK_MIF1, 1330 19, CLK_IGNORE_UNUSED, 0), 1331 GATE(CLK_ACLK_ASYNCAXIM_DREX1_1, "aclk_asyncaxim_drex1_1", 1332 "div_aclk_drex1", ENABLE_ACLK_MIF1, 1333 18, CLK_IGNORE_UNUSED, 0), 1334 GATE(CLK_ACLK_ASYNCAXIS_DREX1_0, "aclk_asyncaxis_drex1_0", 1335 "div_aclk_mif_133", ENABLE_ACLK_MIF1, 1336 17, CLK_IGNORE_UNUSED, 0), 1337 GATE(CLK_ACLK_ASYNCAXIM_DREX1_0, "aclk_asyncaxim_drex1_0", 1338 "div_aclk_drex1", ENABLE_ACLK_MIF1, 1339 16, CLK_IGNORE_UNUSED, 0), 1340 GATE(CLK_ACLK_ASYNCAXIS_DREX0_3, "aclk_asyncaxis_drex0_3", 1341 "div_aclk_mif_133", ENABLE_ACLK_MIF1, 1342 15, CLK_IGNORE_UNUSED, 0), 1343 GATE(CLK_ACLK_ASYNCAXIM_DREX0_3, "aclk_asyncaxim_drex0_3", 1344 "div_aclk_drex0", ENABLE_ACLK_MIF1, 1345 14, CLK_IGNORE_UNUSED, 0), 1346 GATE(CLK_ACLK_ASYNCAXIS_DREX0_1, "aclk_asyncaxis_drex0_1", 1347 "div_aclk_mif_133", ENABLE_ACLK_MIF1, 1348 13, CLK_IGNORE_UNUSED, 0), 1349 GATE(CLK_ACLK_ASYNCAXIM_DREX0_1, "aclk_asyncaxim_drex0_1", 1350 "div_aclk_drex0", ENABLE_ACLK_MIF1, 1351 12, CLK_IGNORE_UNUSED, 0), 1352 GATE(CLK_ACLK_ASYNCAXIS_DREX0_0, "aclk_asyncaxis_drex0_0", 1353 "div_aclk_mif_133", ENABLE_ACLK_MIF1, 1354 11, CLK_IGNORE_UNUSED, 0), 1355 GATE(CLK_ACLK_ASYNCAXIM_DREX0_0, "aclk_asyncaxim_drex0_0", 1356 "div_aclk_drex0", ENABLE_ACLK_MIF1, 1357 10, CLK_IGNORE_UNUSED, 0), 1358 GATE(CLK_ACLK_AHB2APB_MIF2P, "aclk_ahb2apb_mif2p", "div_aclk_mif_133", 1359 ENABLE_ACLK_MIF1, 9, CLK_IGNORE_UNUSED, 0), 1360 GATE(CLK_ACLK_AHB2APB_MIF1P, "aclk_ahb2apb_mif1p", "div_aclk_mif_133", 1361 ENABLE_ACLK_MIF1, 8, CLK_IGNORE_UNUSED, 0), 1362 GATE(CLK_ACLK_AHB2APB_MIF0P, "aclk_ahb2apb_mif0p", "div_aclk_mif_133", 1363 ENABLE_ACLK_MIF1, 7, CLK_IGNORE_UNUSED, 0), 1364 GATE(CLK_ACLK_IXIU_CCI, "aclk_ixiu_cci", "div_aclk_mif_400", 1365 ENABLE_ACLK_MIF1, 6, CLK_IGNORE_UNUSED, 0), 1366 GATE(CLK_ACLK_XIU_MIFSFRX, "aclk_xiu_mifsfrx", "div_aclk_mif_200", 1367 ENABLE_ACLK_MIF1, 5, CLK_IGNORE_UNUSED, 0), 1368 GATE(CLK_ACLK_MIFNP_133, "aclk_mifnp_133", "div_aclk_mif_133", 1369 ENABLE_ACLK_MIF1, 4, CLK_IGNORE_UNUSED, 0), 1370 GATE(CLK_ACLK_MIFNM_200, "aclk_mifnm_200", "div_aclk_mifnm_200", 1371 ENABLE_ACLK_MIF1, 3, CLK_IGNORE_UNUSED, 0), 1372 GATE(CLK_ACLK_MIFND_133, "aclk_mifnd_133", "div_aclk_mifnd_133", 1373 ENABLE_ACLK_MIF1, 2, CLK_IGNORE_UNUSED, 0), 1374 GATE(CLK_ACLK_MIFND_400, "aclk_mifnd_400", "div_aclk_mif_400", 1375 ENABLE_ACLK_MIF1, 1, CLK_IGNORE_UNUSED, 0), 1376 GATE(CLK_ACLK_CCI, "aclk_cci", "div_aclk_mif_400", ENABLE_ACLK_MIF1, 1377 0, CLK_IGNORE_UNUSED, 0), 1378 1379 /* ENABLE_ACLK_MIF2 */ 1380 GATE(CLK_ACLK_MIFND_266, "aclk_mifnd_266", "div_aclk_mif_266", 1381 ENABLE_ACLK_MIF2, 20, CLK_IGNORE_UNUSED, 0), 1382 GATE(CLK_ACLK_PPMU_DREX1S3, "aclk_ppmu_drex1s3", "div_aclk_drex1", 1383 ENABLE_ACLK_MIF2, 17, CLK_IGNORE_UNUSED, 0), 1384 GATE(CLK_ACLK_PPMU_DREX1S1, "aclk_ppmu_drex1s1", "div_aclk_drex1", 1385 ENABLE_ACLK_MIF2, 16, CLK_IGNORE_UNUSED, 0), 1386 GATE(CLK_ACLK_PPMU_DREX1S0, "aclk_ppmu_drex1s0", "div_aclk_drex1", 1387 ENABLE_ACLK_MIF2, 15, CLK_IGNORE_UNUSED, 0), 1388 GATE(CLK_ACLK_PPMU_DREX0S3, "aclk_ppmu_drex0s3", "div_aclk_drex0", 1389 ENABLE_ACLK_MIF2, 14, CLK_IGNORE_UNUSED, 0), 1390 GATE(CLK_ACLK_PPMU_DREX0S1, "aclk_ppmu_drex0s1", "div_aclk_drex0", 1391 ENABLE_ACLK_MIF2, 13, CLK_IGNORE_UNUSED, 0), 1392 GATE(CLK_ACLK_PPMU_DREX0S0, "aclk_ppmu_drex0s0", "div_aclk_drex0", 1393 ENABLE_ACLK_MIF2, 12, CLK_IGNORE_UNUSED, 0), 1394 GATE(CLK_ACLK_AXIDS_CCI_MIFSFRX, "aclk_axids_cci_mifsfrx", 1395 "div_aclk_mif_200", ENABLE_ACLK_MIF2, 7, 1396 CLK_IGNORE_UNUSED, 0), 1397 GATE(CLK_ACLK_AXISYNCDNS_CCI, "aclk_axisyncdns_cci", 1398 "div_aclk_mif_400", ENABLE_ACLK_MIF2, 1399 5, CLK_IGNORE_UNUSED, 0), 1400 GATE(CLK_ACLK_AXISYNCDN_CCI, "aclk_axisyncdn_cci", "div_aclk_mif_400", 1401 ENABLE_ACLK_MIF2, 4, CLK_IGNORE_UNUSED, 0), 1402 GATE(CLK_ACLK_AXISYNCDN_NOC_D, "aclk_axisyncdn_noc_d", 1403 "div_aclk_mif_200", ENABLE_ACLK_MIF2, 1404 3, CLK_IGNORE_UNUSED, 0), 1405 GATE(CLK_ACLK_ASYNCAPBS_MIF_CSSYS, "aclk_asyncapbs_mif_cssys", 1406 "div_aclk_mifnd_133", ENABLE_ACLK_MIF2, 0, 0, 0), 1407 1408 /* ENABLE_ACLK_MIF3 */ 1409 GATE(CLK_ACLK_BUS2_400, "aclk_bus2_400", "div_aclk_bus2_400", 1410 ENABLE_ACLK_MIF3, 4, 1411 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), 1412 GATE(CLK_ACLK_DISP_333, "aclk_disp_333", "div_aclk_disp_333", 1413 ENABLE_ACLK_MIF3, 1, 1414 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), 1415 GATE(CLK_ACLK_CPIF_200, "aclk_cpif_200", "div_aclk_cpif_200", 1416 ENABLE_ACLK_MIF3, 0, 1417 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), 1418 1419 /* ENABLE_PCLK_MIF */ 1420 GATE(CLK_PCLK_PPMU_DREX1S3, "pclk_ppmu_drex1s3", "div_aclk_drex1", 1421 ENABLE_PCLK_MIF, 29, CLK_IGNORE_UNUSED, 0), 1422 GATE(CLK_PCLK_PPMU_DREX1S1, "pclk_ppmu_drex1s1", "div_aclk_drex1", 1423 ENABLE_PCLK_MIF, 28, CLK_IGNORE_UNUSED, 0), 1424 GATE(CLK_PCLK_PPMU_DREX1S0, "pclk_ppmu_drex1s0", "div_aclk_drex1", 1425 ENABLE_PCLK_MIF, 27, CLK_IGNORE_UNUSED, 0), 1426 GATE(CLK_PCLK_PPMU_DREX0S3, "pclk_ppmu_drex0s3", "div_aclk_drex0", 1427 ENABLE_PCLK_MIF, 26, CLK_IGNORE_UNUSED, 0), 1428 GATE(CLK_PCLK_PPMU_DREX0S1, "pclk_ppmu_drex0s1", "div_aclk_drex0", 1429 ENABLE_PCLK_MIF, 25, CLK_IGNORE_UNUSED, 0), 1430 GATE(CLK_PCLK_PPMU_DREX0S0, "pclk_ppmu_drex0s0", "div_aclk_drex0", 1431 ENABLE_PCLK_MIF, 24, CLK_IGNORE_UNUSED, 0), 1432 GATE(CLK_PCLK_ASYNCAXI_NOC_P_CCI, "pclk_asyncaxi_noc_p_cci", 1433 "div_aclk_mif_133", ENABLE_PCLK_MIF, 21, 1434 CLK_IGNORE_UNUSED, 0), 1435 GATE(CLK_PCLK_ASYNCAXI_CP1, "pclk_asyncaxi_cp1", "div_aclk_mif_133", 1436 ENABLE_PCLK_MIF, 19, 0, 0), 1437 GATE(CLK_PCLK_ASYNCAXI_CP0, "pclk_asyncaxi_cp0", "div_aclk_mif_133", 1438 ENABLE_PCLK_MIF, 18, 0, 0), 1439 GATE(CLK_PCLK_ASYNCAXI_DREX1_3, "pclk_asyncaxi_drex1_3", 1440 "div_aclk_mif_133", ENABLE_PCLK_MIF, 17, 0, 0), 1441 GATE(CLK_PCLK_ASYNCAXI_DREX1_1, "pclk_asyncaxi_drex1_1", 1442 "div_aclk_mif_133", ENABLE_PCLK_MIF, 16, 0, 0), 1443 GATE(CLK_PCLK_ASYNCAXI_DREX1_0, "pclk_asyncaxi_drex1_0", 1444 "div_aclk_mif_133", ENABLE_PCLK_MIF, 15, 0, 0), 1445 GATE(CLK_PCLK_ASYNCAXI_DREX0_3, "pclk_asyncaxi_drex0_3", 1446 "div_aclk_mif_133", ENABLE_PCLK_MIF, 14, 0, 0), 1447 GATE(CLK_PCLK_ASYNCAXI_DREX0_1, "pclk_asyncaxi_drex0_1", 1448 "div_aclk_mif_133", ENABLE_PCLK_MIF, 13, 0, 0), 1449 GATE(CLK_PCLK_ASYNCAXI_DREX0_0, "pclk_asyncaxi_drex0_0", 1450 "div_aclk_mif_133", ENABLE_PCLK_MIF, 12, 0, 0), 1451 GATE(CLK_PCLK_MIFSRVND_133, "pclk_mifsrvnd_133", "div_aclk_mif_133", 1452 ENABLE_PCLK_MIF, 11, 0, 0), 1453 GATE(CLK_PCLK_PMU_MIF, "pclk_pmu_mif", "div_aclk_mif_133", 1454 ENABLE_PCLK_MIF, 10, CLK_IGNORE_UNUSED, 0), 1455 GATE(CLK_PCLK_SYSREG_MIF, "pclk_sysreg_mif", "div_aclk_mif_133", 1456 ENABLE_PCLK_MIF, 9, CLK_IGNORE_UNUSED, 0), 1457 GATE(CLK_PCLK_GPIO_ALIVE, "pclk_gpio_alive", "div_aclk_mif_133", 1458 ENABLE_PCLK_MIF, 8, CLK_IGNORE_UNUSED, 0), 1459 GATE(CLK_PCLK_ABB, "pclk_abb", "div_aclk_mif_133", 1460 ENABLE_PCLK_MIF, 7, 0, 0), 1461 GATE(CLK_PCLK_PMU_APBIF, "pclk_pmu_apbif", "div_aclk_mif_133", 1462 ENABLE_PCLK_MIF, 6, CLK_IGNORE_UNUSED, 0), 1463 GATE(CLK_PCLK_DDR_PHY1, "pclk_ddr_phy1", "div_aclk_mif_133", 1464 ENABLE_PCLK_MIF, 5, 0, 0), 1465 GATE(CLK_PCLK_DREX1, "pclk_drex1", "div_aclk_mif_133", 1466 ENABLE_PCLK_MIF, 3, CLK_IGNORE_UNUSED, 0), 1467 GATE(CLK_PCLK_DDR_PHY0, "pclk_ddr_phy0", "div_aclk_mif_133", 1468 ENABLE_PCLK_MIF, 2, 0, 0), 1469 GATE(CLK_PCLK_DREX0, "pclk_drex0", "div_aclk_mif_133", 1470 ENABLE_PCLK_MIF, 0, CLK_IGNORE_UNUSED, 0), 1471 1472 /* ENABLE_PCLK_MIF_SECURE_DREX0_TZ */ 1473 GATE(CLK_PCLK_DREX0_TZ, "pclk_drex0_tz", "div_aclk_mif_133", 1474 ENABLE_PCLK_MIF_SECURE_DREX0_TZ, 0, 1475 CLK_IGNORE_UNUSED, 0), 1476 1477 /* ENABLE_PCLK_MIF_SECURE_DREX1_TZ */ 1478 GATE(CLK_PCLK_DREX1_TZ, "pclk_drex1_tz", "div_aclk_mif_133", 1479 ENABLE_PCLK_MIF_SECURE_DREX1_TZ, 0, 1480 CLK_IGNORE_UNUSED, 0), 1481 1482 /* ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT */ 1483 GATE(CLK_PCLK_MONOTONIC_CNT, "pclk_monotonic_cnt", "div_aclk_mif_133", 1484 ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT, 0, 0, 0), 1485 1486 /* ENABLE_PCLK_MIF_SECURE_RTC */ 1487 GATE(CLK_PCLK_RTC, "pclk_rtc", "div_aclk_mif_133", 1488 ENABLE_PCLK_MIF_SECURE_RTC, 0, 0, 0), 1489 1490 /* ENABLE_SCLK_MIF */ 1491 GATE(CLK_SCLK_DSIM1_DISP, "sclk_dsim1_disp", "div_sclk_dsim1", 1492 ENABLE_SCLK_MIF, 15, CLK_IGNORE_UNUSED, 0), 1493 GATE(CLK_SCLK_DECON_TV_VCLK_DISP, "sclk_decon_tv_vclk_disp", 1494 "div_sclk_decon_tv_vclk", ENABLE_SCLK_MIF, 1495 14, CLK_IGNORE_UNUSED, 0), 1496 GATE(CLK_SCLK_DSIM0_DISP, "sclk_dsim0_disp", "div_sclk_dsim0", 1497 ENABLE_SCLK_MIF, 9, CLK_IGNORE_UNUSED, 0), 1498 GATE(CLK_SCLK_DSD_DISP, "sclk_dsd_disp", "div_sclk_dsd", 1499 ENABLE_SCLK_MIF, 8, CLK_IGNORE_UNUSED, 0), 1500 GATE(CLK_SCLK_DECON_TV_ECLK_DISP, "sclk_decon_tv_eclk_disp", 1501 "div_sclk_decon_tv_eclk", ENABLE_SCLK_MIF, 1502 7, CLK_IGNORE_UNUSED, 0), 1503 GATE(CLK_SCLK_DECON_VCLK_DISP, "sclk_decon_vclk_disp", 1504 "div_sclk_decon_vclk", ENABLE_SCLK_MIF, 1505 6, CLK_IGNORE_UNUSED, 0), 1506 GATE(CLK_SCLK_DECON_ECLK_DISP, "sclk_decon_eclk_disp", 1507 "div_sclk_decon_eclk", ENABLE_SCLK_MIF, 1508 5, CLK_IGNORE_UNUSED, 0), 1509 GATE(CLK_SCLK_HPM_MIF, "sclk_hpm_mif", "div_sclk_hpm_mif", 1510 ENABLE_SCLK_MIF, 4, 1511 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), 1512 GATE(CLK_SCLK_MFC_PLL, "sclk_mfc_pll", "mout_mfc_pll_div2", 1513 ENABLE_SCLK_MIF, 3, CLK_IGNORE_UNUSED, 0), 1514 GATE(CLK_SCLK_BUS_PLL, "sclk_bus_pll", "mout_bus_pll_div2", 1515 ENABLE_SCLK_MIF, 2, CLK_IGNORE_UNUSED, 0), 1516 GATE(CLK_SCLK_BUS_PLL_APOLLO, "sclk_bus_pll_apollo", "sclk_bus_pll", 1517 ENABLE_SCLK_MIF, 1, CLK_IGNORE_UNUSED, 0), 1518 GATE(CLK_SCLK_BUS_PLL_ATLAS, "sclk_bus_pll_atlas", "sclk_bus_pll", 1519 ENABLE_SCLK_MIF, 0, CLK_IGNORE_UNUSED, 0), 1520 }; 1521 1522 static const struct samsung_cmu_info mif_cmu_info __initconst = { 1523 .pll_clks = mif_pll_clks, 1524 .nr_pll_clks = ARRAY_SIZE(mif_pll_clks), 1525 .mux_clks = mif_mux_clks, 1526 .nr_mux_clks = ARRAY_SIZE(mif_mux_clks), 1527 .div_clks = mif_div_clks, 1528 .nr_div_clks = ARRAY_SIZE(mif_div_clks), 1529 .gate_clks = mif_gate_clks, 1530 .nr_gate_clks = ARRAY_SIZE(mif_gate_clks), 1531 .fixed_factor_clks = mif_fixed_factor_clks, 1532 .nr_fixed_factor_clks = ARRAY_SIZE(mif_fixed_factor_clks), 1533 .nr_clk_ids = MIF_NR_CLK, 1534 .clk_regs = mif_clk_regs, 1535 .nr_clk_regs = ARRAY_SIZE(mif_clk_regs), 1536 }; 1537 1538 static void __init exynos5433_cmu_mif_init(struct device_node *np) 1539 { 1540 samsung_cmu_register_one(np, &mif_cmu_info); 1541 } 1542 CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif", 1543 exynos5433_cmu_mif_init); 1544 1545 /* 1546 * Register offset definitions for CMU_PERIC 1547 */ 1548 #define DIV_PERIC 0x0600 1549 #define DIV_STAT_PERIC 0x0700 1550 #define ENABLE_ACLK_PERIC 0x0800 1551 #define ENABLE_PCLK_PERIC0 0x0900 1552 #define ENABLE_PCLK_PERIC1 0x0904 1553 #define ENABLE_SCLK_PERIC 0x0A00 1554 #define ENABLE_IP_PERIC0 0x0B00 1555 #define ENABLE_IP_PERIC1 0x0B04 1556 #define ENABLE_IP_PERIC2 0x0B08 1557 1558 static const unsigned long peric_clk_regs[] __initconst = { 1559 DIV_PERIC, 1560 ENABLE_ACLK_PERIC, 1561 ENABLE_PCLK_PERIC0, 1562 ENABLE_PCLK_PERIC1, 1563 ENABLE_SCLK_PERIC, 1564 ENABLE_IP_PERIC0, 1565 ENABLE_IP_PERIC1, 1566 ENABLE_IP_PERIC2, 1567 }; 1568 1569 static const struct samsung_clk_reg_dump peric_suspend_regs[] = { 1570 /* pclk: sci, pmu, sysreg, gpio_{finger, ese, touch, nfc}, uart2-0 */ 1571 { ENABLE_PCLK_PERIC0, 0xe00ff000 }, 1572 /* sclk: uart2-0 */ 1573 { ENABLE_SCLK_PERIC, 0x7 }, 1574 }; 1575 1576 static const struct samsung_div_clock peric_div_clks[] __initconst = { 1577 /* DIV_PERIC */ 1578 DIV(CLK_DIV_SCLK_SCI, "div_sclk_sci", "oscclk", DIV_PERIC, 4, 4), 1579 DIV(CLK_DIV_SCLK_SC_IN, "div_sclk_sc_in", "oscclk", DIV_PERIC, 0, 4), 1580 }; 1581 1582 static const struct samsung_gate_clock peric_gate_clks[] __initconst = { 1583 /* ENABLE_ACLK_PERIC */ 1584 GATE(CLK_ACLK_AHB2APB_PERIC2P, "aclk_ahb2apb_peric2p", "aclk_peric_66", 1585 ENABLE_ACLK_PERIC, 3, CLK_IGNORE_UNUSED, 0), 1586 GATE(CLK_ACLK_AHB2APB_PERIC1P, "aclk_ahb2apb_peric1p", "aclk_peric_66", 1587 ENABLE_ACLK_PERIC, 2, CLK_IGNORE_UNUSED, 0), 1588 GATE(CLK_ACLK_AHB2APB_PERIC0P, "aclk_ahb2apb_peric0p", "aclk_peric_66", 1589 ENABLE_ACLK_PERIC, 1, CLK_IGNORE_UNUSED, 0), 1590 GATE(CLK_ACLK_PERICNP_66, "aclk_pericnp_66", "aclk_peric_66", 1591 ENABLE_ACLK_PERIC, 0, CLK_IGNORE_UNUSED, 0), 1592 1593 /* ENABLE_PCLK_PERIC0 */ 1594 GATE(CLK_PCLK_SCI, "pclk_sci", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1595 31, CLK_SET_RATE_PARENT, 0), 1596 GATE(CLK_PCLK_GPIO_FINGER, "pclk_gpio_finger", "aclk_peric_66", 1597 ENABLE_PCLK_PERIC0, 30, CLK_IGNORE_UNUSED, 0), 1598 GATE(CLK_PCLK_GPIO_ESE, "pclk_gpio_ese", "aclk_peric_66", 1599 ENABLE_PCLK_PERIC0, 29, CLK_IGNORE_UNUSED, 0), 1600 GATE(CLK_PCLK_PWM, "pclk_pwm", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1601 28, CLK_SET_RATE_PARENT, 0), 1602 GATE(CLK_PCLK_SPDIF, "pclk_spdif", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1603 26, CLK_SET_RATE_PARENT, 0), 1604 GATE(CLK_PCLK_PCM1, "pclk_pcm1", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1605 25, CLK_SET_RATE_PARENT, 0), 1606 GATE(CLK_PCLK_I2S1, "pclk_i2s", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1607 24, CLK_SET_RATE_PARENT, 0), 1608 GATE(CLK_PCLK_SPI2, "pclk_spi2", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1609 23, CLK_SET_RATE_PARENT, 0), 1610 GATE(CLK_PCLK_SPI1, "pclk_spi1", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1611 22, CLK_SET_RATE_PARENT, 0), 1612 GATE(CLK_PCLK_SPI0, "pclk_spi0", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1613 21, CLK_SET_RATE_PARENT, 0), 1614 GATE(CLK_PCLK_ADCIF, "pclk_adcif", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1615 20, CLK_SET_RATE_PARENT, 0), 1616 GATE(CLK_PCLK_GPIO_TOUCH, "pclk_gpio_touch", "aclk_peric_66", 1617 ENABLE_PCLK_PERIC0, 19, CLK_IGNORE_UNUSED, 0), 1618 GATE(CLK_PCLK_GPIO_NFC, "pclk_gpio_nfc", "aclk_peric_66", 1619 ENABLE_PCLK_PERIC0, 18, CLK_IGNORE_UNUSED, 0), 1620 GATE(CLK_PCLK_GPIO_PERIC, "pclk_gpio_peric", "aclk_peric_66", 1621 ENABLE_PCLK_PERIC0, 17, CLK_IGNORE_UNUSED, 0), 1622 GATE(CLK_PCLK_PMU_PERIC, "pclk_pmu_peric", "aclk_peric_66", 1623 ENABLE_PCLK_PERIC0, 16, CLK_SET_RATE_PARENT, 0), 1624 GATE(CLK_PCLK_SYSREG_PERIC, "pclk_sysreg_peric", "aclk_peric_66", 1625 ENABLE_PCLK_PERIC0, 15, 1626 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 1627 GATE(CLK_PCLK_UART2, "pclk_uart2", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1628 14, CLK_SET_RATE_PARENT, 0), 1629 GATE(CLK_PCLK_UART1, "pclk_uart1", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1630 13, CLK_SET_RATE_PARENT, 0), 1631 GATE(CLK_PCLK_UART0, "pclk_uart0", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1632 12, CLK_SET_RATE_PARENT, 0), 1633 GATE(CLK_PCLK_HSI2C3, "pclk_hsi2c3", "aclk_peric_66", 1634 ENABLE_PCLK_PERIC0, 11, CLK_SET_RATE_PARENT, 0), 1635 GATE(CLK_PCLK_HSI2C2, "pclk_hsi2c2", "aclk_peric_66", 1636 ENABLE_PCLK_PERIC0, 10, CLK_SET_RATE_PARENT, 0), 1637 GATE(CLK_PCLK_HSI2C1, "pclk_hsi2c1", "aclk_peric_66", 1638 ENABLE_PCLK_PERIC0, 9, CLK_SET_RATE_PARENT, 0), 1639 GATE(CLK_PCLK_HSI2C0, "pclk_hsi2c0", "aclk_peric_66", 1640 ENABLE_PCLK_PERIC0, 8, CLK_SET_RATE_PARENT, 0), 1641 GATE(CLK_PCLK_I2C7, "pclk_i2c7", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1642 7, CLK_SET_RATE_PARENT, 0), 1643 GATE(CLK_PCLK_I2C6, "pclk_i2c6", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1644 6, CLK_SET_RATE_PARENT, 0), 1645 GATE(CLK_PCLK_I2C5, "pclk_i2c5", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1646 5, CLK_SET_RATE_PARENT, 0), 1647 GATE(CLK_PCLK_I2C4, "pclk_i2c4", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1648 4, CLK_SET_RATE_PARENT, 0), 1649 GATE(CLK_PCLK_I2C3, "pclk_i2c3", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1650 3, CLK_SET_RATE_PARENT, 0), 1651 GATE(CLK_PCLK_I2C2, "pclk_i2c2", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1652 2, CLK_SET_RATE_PARENT, 0), 1653 GATE(CLK_PCLK_I2C1, "pclk_i2c1", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1654 1, CLK_SET_RATE_PARENT, 0), 1655 GATE(CLK_PCLK_I2C0, "pclk_i2c0", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1656 0, CLK_SET_RATE_PARENT, 0), 1657 1658 /* ENABLE_PCLK_PERIC1 */ 1659 GATE(CLK_PCLK_SPI4, "pclk_spi4", "aclk_peric_66", ENABLE_PCLK_PERIC1, 1660 9, CLK_SET_RATE_PARENT, 0), 1661 GATE(CLK_PCLK_SPI3, "pclk_spi3", "aclk_peric_66", ENABLE_PCLK_PERIC1, 1662 8, CLK_SET_RATE_PARENT, 0), 1663 GATE(CLK_PCLK_HSI2C11, "pclk_hsi2c11", "aclk_peric_66", 1664 ENABLE_PCLK_PERIC1, 7, CLK_SET_RATE_PARENT, 0), 1665 GATE(CLK_PCLK_HSI2C10, "pclk_hsi2c10", "aclk_peric_66", 1666 ENABLE_PCLK_PERIC1, 6, CLK_SET_RATE_PARENT, 0), 1667 GATE(CLK_PCLK_HSI2C9, "pclk_hsi2c9", "aclk_peric_66", 1668 ENABLE_PCLK_PERIC1, 5, CLK_SET_RATE_PARENT, 0), 1669 GATE(CLK_PCLK_HSI2C8, "pclk_hsi2c8", "aclk_peric_66", 1670 ENABLE_PCLK_PERIC1, 4, CLK_SET_RATE_PARENT, 0), 1671 GATE(CLK_PCLK_HSI2C7, "pclk_hsi2c7", "aclk_peric_66", 1672 ENABLE_PCLK_PERIC1, 3, CLK_SET_RATE_PARENT, 0), 1673 GATE(CLK_PCLK_HSI2C6, "pclk_hsi2c6", "aclk_peric_66", 1674 ENABLE_PCLK_PERIC1, 2, CLK_SET_RATE_PARENT, 0), 1675 GATE(CLK_PCLK_HSI2C5, "pclk_hsi2c5", "aclk_peric_66", 1676 ENABLE_PCLK_PERIC1, 1, CLK_SET_RATE_PARENT, 0), 1677 GATE(CLK_PCLK_HSI2C4, "pclk_hsi2c4", "aclk_peric_66", 1678 ENABLE_PCLK_PERIC1, 0, CLK_SET_RATE_PARENT, 0), 1679 1680 /* ENABLE_SCLK_PERIC */ 1681 GATE(CLK_SCLK_IOCLK_SPI4, "sclk_ioclk_spi4", "ioclk_spi4_clk_in", 1682 ENABLE_SCLK_PERIC, 21, CLK_SET_RATE_PARENT, 0), 1683 GATE(CLK_SCLK_IOCLK_SPI3, "sclk_ioclk_spi3", "ioclk_spi3_clk_in", 1684 ENABLE_SCLK_PERIC, 20, CLK_SET_RATE_PARENT, 0), 1685 GATE(CLK_SCLK_SPI4, "sclk_spi4", "sclk_spi4_peric", ENABLE_SCLK_PERIC, 1686 19, CLK_SET_RATE_PARENT, 0), 1687 GATE(CLK_SCLK_SPI3, "sclk_spi3", "sclk_spi3_peric", ENABLE_SCLK_PERIC, 1688 18, CLK_SET_RATE_PARENT, 0), 1689 GATE(CLK_SCLK_SCI, "sclk_sci", "div_sclk_sci", ENABLE_SCLK_PERIC, 1690 17, 0, 0), 1691 GATE(CLK_SCLK_SC_IN, "sclk_sc_in", "div_sclk_sc_in", ENABLE_SCLK_PERIC, 1692 16, 0, 0), 1693 GATE(CLK_SCLK_PWM, "sclk_pwm", "oscclk", ENABLE_SCLK_PERIC, 15, 0, 0), 1694 GATE(CLK_SCLK_IOCLK_SPI2, "sclk_ioclk_spi2", "ioclk_spi2_clk_in", 1695 ENABLE_SCLK_PERIC, 13, CLK_SET_RATE_PARENT, 0), 1696 GATE(CLK_SCLK_IOCLK_SPI1, "sclk_ioclk_spi1", "ioclk_spi1_clk_in", 1697 ENABLE_SCLK_PERIC, 12, CLK_SET_RATE_PARENT, 0), 1698 GATE(CLK_SCLK_IOCLK_SPI0, "sclk_ioclk_spi0", "ioclk_spi0_clk_in", 1699 ENABLE_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0), 1700 GATE(CLK_SCLK_IOCLK_I2S1_BCLK, "sclk_ioclk_i2s1_bclk", 1701 "ioclk_i2s1_bclk_in", ENABLE_SCLK_PERIC, 10, 1702 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 1703 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "sclk_spdif_peric", 1704 ENABLE_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0), 1705 GATE(CLK_SCLK_PCM1, "sclk_pcm1", "sclk_pcm1_peric", 1706 ENABLE_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0), 1707 GATE(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_i2s1_peric", 1708 ENABLE_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0), 1709 GATE(CLK_SCLK_SPI2, "sclk_spi2", "sclk_spi2_peric", ENABLE_SCLK_PERIC, 1710 5, CLK_SET_RATE_PARENT, 0), 1711 GATE(CLK_SCLK_SPI1, "sclk_spi1", "sclk_spi1_peric", ENABLE_SCLK_PERIC, 1712 4, CLK_SET_RATE_PARENT, 0), 1713 GATE(CLK_SCLK_SPI0, "sclk_spi0", "sclk_spi0_peric", ENABLE_SCLK_PERIC, 1714 3, CLK_SET_RATE_PARENT, 0), 1715 GATE(CLK_SCLK_UART2, "sclk_uart2", "sclk_uart2_peric", 1716 ENABLE_SCLK_PERIC, 2, 1717 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 1718 GATE(CLK_SCLK_UART1, "sclk_uart1", "sclk_uart1_peric", 1719 ENABLE_SCLK_PERIC, 1, 1720 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 1721 GATE(CLK_SCLK_UART0, "sclk_uart0", "sclk_uart0_peric", 1722 ENABLE_SCLK_PERIC, 0, 1723 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 1724 }; 1725 1726 static const struct samsung_cmu_info peric_cmu_info __initconst = { 1727 .div_clks = peric_div_clks, 1728 .nr_div_clks = ARRAY_SIZE(peric_div_clks), 1729 .gate_clks = peric_gate_clks, 1730 .nr_gate_clks = ARRAY_SIZE(peric_gate_clks), 1731 .nr_clk_ids = PERIC_NR_CLK, 1732 .clk_regs = peric_clk_regs, 1733 .nr_clk_regs = ARRAY_SIZE(peric_clk_regs), 1734 .suspend_regs = peric_suspend_regs, 1735 .nr_suspend_regs = ARRAY_SIZE(peric_suspend_regs), 1736 }; 1737 1738 static void __init exynos5433_cmu_peric_init(struct device_node *np) 1739 { 1740 samsung_cmu_register_one(np, &peric_cmu_info); 1741 } 1742 1743 CLK_OF_DECLARE(exynos5433_cmu_peric, "samsung,exynos5433-cmu-peric", 1744 exynos5433_cmu_peric_init); 1745 1746 /* 1747 * Register offset definitions for CMU_PERIS 1748 */ 1749 #define ENABLE_ACLK_PERIS 0x0800 1750 #define ENABLE_PCLK_PERIS 0x0900 1751 #define ENABLE_PCLK_PERIS_SECURE_TZPC 0x0904 1752 #define ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF 0x0908 1753 #define ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF 0x090c 1754 #define ENABLE_PCLK_PERIS_SECURE_TOPRTC 0x0910 1755 #define ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF 0x0914 1756 #define ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF 0x0918 1757 #define ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF 0x091c 1758 #define ENABLE_SCLK_PERIS 0x0a00 1759 #define ENABLE_SCLK_PERIS_SECURE_SECKEY 0x0a04 1760 #define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0a08 1761 #define ENABLE_SCLK_PERIS_SECURE_TOPRTC 0x0a0c 1762 #define ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE 0x0a10 1763 #define ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT 0x0a14 1764 #define ENABLE_SCLK_PERIS_SECURE_OTP_CON 0x0a18 1765 #define ENABLE_IP_PERIS0 0x0b00 1766 #define ENABLE_IP_PERIS1 0x0b04 1767 #define ENABLE_IP_PERIS_SECURE_TZPC 0x0b08 1768 #define ENABLE_IP_PERIS_SECURE_SECKEY 0x0b0c 1769 #define ENABLE_IP_PERIS_SECURE_CHIPID 0x0b10 1770 #define ENABLE_IP_PERIS_SECURE_TOPRTC 0x0b14 1771 #define ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE 0x0b18 1772 #define ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT 0x0b1c 1773 #define ENABLE_IP_PERIS_SECURE_OTP_CON 0x0b20 1774 1775 static const unsigned long peris_clk_regs[] __initconst = { 1776 ENABLE_ACLK_PERIS, 1777 ENABLE_PCLK_PERIS, 1778 ENABLE_PCLK_PERIS_SECURE_TZPC, 1779 ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF, 1780 ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF, 1781 ENABLE_PCLK_PERIS_SECURE_TOPRTC, 1782 ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF, 1783 ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF, 1784 ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF, 1785 ENABLE_SCLK_PERIS, 1786 ENABLE_SCLK_PERIS_SECURE_SECKEY, 1787 ENABLE_SCLK_PERIS_SECURE_CHIPID, 1788 ENABLE_SCLK_PERIS_SECURE_TOPRTC, 1789 ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE, 1790 ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT, 1791 ENABLE_SCLK_PERIS_SECURE_OTP_CON, 1792 ENABLE_IP_PERIS0, 1793 ENABLE_IP_PERIS1, 1794 ENABLE_IP_PERIS_SECURE_TZPC, 1795 ENABLE_IP_PERIS_SECURE_SECKEY, 1796 ENABLE_IP_PERIS_SECURE_CHIPID, 1797 ENABLE_IP_PERIS_SECURE_TOPRTC, 1798 ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE, 1799 ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT, 1800 ENABLE_IP_PERIS_SECURE_OTP_CON, 1801 }; 1802 1803 static const struct samsung_gate_clock peris_gate_clks[] __initconst = { 1804 /* ENABLE_ACLK_PERIS */ 1805 GATE(CLK_ACLK_AHB2APB_PERIS1P, "aclk_ahb2apb_peris1p", "aclk_peris_66", 1806 ENABLE_ACLK_PERIS, 2, CLK_IGNORE_UNUSED, 0), 1807 GATE(CLK_ACLK_AHB2APB_PERIS0P, "aclk_ahb2apb_peris0p", "aclk_peris_66", 1808 ENABLE_ACLK_PERIS, 1, CLK_IGNORE_UNUSED, 0), 1809 GATE(CLK_ACLK_PERISNP_66, "aclk_perisnp_66", "aclk_peris_66", 1810 ENABLE_ACLK_PERIS, 0, CLK_IGNORE_UNUSED, 0), 1811 1812 /* ENABLE_PCLK_PERIS */ 1813 GATE(CLK_PCLK_HPM_APBIF, "pclk_hpm_apbif", "aclk_peris_66", 1814 ENABLE_PCLK_PERIS, 30, CLK_IGNORE_UNUSED, 0), 1815 GATE(CLK_PCLK_TMU1_APBIF, "pclk_tmu1_apbif", "aclk_peris_66", 1816 ENABLE_PCLK_PERIS, 24, CLK_IGNORE_UNUSED, 0), 1817 GATE(CLK_PCLK_TMU0_APBIF, "pclk_tmu0_apbif", "aclk_peris_66", 1818 ENABLE_PCLK_PERIS, 23, CLK_IGNORE_UNUSED, 0), 1819 GATE(CLK_PCLK_PMU_PERIS, "pclk_pmu_peris", "aclk_peris_66", 1820 ENABLE_PCLK_PERIS, 22, CLK_IGNORE_UNUSED, 0), 1821 GATE(CLK_PCLK_SYSREG_PERIS, "pclk_sysreg_peris", "aclk_peris_66", 1822 ENABLE_PCLK_PERIS, 21, CLK_IGNORE_UNUSED, 0), 1823 GATE(CLK_PCLK_CMU_TOP_APBIF, "pclk_cmu_top_apbif", "aclk_peris_66", 1824 ENABLE_PCLK_PERIS, 20, CLK_IGNORE_UNUSED, 0), 1825 GATE(CLK_PCLK_WDT_APOLLO, "pclk_wdt_apollo", "aclk_peris_66", 1826 ENABLE_PCLK_PERIS, 17, CLK_IGNORE_UNUSED, 0), 1827 GATE(CLK_PCLK_WDT_ATLAS, "pclk_wdt_atlas", "aclk_peris_66", 1828 ENABLE_PCLK_PERIS, 16, CLK_IGNORE_UNUSED, 0), 1829 GATE(CLK_PCLK_MCT, "pclk_mct", "aclk_peris_66", 1830 ENABLE_PCLK_PERIS, 15, CLK_IGNORE_UNUSED, 0), 1831 GATE(CLK_PCLK_HDMI_CEC, "pclk_hdmi_cec", "aclk_peris_66", 1832 ENABLE_PCLK_PERIS, 14, CLK_IGNORE_UNUSED, 0), 1833 1834 /* ENABLE_PCLK_PERIS_SECURE_TZPC */ 1835 GATE(CLK_PCLK_TZPC12, "pclk_tzpc12", "aclk_peris_66", 1836 ENABLE_PCLK_PERIS_SECURE_TZPC, 12, CLK_IGNORE_UNUSED, 0), 1837 GATE(CLK_PCLK_TZPC11, "pclk_tzpc11", "aclk_peris_66", 1838 ENABLE_PCLK_PERIS_SECURE_TZPC, 11, CLK_IGNORE_UNUSED, 0), 1839 GATE(CLK_PCLK_TZPC10, "pclk_tzpc10", "aclk_peris_66", 1840 ENABLE_PCLK_PERIS_SECURE_TZPC, 10, CLK_IGNORE_UNUSED, 0), 1841 GATE(CLK_PCLK_TZPC9, "pclk_tzpc9", "aclk_peris_66", 1842 ENABLE_PCLK_PERIS_SECURE_TZPC, 9, CLK_IGNORE_UNUSED, 0), 1843 GATE(CLK_PCLK_TZPC8, "pclk_tzpc8", "aclk_peris_66", 1844 ENABLE_PCLK_PERIS_SECURE_TZPC, 8, CLK_IGNORE_UNUSED, 0), 1845 GATE(CLK_PCLK_TZPC7, "pclk_tzpc7", "aclk_peris_66", 1846 ENABLE_PCLK_PERIS_SECURE_TZPC, 7, CLK_IGNORE_UNUSED, 0), 1847 GATE(CLK_PCLK_TZPC6, "pclk_tzpc6", "aclk_peris_66", 1848 ENABLE_PCLK_PERIS_SECURE_TZPC, 6, CLK_IGNORE_UNUSED, 0), 1849 GATE(CLK_PCLK_TZPC5, "pclk_tzpc5", "aclk_peris_66", 1850 ENABLE_PCLK_PERIS_SECURE_TZPC, 5, CLK_IGNORE_UNUSED, 0), 1851 GATE(CLK_PCLK_TZPC4, "pclk_tzpc4", "aclk_peris_66", 1852 ENABLE_PCLK_PERIS_SECURE_TZPC, 4, CLK_IGNORE_UNUSED, 0), 1853 GATE(CLK_PCLK_TZPC3, "pclk_tzpc3", "aclk_peris_66", 1854 ENABLE_PCLK_PERIS_SECURE_TZPC, 3, CLK_IGNORE_UNUSED, 0), 1855 GATE(CLK_PCLK_TZPC2, "pclk_tzpc2", "aclk_peris_66", 1856 ENABLE_PCLK_PERIS_SECURE_TZPC, 2, CLK_IGNORE_UNUSED, 0), 1857 GATE(CLK_PCLK_TZPC1, "pclk_tzpc1", "aclk_peris_66", 1858 ENABLE_PCLK_PERIS_SECURE_TZPC, 1, CLK_IGNORE_UNUSED, 0), 1859 GATE(CLK_PCLK_TZPC0, "pclk_tzpc0", "aclk_peris_66", 1860 ENABLE_PCLK_PERIS_SECURE_TZPC, 0, CLK_IGNORE_UNUSED, 0), 1861 1862 /* ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF */ 1863 GATE(CLK_PCLK_SECKEY_APBIF, "pclk_seckey_apbif", "aclk_peris_66", 1864 ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF, 0, CLK_IGNORE_UNUSED, 0), 1865 1866 /* ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF */ 1867 GATE(CLK_PCLK_CHIPID_APBIF, "pclk_chipid_apbif", "aclk_peris_66", 1868 ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF, 0, CLK_IGNORE_UNUSED, 0), 1869 1870 /* ENABLE_PCLK_PERIS_SECURE_TOPRTC */ 1871 GATE(CLK_PCLK_TOPRTC, "pclk_toprtc", "aclk_peris_66", 1872 ENABLE_PCLK_PERIS_SECURE_TOPRTC, 0, 0, 0), 1873 1874 /* ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF */ 1875 GATE(CLK_PCLK_CUSTOM_EFUSE_APBIF, "pclk_custom_efuse_apbif", 1876 "aclk_peris_66", 1877 ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF, 0, 0, 0), 1878 1879 /* ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF */ 1880 GATE(CLK_PCLK_ANTIRBK_CNT_APBIF, "pclk_antirbk_cnt_apbif", 1881 "aclk_peris_66", 1882 ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF, 0, 0, 0), 1883 1884 /* ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF */ 1885 GATE(CLK_PCLK_OTP_CON_APBIF, "pclk_otp_con_apbif", 1886 "aclk_peris_66", 1887 ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF, 0, 0, 0), 1888 1889 /* ENABLE_SCLK_PERIS */ 1890 GATE(CLK_SCLK_ASV_TB, "sclk_asv_tb", "oscclk_efuse_common", 1891 ENABLE_SCLK_PERIS, 10, 0, 0), 1892 GATE(CLK_SCLK_TMU1, "sclk_tmu1", "oscclk_efuse_common", 1893 ENABLE_SCLK_PERIS, 4, 0, 0), 1894 GATE(CLK_SCLK_TMU0, "sclk_tmu0", "oscclk_efuse_common", 1895 ENABLE_SCLK_PERIS, 3, 0, 0), 1896 1897 /* ENABLE_SCLK_PERIS_SECURE_SECKEY */ 1898 GATE(CLK_SCLK_SECKEY, "sclk_seckey", "oscclk_efuse_common", 1899 ENABLE_SCLK_PERIS_SECURE_SECKEY, 0, CLK_IGNORE_UNUSED, 0), 1900 1901 /* ENABLE_SCLK_PERIS_SECURE_CHIPID */ 1902 GATE(CLK_SCLK_CHIPID, "sclk_chipid", "oscclk_efuse_common", 1903 ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, CLK_IGNORE_UNUSED, 0), 1904 1905 /* ENABLE_SCLK_PERIS_SECURE_TOPRTC */ 1906 GATE(CLK_SCLK_TOPRTC, "sclk_toprtc", "oscclk_efuse_common", 1907 ENABLE_SCLK_PERIS_SECURE_TOPRTC, 0, 0, 0), 1908 1909 /* ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE */ 1910 GATE(CLK_SCLK_CUSTOM_EFUSE, "sclk_custom_efuse", "oscclk_efuse_common", 1911 ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE, 0, 0, 0), 1912 1913 /* ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT */ 1914 GATE(CLK_SCLK_ANTIRBK_CNT, "sclk_antirbk_cnt", "oscclk_efuse_common", 1915 ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT, 0, 0, 0), 1916 1917 /* ENABLE_SCLK_PERIS_SECURE_OTP_CON */ 1918 GATE(CLK_SCLK_OTP_CON, "sclk_otp_con", "oscclk_efuse_common", 1919 ENABLE_SCLK_PERIS_SECURE_OTP_CON, 0, 0, 0), 1920 }; 1921 1922 static const struct samsung_cmu_info peris_cmu_info __initconst = { 1923 .gate_clks = peris_gate_clks, 1924 .nr_gate_clks = ARRAY_SIZE(peris_gate_clks), 1925 .nr_clk_ids = PERIS_NR_CLK, 1926 .clk_regs = peris_clk_regs, 1927 .nr_clk_regs = ARRAY_SIZE(peris_clk_regs), 1928 }; 1929 1930 static void __init exynos5433_cmu_peris_init(struct device_node *np) 1931 { 1932 samsung_cmu_register_one(np, &peris_cmu_info); 1933 } 1934 1935 CLK_OF_DECLARE(exynos5433_cmu_peris, "samsung,exynos5433-cmu-peris", 1936 exynos5433_cmu_peris_init); 1937 1938 /* 1939 * Register offset definitions for CMU_FSYS 1940 */ 1941 #define MUX_SEL_FSYS0 0x0200 1942 #define MUX_SEL_FSYS1 0x0204 1943 #define MUX_SEL_FSYS2 0x0208 1944 #define MUX_SEL_FSYS3 0x020c 1945 #define MUX_SEL_FSYS4 0x0210 1946 #define MUX_ENABLE_FSYS0 0x0300 1947 #define MUX_ENABLE_FSYS1 0x0304 1948 #define MUX_ENABLE_FSYS2 0x0308 1949 #define MUX_ENABLE_FSYS3 0x030c 1950 #define MUX_ENABLE_FSYS4 0x0310 1951 #define MUX_STAT_FSYS0 0x0400 1952 #define MUX_STAT_FSYS1 0x0404 1953 #define MUX_STAT_FSYS2 0x0408 1954 #define MUX_STAT_FSYS3 0x040c 1955 #define MUX_STAT_FSYS4 0x0410 1956 #define MUX_IGNORE_FSYS2 0x0508 1957 #define MUX_IGNORE_FSYS3 0x050c 1958 #define ENABLE_ACLK_FSYS0 0x0800 1959 #define ENABLE_ACLK_FSYS1 0x0804 1960 #define ENABLE_PCLK_FSYS 0x0900 1961 #define ENABLE_SCLK_FSYS 0x0a00 1962 #define ENABLE_IP_FSYS0 0x0b00 1963 #define ENABLE_IP_FSYS1 0x0b04 1964 1965 /* list of all parent clock list */ 1966 PNAME(mout_sclk_ufs_mphy_user_p) = { "oscclk", "sclk_ufs_mphy", }; 1967 PNAME(mout_aclk_fsys_200_user_p) = { "oscclk", "aclk_fsys_200", }; 1968 PNAME(mout_sclk_pcie_100_user_p) = { "oscclk", "sclk_pcie_100_fsys",}; 1969 PNAME(mout_sclk_ufsunipro_user_p) = { "oscclk", "sclk_ufsunipro_fsys",}; 1970 PNAME(mout_sclk_mmc2_user_p) = { "oscclk", "sclk_mmc2_fsys", }; 1971 PNAME(mout_sclk_mmc1_user_p) = { "oscclk", "sclk_mmc1_fsys", }; 1972 PNAME(mout_sclk_mmc0_user_p) = { "oscclk", "sclk_mmc0_fsys", }; 1973 PNAME(mout_sclk_usbhost30_user_p) = { "oscclk", "sclk_usbhost30_fsys",}; 1974 PNAME(mout_sclk_usbdrd30_user_p) = { "oscclk", "sclk_usbdrd30_fsys", }; 1975 1976 PNAME(mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p) 1977 = { "oscclk", "phyclk_usbhost30_uhost30_pipe_pclk_phy", }; 1978 PNAME(mout_phyclk_usbhost30_uhost30_phyclock_user_p) 1979 = { "oscclk", "phyclk_usbhost30_uhost30_phyclock_phy", }; 1980 PNAME(mout_phyclk_usbhost20_phy_hsic1_p) 1981 = { "oscclk", "phyclk_usbhost20_phy_hsic1_phy", }; 1982 PNAME(mout_phyclk_usbhost20_phy_clk48mohci_user_p) 1983 = { "oscclk", "phyclk_usbhost20_phy_clk48mohci_phy", }; 1984 PNAME(mout_phyclk_usbhost20_phy_phyclock_user_p) 1985 = { "oscclk", "phyclk_usbhost20_phy_phyclock_phy", }; 1986 PNAME(mout_phyclk_usbhost20_phy_freeclk_user_p) 1987 = { "oscclk", "phyclk_usbhost20_phy_freeclk_phy", }; 1988 PNAME(mout_phyclk_usbdrd30_udrd30_pipe_pclk_p) 1989 = { "oscclk", "phyclk_usbdrd30_udrd30_pipe_pclk_phy", }; 1990 PNAME(mout_phyclk_usbdrd30_udrd30_phyclock_user_p) 1991 = { "oscclk", "phyclk_usbdrd30_udrd30_phyclock_phy", }; 1992 PNAME(mout_phyclk_ufs_rx1_symbol_user_p) 1993 = { "oscclk", "phyclk_ufs_rx1_symbol_phy", }; 1994 PNAME(mout_phyclk_ufs_rx0_symbol_user_p) 1995 = { "oscclk", "phyclk_ufs_rx0_symbol_phy", }; 1996 PNAME(mout_phyclk_ufs_tx1_symbol_user_p) 1997 = { "oscclk", "phyclk_ufs_tx1_symbol_phy", }; 1998 PNAME(mout_phyclk_ufs_tx0_symbol_user_p) 1999 = { "oscclk", "phyclk_ufs_tx0_symbol_phy", }; 2000 PNAME(mout_phyclk_lli_mphy_to_ufs_user_p) 2001 = { "oscclk", "phyclk_lli_mphy_to_ufs_phy", }; 2002 PNAME(mout_sclk_mphy_p) 2003 = { "mout_sclk_ufs_mphy_user", 2004 "mout_phyclk_lli_mphy_to_ufs_user", }; 2005 2006 static const unsigned long fsys_clk_regs[] __initconst = { 2007 MUX_SEL_FSYS0, 2008 MUX_SEL_FSYS1, 2009 MUX_SEL_FSYS2, 2010 MUX_SEL_FSYS3, 2011 MUX_SEL_FSYS4, 2012 MUX_ENABLE_FSYS0, 2013 MUX_ENABLE_FSYS1, 2014 MUX_ENABLE_FSYS2, 2015 MUX_ENABLE_FSYS3, 2016 MUX_ENABLE_FSYS4, 2017 MUX_IGNORE_FSYS2, 2018 MUX_IGNORE_FSYS3, 2019 ENABLE_ACLK_FSYS0, 2020 ENABLE_ACLK_FSYS1, 2021 ENABLE_PCLK_FSYS, 2022 ENABLE_SCLK_FSYS, 2023 ENABLE_IP_FSYS0, 2024 ENABLE_IP_FSYS1, 2025 }; 2026 2027 static const struct samsung_clk_reg_dump fsys_suspend_regs[] = { 2028 { MUX_SEL_FSYS0, 0 }, 2029 { MUX_SEL_FSYS1, 0 }, 2030 { MUX_SEL_FSYS2, 0 }, 2031 { MUX_SEL_FSYS3, 0 }, 2032 { MUX_SEL_FSYS4, 0 }, 2033 }; 2034 2035 static const struct samsung_fixed_rate_clock fsys_fixed_clks[] __initconst = { 2036 /* PHY clocks from USBDRD30_PHY */ 2037 FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY, 2038 "phyclk_usbdrd30_udrd30_phyclock_phy", NULL, 2039 0, 60000000), 2040 FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY, 2041 "phyclk_usbdrd30_udrd30_pipe_pclk_phy", NULL, 2042 0, 125000000), 2043 /* PHY clocks from USBHOST30_PHY */ 2044 FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY, 2045 "phyclk_usbhost30_uhost30_phyclock_phy", NULL, 2046 0, 60000000), 2047 FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY, 2048 "phyclk_usbhost30_uhost30_pipe_pclk_phy", NULL, 2049 0, 125000000), 2050 /* PHY clocks from USBHOST20_PHY */ 2051 FRATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK_PHY, 2052 "phyclk_usbhost20_phy_freeclk_phy", NULL, 0, 60000000), 2053 FRATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK_PHY, 2054 "phyclk_usbhost20_phy_phyclock_phy", NULL, 0, 60000000), 2055 FRATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI_PHY, 2056 "phyclk_usbhost20_phy_clk48mohci_phy", NULL, 2057 0, 48000000), 2058 FRATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1_PHY, 2059 "phyclk_usbhost20_phy_hsic1_phy", NULL, 0, 2060 60000000), 2061 /* PHY clocks from UFS_PHY */ 2062 FRATE(CLK_PHYCLK_UFS_TX0_SYMBOL_PHY, "phyclk_ufs_tx0_symbol_phy", 2063 NULL, 0, 300000000), 2064 FRATE(CLK_PHYCLK_UFS_RX0_SYMBOL_PHY, "phyclk_ufs_rx0_symbol_phy", 2065 NULL, 0, 300000000), 2066 FRATE(CLK_PHYCLK_UFS_TX1_SYMBOL_PHY, "phyclk_ufs_tx1_symbol_phy", 2067 NULL, 0, 300000000), 2068 FRATE(CLK_PHYCLK_UFS_RX1_SYMBOL_PHY, "phyclk_ufs_rx1_symbol_phy", 2069 NULL, 0, 300000000), 2070 /* PHY clocks from LLI_PHY */ 2071 FRATE(CLK_PHYCLK_LLI_MPHY_TO_UFS_PHY, "phyclk_lli_mphy_to_ufs_phy", 2072 NULL, 0, 26000000), 2073 }; 2074 2075 static const struct samsung_mux_clock fsys_mux_clks[] __initconst = { 2076 /* MUX_SEL_FSYS0 */ 2077 MUX(CLK_MOUT_SCLK_UFS_MPHY_USER, "mout_sclk_ufs_mphy_user", 2078 mout_sclk_ufs_mphy_user_p, MUX_SEL_FSYS0, 4, 1), 2079 MUX(CLK_MOUT_ACLK_FSYS_200_USER, "mout_aclk_fsys_200_user", 2080 mout_aclk_fsys_200_user_p, MUX_SEL_FSYS0, 0, 1), 2081 2082 /* MUX_SEL_FSYS1 */ 2083 MUX(CLK_MOUT_SCLK_PCIE_100_USER, "mout_sclk_pcie_100_user", 2084 mout_sclk_pcie_100_user_p, MUX_SEL_FSYS1, 28, 1), 2085 MUX(CLK_MOUT_SCLK_UFSUNIPRO_USER, "mout_sclk_ufsunipro_user", 2086 mout_sclk_ufsunipro_user_p, MUX_SEL_FSYS1, 24, 1), 2087 MUX(CLK_MOUT_SCLK_MMC2_USER, "mout_sclk_mmc2_user", 2088 mout_sclk_mmc2_user_p, MUX_SEL_FSYS1, 20, 1), 2089 MUX(CLK_MOUT_SCLK_MMC1_USER, "mout_sclk_mmc1_user", 2090 mout_sclk_mmc1_user_p, MUX_SEL_FSYS1, 16, 1), 2091 MUX(CLK_MOUT_SCLK_MMC0_USER, "mout_sclk_mmc0_user", 2092 mout_sclk_mmc0_user_p, MUX_SEL_FSYS1, 12, 1), 2093 MUX(CLK_MOUT_SCLK_USBHOST30_USER, "mout_sclk_usbhost30_user", 2094 mout_sclk_usbhost30_user_p, MUX_SEL_FSYS1, 4, 1), 2095 MUX(CLK_MOUT_SCLK_USBDRD30_USER, "mout_sclk_usbdrd30_user", 2096 mout_sclk_usbdrd30_user_p, MUX_SEL_FSYS1, 0, 1), 2097 2098 /* MUX_SEL_FSYS2 */ 2099 MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER, 2100 "mout_phyclk_usbhost30_uhost30_pipe_pclk_user", 2101 mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p, 2102 MUX_SEL_FSYS2, 28, 1), 2103 MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER, 2104 "mout_phyclk_usbhost30_uhost30_phyclock_user", 2105 mout_phyclk_usbhost30_uhost30_phyclock_user_p, 2106 MUX_SEL_FSYS2, 24, 1), 2107 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER, 2108 "mout_phyclk_usbhost20_phy_hsic1", 2109 mout_phyclk_usbhost20_phy_hsic1_p, 2110 MUX_SEL_FSYS2, 20, 1), 2111 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER, 2112 "mout_phyclk_usbhost20_phy_clk48mohci_user", 2113 mout_phyclk_usbhost20_phy_clk48mohci_user_p, 2114 MUX_SEL_FSYS2, 16, 1), 2115 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER, 2116 "mout_phyclk_usbhost20_phy_phyclock_user", 2117 mout_phyclk_usbhost20_phy_phyclock_user_p, 2118 MUX_SEL_FSYS2, 12, 1), 2119 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER, 2120 "mout_phyclk_usbhost20_phy_freeclk_user", 2121 mout_phyclk_usbhost20_phy_freeclk_user_p, 2122 MUX_SEL_FSYS2, 8, 1), 2123 MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER, 2124 "mout_phyclk_usbdrd30_udrd30_pipe_pclk_user", 2125 mout_phyclk_usbdrd30_udrd30_pipe_pclk_p, 2126 MUX_SEL_FSYS2, 4, 1), 2127 MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER, 2128 "mout_phyclk_usbdrd30_udrd30_phyclock_user", 2129 mout_phyclk_usbdrd30_udrd30_phyclock_user_p, 2130 MUX_SEL_FSYS2, 0, 1), 2131 2132 /* MUX_SEL_FSYS3 */ 2133 MUX(CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER, 2134 "mout_phyclk_ufs_rx1_symbol_user", 2135 mout_phyclk_ufs_rx1_symbol_user_p, 2136 MUX_SEL_FSYS3, 16, 1), 2137 MUX(CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER, 2138 "mout_phyclk_ufs_rx0_symbol_user", 2139 mout_phyclk_ufs_rx0_symbol_user_p, 2140 MUX_SEL_FSYS3, 12, 1), 2141 MUX(CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER, 2142 "mout_phyclk_ufs_tx1_symbol_user", 2143 mout_phyclk_ufs_tx1_symbol_user_p, 2144 MUX_SEL_FSYS3, 8, 1), 2145 MUX(CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER, 2146 "mout_phyclk_ufs_tx0_symbol_user", 2147 mout_phyclk_ufs_tx0_symbol_user_p, 2148 MUX_SEL_FSYS3, 4, 1), 2149 MUX(CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER, 2150 "mout_phyclk_lli_mphy_to_ufs_user", 2151 mout_phyclk_lli_mphy_to_ufs_user_p, 2152 MUX_SEL_FSYS3, 0, 1), 2153 2154 /* MUX_SEL_FSYS4 */ 2155 MUX(CLK_MOUT_SCLK_MPHY, "mout_sclk_mphy", mout_sclk_mphy_p, 2156 MUX_SEL_FSYS4, 0, 1), 2157 }; 2158 2159 static const struct samsung_gate_clock fsys_gate_clks[] __initconst = { 2160 /* ENABLE_ACLK_FSYS0 */ 2161 GATE(CLK_ACLK_PCIE, "aclk_pcie", "mout_aclk_fsys_200_user", 2162 ENABLE_ACLK_FSYS0, 13, CLK_IGNORE_UNUSED, 0), 2163 GATE(CLK_ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys_200_user", 2164 ENABLE_ACLK_FSYS0, 11, CLK_IGNORE_UNUSED, 0), 2165 GATE(CLK_ACLK_TSI, "aclk_tsi", "mout_aclk_fsys_200_user", 2166 ENABLE_ACLK_FSYS0, 10, CLK_IGNORE_UNUSED, 0), 2167 GATE(CLK_ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys_200_user", 2168 ENABLE_ACLK_FSYS0, 8, CLK_IGNORE_UNUSED, 0), 2169 GATE(CLK_ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys_200_user", 2170 ENABLE_ACLK_FSYS0, 7, CLK_IGNORE_UNUSED, 0), 2171 GATE(CLK_ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys_200_user", 2172 ENABLE_ACLK_FSYS0, 6, CLK_IGNORE_UNUSED, 0), 2173 GATE(CLK_ACLK_UFS, "aclk_ufs", "mout_aclk_fsys_200_user", 2174 ENABLE_ACLK_FSYS0, 5, CLK_IGNORE_UNUSED, 0), 2175 GATE(CLK_ACLK_USBHOST20, "aclk_usbhost20", "mout_aclk_fsys_200_user", 2176 ENABLE_ACLK_FSYS0, 3, CLK_IGNORE_UNUSED, 0), 2177 GATE(CLK_ACLK_USBHOST30, "aclk_usbhost30", "mout_aclk_fsys_200_user", 2178 ENABLE_ACLK_FSYS0, 2, CLK_IGNORE_UNUSED, 0), 2179 GATE(CLK_ACLK_USBDRD30, "aclk_usbdrd30", "mout_aclk_fsys_200_user", 2180 ENABLE_ACLK_FSYS0, 1, CLK_IGNORE_UNUSED, 0), 2181 GATE(CLK_ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys_200_user", 2182 ENABLE_ACLK_FSYS0, 0, CLK_IGNORE_UNUSED, 0), 2183 2184 /* ENABLE_ACLK_FSYS1 */ 2185 GATE(CLK_ACLK_XIU_FSYSPX, "aclk_xiu_fsyspx", "mout_aclk_fsys_200_user", 2186 ENABLE_ACLK_FSYS1, 27, CLK_IGNORE_UNUSED, 0), 2187 GATE(CLK_ACLK_AHB_USBLINKH1, "aclk_ahb_usblinkh1", 2188 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 2189 26, CLK_IGNORE_UNUSED, 0), 2190 GATE(CLK_ACLK_SMMU_PDMA1, "aclk_smmu_pdma1", "mout_aclk_fsys_200_user", 2191 ENABLE_ACLK_FSYS1, 25, CLK_IGNORE_UNUSED, 0), 2192 GATE(CLK_ACLK_BTS_PCIE, "aclk_bts_pcie", "mout_aclk_fsys_200_user", 2193 ENABLE_ACLK_FSYS1, 24, CLK_IGNORE_UNUSED, 0), 2194 GATE(CLK_ACLK_AXIUS_PDMA1, "aclk_axius_pdma1", 2195 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 2196 22, CLK_IGNORE_UNUSED, 0), 2197 GATE(CLK_ACLK_SMMU_PDMA0, "aclk_smmu_pdma0", "mout_aclk_fsys_200_user", 2198 ENABLE_ACLK_FSYS1, 17, CLK_IGNORE_UNUSED, 0), 2199 GATE(CLK_ACLK_BTS_UFS, "aclk_bts_ufs", "mout_aclk_fsys_200_user", 2200 ENABLE_ACLK_FSYS1, 14, CLK_IGNORE_UNUSED, 0), 2201 GATE(CLK_ACLK_BTS_USBHOST30, "aclk_bts_usbhost30", 2202 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 2203 13, 0, 0), 2204 GATE(CLK_ACLK_BTS_USBDRD30, "aclk_bts_usbdrd30", 2205 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 2206 12, 0, 0), 2207 GATE(CLK_ACLK_AXIUS_PDMA0, "aclk_axius_pdma0", 2208 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 2209 11, CLK_IGNORE_UNUSED, 0), 2210 GATE(CLK_ACLK_AXIUS_USBHS, "aclk_axius_usbhs", 2211 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 2212 10, CLK_IGNORE_UNUSED, 0), 2213 GATE(CLK_ACLK_AXIUS_FSYSSX, "aclk_axius_fsyssx", 2214 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 2215 9, CLK_IGNORE_UNUSED, 0), 2216 GATE(CLK_ACLK_AHB2APB_FSYSP, "aclk_ahb2apb_fsysp", 2217 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 2218 8, CLK_IGNORE_UNUSED, 0), 2219 GATE(CLK_ACLK_AHB2AXI_USBHS, "aclk_ahb2axi_usbhs", 2220 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 2221 7, CLK_IGNORE_UNUSED, 0), 2222 GATE(CLK_ACLK_AHB_USBLINKH0, "aclk_ahb_usblinkh0", 2223 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 2224 6, CLK_IGNORE_UNUSED, 0), 2225 GATE(CLK_ACLK_AHB_USBHS, "aclk_ahb_usbhs", "mout_aclk_fsys_200_user", 2226 ENABLE_ACLK_FSYS1, 5, CLK_IGNORE_UNUSED, 0), 2227 GATE(CLK_ACLK_AHB_FSYSH, "aclk_ahb_fsysh", "mout_aclk_fsys_200_user", 2228 ENABLE_ACLK_FSYS1, 4, CLK_IGNORE_UNUSED, 0), 2229 GATE(CLK_ACLK_XIU_FSYSX, "aclk_xiu_fsysx", "mout_aclk_fsys_200_user", 2230 ENABLE_ACLK_FSYS1, 3, CLK_IGNORE_UNUSED, 0), 2231 GATE(CLK_ACLK_XIU_FSYSSX, "aclk_xiu_fsyssx", "mout_aclk_fsys_200_user", 2232 ENABLE_ACLK_FSYS1, 2, CLK_IGNORE_UNUSED, 0), 2233 GATE(CLK_ACLK_FSYSNP_200, "aclk_fsysnp_200", "mout_aclk_fsys_200_user", 2234 ENABLE_ACLK_FSYS1, 1, CLK_IGNORE_UNUSED, 0), 2235 GATE(CLK_ACLK_FSYSND_200, "aclk_fsysnd_200", "mout_aclk_fsys_200_user", 2236 ENABLE_ACLK_FSYS1, 0, CLK_IGNORE_UNUSED, 0), 2237 2238 /* ENABLE_PCLK_FSYS */ 2239 GATE(CLK_PCLK_PCIE_CTRL, "pclk_pcie_ctrl", "mout_aclk_fsys_200_user", 2240 ENABLE_PCLK_FSYS, 17, CLK_IGNORE_UNUSED, 0), 2241 GATE(CLK_PCLK_SMMU_PDMA1, "pclk_smmu_pdma1", "mout_aclk_fsys_200_user", 2242 ENABLE_PCLK_FSYS, 16, CLK_IGNORE_UNUSED, 0), 2243 GATE(CLK_PCLK_PCIE_PHY, "pclk_pcie_phy", "mout_aclk_fsys_200_user", 2244 ENABLE_PCLK_FSYS, 14, CLK_IGNORE_UNUSED, 0), 2245 GATE(CLK_PCLK_BTS_PCIE, "pclk_bts_pcie", "mout_aclk_fsys_200_user", 2246 ENABLE_PCLK_FSYS, 13, CLK_IGNORE_UNUSED, 0), 2247 GATE(CLK_PCLK_SMMU_PDMA0, "pclk_smmu_pdma0", "mout_aclk_fsys_200_user", 2248 ENABLE_PCLK_FSYS, 8, CLK_IGNORE_UNUSED, 0), 2249 GATE(CLK_PCLK_BTS_UFS, "pclk_bts_ufs", "mout_aclk_fsys_200_user", 2250 ENABLE_PCLK_FSYS, 5, 0, 0), 2251 GATE(CLK_PCLK_BTS_USBHOST30, "pclk_bts_usbhost30", 2252 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 4, 0, 0), 2253 GATE(CLK_PCLK_BTS_USBDRD30, "pclk_bts_usbdrd30", 2254 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 3, 0, 0), 2255 GATE(CLK_PCLK_GPIO_FSYS, "pclk_gpio_fsys", "mout_aclk_fsys_200_user", 2256 ENABLE_PCLK_FSYS, 2, CLK_IGNORE_UNUSED, 0), 2257 GATE(CLK_PCLK_PMU_FSYS, "pclk_pmu_fsys", "mout_aclk_fsys_200_user", 2258 ENABLE_PCLK_FSYS, 1, CLK_IGNORE_UNUSED, 0), 2259 GATE(CLK_PCLK_SYSREG_FSYS, "pclk_sysreg_fsys", 2260 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 2261 0, CLK_IGNORE_UNUSED, 0), 2262 2263 /* ENABLE_SCLK_FSYS */ 2264 GATE(CLK_SCLK_PCIE_100, "sclk_pcie_100", "mout_sclk_pcie_100_user", 2265 ENABLE_SCLK_FSYS, 21, 0, 0), 2266 GATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK, 2267 "phyclk_usbhost30_uhost30_pipe_pclk", 2268 "mout_phyclk_usbhost30_uhost30_pipe_pclk_user", 2269 ENABLE_SCLK_FSYS, 18, 0, 0), 2270 GATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK, 2271 "phyclk_usbhost30_uhost30_phyclock", 2272 "mout_phyclk_usbhost30_uhost30_phyclock_user", 2273 ENABLE_SCLK_FSYS, 17, 0, 0), 2274 GATE(CLK_PHYCLK_UFS_RX1_SYMBOL, "phyclk_ufs_rx1_symbol", 2275 "mout_phyclk_ufs_rx1_symbol_user", ENABLE_SCLK_FSYS, 2276 16, 0, 0), 2277 GATE(CLK_PHYCLK_UFS_RX0_SYMBOL, "phyclk_ufs_rx0_symbol", 2278 "mout_phyclk_ufs_rx0_symbol_user", ENABLE_SCLK_FSYS, 2279 15, 0, 0), 2280 GATE(CLK_PHYCLK_UFS_TX1_SYMBOL, "phyclk_ufs_tx1_symbol", 2281 "mout_phyclk_ufs_tx1_symbol_user", ENABLE_SCLK_FSYS, 2282 14, 0, 0), 2283 GATE(CLK_PHYCLK_UFS_TX0_SYMBOL, "phyclk_ufs_tx0_symbol", 2284 "mout_phyclk_ufs_tx0_symbol_user", ENABLE_SCLK_FSYS, 2285 13, 0, 0), 2286 GATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1, "phyclk_usbhost20_phy_hsic1", 2287 "mout_phyclk_usbhost20_phy_hsic1", ENABLE_SCLK_FSYS, 2288 12, 0, 0), 2289 GATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI, 2290 "phyclk_usbhost20_phy_clk48mohci", 2291 "mout_phyclk_usbhost20_phy_clk48mohci_user", 2292 ENABLE_SCLK_FSYS, 11, 0, 0), 2293 GATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK, 2294 "phyclk_usbhost20_phy_phyclock", 2295 "mout_phyclk_usbhost20_phy_phyclock_user", 2296 ENABLE_SCLK_FSYS, 10, 0, 0), 2297 GATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK, 2298 "phyclk_usbhost20_phy_freeclk", 2299 "mout_phyclk_usbhost20_phy_freeclk_user", 2300 ENABLE_SCLK_FSYS, 9, 0, 0), 2301 GATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK, 2302 "phyclk_usbdrd30_udrd30_pipe_pclk", 2303 "mout_phyclk_usbdrd30_udrd30_pipe_pclk_user", 2304 ENABLE_SCLK_FSYS, 8, 0, 0), 2305 GATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK, 2306 "phyclk_usbdrd30_udrd30_phyclock", 2307 "mout_phyclk_usbdrd30_udrd30_phyclock_user", 2308 ENABLE_SCLK_FSYS, 7, 0, 0), 2309 GATE(CLK_SCLK_MPHY, "sclk_mphy", "mout_sclk_mphy", 2310 ENABLE_SCLK_FSYS, 6, 0, 0), 2311 GATE(CLK_SCLK_UFSUNIPRO, "sclk_ufsunipro", "mout_sclk_ufsunipro_user", 2312 ENABLE_SCLK_FSYS, 5, 0, 0), 2313 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "mout_sclk_mmc2_user", 2314 ENABLE_SCLK_FSYS, 4, CLK_SET_RATE_PARENT, 0), 2315 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "mout_sclk_mmc1_user", 2316 ENABLE_SCLK_FSYS, 3, CLK_SET_RATE_PARENT, 0), 2317 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "mout_sclk_mmc0_user", 2318 ENABLE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0), 2319 GATE(CLK_SCLK_USBHOST30, "sclk_usbhost30", "mout_sclk_usbhost30_user", 2320 ENABLE_SCLK_FSYS, 1, 0, 0), 2321 GATE(CLK_SCLK_USBDRD30, "sclk_usbdrd30", "mout_sclk_usbdrd30_user", 2322 ENABLE_SCLK_FSYS, 0, 0, 0), 2323 2324 /* ENABLE_IP_FSYS0 */ 2325 GATE(CLK_PCIE, "pcie", "sclk_pcie_100", ENABLE_IP_FSYS0, 17, 0, 0), 2326 GATE(CLK_PDMA1, "pdma1", "aclk_pdma1", ENABLE_IP_FSYS0, 15, 0, 0), 2327 GATE(CLK_PDMA0, "pdma0", "aclk_pdma0", ENABLE_IP_FSYS0, 0, 0, 0), 2328 }; 2329 2330 static const struct samsung_cmu_info fsys_cmu_info __initconst = { 2331 .mux_clks = fsys_mux_clks, 2332 .nr_mux_clks = ARRAY_SIZE(fsys_mux_clks), 2333 .gate_clks = fsys_gate_clks, 2334 .nr_gate_clks = ARRAY_SIZE(fsys_gate_clks), 2335 .fixed_clks = fsys_fixed_clks, 2336 .nr_fixed_clks = ARRAY_SIZE(fsys_fixed_clks), 2337 .nr_clk_ids = FSYS_NR_CLK, 2338 .clk_regs = fsys_clk_regs, 2339 .nr_clk_regs = ARRAY_SIZE(fsys_clk_regs), 2340 .suspend_regs = fsys_suspend_regs, 2341 .nr_suspend_regs = ARRAY_SIZE(fsys_suspend_regs), 2342 .clk_name = "aclk_fsys_200", 2343 }; 2344 2345 /* 2346 * Register offset definitions for CMU_G2D 2347 */ 2348 #define MUX_SEL_G2D0 0x0200 2349 #define MUX_SEL_ENABLE_G2D0 0x0300 2350 #define MUX_SEL_STAT_G2D0 0x0400 2351 #define DIV_G2D 0x0600 2352 #define DIV_STAT_G2D 0x0700 2353 #define DIV_ENABLE_ACLK_G2D 0x0800 2354 #define DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D 0x0804 2355 #define DIV_ENABLE_PCLK_G2D 0x0900 2356 #define DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D 0x0904 2357 #define DIV_ENABLE_IP_G2D0 0x0b00 2358 #define DIV_ENABLE_IP_G2D1 0x0b04 2359 #define DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D 0x0b08 2360 2361 static const unsigned long g2d_clk_regs[] __initconst = { 2362 MUX_SEL_G2D0, 2363 MUX_SEL_ENABLE_G2D0, 2364 DIV_G2D, 2365 DIV_ENABLE_ACLK_G2D, 2366 DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D, 2367 DIV_ENABLE_PCLK_G2D, 2368 DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D, 2369 DIV_ENABLE_IP_G2D0, 2370 DIV_ENABLE_IP_G2D1, 2371 DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D, 2372 }; 2373 2374 static const struct samsung_clk_reg_dump g2d_suspend_regs[] = { 2375 { MUX_SEL_G2D0, 0 }, 2376 }; 2377 2378 /* list of all parent clock list */ 2379 PNAME(mout_aclk_g2d_266_user_p) = { "oscclk", "aclk_g2d_266", }; 2380 PNAME(mout_aclk_g2d_400_user_p) = { "oscclk", "aclk_g2d_400", }; 2381 2382 static const struct samsung_mux_clock g2d_mux_clks[] __initconst = { 2383 /* MUX_SEL_G2D0 */ 2384 MUX(CLK_MUX_ACLK_G2D_266_USER, "mout_aclk_g2d_266_user", 2385 mout_aclk_g2d_266_user_p, MUX_SEL_G2D0, 4, 1), 2386 MUX(CLK_MUX_ACLK_G2D_400_USER, "mout_aclk_g2d_400_user", 2387 mout_aclk_g2d_400_user_p, MUX_SEL_G2D0, 0, 1), 2388 }; 2389 2390 static const struct samsung_div_clock g2d_div_clks[] __initconst = { 2391 /* DIV_G2D */ 2392 DIV(CLK_DIV_PCLK_G2D, "div_pclk_g2d", "mout_aclk_g2d_266_user", 2393 DIV_G2D, 0, 2), 2394 }; 2395 2396 static const struct samsung_gate_clock g2d_gate_clks[] __initconst = { 2397 /* DIV_ENABLE_ACLK_G2D */ 2398 GATE(CLK_ACLK_SMMU_MDMA1, "aclk_smmu_mdma1", "mout_aclk_g2d_266_user", 2399 DIV_ENABLE_ACLK_G2D, 12, 0, 0), 2400 GATE(CLK_ACLK_BTS_MDMA1, "aclk_bts_mdam1", "mout_aclk_g2d_266_user", 2401 DIV_ENABLE_ACLK_G2D, 11, 0, 0), 2402 GATE(CLK_ACLK_BTS_G2D, "aclk_bts_g2d", "mout_aclk_g2d_400_user", 2403 DIV_ENABLE_ACLK_G2D, 10, 0, 0), 2404 GATE(CLK_ACLK_ALB_G2D, "aclk_alb_g2d", "mout_aclk_g2d_400_user", 2405 DIV_ENABLE_ACLK_G2D, 9, 0, 0), 2406 GATE(CLK_ACLK_AXIUS_G2DX, "aclk_axius_g2dx", "mout_aclk_g2d_400_user", 2407 DIV_ENABLE_ACLK_G2D, 8, 0, 0), 2408 GATE(CLK_ACLK_ASYNCAXI_SYSX, "aclk_asyncaxi_sysx", 2409 "mout_aclk_g2d_400_user", DIV_ENABLE_ACLK_G2D, 2410 7, 0, 0), 2411 GATE(CLK_ACLK_AHB2APB_G2D1P, "aclk_ahb2apb_g2d1p", "div_pclk_g2d", 2412 DIV_ENABLE_ACLK_G2D, 6, CLK_IGNORE_UNUSED, 0), 2413 GATE(CLK_ACLK_AHB2APB_G2D0P, "aclk_ahb2apb_g2d0p", "div_pclk_g2d", 2414 DIV_ENABLE_ACLK_G2D, 5, CLK_IGNORE_UNUSED, 0), 2415 GATE(CLK_ACLK_XIU_G2DX, "aclk_xiu_g2dx", "mout_aclk_g2d_400_user", 2416 DIV_ENABLE_ACLK_G2D, 4, CLK_IGNORE_UNUSED, 0), 2417 GATE(CLK_ACLK_G2DNP_133, "aclk_g2dnp_133", "div_pclk_g2d", 2418 DIV_ENABLE_ACLK_G2D, 3, CLK_IGNORE_UNUSED, 0), 2419 GATE(CLK_ACLK_G2DND_400, "aclk_g2dnd_400", "mout_aclk_g2d_400_user", 2420 DIV_ENABLE_ACLK_G2D, 2, CLK_IGNORE_UNUSED, 0), 2421 GATE(CLK_ACLK_MDMA1, "aclk_mdma1", "mout_aclk_g2d_266_user", 2422 DIV_ENABLE_ACLK_G2D, 1, 0, 0), 2423 GATE(CLK_ACLK_G2D, "aclk_g2d", "mout_aclk_g2d_400_user", 2424 DIV_ENABLE_ACLK_G2D, 0, 0, 0), 2425 2426 /* DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D */ 2427 GATE(CLK_ACLK_SMMU_G2D, "aclk_smmu_g2d", "mout_aclk_g2d_400_user", 2428 DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D, 0, 0, 0), 2429 2430 /* DIV_ENABLE_PCLK_G2D */ 2431 GATE(CLK_PCLK_SMMU_MDMA1, "pclk_smmu_mdma1", "div_pclk_g2d", 2432 DIV_ENABLE_PCLK_G2D, 7, 0, 0), 2433 GATE(CLK_PCLK_BTS_MDMA1, "pclk_bts_mdam1", "div_pclk_g2d", 2434 DIV_ENABLE_PCLK_G2D, 6, 0, 0), 2435 GATE(CLK_PCLK_BTS_G2D, "pclk_bts_g2d", "div_pclk_g2d", 2436 DIV_ENABLE_PCLK_G2D, 5, 0, 0), 2437 GATE(CLK_PCLK_ALB_G2D, "pclk_alb_g2d", "div_pclk_g2d", 2438 DIV_ENABLE_PCLK_G2D, 4, 0, 0), 2439 GATE(CLK_PCLK_ASYNCAXI_SYSX, "pclk_asyncaxi_sysx", "div_pclk_g2d", 2440 DIV_ENABLE_PCLK_G2D, 3, 0, 0), 2441 GATE(CLK_PCLK_PMU_G2D, "pclk_pmu_g2d", "div_pclk_g2d", 2442 DIV_ENABLE_PCLK_G2D, 2, CLK_IGNORE_UNUSED, 0), 2443 GATE(CLK_PCLK_SYSREG_G2D, "pclk_sysreg_g2d", "div_pclk_g2d", 2444 DIV_ENABLE_PCLK_G2D, 1, CLK_IGNORE_UNUSED, 0), 2445 GATE(CLK_PCLK_G2D, "pclk_g2d", "div_pclk_g2d", DIV_ENABLE_PCLK_G2D, 2446 0, 0, 0), 2447 2448 /* DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D */ 2449 GATE(CLK_PCLK_SMMU_G2D, "pclk_smmu_g2d", "div_pclk_g2d", 2450 DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D, 0, 0, 0), 2451 }; 2452 2453 static const struct samsung_cmu_info g2d_cmu_info __initconst = { 2454 .mux_clks = g2d_mux_clks, 2455 .nr_mux_clks = ARRAY_SIZE(g2d_mux_clks), 2456 .div_clks = g2d_div_clks, 2457 .nr_div_clks = ARRAY_SIZE(g2d_div_clks), 2458 .gate_clks = g2d_gate_clks, 2459 .nr_gate_clks = ARRAY_SIZE(g2d_gate_clks), 2460 .nr_clk_ids = G2D_NR_CLK, 2461 .clk_regs = g2d_clk_regs, 2462 .nr_clk_regs = ARRAY_SIZE(g2d_clk_regs), 2463 .suspend_regs = g2d_suspend_regs, 2464 .nr_suspend_regs = ARRAY_SIZE(g2d_suspend_regs), 2465 .clk_name = "aclk_g2d_400", 2466 }; 2467 2468 /* 2469 * Register offset definitions for CMU_DISP 2470 */ 2471 #define DISP_PLL_LOCK 0x0000 2472 #define DISP_PLL_CON0 0x0100 2473 #define DISP_PLL_CON1 0x0104 2474 #define DISP_PLL_FREQ_DET 0x0108 2475 #define MUX_SEL_DISP0 0x0200 2476 #define MUX_SEL_DISP1 0x0204 2477 #define MUX_SEL_DISP2 0x0208 2478 #define MUX_SEL_DISP3 0x020c 2479 #define MUX_SEL_DISP4 0x0210 2480 #define MUX_ENABLE_DISP0 0x0300 2481 #define MUX_ENABLE_DISP1 0x0304 2482 #define MUX_ENABLE_DISP2 0x0308 2483 #define MUX_ENABLE_DISP3 0x030c 2484 #define MUX_ENABLE_DISP4 0x0310 2485 #define MUX_STAT_DISP0 0x0400 2486 #define MUX_STAT_DISP1 0x0404 2487 #define MUX_STAT_DISP2 0x0408 2488 #define MUX_STAT_DISP3 0x040c 2489 #define MUX_STAT_DISP4 0x0410 2490 #define MUX_IGNORE_DISP2 0x0508 2491 #define DIV_DISP 0x0600 2492 #define DIV_DISP_PLL_FREQ_DET 0x0604 2493 #define DIV_STAT_DISP 0x0700 2494 #define DIV_STAT_DISP_PLL_FREQ_DET 0x0704 2495 #define ENABLE_ACLK_DISP0 0x0800 2496 #define ENABLE_ACLK_DISP1 0x0804 2497 #define ENABLE_PCLK_DISP 0x0900 2498 #define ENABLE_SCLK_DISP 0x0a00 2499 #define ENABLE_IP_DISP0 0x0b00 2500 #define ENABLE_IP_DISP1 0x0b04 2501 #define CLKOUT_CMU_DISP 0x0c00 2502 #define CLKOUT_CMU_DISP_DIV_STAT 0x0c04 2503 2504 static const unsigned long disp_clk_regs[] __initconst = { 2505 DISP_PLL_LOCK, 2506 DISP_PLL_CON0, 2507 DISP_PLL_CON1, 2508 DISP_PLL_FREQ_DET, 2509 MUX_SEL_DISP0, 2510 MUX_SEL_DISP1, 2511 MUX_SEL_DISP2, 2512 MUX_SEL_DISP3, 2513 MUX_SEL_DISP4, 2514 MUX_ENABLE_DISP0, 2515 MUX_ENABLE_DISP1, 2516 MUX_ENABLE_DISP2, 2517 MUX_ENABLE_DISP3, 2518 MUX_ENABLE_DISP4, 2519 MUX_IGNORE_DISP2, 2520 DIV_DISP, 2521 DIV_DISP_PLL_FREQ_DET, 2522 ENABLE_ACLK_DISP0, 2523 ENABLE_ACLK_DISP1, 2524 ENABLE_PCLK_DISP, 2525 ENABLE_SCLK_DISP, 2526 ENABLE_IP_DISP0, 2527 ENABLE_IP_DISP1, 2528 CLKOUT_CMU_DISP, 2529 CLKOUT_CMU_DISP_DIV_STAT, 2530 }; 2531 2532 static const struct samsung_clk_reg_dump disp_suspend_regs[] = { 2533 /* PLL has to be enabled for suspend */ 2534 { DISP_PLL_CON0, 0x85f40502 }, 2535 /* ignore status of external PHY muxes during suspend to avoid hangs */ 2536 { MUX_IGNORE_DISP2, 0x00111111 }, 2537 { MUX_SEL_DISP0, 0 }, 2538 { MUX_SEL_DISP1, 0 }, 2539 { MUX_SEL_DISP2, 0 }, 2540 { MUX_SEL_DISP3, 0 }, 2541 { MUX_SEL_DISP4, 0 }, 2542 }; 2543 2544 /* list of all parent clock list */ 2545 PNAME(mout_disp_pll_p) = { "oscclk", "fout_disp_pll", }; 2546 PNAME(mout_sclk_dsim1_user_p) = { "oscclk", "sclk_dsim1_disp", }; 2547 PNAME(mout_sclk_dsim0_user_p) = { "oscclk", "sclk_dsim0_disp", }; 2548 PNAME(mout_sclk_dsd_user_p) = { "oscclk", "sclk_dsd_disp", }; 2549 PNAME(mout_sclk_decon_tv_eclk_user_p) = { "oscclk", 2550 "sclk_decon_tv_eclk_disp", }; 2551 PNAME(mout_sclk_decon_vclk_user_p) = { "oscclk", 2552 "sclk_decon_vclk_disp", }; 2553 PNAME(mout_sclk_decon_eclk_user_p) = { "oscclk", 2554 "sclk_decon_eclk_disp", }; 2555 PNAME(mout_sclk_decon_tv_vlkc_user_p) = { "oscclk", 2556 "sclk_decon_tv_vclk_disp", }; 2557 PNAME(mout_aclk_disp_333_user_p) = { "oscclk", "aclk_disp_333", }; 2558 2559 PNAME(mout_phyclk_mipidphy1_bitclkdiv8_user_p) = { "oscclk", 2560 "phyclk_mipidphy1_bitclkdiv8_phy", }; 2561 PNAME(mout_phyclk_mipidphy1_rxclkesc0_user_p) = { "oscclk", 2562 "phyclk_mipidphy1_rxclkesc0_phy", }; 2563 PNAME(mout_phyclk_mipidphy0_bitclkdiv8_user_p) = { "oscclk", 2564 "phyclk_mipidphy0_bitclkdiv8_phy", }; 2565 PNAME(mout_phyclk_mipidphy0_rxclkesc0_user_p) = { "oscclk", 2566 "phyclk_mipidphy0_rxclkesc0_phy", }; 2567 PNAME(mout_phyclk_hdmiphy_tmds_clko_user_p) = { "oscclk", 2568 "phyclk_hdmiphy_tmds_clko_phy", }; 2569 PNAME(mout_phyclk_hdmiphy_pixel_clko_user_p) = { "oscclk", 2570 "phyclk_hdmiphy_pixel_clko_phy", }; 2571 2572 PNAME(mout_sclk_dsim0_p) = { "mout_disp_pll", 2573 "mout_sclk_dsim0_user", }; 2574 PNAME(mout_sclk_decon_tv_eclk_p) = { "mout_disp_pll", 2575 "mout_sclk_decon_tv_eclk_user", }; 2576 PNAME(mout_sclk_decon_vclk_p) = { "mout_disp_pll", 2577 "mout_sclk_decon_vclk_user", }; 2578 PNAME(mout_sclk_decon_eclk_p) = { "mout_disp_pll", 2579 "mout_sclk_decon_eclk_user", }; 2580 2581 PNAME(mout_sclk_dsim1_b_disp_p) = { "mout_sclk_dsim1_a_disp", 2582 "mout_sclk_dsim1_user", }; 2583 PNAME(mout_sclk_decon_tv_vclk_c_disp_p) = { 2584 "mout_phyclk_hdmiphy_pixel_clko_user", 2585 "mout_sclk_decon_tv_vclk_b_disp", }; 2586 PNAME(mout_sclk_decon_tv_vclk_b_disp_p) = { "mout_sclk_decon_tv_vclk_a_disp", 2587 "mout_sclk_decon_tv_vclk_user", }; 2588 2589 static const struct samsung_pll_clock disp_pll_clks[] __initconst = { 2590 PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll", "oscclk", 2591 DISP_PLL_LOCK, DISP_PLL_CON0, exynos5433_pll_rates), 2592 }; 2593 2594 static const struct samsung_fixed_factor_clock disp_fixed_factor_clks[] __initconst = { 2595 /* 2596 * sclk_rgb_{vclk|tv_vclk} is half clock of sclk_decon_{vclk|tv_vclk}. 2597 * The divider has fixed value (2) between sclk_rgb_{vclk|tv_vclk} 2598 * and sclk_decon_{vclk|tv_vclk}. 2599 */ 2600 FFACTOR(CLK_SCLK_RGB_VCLK, "sclk_rgb_vclk", "sclk_decon_vclk", 2601 1, 2, 0), 2602 FFACTOR(CLK_SCLK_RGB_TV_VCLK, "sclk_rgb_tv_vclk", "sclk_decon_tv_vclk", 2603 1, 2, 0), 2604 }; 2605 2606 static const struct samsung_fixed_rate_clock disp_fixed_clks[] __initconst = { 2607 /* PHY clocks from MIPI_DPHY1 */ 2608 FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, 0, 188000000), 2609 FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, 0, 100000000), 2610 /* PHY clocks from MIPI_DPHY0 */ 2611 FRATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY, "phyclk_mipidphy0_bitclkdiv8_phy", 2612 NULL, 0, 188000000), 2613 FRATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY, "phyclk_mipidphy0_rxclkesc0_phy", 2614 NULL, 0, 100000000), 2615 /* PHY clocks from HDMI_PHY */ 2616 FRATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY, "phyclk_hdmiphy_tmds_clko_phy", 2617 NULL, 0, 300000000), 2618 FRATE(CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY, "phyclk_hdmiphy_pixel_clko_phy", 2619 NULL, 0, 166000000), 2620 }; 2621 2622 static const struct samsung_mux_clock disp_mux_clks[] __initconst = { 2623 /* MUX_SEL_DISP0 */ 2624 MUX(CLK_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p, MUX_SEL_DISP0, 2625 0, 1), 2626 2627 /* MUX_SEL_DISP1 */ 2628 MUX(CLK_MOUT_SCLK_DSIM1_USER, "mout_sclk_dsim1_user", 2629 mout_sclk_dsim1_user_p, MUX_SEL_DISP1, 28, 1), 2630 MUX(CLK_MOUT_SCLK_DSIM0_USER, "mout_sclk_dsim0_user", 2631 mout_sclk_dsim0_user_p, MUX_SEL_DISP1, 24, 1), 2632 MUX(CLK_MOUT_SCLK_DSD_USER, "mout_sclk_dsd_user", mout_sclk_dsd_user_p, 2633 MUX_SEL_DISP1, 20, 1), 2634 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_USER, "mout_sclk_decon_tv_eclk_user", 2635 mout_sclk_decon_tv_eclk_user_p, MUX_SEL_DISP1, 16, 1), 2636 MUX(CLK_MOUT_SCLK_DECON_VCLK_USER, "mout_sclk_decon_vclk_user", 2637 mout_sclk_decon_vclk_user_p, MUX_SEL_DISP1, 12, 1), 2638 MUX(CLK_MOUT_SCLK_DECON_ECLK_USER, "mout_sclk_decon_eclk_user", 2639 mout_sclk_decon_eclk_user_p, MUX_SEL_DISP1, 8, 1), 2640 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_USER, "mout_sclk_decon_tv_vclk_user", 2641 mout_sclk_decon_tv_vlkc_user_p, MUX_SEL_DISP1, 4, 1), 2642 MUX(CLK_MOUT_ACLK_DISP_333_USER, "mout_aclk_disp_333_user", 2643 mout_aclk_disp_333_user_p, MUX_SEL_DISP1, 0, 1), 2644 2645 /* MUX_SEL_DISP2 */ 2646 MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER, 2647 "mout_phyclk_mipidphy1_bitclkdiv8_user", 2648 mout_phyclk_mipidphy1_bitclkdiv8_user_p, MUX_SEL_DISP2, 2649 20, 1), 2650 MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER, 2651 "mout_phyclk_mipidphy1_rxclkesc0_user", 2652 mout_phyclk_mipidphy1_rxclkesc0_user_p, MUX_SEL_DISP2, 2653 16, 1), 2654 MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER, 2655 "mout_phyclk_mipidphy0_bitclkdiv8_user", 2656 mout_phyclk_mipidphy0_bitclkdiv8_user_p, MUX_SEL_DISP2, 2657 12, 1), 2658 MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER, 2659 "mout_phyclk_mipidphy0_rxclkesc0_user", 2660 mout_phyclk_mipidphy0_rxclkesc0_user_p, MUX_SEL_DISP2, 2661 8, 1), 2662 MUX(CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER, 2663 "mout_phyclk_hdmiphy_tmds_clko_user", 2664 mout_phyclk_hdmiphy_tmds_clko_user_p, MUX_SEL_DISP2, 2665 4, 1), 2666 MUX(CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER, 2667 "mout_phyclk_hdmiphy_pixel_clko_user", 2668 mout_phyclk_hdmiphy_pixel_clko_user_p, MUX_SEL_DISP2, 2669 0, 1), 2670 2671 /* MUX_SEL_DISP3 */ 2672 MUX(CLK_MOUT_SCLK_DSIM0, "mout_sclk_dsim0", mout_sclk_dsim0_p, 2673 MUX_SEL_DISP3, 12, 1), 2674 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK, "mout_sclk_decon_tv_eclk", 2675 mout_sclk_decon_tv_eclk_p, MUX_SEL_DISP3, 8, 1), 2676 MUX(CLK_MOUT_SCLK_DECON_VCLK, "mout_sclk_decon_vclk", 2677 mout_sclk_decon_vclk_p, MUX_SEL_DISP3, 4, 1), 2678 MUX(CLK_MOUT_SCLK_DECON_ECLK, "mout_sclk_decon_eclk", 2679 mout_sclk_decon_eclk_p, MUX_SEL_DISP3, 0, 1), 2680 2681 /* MUX_SEL_DISP4 */ 2682 MUX(CLK_MOUT_SCLK_DSIM1_B_DISP, "mout_sclk_dsim1_b_disp", 2683 mout_sclk_dsim1_b_disp_p, MUX_SEL_DISP4, 16, 1), 2684 MUX(CLK_MOUT_SCLK_DSIM1_A_DISP, "mout_sclk_dsim1_a_disp", 2685 mout_sclk_dsim0_p, MUX_SEL_DISP4, 12, 1), 2686 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP, 2687 "mout_sclk_decon_tv_vclk_c_disp", 2688 mout_sclk_decon_tv_vclk_c_disp_p, MUX_SEL_DISP4, 8, 1), 2689 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP, 2690 "mout_sclk_decon_tv_vclk_b_disp", 2691 mout_sclk_decon_tv_vclk_b_disp_p, MUX_SEL_DISP4, 4, 1), 2692 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP, 2693 "mout_sclk_decon_tv_vclk_a_disp", 2694 mout_sclk_decon_vclk_p, MUX_SEL_DISP4, 0, 1), 2695 }; 2696 2697 static const struct samsung_div_clock disp_div_clks[] __initconst = { 2698 /* DIV_DISP */ 2699 DIV(CLK_DIV_SCLK_DSIM1_DISP, "div_sclk_dsim1_disp", 2700 "mout_sclk_dsim1_b_disp", DIV_DISP, 24, 3), 2701 DIV(CLK_DIV_SCLK_DECON_TV_VCLK_DISP, "div_sclk_decon_tv_vclk_disp", 2702 "mout_sclk_decon_tv_vclk_c_disp", DIV_DISP, 20, 3), 2703 DIV(CLK_DIV_SCLK_DSIM0_DISP, "div_sclk_dsim0_disp", "mout_sclk_dsim0", 2704 DIV_DISP, 16, 3), 2705 DIV(CLK_DIV_SCLK_DECON_TV_ECLK_DISP, "div_sclk_decon_tv_eclk_disp", 2706 "mout_sclk_decon_tv_eclk", DIV_DISP, 12, 3), 2707 DIV(CLK_DIV_SCLK_DECON_VCLK_DISP, "div_sclk_decon_vclk_disp", 2708 "mout_sclk_decon_vclk", DIV_DISP, 8, 3), 2709 DIV(CLK_DIV_SCLK_DECON_ECLK_DISP, "div_sclk_decon_eclk_disp", 2710 "mout_sclk_decon_eclk", DIV_DISP, 4, 3), 2711 DIV(CLK_DIV_PCLK_DISP, "div_pclk_disp", "mout_aclk_disp_333_user", 2712 DIV_DISP, 0, 2), 2713 }; 2714 2715 static const struct samsung_gate_clock disp_gate_clks[] __initconst = { 2716 /* ENABLE_ACLK_DISP0 */ 2717 GATE(CLK_ACLK_DECON_TV, "aclk_decon_tv", "mout_aclk_disp_333_user", 2718 ENABLE_ACLK_DISP0, 2, 0, 0), 2719 GATE(CLK_ACLK_DECON, "aclk_decon", "mout_aclk_disp_333_user", 2720 ENABLE_ACLK_DISP0, 0, 0, 0), 2721 2722 /* ENABLE_ACLK_DISP1 */ 2723 GATE(CLK_ACLK_SMMU_TV1X, "aclk_smmu_tv1x", "mout_aclk_disp_333_user", 2724 ENABLE_ACLK_DISP1, 25, 0, 0), 2725 GATE(CLK_ACLK_SMMU_TV0X, "aclk_smmu_tv0x", "mout_aclk_disp_333_user", 2726 ENABLE_ACLK_DISP1, 24, 0, 0), 2727 GATE(CLK_ACLK_SMMU_DECON1X, "aclk_smmu_decon1x", 2728 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 23, 0, 0), 2729 GATE(CLK_ACLK_SMMU_DECON0X, "aclk_smmu_decon0x", 2730 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 22, 0, 0), 2731 GATE(CLK_ACLK_BTS_DECON_TV_M3, "aclk_bts_decon_tv_m3", 2732 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 21, 0, 0), 2733 GATE(CLK_ACLK_BTS_DECON_TV_M2, "aclk_bts_decon_tv_m2", 2734 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 20, 0, 0), 2735 GATE(CLK_ACLK_BTS_DECON_TV_M1, "aclk_bts_decon_tv_m1", 2736 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 19, 0, 0), 2737 GATE(CLK_ACLK_BTS_DECON_TV_M0, "aclk-bts_decon_tv_m0", 2738 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 18, 0, 0), 2739 GATE(CLK_ACLK_BTS_DECON_NM4, "aclk_bts_decon_nm4", 2740 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 17, 0, 0), 2741 GATE(CLK_ACLK_BTS_DECON_NM3, "aclk_bts_decon_nm3", 2742 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 16, 0, 0), 2743 GATE(CLK_ACLK_BTS_DECON_NM2, "aclk_bts_decon_nm2", 2744 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 15, 0, 0), 2745 GATE(CLK_ACLK_BTS_DECON_NM1, "aclk_bts_decon_nm1", 2746 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 14, 0, 0), 2747 GATE(CLK_ACLK_BTS_DECON_NM0, "aclk_bts_decon_nm0", 2748 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 13, 0, 0), 2749 GATE(CLK_ACLK_AHB2APB_DISPSFR2P, "aclk_ahb2apb_dispsfr2p", 2750 "div_pclk_disp", ENABLE_ACLK_DISP1, 2751 12, CLK_IGNORE_UNUSED, 0), 2752 GATE(CLK_ACLK_AHB2APB_DISPSFR1P, "aclk_ahb2apb_dispsfr1p", 2753 "div_pclk_disp", ENABLE_ACLK_DISP1, 2754 11, CLK_IGNORE_UNUSED, 0), 2755 GATE(CLK_ACLK_AHB2APB_DISPSFR0P, "aclk_ahb2apb_dispsfr0p", 2756 "div_pclk_disp", ENABLE_ACLK_DISP1, 2757 10, CLK_IGNORE_UNUSED, 0), 2758 GATE(CLK_ACLK_AHB_DISPH, "aclk_ahb_disph", "div_pclk_disp", 2759 ENABLE_ACLK_DISP1, 8, CLK_IGNORE_UNUSED, 0), 2760 GATE(CLK_ACLK_XIU_TV1X, "aclk_xiu_tv1x", "mout_aclk_disp_333_user", 2761 ENABLE_ACLK_DISP1, 7, 0, 0), 2762 GATE(CLK_ACLK_XIU_TV0X, "aclk_xiu_tv0x", "mout_aclk_disp_333_user", 2763 ENABLE_ACLK_DISP1, 6, 0, 0), 2764 GATE(CLK_ACLK_XIU_DECON1X, "aclk_xiu_decon1x", 2765 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 5, 0, 0), 2766 GATE(CLK_ACLK_XIU_DECON0X, "aclk_xiu_decon0x", 2767 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 4, 0, 0), 2768 GATE(CLK_ACLK_XIU_DISP1X, "aclk_xiu_disp1x", "mout_aclk_disp_333_user", 2769 ENABLE_ACLK_DISP1, 3, CLK_IGNORE_UNUSED, 0), 2770 GATE(CLK_ACLK_XIU_DISPNP_100, "aclk_xiu_dispnp_100", "div_pclk_disp", 2771 ENABLE_ACLK_DISP1, 2, CLK_IGNORE_UNUSED, 0), 2772 GATE(CLK_ACLK_DISP1ND_333, "aclk_disp1nd_333", 2773 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 1, 2774 CLK_IGNORE_UNUSED, 0), 2775 GATE(CLK_ACLK_DISP0ND_333, "aclk_disp0nd_333", 2776 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 2777 0, CLK_IGNORE_UNUSED, 0), 2778 2779 /* ENABLE_PCLK_DISP */ 2780 GATE(CLK_PCLK_SMMU_TV1X, "pclk_smmu_tv1x", "div_pclk_disp", 2781 ENABLE_PCLK_DISP, 23, 0, 0), 2782 GATE(CLK_PCLK_SMMU_TV0X, "pclk_smmu_tv0x", "div_pclk_disp", 2783 ENABLE_PCLK_DISP, 22, 0, 0), 2784 GATE(CLK_PCLK_SMMU_DECON1X, "pclk_smmu_decon1x", "div_pclk_disp", 2785 ENABLE_PCLK_DISP, 21, 0, 0), 2786 GATE(CLK_PCLK_SMMU_DECON0X, "pclk_smmu_decon0x", "div_pclk_disp", 2787 ENABLE_PCLK_DISP, 20, 0, 0), 2788 GATE(CLK_PCLK_BTS_DECON_TV_M3, "pclk_bts_decon_tv_m3", "div_pclk_disp", 2789 ENABLE_PCLK_DISP, 19, 0, 0), 2790 GATE(CLK_PCLK_BTS_DECON_TV_M2, "pclk_bts_decon_tv_m2", "div_pclk_disp", 2791 ENABLE_PCLK_DISP, 18, 0, 0), 2792 GATE(CLK_PCLK_BTS_DECON_TV_M1, "pclk_bts_decon_tv_m1", "div_pclk_disp", 2793 ENABLE_PCLK_DISP, 17, 0, 0), 2794 GATE(CLK_PCLK_BTS_DECON_TV_M0, "pclk_bts_decon_tv_m0", "div_pclk_disp", 2795 ENABLE_PCLK_DISP, 16, 0, 0), 2796 GATE(CLK_PCLK_BTS_DECONM4, "pclk_bts_deconm4", "div_pclk_disp", 2797 ENABLE_PCLK_DISP, 15, 0, 0), 2798 GATE(CLK_PCLK_BTS_DECONM3, "pclk_bts_deconm3", "div_pclk_disp", 2799 ENABLE_PCLK_DISP, 14, 0, 0), 2800 GATE(CLK_PCLK_BTS_DECONM2, "pclk_bts_deconm2", "div_pclk_disp", 2801 ENABLE_PCLK_DISP, 13, 0, 0), 2802 GATE(CLK_PCLK_BTS_DECONM1, "pclk_bts_deconm1", "div_pclk_disp", 2803 ENABLE_PCLK_DISP, 12, 0, 0), 2804 GATE(CLK_PCLK_BTS_DECONM0, "pclk_bts_deconm0", "div_pclk_disp", 2805 ENABLE_PCLK_DISP, 11, 0, 0), 2806 GATE(CLK_PCLK_MIC1, "pclk_mic1", "div_pclk_disp", 2807 ENABLE_PCLK_DISP, 10, 0, 0), 2808 GATE(CLK_PCLK_PMU_DISP, "pclk_pmu_disp", "div_pclk_disp", 2809 ENABLE_PCLK_DISP, 9, CLK_IGNORE_UNUSED, 0), 2810 GATE(CLK_PCLK_SYSREG_DISP, "pclk_sysreg_disp", "div_pclk_disp", 2811 ENABLE_PCLK_DISP, 8, CLK_IGNORE_UNUSED, 0), 2812 GATE(CLK_PCLK_HDMIPHY, "pclk_hdmiphy", "div_pclk_disp", 2813 ENABLE_PCLK_DISP, 7, 0, 0), 2814 GATE(CLK_PCLK_HDMI, "pclk_hdmi", "div_pclk_disp", 2815 ENABLE_PCLK_DISP, 6, 0, 0), 2816 GATE(CLK_PCLK_MIC0, "pclk_mic0", "div_pclk_disp", 2817 ENABLE_PCLK_DISP, 5, 0, 0), 2818 GATE(CLK_PCLK_DSIM1, "pclk_dsim1", "div_pclk_disp", 2819 ENABLE_PCLK_DISP, 3, 0, 0), 2820 GATE(CLK_PCLK_DSIM0, "pclk_dsim0", "div_pclk_disp", 2821 ENABLE_PCLK_DISP, 2, 0, 0), 2822 GATE(CLK_PCLK_DECON_TV, "pclk_decon_tv", "div_pclk_disp", 2823 ENABLE_PCLK_DISP, 1, 0, 0), 2824 GATE(CLK_PCLK_DECON, "pclk_decon", "div_pclk_disp", 2825 ENABLE_PCLK_DISP, 0, 0, 0), 2826 2827 /* ENABLE_SCLK_DISP */ 2828 GATE(CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8, "phyclk_mipidphy1_bitclkdiv8", 2829 "mout_phyclk_mipidphy1_bitclkdiv8_user", 2830 ENABLE_SCLK_DISP, 26, 0, 0), 2831 GATE(CLK_PHYCLK_MIPIDPHY1_RXCLKESC0, "phyclk_mipidphy1_rxclkesc0", 2832 "mout_phyclk_mipidphy1_rxclkesc0_user", 2833 ENABLE_SCLK_DISP, 25, 0, 0), 2834 GATE(CLK_SCLK_RGB_TV_VCLK_TO_DSIM1, "sclk_rgb_tv_vclk_to_dsim1", 2835 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 24, 0, 0), 2836 GATE(CLK_SCLK_RGB_TV_VCLK_TO_MIC1, "sclk_rgb_tv_vclk_to_mic1", 2837 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 23, 0, 0), 2838 GATE(CLK_SCLK_DSIM1, "sclk_dsim1", "div_sclk_dsim1_disp", 2839 ENABLE_SCLK_DISP, 22, 0, 0), 2840 GATE(CLK_SCLK_DECON_TV_VCLK, "sclk_decon_tv_vclk", 2841 "div_sclk_decon_tv_vclk_disp", 2842 ENABLE_SCLK_DISP, 21, 0, 0), 2843 GATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8, "phyclk_mipidphy0_bitclkdiv8", 2844 "mout_phyclk_mipidphy0_bitclkdiv8_user", 2845 ENABLE_SCLK_DISP, 15, 0, 0), 2846 GATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0, "phyclk_mipidphy0_rxclkesc0", 2847 "mout_phyclk_mipidphy0_rxclkesc0_user", 2848 ENABLE_SCLK_DISP, 14, 0, 0), 2849 GATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO, "phyclk_hdmiphy_tmds_clko", 2850 "mout_phyclk_hdmiphy_tmds_clko_user", 2851 ENABLE_SCLK_DISP, 13, 0, 0), 2852 GATE(CLK_PHYCLK_HDMI_PIXEL, "phyclk_hdmi_pixel", 2853 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 12, 0, 0), 2854 GATE(CLK_SCLK_RGB_VCLK_TO_SMIES, "sclk_rgb_vclk_to_smies", 2855 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 11, 0, 0), 2856 GATE(CLK_SCLK_RGB_VCLK_TO_DSIM0, "sclk_rgb_vclk_to_dsim0", 2857 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 9, 0, 0), 2858 GATE(CLK_SCLK_RGB_VCLK_TO_MIC0, "sclk_rgb_vclk_to_mic0", 2859 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 8, 0, 0), 2860 GATE(CLK_SCLK_DSD, "sclk_dsd", "mout_sclk_dsd_user", 2861 ENABLE_SCLK_DISP, 7, 0, 0), 2862 GATE(CLK_SCLK_HDMI_SPDIF, "sclk_hdmi_spdif", "sclk_hdmi_spdif_disp", 2863 ENABLE_SCLK_DISP, 6, 0, 0), 2864 GATE(CLK_SCLK_DSIM0, "sclk_dsim0", "div_sclk_dsim0_disp", 2865 ENABLE_SCLK_DISP, 5, 0, 0), 2866 GATE(CLK_SCLK_DECON_TV_ECLK, "sclk_decon_tv_eclk", 2867 "div_sclk_decon_tv_eclk_disp", 2868 ENABLE_SCLK_DISP, 4, 0, 0), 2869 GATE(CLK_SCLK_DECON_VCLK, "sclk_decon_vclk", 2870 "div_sclk_decon_vclk_disp", ENABLE_SCLK_DISP, 3, 0, 0), 2871 GATE(CLK_SCLK_DECON_ECLK, "sclk_decon_eclk", 2872 "div_sclk_decon_eclk_disp", ENABLE_SCLK_DISP, 2, 0, 0), 2873 }; 2874 2875 static const struct samsung_cmu_info disp_cmu_info __initconst = { 2876 .pll_clks = disp_pll_clks, 2877 .nr_pll_clks = ARRAY_SIZE(disp_pll_clks), 2878 .mux_clks = disp_mux_clks, 2879 .nr_mux_clks = ARRAY_SIZE(disp_mux_clks), 2880 .div_clks = disp_div_clks, 2881 .nr_div_clks = ARRAY_SIZE(disp_div_clks), 2882 .gate_clks = disp_gate_clks, 2883 .nr_gate_clks = ARRAY_SIZE(disp_gate_clks), 2884 .fixed_clks = disp_fixed_clks, 2885 .nr_fixed_clks = ARRAY_SIZE(disp_fixed_clks), 2886 .fixed_factor_clks = disp_fixed_factor_clks, 2887 .nr_fixed_factor_clks = ARRAY_SIZE(disp_fixed_factor_clks), 2888 .nr_clk_ids = DISP_NR_CLK, 2889 .clk_regs = disp_clk_regs, 2890 .nr_clk_regs = ARRAY_SIZE(disp_clk_regs), 2891 .suspend_regs = disp_suspend_regs, 2892 .nr_suspend_regs = ARRAY_SIZE(disp_suspend_regs), 2893 .clk_name = "aclk_disp_333", 2894 }; 2895 2896 /* 2897 * Register offset definitions for CMU_AUD 2898 */ 2899 #define MUX_SEL_AUD0 0x0200 2900 #define MUX_SEL_AUD1 0x0204 2901 #define MUX_ENABLE_AUD0 0x0300 2902 #define MUX_ENABLE_AUD1 0x0304 2903 #define MUX_STAT_AUD0 0x0400 2904 #define DIV_AUD0 0x0600 2905 #define DIV_AUD1 0x0604 2906 #define DIV_STAT_AUD0 0x0700 2907 #define DIV_STAT_AUD1 0x0704 2908 #define ENABLE_ACLK_AUD 0x0800 2909 #define ENABLE_PCLK_AUD 0x0900 2910 #define ENABLE_SCLK_AUD0 0x0a00 2911 #define ENABLE_SCLK_AUD1 0x0a04 2912 #define ENABLE_IP_AUD0 0x0b00 2913 #define ENABLE_IP_AUD1 0x0b04 2914 2915 static const unsigned long aud_clk_regs[] __initconst = { 2916 MUX_SEL_AUD0, 2917 MUX_SEL_AUD1, 2918 MUX_ENABLE_AUD0, 2919 MUX_ENABLE_AUD1, 2920 DIV_AUD0, 2921 DIV_AUD1, 2922 ENABLE_ACLK_AUD, 2923 ENABLE_PCLK_AUD, 2924 ENABLE_SCLK_AUD0, 2925 ENABLE_SCLK_AUD1, 2926 ENABLE_IP_AUD0, 2927 ENABLE_IP_AUD1, 2928 }; 2929 2930 static const struct samsung_clk_reg_dump aud_suspend_regs[] = { 2931 { MUX_SEL_AUD0, 0 }, 2932 { MUX_SEL_AUD1, 0 }, 2933 }; 2934 2935 /* list of all parent clock list */ 2936 PNAME(mout_aud_pll_user_aud_p) = { "oscclk", "fout_aud_pll", }; 2937 PNAME(mout_sclk_aud_pcm_p) = { "mout_aud_pll_user", "ioclk_audiocdclk0",}; 2938 2939 static const struct samsung_fixed_rate_clock aud_fixed_clks[] __initconst = { 2940 FRATE(0, "ioclk_jtag_tclk", NULL, 0, 33000000), 2941 FRATE(0, "ioclk_slimbus_clk", NULL, 0, 25000000), 2942 FRATE(0, "ioclk_i2s_bclk", NULL, 0, 50000000), 2943 }; 2944 2945 static const struct samsung_mux_clock aud_mux_clks[] __initconst = { 2946 /* MUX_SEL_AUD0 */ 2947 MUX(CLK_MOUT_AUD_PLL_USER, "mout_aud_pll_user", 2948 mout_aud_pll_user_aud_p, MUX_SEL_AUD0, 0, 1), 2949 2950 /* MUX_SEL_AUD1 */ 2951 MUX(CLK_MOUT_SCLK_AUD_PCM, "mout_sclk_aud_pcm", mout_sclk_aud_pcm_p, 2952 MUX_SEL_AUD1, 8, 1), 2953 MUX(CLK_MOUT_SCLK_AUD_I2S, "mout_sclk_aud_i2s", mout_sclk_aud_pcm_p, 2954 MUX_SEL_AUD1, 0, 1), 2955 }; 2956 2957 static const struct samsung_div_clock aud_div_clks[] __initconst = { 2958 /* DIV_AUD0 */ 2959 DIV(CLK_DIV_ATCLK_AUD, "div_atclk_aud", "div_aud_ca5", DIV_AUD0, 2960 12, 4), 2961 DIV(CLK_DIV_PCLK_DBG_AUD, "div_pclk_dbg_aud", "div_aud_ca5", DIV_AUD0, 2962 8, 4), 2963 DIV(CLK_DIV_ACLK_AUD, "div_aclk_aud", "div_aud_ca5", DIV_AUD0, 2964 4, 4), 2965 DIV(CLK_DIV_AUD_CA5, "div_aud_ca5", "mout_aud_pll_user", DIV_AUD0, 2966 0, 4), 2967 2968 /* DIV_AUD1 */ 2969 DIV(CLK_DIV_SCLK_AUD_SLIMBUS, "div_sclk_aud_slimbus", 2970 "mout_aud_pll_user", DIV_AUD1, 16, 5), 2971 DIV(CLK_DIV_SCLK_AUD_UART, "div_sclk_aud_uart", "mout_aud_pll_user", 2972 DIV_AUD1, 12, 4), 2973 DIV(CLK_DIV_SCLK_AUD_PCM, "div_sclk_aud_pcm", "mout_sclk_aud_pcm", 2974 DIV_AUD1, 4, 8), 2975 DIV(CLK_DIV_SCLK_AUD_I2S, "div_sclk_aud_i2s", "mout_sclk_aud_i2s", 2976 DIV_AUD1, 0, 4), 2977 }; 2978 2979 static const struct samsung_gate_clock aud_gate_clks[] __initconst = { 2980 /* ENABLE_ACLK_AUD */ 2981 GATE(CLK_ACLK_INTR_CTRL, "aclk_intr_ctrl", "div_aclk_aud", 2982 ENABLE_ACLK_AUD, 12, 0, 0), 2983 GATE(CLK_ACLK_SMMU_LPASSX, "aclk_smmu_lpassx", "div_aclk_aud", 2984 ENABLE_ACLK_AUD, 7, 0, 0), 2985 GATE(CLK_ACLK_XIU_LPASSX, "aclk_xiu_lpassx", "div_aclk_aud", 2986 ENABLE_ACLK_AUD, 0, 4, 0), 2987 GATE(CLK_ACLK_AUDNP_133, "aclk_audnp_133", "div_aclk_aud", 2988 ENABLE_ACLK_AUD, 0, 3, 0), 2989 GATE(CLK_ACLK_AUDND_133, "aclk_audnd_133", "div_aclk_aud", 2990 ENABLE_ACLK_AUD, 0, 2, 0), 2991 GATE(CLK_ACLK_SRAMC, "aclk_sramc", "div_aclk_aud", ENABLE_ACLK_AUD, 2992 0, 1, 0), 2993 GATE(CLK_ACLK_DMAC, "aclk_dmac", "div_aclk_aud", ENABLE_ACLK_AUD, 2994 0, CLK_IGNORE_UNUSED, 0), 2995 2996 /* ENABLE_PCLK_AUD */ 2997 GATE(CLK_PCLK_WDT1, "pclk_wdt1", "div_aclk_aud", ENABLE_PCLK_AUD, 2998 13, 0, 0), 2999 GATE(CLK_PCLK_WDT0, "pclk_wdt0", "div_aclk_aud", ENABLE_PCLK_AUD, 3000 12, 0, 0), 3001 GATE(CLK_PCLK_SFR1, "pclk_sfr1", "div_aclk_aud", ENABLE_PCLK_AUD, 3002 11, 0, 0), 3003 GATE(CLK_PCLK_SMMU_LPASSX, "pclk_smmu_lpassx", "div_aclk_aud", 3004 ENABLE_PCLK_AUD, 10, 0, 0), 3005 GATE(CLK_PCLK_GPIO_AUD, "pclk_gpio_aud", "div_aclk_aud", 3006 ENABLE_PCLK_AUD, 9, CLK_IGNORE_UNUSED, 0), 3007 GATE(CLK_PCLK_PMU_AUD, "pclk_pmu_aud", "div_aclk_aud", 3008 ENABLE_PCLK_AUD, 8, CLK_IGNORE_UNUSED, 0), 3009 GATE(CLK_PCLK_SYSREG_AUD, "pclk_sysreg_aud", "div_aclk_aud", 3010 ENABLE_PCLK_AUD, 7, CLK_IGNORE_UNUSED, 0), 3011 GATE(CLK_PCLK_AUD_SLIMBUS, "pclk_aud_slimbus", "div_aclk_aud", 3012 ENABLE_PCLK_AUD, 6, 0, 0), 3013 GATE(CLK_PCLK_AUD_UART, "pclk_aud_uart", "div_aclk_aud", 3014 ENABLE_PCLK_AUD, 5, 0, 0), 3015 GATE(CLK_PCLK_AUD_PCM, "pclk_aud_pcm", "div_aclk_aud", 3016 ENABLE_PCLK_AUD, 4, 0, 0), 3017 GATE(CLK_PCLK_AUD_I2S, "pclk_aud_i2s", "div_aclk_aud", 3018 ENABLE_PCLK_AUD, 3, 0, 0), 3019 GATE(CLK_PCLK_TIMER, "pclk_timer", "div_aclk_aud", ENABLE_PCLK_AUD, 3020 2, 0, 0), 3021 GATE(CLK_PCLK_SFR0_CTRL, "pclk_sfr0_ctrl", "div_aclk_aud", 3022 ENABLE_PCLK_AUD, 0, 0, 0), 3023 3024 /* ENABLE_SCLK_AUD0 */ 3025 GATE(CLK_ATCLK_AUD, "atclk_aud", "div_atclk_aud", ENABLE_SCLK_AUD0, 3026 2, CLK_IGNORE_UNUSED, 0), 3027 GATE(CLK_PCLK_DBG_AUD, "pclk_dbg_aud", "div_pclk_dbg_aud", 3028 ENABLE_SCLK_AUD0, 1, 0, 0), 3029 GATE(CLK_SCLK_AUD_CA5, "sclk_aud_ca5", "div_aud_ca5", ENABLE_SCLK_AUD0, 3030 0, 0, 0), 3031 3032 /* ENABLE_SCLK_AUD1 */ 3033 GATE(CLK_SCLK_JTAG_TCK, "sclk_jtag_tck", "ioclk_jtag_tclk", 3034 ENABLE_SCLK_AUD1, 6, 0, 0), 3035 GATE(CLK_SCLK_SLIMBUS_CLKIN, "sclk_slimbus_clkin", "ioclk_slimbus_clk", 3036 ENABLE_SCLK_AUD1, 5, 0, 0), 3037 GATE(CLK_SCLK_AUD_SLIMBUS, "sclk_aud_slimbus", "div_sclk_aud_slimbus", 3038 ENABLE_SCLK_AUD1, 4, 0, 0), 3039 GATE(CLK_SCLK_AUD_UART, "sclk_aud_uart", "div_sclk_aud_uart", 3040 ENABLE_SCLK_AUD1, 3, CLK_IGNORE_UNUSED, 0), 3041 GATE(CLK_SCLK_AUD_PCM, "sclk_aud_pcm", "div_sclk_aud_pcm", 3042 ENABLE_SCLK_AUD1, 2, 0, 0), 3043 GATE(CLK_SCLK_I2S_BCLK, "sclk_i2s_bclk", "ioclk_i2s_bclk", 3044 ENABLE_SCLK_AUD1, 1, CLK_IGNORE_UNUSED, 0), 3045 GATE(CLK_SCLK_AUD_I2S, "sclk_aud_i2s", "div_sclk_aud_i2s", 3046 ENABLE_SCLK_AUD1, 0, CLK_IGNORE_UNUSED, 0), 3047 }; 3048 3049 static const struct samsung_cmu_info aud_cmu_info __initconst = { 3050 .mux_clks = aud_mux_clks, 3051 .nr_mux_clks = ARRAY_SIZE(aud_mux_clks), 3052 .div_clks = aud_div_clks, 3053 .nr_div_clks = ARRAY_SIZE(aud_div_clks), 3054 .gate_clks = aud_gate_clks, 3055 .nr_gate_clks = ARRAY_SIZE(aud_gate_clks), 3056 .fixed_clks = aud_fixed_clks, 3057 .nr_fixed_clks = ARRAY_SIZE(aud_fixed_clks), 3058 .nr_clk_ids = AUD_NR_CLK, 3059 .clk_regs = aud_clk_regs, 3060 .nr_clk_regs = ARRAY_SIZE(aud_clk_regs), 3061 .suspend_regs = aud_suspend_regs, 3062 .nr_suspend_regs = ARRAY_SIZE(aud_suspend_regs), 3063 .clk_name = "fout_aud_pll", 3064 }; 3065 3066 /* 3067 * Register offset definitions for CMU_BUS{0|1|2} 3068 */ 3069 #define DIV_BUS 0x0600 3070 #define DIV_STAT_BUS 0x0700 3071 #define ENABLE_ACLK_BUS 0x0800 3072 #define ENABLE_PCLK_BUS 0x0900 3073 #define ENABLE_IP_BUS0 0x0b00 3074 #define ENABLE_IP_BUS1 0x0b04 3075 3076 #define MUX_SEL_BUS2 0x0200 /* Only for CMU_BUS2 */ 3077 #define MUX_ENABLE_BUS2 0x0300 /* Only for CMU_BUS2 */ 3078 #define MUX_STAT_BUS2 0x0400 /* Only for CMU_BUS2 */ 3079 3080 /* list of all parent clock list */ 3081 PNAME(mout_aclk_bus2_400_p) = { "oscclk", "aclk_bus2_400", }; 3082 3083 #define CMU_BUS_COMMON_CLK_REGS \ 3084 DIV_BUS, \ 3085 ENABLE_ACLK_BUS, \ 3086 ENABLE_PCLK_BUS, \ 3087 ENABLE_IP_BUS0, \ 3088 ENABLE_IP_BUS1 3089 3090 static const unsigned long bus01_clk_regs[] __initconst = { 3091 CMU_BUS_COMMON_CLK_REGS, 3092 }; 3093 3094 static const unsigned long bus2_clk_regs[] __initconst = { 3095 MUX_SEL_BUS2, 3096 MUX_ENABLE_BUS2, 3097 CMU_BUS_COMMON_CLK_REGS, 3098 }; 3099 3100 static const struct samsung_div_clock bus0_div_clks[] __initconst = { 3101 /* DIV_BUS0 */ 3102 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus0_133", "aclk_bus0_400", 3103 DIV_BUS, 0, 3), 3104 }; 3105 3106 /* CMU_BUS0 clocks */ 3107 static const struct samsung_gate_clock bus0_gate_clks[] __initconst = { 3108 /* ENABLE_ACLK_BUS0 */ 3109 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus0p", "div_pclk_bus0_133", 3110 ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0), 3111 GATE(CLK_ACLK_BUSNP_133, "aclk_bus0np_133", "div_pclk_bus0_133", 3112 ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0), 3113 GATE(CLK_ACLK_BUSND_400, "aclk_bus0nd_400", "aclk_bus0_400", 3114 ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0), 3115 3116 /* ENABLE_PCLK_BUS0 */ 3117 GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus0srvnd_133", "div_pclk_bus0_133", 3118 ENABLE_PCLK_BUS, 2, 0, 0), 3119 GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus0", "div_pclk_bus0_133", 3120 ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0), 3121 GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus0", "div_pclk_bus0_133", 3122 ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0), 3123 }; 3124 3125 /* CMU_BUS1 clocks */ 3126 static const struct samsung_div_clock bus1_div_clks[] __initconst = { 3127 /* DIV_BUS1 */ 3128 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus1_133", "aclk_bus1_400", 3129 DIV_BUS, 0, 3), 3130 }; 3131 3132 static const struct samsung_gate_clock bus1_gate_clks[] __initconst = { 3133 /* ENABLE_ACLK_BUS1 */ 3134 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus1p", "div_pclk_bus1_133", 3135 ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0), 3136 GATE(CLK_ACLK_BUSNP_133, "aclk_bus1np_133", "div_pclk_bus1_133", 3137 ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0), 3138 GATE(CLK_ACLK_BUSND_400, "aclk_bus1nd_400", "aclk_bus1_400", 3139 ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0), 3140 3141 /* ENABLE_PCLK_BUS1 */ 3142 GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus1srvnd_133", "div_pclk_bus1_133", 3143 ENABLE_PCLK_BUS, 2, 0, 0), 3144 GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus1", "div_pclk_bus1_133", 3145 ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0), 3146 GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus1", "div_pclk_bus1_133", 3147 ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0), 3148 }; 3149 3150 /* CMU_BUS2 clocks */ 3151 static const struct samsung_mux_clock bus2_mux_clks[] __initconst = { 3152 /* MUX_SEL_BUS2 */ 3153 MUX(CLK_MOUT_ACLK_BUS2_400_USER, "mout_aclk_bus2_400_user", 3154 mout_aclk_bus2_400_p, MUX_SEL_BUS2, 0, 1), 3155 }; 3156 3157 static const struct samsung_div_clock bus2_div_clks[] __initconst = { 3158 /* DIV_BUS2 */ 3159 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus2_133", 3160 "mout_aclk_bus2_400_user", DIV_BUS, 0, 3), 3161 }; 3162 3163 static const struct samsung_gate_clock bus2_gate_clks[] __initconst = { 3164 /* ENABLE_ACLK_BUS2 */ 3165 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus2p", "div_pclk_bus2_133", 3166 ENABLE_ACLK_BUS, 3, CLK_IGNORE_UNUSED, 0), 3167 GATE(CLK_ACLK_BUSNP_133, "aclk_bus2np_133", "div_pclk_bus2_133", 3168 ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0), 3169 GATE(CLK_ACLK_BUS2BEND_400, "aclk_bus2bend_400", 3170 "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS, 3171 1, CLK_IGNORE_UNUSED, 0), 3172 GATE(CLK_ACLK_BUS2RTND_400, "aclk_bus2rtnd_400", 3173 "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS, 3174 0, CLK_IGNORE_UNUSED, 0), 3175 3176 /* ENABLE_PCLK_BUS2 */ 3177 GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus2srvnd_133", "div_pclk_bus2_133", 3178 ENABLE_PCLK_BUS, 2, 0, 0), 3179 GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus2", "div_pclk_bus2_133", 3180 ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0), 3181 GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus2", "div_pclk_bus2_133", 3182 ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0), 3183 }; 3184 3185 #define CMU_BUS_INFO_CLKS(id) \ 3186 .div_clks = bus##id##_div_clks, \ 3187 .nr_div_clks = ARRAY_SIZE(bus##id##_div_clks), \ 3188 .gate_clks = bus##id##_gate_clks, \ 3189 .nr_gate_clks = ARRAY_SIZE(bus##id##_gate_clks), \ 3190 .nr_clk_ids = BUSx_NR_CLK 3191 3192 static const struct samsung_cmu_info bus0_cmu_info __initconst = { 3193 CMU_BUS_INFO_CLKS(0), 3194 .clk_regs = bus01_clk_regs, 3195 .nr_clk_regs = ARRAY_SIZE(bus01_clk_regs), 3196 }; 3197 3198 static const struct samsung_cmu_info bus1_cmu_info __initconst = { 3199 CMU_BUS_INFO_CLKS(1), 3200 .clk_regs = bus01_clk_regs, 3201 .nr_clk_regs = ARRAY_SIZE(bus01_clk_regs), 3202 }; 3203 3204 static const struct samsung_cmu_info bus2_cmu_info __initconst = { 3205 CMU_BUS_INFO_CLKS(2), 3206 .mux_clks = bus2_mux_clks, 3207 .nr_mux_clks = ARRAY_SIZE(bus2_mux_clks), 3208 .clk_regs = bus2_clk_regs, 3209 .nr_clk_regs = ARRAY_SIZE(bus2_clk_regs), 3210 }; 3211 3212 #define exynos5433_cmu_bus_init(id) \ 3213 static void __init exynos5433_cmu_bus##id##_init(struct device_node *np)\ 3214 { \ 3215 samsung_cmu_register_one(np, &bus##id##_cmu_info); \ 3216 } \ 3217 CLK_OF_DECLARE(exynos5433_cmu_bus##id, \ 3218 "samsung,exynos5433-cmu-bus"#id, \ 3219 exynos5433_cmu_bus##id##_init) 3220 3221 exynos5433_cmu_bus_init(0); 3222 exynos5433_cmu_bus_init(1); 3223 exynos5433_cmu_bus_init(2); 3224 3225 /* 3226 * Register offset definitions for CMU_G3D 3227 */ 3228 #define G3D_PLL_LOCK 0x0000 3229 #define G3D_PLL_CON0 0x0100 3230 #define G3D_PLL_CON1 0x0104 3231 #define G3D_PLL_FREQ_DET 0x010c 3232 #define MUX_SEL_G3D 0x0200 3233 #define MUX_ENABLE_G3D 0x0300 3234 #define MUX_STAT_G3D 0x0400 3235 #define DIV_G3D 0x0600 3236 #define DIV_G3D_PLL_FREQ_DET 0x0604 3237 #define DIV_STAT_G3D 0x0700 3238 #define DIV_STAT_G3D_PLL_FREQ_DET 0x0704 3239 #define ENABLE_ACLK_G3D 0x0800 3240 #define ENABLE_PCLK_G3D 0x0900 3241 #define ENABLE_SCLK_G3D 0x0a00 3242 #define ENABLE_IP_G3D0 0x0b00 3243 #define ENABLE_IP_G3D1 0x0b04 3244 #define CLKOUT_CMU_G3D 0x0c00 3245 #define CLKOUT_CMU_G3D_DIV_STAT 0x0c04 3246 #define CLK_STOPCTRL 0x1000 3247 3248 static const unsigned long g3d_clk_regs[] __initconst = { 3249 G3D_PLL_LOCK, 3250 G3D_PLL_CON0, 3251 G3D_PLL_CON1, 3252 G3D_PLL_FREQ_DET, 3253 MUX_SEL_G3D, 3254 MUX_ENABLE_G3D, 3255 DIV_G3D, 3256 DIV_G3D_PLL_FREQ_DET, 3257 ENABLE_ACLK_G3D, 3258 ENABLE_PCLK_G3D, 3259 ENABLE_SCLK_G3D, 3260 ENABLE_IP_G3D0, 3261 ENABLE_IP_G3D1, 3262 CLKOUT_CMU_G3D, 3263 CLKOUT_CMU_G3D_DIV_STAT, 3264 CLK_STOPCTRL, 3265 }; 3266 3267 static const struct samsung_clk_reg_dump g3d_suspend_regs[] = { 3268 { MUX_SEL_G3D, 0 }, 3269 }; 3270 3271 /* list of all parent clock list */ 3272 PNAME(mout_aclk_g3d_400_p) = { "mout_g3d_pll", "aclk_g3d_400", }; 3273 PNAME(mout_g3d_pll_p) = { "oscclk", "fout_g3d_pll", }; 3274 3275 static const struct samsung_pll_clock g3d_pll_clks[] __initconst = { 3276 PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk", 3277 G3D_PLL_LOCK, G3D_PLL_CON0, exynos5433_pll_rates), 3278 }; 3279 3280 static const struct samsung_mux_clock g3d_mux_clks[] __initconst = { 3281 /* MUX_SEL_G3D */ 3282 MUX_F(CLK_MOUT_ACLK_G3D_400, "mout_aclk_g3d_400", mout_aclk_g3d_400_p, 3283 MUX_SEL_G3D, 8, 1, CLK_SET_RATE_PARENT, 0), 3284 MUX_F(CLK_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p, 3285 MUX_SEL_G3D, 0, 1, CLK_SET_RATE_PARENT, 0), 3286 }; 3287 3288 static const struct samsung_div_clock g3d_div_clks[] __initconst = { 3289 /* DIV_G3D */ 3290 DIV(CLK_DIV_SCLK_HPM_G3D, "div_sclk_hpm_g3d", "mout_g3d_pll", DIV_G3D, 3291 8, 2), 3292 DIV(CLK_DIV_PCLK_G3D, "div_pclk_g3d", "div_aclk_g3d", DIV_G3D, 3293 4, 3), 3294 DIV_F(CLK_DIV_ACLK_G3D, "div_aclk_g3d", "mout_aclk_g3d_400", DIV_G3D, 3295 0, 3, CLK_SET_RATE_PARENT, 0), 3296 }; 3297 3298 static const struct samsung_gate_clock g3d_gate_clks[] __initconst = { 3299 /* ENABLE_ACLK_G3D */ 3300 GATE(CLK_ACLK_BTS_G3D1, "aclk_bts_g3d1", "div_aclk_g3d", 3301 ENABLE_ACLK_G3D, 7, 0, 0), 3302 GATE(CLK_ACLK_BTS_G3D0, "aclk_bts_g3d0", "div_aclk_g3d", 3303 ENABLE_ACLK_G3D, 6, 0, 0), 3304 GATE(CLK_ACLK_ASYNCAPBS_G3D, "aclk_asyncapbs_g3d", "div_pclk_g3d", 3305 ENABLE_ACLK_G3D, 5, CLK_IGNORE_UNUSED, 0), 3306 GATE(CLK_ACLK_ASYNCAPBM_G3D, "aclk_asyncapbm_g3d", "div_aclk_g3d", 3307 ENABLE_ACLK_G3D, 4, CLK_IGNORE_UNUSED, 0), 3308 GATE(CLK_ACLK_AHB2APB_G3DP, "aclk_ahb2apb_g3dp", "div_pclk_g3d", 3309 ENABLE_ACLK_G3D, 3, CLK_IGNORE_UNUSED, 0), 3310 GATE(CLK_ACLK_G3DNP_150, "aclk_g3dnp_150", "div_pclk_g3d", 3311 ENABLE_ACLK_G3D, 2, CLK_IGNORE_UNUSED, 0), 3312 GATE(CLK_ACLK_G3DND_600, "aclk_g3dnd_600", "div_aclk_g3d", 3313 ENABLE_ACLK_G3D, 1, CLK_IGNORE_UNUSED, 0), 3314 GATE(CLK_ACLK_G3D, "aclk_g3d", "div_aclk_g3d", 3315 ENABLE_ACLK_G3D, 0, CLK_SET_RATE_PARENT, 0), 3316 3317 /* ENABLE_PCLK_G3D */ 3318 GATE(CLK_PCLK_BTS_G3D1, "pclk_bts_g3d1", "div_pclk_g3d", 3319 ENABLE_PCLK_G3D, 3, 0, 0), 3320 GATE(CLK_PCLK_BTS_G3D0, "pclk_bts_g3d0", "div_pclk_g3d", 3321 ENABLE_PCLK_G3D, 2, 0, 0), 3322 GATE(CLK_PCLK_PMU_G3D, "pclk_pmu_g3d", "div_pclk_g3d", 3323 ENABLE_PCLK_G3D, 1, CLK_IGNORE_UNUSED, 0), 3324 GATE(CLK_PCLK_SYSREG_G3D, "pclk_sysreg_g3d", "div_pclk_g3d", 3325 ENABLE_PCLK_G3D, 0, CLK_IGNORE_UNUSED, 0), 3326 3327 /* ENABLE_SCLK_G3D */ 3328 GATE(CLK_SCLK_HPM_G3D, "sclk_hpm_g3d", "div_sclk_hpm_g3d", 3329 ENABLE_SCLK_G3D, 0, 0, 0), 3330 }; 3331 3332 static const struct samsung_cmu_info g3d_cmu_info __initconst = { 3333 .pll_clks = g3d_pll_clks, 3334 .nr_pll_clks = ARRAY_SIZE(g3d_pll_clks), 3335 .mux_clks = g3d_mux_clks, 3336 .nr_mux_clks = ARRAY_SIZE(g3d_mux_clks), 3337 .div_clks = g3d_div_clks, 3338 .nr_div_clks = ARRAY_SIZE(g3d_div_clks), 3339 .gate_clks = g3d_gate_clks, 3340 .nr_gate_clks = ARRAY_SIZE(g3d_gate_clks), 3341 .nr_clk_ids = G3D_NR_CLK, 3342 .clk_regs = g3d_clk_regs, 3343 .nr_clk_regs = ARRAY_SIZE(g3d_clk_regs), 3344 .suspend_regs = g3d_suspend_regs, 3345 .nr_suspend_regs = ARRAY_SIZE(g3d_suspend_regs), 3346 .clk_name = "aclk_g3d_400", 3347 }; 3348 3349 /* 3350 * Register offset definitions for CMU_GSCL 3351 */ 3352 #define MUX_SEL_GSCL 0x0200 3353 #define MUX_ENABLE_GSCL 0x0300 3354 #define MUX_STAT_GSCL 0x0400 3355 #define ENABLE_ACLK_GSCL 0x0800 3356 #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 0x0804 3357 #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 0x0808 3358 #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 0x080c 3359 #define ENABLE_PCLK_GSCL 0x0900 3360 #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 0x0904 3361 #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 0x0908 3362 #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 0x090c 3363 #define ENABLE_IP_GSCL0 0x0b00 3364 #define ENABLE_IP_GSCL1 0x0b04 3365 #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL0 0x0b08 3366 #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL1 0x0b0c 3367 #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL2 0x0b10 3368 3369 static const unsigned long gscl_clk_regs[] __initconst = { 3370 MUX_SEL_GSCL, 3371 MUX_ENABLE_GSCL, 3372 ENABLE_ACLK_GSCL, 3373 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0, 3374 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1, 3375 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2, 3376 ENABLE_PCLK_GSCL, 3377 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 3378 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1, 3379 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2, 3380 ENABLE_IP_GSCL0, 3381 ENABLE_IP_GSCL1, 3382 ENABLE_IP_GSCL_SECURE_SMMU_GSCL0, 3383 ENABLE_IP_GSCL_SECURE_SMMU_GSCL1, 3384 ENABLE_IP_GSCL_SECURE_SMMU_GSCL2, 3385 }; 3386 3387 static const struct samsung_clk_reg_dump gscl_suspend_regs[] = { 3388 { MUX_SEL_GSCL, 0 }, 3389 { ENABLE_ACLK_GSCL, 0xfff }, 3390 { ENABLE_PCLK_GSCL, 0xff }, 3391 }; 3392 3393 /* list of all parent clock list */ 3394 PNAME(aclk_gscl_111_user_p) = { "oscclk", "aclk_gscl_111", }; 3395 PNAME(aclk_gscl_333_user_p) = { "oscclk", "aclk_gscl_333", }; 3396 3397 static const struct samsung_mux_clock gscl_mux_clks[] __initconst = { 3398 /* MUX_SEL_GSCL */ 3399 MUX(CLK_MOUT_ACLK_GSCL_111_USER, "mout_aclk_gscl_111_user", 3400 aclk_gscl_111_user_p, MUX_SEL_GSCL, 4, 1), 3401 MUX(CLK_MOUT_ACLK_GSCL_333_USER, "mout_aclk_gscl_333_user", 3402 aclk_gscl_333_user_p, MUX_SEL_GSCL, 0, 1), 3403 }; 3404 3405 static const struct samsung_gate_clock gscl_gate_clks[] __initconst = { 3406 /* ENABLE_ACLK_GSCL */ 3407 GATE(CLK_ACLK_BTS_GSCL2, "aclk_bts_gscl2", "mout_aclk_gscl_333_user", 3408 ENABLE_ACLK_GSCL, 11, 0, 0), 3409 GATE(CLK_ACLK_BTS_GSCL1, "aclk_bts_gscl1", "mout_aclk_gscl_333_user", 3410 ENABLE_ACLK_GSCL, 10, 0, 0), 3411 GATE(CLK_ACLK_BTS_GSCL0, "aclk_bts_gscl0", "mout_aclk_gscl_333_user", 3412 ENABLE_ACLK_GSCL, 9, 0, 0), 3413 GATE(CLK_ACLK_AHB2APB_GSCLP, "aclk_ahb2apb_gsclp", 3414 "mout_aclk_gscl_111_user", ENABLE_ACLK_GSCL, 3415 8, CLK_IGNORE_UNUSED, 0), 3416 GATE(CLK_ACLK_XIU_GSCLX, "aclk_xiu_gsclx", "mout_aclk_gscl_333_user", 3417 ENABLE_ACLK_GSCL, 7, 0, 0), 3418 GATE(CLK_ACLK_GSCLNP_111, "aclk_gsclnp_111", "mout_aclk_gscl_111_user", 3419 ENABLE_ACLK_GSCL, 6, CLK_IGNORE_UNUSED, 0), 3420 GATE(CLK_ACLK_GSCLRTND_333, "aclk_gsclrtnd_333", 3421 "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 5, 3422 CLK_IGNORE_UNUSED, 0), 3423 GATE(CLK_ACLK_GSCLBEND_333, "aclk_gsclbend_333", 3424 "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 4, 3425 CLK_IGNORE_UNUSED, 0), 3426 GATE(CLK_ACLK_GSD, "aclk_gsd", "mout_aclk_gscl_333_user", 3427 ENABLE_ACLK_GSCL, 3, 0, 0), 3428 GATE(CLK_ACLK_GSCL2, "aclk_gscl2", "mout_aclk_gscl_333_user", 3429 ENABLE_ACLK_GSCL, 2, 0, 0), 3430 GATE(CLK_ACLK_GSCL1, "aclk_gscl1", "mout_aclk_gscl_333_user", 3431 ENABLE_ACLK_GSCL, 1, 0, 0), 3432 GATE(CLK_ACLK_GSCL0, "aclk_gscl0", "mout_aclk_gscl_333_user", 3433 ENABLE_ACLK_GSCL, 0, 0, 0), 3434 3435 /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 */ 3436 GATE(CLK_ACLK_SMMU_GSCL0, "aclk_smmu_gscl0", "mout_aclk_gscl_333_user", 3437 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0), 3438 3439 /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 */ 3440 GATE(CLK_ACLK_SMMU_GSCL1, "aclk_smmu_gscl1", "mout_aclk_gscl_333_user", 3441 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1, 0, 0, 0), 3442 3443 /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 */ 3444 GATE(CLK_ACLK_SMMU_GSCL2, "aclk_smmu_gscl2", "mout_aclk_gscl_333_user", 3445 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0), 3446 3447 /* ENABLE_PCLK_GSCL */ 3448 GATE(CLK_PCLK_BTS_GSCL2, "pclk_bts_gscl2", "mout_aclk_gscl_111_user", 3449 ENABLE_PCLK_GSCL, 7, 0, 0), 3450 GATE(CLK_PCLK_BTS_GSCL1, "pclk_bts_gscl1", "mout_aclk_gscl_111_user", 3451 ENABLE_PCLK_GSCL, 6, 0, 0), 3452 GATE(CLK_PCLK_BTS_GSCL0, "pclk_bts_gscl0", "mout_aclk_gscl_111_user", 3453 ENABLE_PCLK_GSCL, 5, 0, 0), 3454 GATE(CLK_PCLK_PMU_GSCL, "pclk_pmu_gscl", "mout_aclk_gscl_111_user", 3455 ENABLE_PCLK_GSCL, 4, CLK_IGNORE_UNUSED, 0), 3456 GATE(CLK_PCLK_SYSREG_GSCL, "pclk_sysreg_gscl", 3457 "mout_aclk_gscl_111_user", ENABLE_PCLK_GSCL, 3458 3, CLK_IGNORE_UNUSED, 0), 3459 GATE(CLK_PCLK_GSCL2, "pclk_gscl2", "mout_aclk_gscl_111_user", 3460 ENABLE_PCLK_GSCL, 2, 0, 0), 3461 GATE(CLK_PCLK_GSCL1, "pclk_gscl1", "mout_aclk_gscl_111_user", 3462 ENABLE_PCLK_GSCL, 1, 0, 0), 3463 GATE(CLK_PCLK_GSCL0, "pclk_gscl0", "mout_aclk_gscl_111_user", 3464 ENABLE_PCLK_GSCL, 0, 0, 0), 3465 3466 /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 */ 3467 GATE(CLK_PCLK_SMMU_GSCL0, "pclk_smmu_gscl0", "mout_aclk_gscl_111_user", 3468 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0), 3469 3470 /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 */ 3471 GATE(CLK_PCLK_SMMU_GSCL1, "pclk_smmu_gscl1", "mout_aclk_gscl_111_user", 3472 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1, 0, 0, 0), 3473 3474 /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 */ 3475 GATE(CLK_PCLK_SMMU_GSCL2, "pclk_smmu_gscl2", "mout_aclk_gscl_111_user", 3476 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0), 3477 }; 3478 3479 static const struct samsung_cmu_info gscl_cmu_info __initconst = { 3480 .mux_clks = gscl_mux_clks, 3481 .nr_mux_clks = ARRAY_SIZE(gscl_mux_clks), 3482 .gate_clks = gscl_gate_clks, 3483 .nr_gate_clks = ARRAY_SIZE(gscl_gate_clks), 3484 .nr_clk_ids = GSCL_NR_CLK, 3485 .clk_regs = gscl_clk_regs, 3486 .nr_clk_regs = ARRAY_SIZE(gscl_clk_regs), 3487 .suspend_regs = gscl_suspend_regs, 3488 .nr_suspend_regs = ARRAY_SIZE(gscl_suspend_regs), 3489 .clk_name = "aclk_gscl_111", 3490 }; 3491 3492 /* 3493 * Register offset definitions for CMU_APOLLO 3494 */ 3495 #define APOLLO_PLL_LOCK 0x0000 3496 #define APOLLO_PLL_CON0 0x0100 3497 #define APOLLO_PLL_CON1 0x0104 3498 #define APOLLO_PLL_FREQ_DET 0x010c 3499 #define MUX_SEL_APOLLO0 0x0200 3500 #define MUX_SEL_APOLLO1 0x0204 3501 #define MUX_SEL_APOLLO2 0x0208 3502 #define MUX_ENABLE_APOLLO0 0x0300 3503 #define MUX_ENABLE_APOLLO1 0x0304 3504 #define MUX_ENABLE_APOLLO2 0x0308 3505 #define MUX_STAT_APOLLO0 0x0400 3506 #define MUX_STAT_APOLLO1 0x0404 3507 #define MUX_STAT_APOLLO2 0x0408 3508 #define DIV_APOLLO0 0x0600 3509 #define DIV_APOLLO1 0x0604 3510 #define DIV_APOLLO_PLL_FREQ_DET 0x0608 3511 #define DIV_STAT_APOLLO0 0x0700 3512 #define DIV_STAT_APOLLO1 0x0704 3513 #define DIV_STAT_APOLLO_PLL_FREQ_DET 0x0708 3514 #define ENABLE_ACLK_APOLLO 0x0800 3515 #define ENABLE_PCLK_APOLLO 0x0900 3516 #define ENABLE_SCLK_APOLLO 0x0a00 3517 #define ENABLE_IP_APOLLO0 0x0b00 3518 #define ENABLE_IP_APOLLO1 0x0b04 3519 #define CLKOUT_CMU_APOLLO 0x0c00 3520 #define CLKOUT_CMU_APOLLO_DIV_STAT 0x0c04 3521 #define ARMCLK_STOPCTRL 0x1000 3522 #define APOLLO_PWR_CTRL 0x1020 3523 #define APOLLO_PWR_CTRL2 0x1024 3524 #define APOLLO_INTR_SPREAD_ENABLE 0x1080 3525 #define APOLLO_INTR_SPREAD_USE_STANDBYWFI 0x1084 3526 #define APOLLO_INTR_SPREAD_BLOCKING_DURATION 0x1088 3527 3528 static const unsigned long apollo_clk_regs[] __initconst = { 3529 APOLLO_PLL_LOCK, 3530 APOLLO_PLL_CON0, 3531 APOLLO_PLL_CON1, 3532 APOLLO_PLL_FREQ_DET, 3533 MUX_SEL_APOLLO0, 3534 MUX_SEL_APOLLO1, 3535 MUX_SEL_APOLLO2, 3536 MUX_ENABLE_APOLLO0, 3537 MUX_ENABLE_APOLLO1, 3538 MUX_ENABLE_APOLLO2, 3539 DIV_APOLLO0, 3540 DIV_APOLLO1, 3541 DIV_APOLLO_PLL_FREQ_DET, 3542 ENABLE_ACLK_APOLLO, 3543 ENABLE_PCLK_APOLLO, 3544 ENABLE_SCLK_APOLLO, 3545 ENABLE_IP_APOLLO0, 3546 ENABLE_IP_APOLLO1, 3547 CLKOUT_CMU_APOLLO, 3548 CLKOUT_CMU_APOLLO_DIV_STAT, 3549 ARMCLK_STOPCTRL, 3550 APOLLO_PWR_CTRL, 3551 APOLLO_PWR_CTRL2, 3552 APOLLO_INTR_SPREAD_ENABLE, 3553 APOLLO_INTR_SPREAD_USE_STANDBYWFI, 3554 APOLLO_INTR_SPREAD_BLOCKING_DURATION, 3555 }; 3556 3557 /* list of all parent clock list */ 3558 PNAME(mout_apollo_pll_p) = { "oscclk", "fout_apollo_pll", }; 3559 PNAME(mout_bus_pll_apollo_user_p) = { "oscclk", "sclk_bus_pll_apollo", }; 3560 PNAME(mout_apollo_p) = { "mout_apollo_pll", 3561 "mout_bus_pll_apollo_user", }; 3562 3563 static const struct samsung_pll_clock apollo_pll_clks[] __initconst = { 3564 PLL(pll_35xx, CLK_FOUT_APOLLO_PLL, "fout_apollo_pll", "oscclk", 3565 APOLLO_PLL_LOCK, APOLLO_PLL_CON0, exynos5433_pll_rates), 3566 }; 3567 3568 static const struct samsung_mux_clock apollo_mux_clks[] __initconst = { 3569 /* MUX_SEL_APOLLO0 */ 3570 MUX_F(CLK_MOUT_APOLLO_PLL, "mout_apollo_pll", mout_apollo_pll_p, 3571 MUX_SEL_APOLLO0, 0, 1, CLK_SET_RATE_PARENT | 3572 CLK_RECALC_NEW_RATES, 0), 3573 3574 /* MUX_SEL_APOLLO1 */ 3575 MUX(CLK_MOUT_BUS_PLL_APOLLO_USER, "mout_bus_pll_apollo_user", 3576 mout_bus_pll_apollo_user_p, MUX_SEL_APOLLO1, 0, 1), 3577 3578 /* MUX_SEL_APOLLO2 */ 3579 MUX_F(CLK_MOUT_APOLLO, "mout_apollo", mout_apollo_p, MUX_SEL_APOLLO2, 3580 0, 1, CLK_SET_RATE_PARENT, 0), 3581 }; 3582 3583 static const struct samsung_div_clock apollo_div_clks[] __initconst = { 3584 /* DIV_APOLLO0 */ 3585 DIV_F(CLK_DIV_CNTCLK_APOLLO, "div_cntclk_apollo", "div_apollo2", 3586 DIV_APOLLO0, 24, 3, CLK_GET_RATE_NOCACHE, 3587 CLK_DIVIDER_READ_ONLY), 3588 DIV_F(CLK_DIV_PCLK_DBG_APOLLO, "div_pclk_dbg_apollo", "div_apollo2", 3589 DIV_APOLLO0, 20, 3, CLK_GET_RATE_NOCACHE, 3590 CLK_DIVIDER_READ_ONLY), 3591 DIV_F(CLK_DIV_ATCLK_APOLLO, "div_atclk_apollo", "div_apollo2", 3592 DIV_APOLLO0, 16, 3, CLK_GET_RATE_NOCACHE, 3593 CLK_DIVIDER_READ_ONLY), 3594 DIV_F(CLK_DIV_PCLK_APOLLO, "div_pclk_apollo", "div_apollo2", 3595 DIV_APOLLO0, 12, 3, CLK_GET_RATE_NOCACHE, 3596 CLK_DIVIDER_READ_ONLY), 3597 DIV_F(CLK_DIV_ACLK_APOLLO, "div_aclk_apollo", "div_apollo2", 3598 DIV_APOLLO0, 8, 3, CLK_GET_RATE_NOCACHE, 3599 CLK_DIVIDER_READ_ONLY), 3600 DIV_F(CLK_DIV_APOLLO2, "div_apollo2", "div_apollo1", 3601 DIV_APOLLO0, 4, 3, CLK_SET_RATE_PARENT, 0), 3602 DIV_F(CLK_DIV_APOLLO1, "div_apollo1", "mout_apollo", 3603 DIV_APOLLO0, 0, 3, CLK_SET_RATE_PARENT, 0), 3604 3605 /* DIV_APOLLO1 */ 3606 DIV_F(CLK_DIV_SCLK_HPM_APOLLO, "div_sclk_hpm_apollo", "mout_apollo", 3607 DIV_APOLLO1, 4, 3, CLK_GET_RATE_NOCACHE, 3608 CLK_DIVIDER_READ_ONLY), 3609 DIV_F(CLK_DIV_APOLLO_PLL, "div_apollo_pll", "mout_apollo", 3610 DIV_APOLLO1, 0, 3, CLK_GET_RATE_NOCACHE, 3611 CLK_DIVIDER_READ_ONLY), 3612 }; 3613 3614 static const struct samsung_gate_clock apollo_gate_clks[] __initconst = { 3615 /* ENABLE_ACLK_APOLLO */ 3616 GATE(CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS, "aclk_asatbslv_apollo_3_cssys", 3617 "div_atclk_apollo", ENABLE_ACLK_APOLLO, 3618 6, CLK_IGNORE_UNUSED, 0), 3619 GATE(CLK_ACLK_ASATBSLV_APOLLO_2_CSSYS, "aclk_asatbslv_apollo_2_cssys", 3620 "div_atclk_apollo", ENABLE_ACLK_APOLLO, 3621 5, CLK_IGNORE_UNUSED, 0), 3622 GATE(CLK_ACLK_ASATBSLV_APOLLO_1_CSSYS, "aclk_asatbslv_apollo_1_cssys", 3623 "div_atclk_apollo", ENABLE_ACLK_APOLLO, 3624 4, CLK_IGNORE_UNUSED, 0), 3625 GATE(CLK_ACLK_ASATBSLV_APOLLO_0_CSSYS, "aclk_asatbslv_apollo_0_cssys", 3626 "div_atclk_apollo", ENABLE_ACLK_APOLLO, 3627 3, CLK_IGNORE_UNUSED, 0), 3628 GATE(CLK_ACLK_ASYNCACES_APOLLO_CCI, "aclk_asyncaces_apollo_cci", 3629 "div_aclk_apollo", ENABLE_ACLK_APOLLO, 3630 2, CLK_IGNORE_UNUSED, 0), 3631 GATE(CLK_ACLK_AHB2APB_APOLLOP, "aclk_ahb2apb_apollop", 3632 "div_pclk_apollo", ENABLE_ACLK_APOLLO, 3633 1, CLK_IGNORE_UNUSED, 0), 3634 GATE(CLK_ACLK_APOLLONP_200, "aclk_apollonp_200", 3635 "div_pclk_apollo", ENABLE_ACLK_APOLLO, 3636 0, CLK_IGNORE_UNUSED, 0), 3637 3638 /* ENABLE_PCLK_APOLLO */ 3639 GATE(CLK_PCLK_ASAPBMST_CSSYS_APOLLO, "pclk_asapbmst_cssys_apollo", 3640 "div_pclk_dbg_apollo", ENABLE_PCLK_APOLLO, 3641 2, CLK_IGNORE_UNUSED, 0), 3642 GATE(CLK_PCLK_PMU_APOLLO, "pclk_pmu_apollo", "div_pclk_apollo", 3643 ENABLE_PCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0), 3644 GATE(CLK_PCLK_SYSREG_APOLLO, "pclk_sysreg_apollo", 3645 "div_pclk_apollo", ENABLE_PCLK_APOLLO, 3646 0, CLK_IGNORE_UNUSED, 0), 3647 3648 /* ENABLE_SCLK_APOLLO */ 3649 GATE(CLK_CNTCLK_APOLLO, "cntclk_apollo", "div_cntclk_apollo", 3650 ENABLE_SCLK_APOLLO, 3, CLK_IGNORE_UNUSED, 0), 3651 GATE(CLK_SCLK_HPM_APOLLO, "sclk_hpm_apollo", "div_sclk_hpm_apollo", 3652 ENABLE_SCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0), 3653 }; 3654 3655 #define E5433_APOLLO_DIV0(cntclk, pclk_dbg, atclk, pclk, aclk) \ 3656 (((cntclk) << 24) | ((pclk_dbg) << 20) | ((atclk) << 16) | \ 3657 ((pclk) << 12) | ((aclk) << 8)) 3658 3659 #define E5433_APOLLO_DIV1(hpm, copy) \ 3660 (((hpm) << 4) | ((copy) << 0)) 3661 3662 static const struct exynos_cpuclk_cfg_data exynos5433_apolloclk_d[] __initconst = { 3663 { 1300000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), }, 3664 { 1200000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), }, 3665 { 1100000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), }, 3666 { 1000000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), }, 3667 { 900000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), }, 3668 { 800000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), }, 3669 { 700000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), }, 3670 { 600000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), }, 3671 { 500000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), }, 3672 { 400000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), }, 3673 { 0 }, 3674 }; 3675 3676 static void __init exynos5433_cmu_apollo_init(struct device_node *np) 3677 { 3678 void __iomem *reg_base; 3679 struct samsung_clk_provider *ctx; 3680 3681 reg_base = of_iomap(np, 0); 3682 if (!reg_base) { 3683 panic("%s: failed to map registers\n", __func__); 3684 return; 3685 } 3686 3687 ctx = samsung_clk_init(np, reg_base, APOLLO_NR_CLK); 3688 if (!ctx) { 3689 panic("%s: unable to allocate ctx\n", __func__); 3690 return; 3691 } 3692 3693 samsung_clk_register_pll(ctx, apollo_pll_clks, 3694 ARRAY_SIZE(apollo_pll_clks), reg_base); 3695 samsung_clk_register_mux(ctx, apollo_mux_clks, 3696 ARRAY_SIZE(apollo_mux_clks)); 3697 samsung_clk_register_div(ctx, apollo_div_clks, 3698 ARRAY_SIZE(apollo_div_clks)); 3699 samsung_clk_register_gate(ctx, apollo_gate_clks, 3700 ARRAY_SIZE(apollo_gate_clks)); 3701 3702 exynos_register_cpu_clock(ctx, CLK_SCLK_APOLLO, "apolloclk", 3703 mout_apollo_p[0], mout_apollo_p[1], 0x200, 3704 exynos5433_apolloclk_d, ARRAY_SIZE(exynos5433_apolloclk_d), 3705 CLK_CPU_HAS_E5433_REGS_LAYOUT); 3706 3707 samsung_clk_sleep_init(reg_base, apollo_clk_regs, 3708 ARRAY_SIZE(apollo_clk_regs)); 3709 3710 samsung_clk_of_add_provider(np, ctx); 3711 } 3712 CLK_OF_DECLARE(exynos5433_cmu_apollo, "samsung,exynos5433-cmu-apollo", 3713 exynos5433_cmu_apollo_init); 3714 3715 /* 3716 * Register offset definitions for CMU_ATLAS 3717 */ 3718 #define ATLAS_PLL_LOCK 0x0000 3719 #define ATLAS_PLL_CON0 0x0100 3720 #define ATLAS_PLL_CON1 0x0104 3721 #define ATLAS_PLL_FREQ_DET 0x010c 3722 #define MUX_SEL_ATLAS0 0x0200 3723 #define MUX_SEL_ATLAS1 0x0204 3724 #define MUX_SEL_ATLAS2 0x0208 3725 #define MUX_ENABLE_ATLAS0 0x0300 3726 #define MUX_ENABLE_ATLAS1 0x0304 3727 #define MUX_ENABLE_ATLAS2 0x0308 3728 #define MUX_STAT_ATLAS0 0x0400 3729 #define MUX_STAT_ATLAS1 0x0404 3730 #define MUX_STAT_ATLAS2 0x0408 3731 #define DIV_ATLAS0 0x0600 3732 #define DIV_ATLAS1 0x0604 3733 #define DIV_ATLAS_PLL_FREQ_DET 0x0608 3734 #define DIV_STAT_ATLAS0 0x0700 3735 #define DIV_STAT_ATLAS1 0x0704 3736 #define DIV_STAT_ATLAS_PLL_FREQ_DET 0x0708 3737 #define ENABLE_ACLK_ATLAS 0x0800 3738 #define ENABLE_PCLK_ATLAS 0x0900 3739 #define ENABLE_SCLK_ATLAS 0x0a00 3740 #define ENABLE_IP_ATLAS0 0x0b00 3741 #define ENABLE_IP_ATLAS1 0x0b04 3742 #define CLKOUT_CMU_ATLAS 0x0c00 3743 #define CLKOUT_CMU_ATLAS_DIV_STAT 0x0c04 3744 #define ARMCLK_STOPCTRL 0x1000 3745 #define ATLAS_PWR_CTRL 0x1020 3746 #define ATLAS_PWR_CTRL2 0x1024 3747 #define ATLAS_INTR_SPREAD_ENABLE 0x1080 3748 #define ATLAS_INTR_SPREAD_USE_STANDBYWFI 0x1084 3749 #define ATLAS_INTR_SPREAD_BLOCKING_DURATION 0x1088 3750 3751 static const unsigned long atlas_clk_regs[] __initconst = { 3752 ATLAS_PLL_LOCK, 3753 ATLAS_PLL_CON0, 3754 ATLAS_PLL_CON1, 3755 ATLAS_PLL_FREQ_DET, 3756 MUX_SEL_ATLAS0, 3757 MUX_SEL_ATLAS1, 3758 MUX_SEL_ATLAS2, 3759 MUX_ENABLE_ATLAS0, 3760 MUX_ENABLE_ATLAS1, 3761 MUX_ENABLE_ATLAS2, 3762 DIV_ATLAS0, 3763 DIV_ATLAS1, 3764 DIV_ATLAS_PLL_FREQ_DET, 3765 ENABLE_ACLK_ATLAS, 3766 ENABLE_PCLK_ATLAS, 3767 ENABLE_SCLK_ATLAS, 3768 ENABLE_IP_ATLAS0, 3769 ENABLE_IP_ATLAS1, 3770 CLKOUT_CMU_ATLAS, 3771 CLKOUT_CMU_ATLAS_DIV_STAT, 3772 ARMCLK_STOPCTRL, 3773 ATLAS_PWR_CTRL, 3774 ATLAS_PWR_CTRL2, 3775 ATLAS_INTR_SPREAD_ENABLE, 3776 ATLAS_INTR_SPREAD_USE_STANDBYWFI, 3777 ATLAS_INTR_SPREAD_BLOCKING_DURATION, 3778 }; 3779 3780 /* list of all parent clock list */ 3781 PNAME(mout_atlas_pll_p) = { "oscclk", "fout_atlas_pll", }; 3782 PNAME(mout_bus_pll_atlas_user_p) = { "oscclk", "sclk_bus_pll_atlas", }; 3783 PNAME(mout_atlas_p) = { "mout_atlas_pll", 3784 "mout_bus_pll_atlas_user", }; 3785 3786 static const struct samsung_pll_clock atlas_pll_clks[] __initconst = { 3787 PLL(pll_35xx, CLK_FOUT_ATLAS_PLL, "fout_atlas_pll", "oscclk", 3788 ATLAS_PLL_LOCK, ATLAS_PLL_CON0, exynos5433_pll_rates), 3789 }; 3790 3791 static const struct samsung_mux_clock atlas_mux_clks[] __initconst = { 3792 /* MUX_SEL_ATLAS0 */ 3793 MUX_F(CLK_MOUT_ATLAS_PLL, "mout_atlas_pll", mout_atlas_pll_p, 3794 MUX_SEL_ATLAS0, 0, 1, CLK_SET_RATE_PARENT | 3795 CLK_RECALC_NEW_RATES, 0), 3796 3797 /* MUX_SEL_ATLAS1 */ 3798 MUX(CLK_MOUT_BUS_PLL_ATLAS_USER, "mout_bus_pll_atlas_user", 3799 mout_bus_pll_atlas_user_p, MUX_SEL_ATLAS1, 0, 1), 3800 3801 /* MUX_SEL_ATLAS2 */ 3802 MUX_F(CLK_MOUT_ATLAS, "mout_atlas", mout_atlas_p, MUX_SEL_ATLAS2, 3803 0, 1, CLK_SET_RATE_PARENT, 0), 3804 }; 3805 3806 static const struct samsung_div_clock atlas_div_clks[] __initconst = { 3807 /* DIV_ATLAS0 */ 3808 DIV_F(CLK_DIV_CNTCLK_ATLAS, "div_cntclk_atlas", "div_atlas2", 3809 DIV_ATLAS0, 24, 3, CLK_GET_RATE_NOCACHE, 3810 CLK_DIVIDER_READ_ONLY), 3811 DIV_F(CLK_DIV_PCLK_DBG_ATLAS, "div_pclk_dbg_atlas", "div_atclk_atlas", 3812 DIV_ATLAS0, 20, 3, CLK_GET_RATE_NOCACHE, 3813 CLK_DIVIDER_READ_ONLY), 3814 DIV_F(CLK_DIV_ATCLK_ATLASO, "div_atclk_atlas", "div_atlas2", 3815 DIV_ATLAS0, 16, 3, CLK_GET_RATE_NOCACHE, 3816 CLK_DIVIDER_READ_ONLY), 3817 DIV_F(CLK_DIV_PCLK_ATLAS, "div_pclk_atlas", "div_atlas2", 3818 DIV_ATLAS0, 12, 3, CLK_GET_RATE_NOCACHE, 3819 CLK_DIVIDER_READ_ONLY), 3820 DIV_F(CLK_DIV_ACLK_ATLAS, "div_aclk_atlas", "div_atlas2", 3821 DIV_ATLAS0, 8, 3, CLK_GET_RATE_NOCACHE, 3822 CLK_DIVIDER_READ_ONLY), 3823 DIV_F(CLK_DIV_ATLAS2, "div_atlas2", "div_atlas1", 3824 DIV_ATLAS0, 4, 3, CLK_SET_RATE_PARENT, 0), 3825 DIV_F(CLK_DIV_ATLAS1, "div_atlas1", "mout_atlas", 3826 DIV_ATLAS0, 0, 3, CLK_SET_RATE_PARENT, 0), 3827 3828 /* DIV_ATLAS1 */ 3829 DIV_F(CLK_DIV_SCLK_HPM_ATLAS, "div_sclk_hpm_atlas", "mout_atlas", 3830 DIV_ATLAS1, 4, 3, CLK_GET_RATE_NOCACHE, 3831 CLK_DIVIDER_READ_ONLY), 3832 DIV_F(CLK_DIV_ATLAS_PLL, "div_atlas_pll", "mout_atlas", 3833 DIV_ATLAS1, 0, 3, CLK_GET_RATE_NOCACHE, 3834 CLK_DIVIDER_READ_ONLY), 3835 }; 3836 3837 static const struct samsung_gate_clock atlas_gate_clks[] __initconst = { 3838 /* ENABLE_ACLK_ATLAS */ 3839 GATE(CLK_ACLK_ATB_AUD_CSSYS, "aclk_atb_aud_cssys", 3840 "div_atclk_atlas", ENABLE_ACLK_ATLAS, 3841 9, CLK_IGNORE_UNUSED, 0), 3842 GATE(CLK_ACLK_ATB_APOLLO3_CSSYS, "aclk_atb_apollo3_cssys", 3843 "div_atclk_atlas", ENABLE_ACLK_ATLAS, 3844 8, CLK_IGNORE_UNUSED, 0), 3845 GATE(CLK_ACLK_ATB_APOLLO2_CSSYS, "aclk_atb_apollo2_cssys", 3846 "div_atclk_atlas", ENABLE_ACLK_ATLAS, 3847 7, CLK_IGNORE_UNUSED, 0), 3848 GATE(CLK_ACLK_ATB_APOLLO1_CSSYS, "aclk_atb_apollo1_cssys", 3849 "div_atclk_atlas", ENABLE_ACLK_ATLAS, 3850 6, CLK_IGNORE_UNUSED, 0), 3851 GATE(CLK_ACLK_ATB_APOLLO0_CSSYS, "aclk_atb_apollo0_cssys", 3852 "div_atclk_atlas", ENABLE_ACLK_ATLAS, 3853 5, CLK_IGNORE_UNUSED, 0), 3854 GATE(CLK_ACLK_ASYNCAHBS_CSSYS_SSS, "aclk_asyncahbs_cssys_sss", 3855 "div_atclk_atlas", ENABLE_ACLK_ATLAS, 3856 4, CLK_IGNORE_UNUSED, 0), 3857 GATE(CLK_ACLK_ASYNCAXIS_CSSYS_CCIX, "aclk_asyncaxis_cssys_ccix", 3858 "div_pclk_dbg_atlas", ENABLE_ACLK_ATLAS, 3859 3, CLK_IGNORE_UNUSED, 0), 3860 GATE(CLK_ACLK_ASYNCACES_ATLAS_CCI, "aclk_asyncaces_atlas_cci", 3861 "div_aclk_atlas", ENABLE_ACLK_ATLAS, 3862 2, CLK_IGNORE_UNUSED, 0), 3863 GATE(CLK_ACLK_AHB2APB_ATLASP, "aclk_ahb2apb_atlasp", "div_pclk_atlas", 3864 ENABLE_ACLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0), 3865 GATE(CLK_ACLK_ATLASNP_200, "aclk_atlasnp_200", "div_pclk_atlas", 3866 ENABLE_ACLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0), 3867 3868 /* ENABLE_PCLK_ATLAS */ 3869 GATE(CLK_PCLK_ASYNCAPB_AUD_CSSYS, "pclk_asyncapb_aud_cssys", 3870 "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS, 3871 5, CLK_IGNORE_UNUSED, 0), 3872 GATE(CLK_PCLK_ASYNCAPB_ISP_CSSYS, "pclk_asyncapb_isp_cssys", 3873 "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS, 3874 4, CLK_IGNORE_UNUSED, 0), 3875 GATE(CLK_PCLK_ASYNCAPB_APOLLO_CSSYS, "pclk_asyncapb_apollo_cssys", 3876 "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS, 3877 3, CLK_IGNORE_UNUSED, 0), 3878 GATE(CLK_PCLK_PMU_ATLAS, "pclk_pmu_atlas", "div_pclk_atlas", 3879 ENABLE_PCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0), 3880 GATE(CLK_PCLK_SYSREG_ATLAS, "pclk_sysreg_atlas", "div_pclk_atlas", 3881 ENABLE_PCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0), 3882 GATE(CLK_PCLK_SECJTAG, "pclk_secjtag", "div_pclk_dbg_atlas", 3883 ENABLE_PCLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0), 3884 3885 /* ENABLE_SCLK_ATLAS */ 3886 GATE(CLK_CNTCLK_ATLAS, "cntclk_atlas", "div_cntclk_atlas", 3887 ENABLE_SCLK_ATLAS, 10, CLK_IGNORE_UNUSED, 0), 3888 GATE(CLK_SCLK_HPM_ATLAS, "sclk_hpm_atlas", "div_sclk_hpm_atlas", 3889 ENABLE_SCLK_ATLAS, 7, CLK_IGNORE_UNUSED, 0), 3890 GATE(CLK_TRACECLK, "traceclk", "div_atclk_atlas", 3891 ENABLE_SCLK_ATLAS, 6, CLK_IGNORE_UNUSED, 0), 3892 GATE(CLK_CTMCLK, "ctmclk", "div_atclk_atlas", 3893 ENABLE_SCLK_ATLAS, 5, CLK_IGNORE_UNUSED, 0), 3894 GATE(CLK_HCLK_CSSYS, "hclk_cssys", "div_atclk_atlas", 3895 ENABLE_SCLK_ATLAS, 4, CLK_IGNORE_UNUSED, 0), 3896 GATE(CLK_PCLK_DBG_CSSYS, "pclk_dbg_cssys", "div_pclk_dbg_atlas", 3897 ENABLE_SCLK_ATLAS, 3, CLK_IGNORE_UNUSED, 0), 3898 GATE(CLK_PCLK_DBG, "pclk_dbg", "div_pclk_dbg_atlas", 3899 ENABLE_SCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0), 3900 GATE(CLK_ATCLK, "atclk", "div_atclk_atlas", 3901 ENABLE_SCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0), 3902 }; 3903 3904 #define E5433_ATLAS_DIV0(cntclk, pclk_dbg, atclk, pclk, aclk) \ 3905 (((cntclk) << 24) | ((pclk_dbg) << 20) | ((atclk) << 16) | \ 3906 ((pclk) << 12) | ((aclk) << 8)) 3907 3908 #define E5433_ATLAS_DIV1(hpm, copy) \ 3909 (((hpm) << 4) | ((copy) << 0)) 3910 3911 static const struct exynos_cpuclk_cfg_data exynos5433_atlasclk_d[] __initconst = { 3912 { 1900000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), }, 3913 { 1800000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), }, 3914 { 1700000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), }, 3915 { 1600000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), }, 3916 { 1500000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), }, 3917 { 1400000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), }, 3918 { 1300000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), }, 3919 { 1200000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), }, 3920 { 1100000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), }, 3921 { 1000000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), }, 3922 { 900000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), }, 3923 { 800000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), }, 3924 { 700000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), }, 3925 { 600000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), }, 3926 { 500000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), }, 3927 { 0 }, 3928 }; 3929 3930 static void __init exynos5433_cmu_atlas_init(struct device_node *np) 3931 { 3932 void __iomem *reg_base; 3933 struct samsung_clk_provider *ctx; 3934 3935 reg_base = of_iomap(np, 0); 3936 if (!reg_base) { 3937 panic("%s: failed to map registers\n", __func__); 3938 return; 3939 } 3940 3941 ctx = samsung_clk_init(np, reg_base, ATLAS_NR_CLK); 3942 if (!ctx) { 3943 panic("%s: unable to allocate ctx\n", __func__); 3944 return; 3945 } 3946 3947 samsung_clk_register_pll(ctx, atlas_pll_clks, 3948 ARRAY_SIZE(atlas_pll_clks), reg_base); 3949 samsung_clk_register_mux(ctx, atlas_mux_clks, 3950 ARRAY_SIZE(atlas_mux_clks)); 3951 samsung_clk_register_div(ctx, atlas_div_clks, 3952 ARRAY_SIZE(atlas_div_clks)); 3953 samsung_clk_register_gate(ctx, atlas_gate_clks, 3954 ARRAY_SIZE(atlas_gate_clks)); 3955 3956 exynos_register_cpu_clock(ctx, CLK_SCLK_ATLAS, "atlasclk", 3957 mout_atlas_p[0], mout_atlas_p[1], 0x200, 3958 exynos5433_atlasclk_d, ARRAY_SIZE(exynos5433_atlasclk_d), 3959 CLK_CPU_HAS_E5433_REGS_LAYOUT); 3960 3961 samsung_clk_sleep_init(reg_base, atlas_clk_regs, 3962 ARRAY_SIZE(atlas_clk_regs)); 3963 3964 samsung_clk_of_add_provider(np, ctx); 3965 } 3966 CLK_OF_DECLARE(exynos5433_cmu_atlas, "samsung,exynos5433-cmu-atlas", 3967 exynos5433_cmu_atlas_init); 3968 3969 /* 3970 * Register offset definitions for CMU_MSCL 3971 */ 3972 #define MUX_SEL_MSCL0 0x0200 3973 #define MUX_SEL_MSCL1 0x0204 3974 #define MUX_ENABLE_MSCL0 0x0300 3975 #define MUX_ENABLE_MSCL1 0x0304 3976 #define MUX_STAT_MSCL0 0x0400 3977 #define MUX_STAT_MSCL1 0x0404 3978 #define DIV_MSCL 0x0600 3979 #define DIV_STAT_MSCL 0x0700 3980 #define ENABLE_ACLK_MSCL 0x0800 3981 #define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 0x0804 3982 #define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 0x0808 3983 #define ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG 0x080c 3984 #define ENABLE_PCLK_MSCL 0x0900 3985 #define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 0x0904 3986 #define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 0x0908 3987 #define ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG 0x090c 3988 #define ENABLE_SCLK_MSCL 0x0a00 3989 #define ENABLE_IP_MSCL0 0x0b00 3990 #define ENABLE_IP_MSCL1 0x0b04 3991 #define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0 0x0b08 3992 #define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1 0x0b0c 3993 #define ENABLE_IP_MSCL_SECURE_SMMU_JPEG 0x0b10 3994 3995 static const unsigned long mscl_clk_regs[] __initconst = { 3996 MUX_SEL_MSCL0, 3997 MUX_SEL_MSCL1, 3998 MUX_ENABLE_MSCL0, 3999 MUX_ENABLE_MSCL1, 4000 DIV_MSCL, 4001 ENABLE_ACLK_MSCL, 4002 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0, 4003 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1, 4004 ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG, 4005 ENABLE_PCLK_MSCL, 4006 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0, 4007 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1, 4008 ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG, 4009 ENABLE_SCLK_MSCL, 4010 ENABLE_IP_MSCL0, 4011 ENABLE_IP_MSCL1, 4012 ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0, 4013 ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1, 4014 ENABLE_IP_MSCL_SECURE_SMMU_JPEG, 4015 }; 4016 4017 static const struct samsung_clk_reg_dump mscl_suspend_regs[] = { 4018 { MUX_SEL_MSCL0, 0 }, 4019 { MUX_SEL_MSCL1, 0 }, 4020 }; 4021 4022 /* list of all parent clock list */ 4023 PNAME(mout_sclk_jpeg_user_p) = { "oscclk", "sclk_jpeg_mscl", }; 4024 PNAME(mout_aclk_mscl_400_user_p) = { "oscclk", "aclk_mscl_400", }; 4025 PNAME(mout_sclk_jpeg_p) = { "mout_sclk_jpeg_user", 4026 "mout_aclk_mscl_400_user", }; 4027 4028 static const struct samsung_mux_clock mscl_mux_clks[] __initconst = { 4029 /* MUX_SEL_MSCL0 */ 4030 MUX(CLK_MOUT_SCLK_JPEG_USER, "mout_sclk_jpeg_user", 4031 mout_sclk_jpeg_user_p, MUX_SEL_MSCL0, 4, 1), 4032 MUX(CLK_MOUT_ACLK_MSCL_400_USER, "mout_aclk_mscl_400_user", 4033 mout_aclk_mscl_400_user_p, MUX_SEL_MSCL0, 0, 1), 4034 4035 /* MUX_SEL_MSCL1 */ 4036 MUX(CLK_MOUT_SCLK_JPEG, "mout_sclk_jpeg", mout_sclk_jpeg_p, 4037 MUX_SEL_MSCL1, 0, 1), 4038 }; 4039 4040 static const struct samsung_div_clock mscl_div_clks[] __initconst = { 4041 /* DIV_MSCL */ 4042 DIV(CLK_DIV_PCLK_MSCL, "div_pclk_mscl", "mout_aclk_mscl_400_user", 4043 DIV_MSCL, 0, 3), 4044 }; 4045 4046 static const struct samsung_gate_clock mscl_gate_clks[] __initconst = { 4047 /* ENABLE_ACLK_MSCL */ 4048 GATE(CLK_ACLK_BTS_JPEG, "aclk_bts_jpeg", "mout_aclk_mscl_400_user", 4049 ENABLE_ACLK_MSCL, 9, 0, 0), 4050 GATE(CLK_ACLK_BTS_M2MSCALER1, "aclk_bts_m2mscaler1", 4051 "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 8, 0, 0), 4052 GATE(CLK_ACLK_BTS_M2MSCALER0, "aclk_bts_m2mscaler0", 4053 "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 7, 0, 0), 4054 GATE(CLK_ACLK_AHB2APB_MSCL0P, "aclk_abh2apb_mscl0p", "div_pclk_mscl", 4055 ENABLE_ACLK_MSCL, 6, CLK_IGNORE_UNUSED, 0), 4056 GATE(CLK_ACLK_XIU_MSCLX, "aclk_xiu_msclx", "mout_aclk_mscl_400_user", 4057 ENABLE_ACLK_MSCL, 5, CLK_IGNORE_UNUSED, 0), 4058 GATE(CLK_ACLK_MSCLNP_100, "aclk_msclnp_100", "div_pclk_mscl", 4059 ENABLE_ACLK_MSCL, 4, CLK_IGNORE_UNUSED, 0), 4060 GATE(CLK_ACLK_MSCLND_400, "aclk_msclnd_400", "mout_aclk_mscl_400_user", 4061 ENABLE_ACLK_MSCL, 3, CLK_IGNORE_UNUSED, 0), 4062 GATE(CLK_ACLK_JPEG, "aclk_jpeg", "mout_aclk_mscl_400_user", 4063 ENABLE_ACLK_MSCL, 2, 0, 0), 4064 GATE(CLK_ACLK_M2MSCALER1, "aclk_m2mscaler1", "mout_aclk_mscl_400_user", 4065 ENABLE_ACLK_MSCL, 1, 0, 0), 4066 GATE(CLK_ACLK_M2MSCALER0, "aclk_m2mscaler0", "mout_aclk_mscl_400_user", 4067 ENABLE_ACLK_MSCL, 0, 0, 0), 4068 4069 /* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 */ 4070 GATE(CLK_ACLK_SMMU_M2MSCALER0, "aclk_smmu_m2mscaler0", 4071 "mout_aclk_mscl_400_user", 4072 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0, 4073 0, CLK_IGNORE_UNUSED, 0), 4074 4075 /* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 */ 4076 GATE(CLK_ACLK_SMMU_M2MSCALER1, "aclk_smmu_m2mscaler1", 4077 "mout_aclk_mscl_400_user", 4078 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1, 4079 0, CLK_IGNORE_UNUSED, 0), 4080 4081 /* ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG */ 4082 GATE(CLK_ACLK_SMMU_JPEG, "aclk_smmu_jpeg", "mout_aclk_mscl_400_user", 4083 ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG, 4084 0, CLK_IGNORE_UNUSED, 0), 4085 4086 /* ENABLE_PCLK_MSCL */ 4087 GATE(CLK_PCLK_BTS_JPEG, "pclk_bts_jpeg", "div_pclk_mscl", 4088 ENABLE_PCLK_MSCL, 7, 0, 0), 4089 GATE(CLK_PCLK_BTS_M2MSCALER1, "pclk_bts_m2mscaler1", "div_pclk_mscl", 4090 ENABLE_PCLK_MSCL, 6, 0, 0), 4091 GATE(CLK_PCLK_BTS_M2MSCALER0, "pclk_bts_m2mscaler0", "div_pclk_mscl", 4092 ENABLE_PCLK_MSCL, 5, 0, 0), 4093 GATE(CLK_PCLK_PMU_MSCL, "pclk_pmu_mscl", "div_pclk_mscl", 4094 ENABLE_PCLK_MSCL, 4, CLK_IGNORE_UNUSED, 0), 4095 GATE(CLK_PCLK_SYSREG_MSCL, "pclk_sysreg_mscl", "div_pclk_mscl", 4096 ENABLE_PCLK_MSCL, 3, CLK_IGNORE_UNUSED, 0), 4097 GATE(CLK_PCLK_JPEG, "pclk_jpeg", "div_pclk_mscl", 4098 ENABLE_PCLK_MSCL, 2, 0, 0), 4099 GATE(CLK_PCLK_M2MSCALER1, "pclk_m2mscaler1", "div_pclk_mscl", 4100 ENABLE_PCLK_MSCL, 1, 0, 0), 4101 GATE(CLK_PCLK_M2MSCALER0, "pclk_m2mscaler0", "div_pclk_mscl", 4102 ENABLE_PCLK_MSCL, 0, 0, 0), 4103 4104 /* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 */ 4105 GATE(CLK_PCLK_SMMU_M2MSCALER0, "pclk_smmu_m2mscaler0", "div_pclk_mscl", 4106 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0, 4107 0, CLK_IGNORE_UNUSED, 0), 4108 4109 /* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 */ 4110 GATE(CLK_PCLK_SMMU_M2MSCALER1, "pclk_smmu_m2mscaler1", "div_pclk_mscl", 4111 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1, 4112 0, CLK_IGNORE_UNUSED, 0), 4113 4114 /* ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG */ 4115 GATE(CLK_PCLK_SMMU_JPEG, "pclk_smmu_jpeg", "div_pclk_mscl", 4116 ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG, 4117 0, CLK_IGNORE_UNUSED, 0), 4118 4119 /* ENABLE_SCLK_MSCL */ 4120 GATE(CLK_SCLK_JPEG, "sclk_jpeg", "mout_sclk_jpeg", ENABLE_SCLK_MSCL, 0, 4121 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), 4122 }; 4123 4124 static const struct samsung_cmu_info mscl_cmu_info __initconst = { 4125 .mux_clks = mscl_mux_clks, 4126 .nr_mux_clks = ARRAY_SIZE(mscl_mux_clks), 4127 .div_clks = mscl_div_clks, 4128 .nr_div_clks = ARRAY_SIZE(mscl_div_clks), 4129 .gate_clks = mscl_gate_clks, 4130 .nr_gate_clks = ARRAY_SIZE(mscl_gate_clks), 4131 .nr_clk_ids = MSCL_NR_CLK, 4132 .clk_regs = mscl_clk_regs, 4133 .nr_clk_regs = ARRAY_SIZE(mscl_clk_regs), 4134 .suspend_regs = mscl_suspend_regs, 4135 .nr_suspend_regs = ARRAY_SIZE(mscl_suspend_regs), 4136 .clk_name = "aclk_mscl_400", 4137 }; 4138 4139 /* 4140 * Register offset definitions for CMU_MFC 4141 */ 4142 #define MUX_SEL_MFC 0x0200 4143 #define MUX_ENABLE_MFC 0x0300 4144 #define MUX_STAT_MFC 0x0400 4145 #define DIV_MFC 0x0600 4146 #define DIV_STAT_MFC 0x0700 4147 #define ENABLE_ACLK_MFC 0x0800 4148 #define ENABLE_ACLK_MFC_SECURE_SMMU_MFC 0x0804 4149 #define ENABLE_PCLK_MFC 0x0900 4150 #define ENABLE_PCLK_MFC_SECURE_SMMU_MFC 0x0904 4151 #define ENABLE_IP_MFC0 0x0b00 4152 #define ENABLE_IP_MFC1 0x0b04 4153 #define ENABLE_IP_MFC_SECURE_SMMU_MFC 0x0b08 4154 4155 static const unsigned long mfc_clk_regs[] __initconst = { 4156 MUX_SEL_MFC, 4157 MUX_ENABLE_MFC, 4158 DIV_MFC, 4159 ENABLE_ACLK_MFC, 4160 ENABLE_ACLK_MFC_SECURE_SMMU_MFC, 4161 ENABLE_PCLK_MFC, 4162 ENABLE_PCLK_MFC_SECURE_SMMU_MFC, 4163 ENABLE_IP_MFC0, 4164 ENABLE_IP_MFC1, 4165 ENABLE_IP_MFC_SECURE_SMMU_MFC, 4166 }; 4167 4168 static const struct samsung_clk_reg_dump mfc_suspend_regs[] = { 4169 { MUX_SEL_MFC, 0 }, 4170 }; 4171 4172 PNAME(mout_aclk_mfc_400_user_p) = { "oscclk", "aclk_mfc_400", }; 4173 4174 static const struct samsung_mux_clock mfc_mux_clks[] __initconst = { 4175 /* MUX_SEL_MFC */ 4176 MUX(CLK_MOUT_ACLK_MFC_400_USER, "mout_aclk_mfc_400_user", 4177 mout_aclk_mfc_400_user_p, MUX_SEL_MFC, 0, 0), 4178 }; 4179 4180 static const struct samsung_div_clock mfc_div_clks[] __initconst = { 4181 /* DIV_MFC */ 4182 DIV(CLK_DIV_PCLK_MFC, "div_pclk_mfc", "mout_aclk_mfc_400_user", 4183 DIV_MFC, 0, 2), 4184 }; 4185 4186 static const struct samsung_gate_clock mfc_gate_clks[] __initconst = { 4187 /* ENABLE_ACLK_MFC */ 4188 GATE(CLK_ACLK_BTS_MFC_1, "aclk_bts_mfc_1", "mout_aclk_mfc_400_user", 4189 ENABLE_ACLK_MFC, 6, 0, 0), 4190 GATE(CLK_ACLK_BTS_MFC_0, "aclk_bts_mfc_0", "mout_aclk_mfc_400_user", 4191 ENABLE_ACLK_MFC, 5, 0, 0), 4192 GATE(CLK_ACLK_AHB2APB_MFCP, "aclk_ahb2apb_mfcp", "div_pclk_mfc", 4193 ENABLE_ACLK_MFC, 4, CLK_IGNORE_UNUSED, 0), 4194 GATE(CLK_ACLK_XIU_MFCX, "aclk_xiu_mfcx", "mout_aclk_mfc_400_user", 4195 ENABLE_ACLK_MFC, 3, CLK_IGNORE_UNUSED, 0), 4196 GATE(CLK_ACLK_MFCNP_100, "aclk_mfcnp_100", "div_pclk_mfc", 4197 ENABLE_ACLK_MFC, 2, CLK_IGNORE_UNUSED, 0), 4198 GATE(CLK_ACLK_MFCND_400, "aclk_mfcnd_400", "mout_aclk_mfc_400_user", 4199 ENABLE_ACLK_MFC, 1, CLK_IGNORE_UNUSED, 0), 4200 GATE(CLK_ACLK_MFC, "aclk_mfc", "mout_aclk_mfc_400_user", 4201 ENABLE_ACLK_MFC, 0, 0, 0), 4202 4203 /* ENABLE_ACLK_MFC_SECURE_SMMU_MFC */ 4204 GATE(CLK_ACLK_SMMU_MFC_1, "aclk_smmu_mfc_1", "mout_aclk_mfc_400_user", 4205 ENABLE_ACLK_MFC_SECURE_SMMU_MFC, 4206 1, CLK_IGNORE_UNUSED, 0), 4207 GATE(CLK_ACLK_SMMU_MFC_0, "aclk_smmu_mfc_0", "mout_aclk_mfc_400_user", 4208 ENABLE_ACLK_MFC_SECURE_SMMU_MFC, 4209 0, CLK_IGNORE_UNUSED, 0), 4210 4211 /* ENABLE_PCLK_MFC */ 4212 GATE(CLK_PCLK_BTS_MFC_1, "pclk_bts_mfc_1", "div_pclk_mfc", 4213 ENABLE_PCLK_MFC, 4, 0, 0), 4214 GATE(CLK_PCLK_BTS_MFC_0, "pclk_bts_mfc_0", "div_pclk_mfc", 4215 ENABLE_PCLK_MFC, 3, 0, 0), 4216 GATE(CLK_PCLK_PMU_MFC, "pclk_pmu_mfc", "div_pclk_mfc", 4217 ENABLE_PCLK_MFC, 2, CLK_IGNORE_UNUSED, 0), 4218 GATE(CLK_PCLK_SYSREG_MFC, "pclk_sysreg_mfc", "div_pclk_mfc", 4219 ENABLE_PCLK_MFC, 1, CLK_IGNORE_UNUSED, 0), 4220 GATE(CLK_PCLK_MFC, "pclk_mfc", "div_pclk_mfc", 4221 ENABLE_PCLK_MFC, 4, CLK_IGNORE_UNUSED, 0), 4222 4223 /* ENABLE_PCLK_MFC_SECURE_SMMU_MFC */ 4224 GATE(CLK_PCLK_SMMU_MFC_1, "pclk_smmu_mfc_1", "div_pclk_mfc", 4225 ENABLE_PCLK_MFC_SECURE_SMMU_MFC, 4226 1, CLK_IGNORE_UNUSED, 0), 4227 GATE(CLK_PCLK_SMMU_MFC_0, "pclk_smmu_mfc_0", "div_pclk_mfc", 4228 ENABLE_PCLK_MFC_SECURE_SMMU_MFC, 4229 0, CLK_IGNORE_UNUSED, 0), 4230 }; 4231 4232 static const struct samsung_cmu_info mfc_cmu_info __initconst = { 4233 .mux_clks = mfc_mux_clks, 4234 .nr_mux_clks = ARRAY_SIZE(mfc_mux_clks), 4235 .div_clks = mfc_div_clks, 4236 .nr_div_clks = ARRAY_SIZE(mfc_div_clks), 4237 .gate_clks = mfc_gate_clks, 4238 .nr_gate_clks = ARRAY_SIZE(mfc_gate_clks), 4239 .nr_clk_ids = MFC_NR_CLK, 4240 .clk_regs = mfc_clk_regs, 4241 .nr_clk_regs = ARRAY_SIZE(mfc_clk_regs), 4242 .suspend_regs = mfc_suspend_regs, 4243 .nr_suspend_regs = ARRAY_SIZE(mfc_suspend_regs), 4244 .clk_name = "aclk_mfc_400", 4245 }; 4246 4247 /* 4248 * Register offset definitions for CMU_HEVC 4249 */ 4250 #define MUX_SEL_HEVC 0x0200 4251 #define MUX_ENABLE_HEVC 0x0300 4252 #define MUX_STAT_HEVC 0x0400 4253 #define DIV_HEVC 0x0600 4254 #define DIV_STAT_HEVC 0x0700 4255 #define ENABLE_ACLK_HEVC 0x0800 4256 #define ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC 0x0804 4257 #define ENABLE_PCLK_HEVC 0x0900 4258 #define ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC 0x0904 4259 #define ENABLE_IP_HEVC0 0x0b00 4260 #define ENABLE_IP_HEVC1 0x0b04 4261 #define ENABLE_IP_HEVC_SECURE_SMMU_HEVC 0x0b08 4262 4263 static const unsigned long hevc_clk_regs[] __initconst = { 4264 MUX_SEL_HEVC, 4265 MUX_ENABLE_HEVC, 4266 DIV_HEVC, 4267 ENABLE_ACLK_HEVC, 4268 ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC, 4269 ENABLE_PCLK_HEVC, 4270 ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC, 4271 ENABLE_IP_HEVC0, 4272 ENABLE_IP_HEVC1, 4273 ENABLE_IP_HEVC_SECURE_SMMU_HEVC, 4274 }; 4275 4276 static const struct samsung_clk_reg_dump hevc_suspend_regs[] = { 4277 { MUX_SEL_HEVC, 0 }, 4278 }; 4279 4280 PNAME(mout_aclk_hevc_400_user_p) = { "oscclk", "aclk_hevc_400", }; 4281 4282 static const struct samsung_mux_clock hevc_mux_clks[] __initconst = { 4283 /* MUX_SEL_HEVC */ 4284 MUX(CLK_MOUT_ACLK_HEVC_400_USER, "mout_aclk_hevc_400_user", 4285 mout_aclk_hevc_400_user_p, MUX_SEL_HEVC, 0, 0), 4286 }; 4287 4288 static const struct samsung_div_clock hevc_div_clks[] __initconst = { 4289 /* DIV_HEVC */ 4290 DIV(CLK_DIV_PCLK_HEVC, "div_pclk_hevc", "mout_aclk_hevc_400_user", 4291 DIV_HEVC, 0, 2), 4292 }; 4293 4294 static const struct samsung_gate_clock hevc_gate_clks[] __initconst = { 4295 /* ENABLE_ACLK_HEVC */ 4296 GATE(CLK_ACLK_BTS_HEVC_1, "aclk_bts_hevc_1", "mout_aclk_hevc_400_user", 4297 ENABLE_ACLK_HEVC, 6, 0, 0), 4298 GATE(CLK_ACLK_BTS_HEVC_0, "aclk_bts_hevc_0", "mout_aclk_hevc_400_user", 4299 ENABLE_ACLK_HEVC, 5, 0, 0), 4300 GATE(CLK_ACLK_AHB2APB_HEVCP, "aclk_ahb2apb_hevcp", "div_pclk_hevc", 4301 ENABLE_ACLK_HEVC, 4, CLK_IGNORE_UNUSED, 0), 4302 GATE(CLK_ACLK_XIU_HEVCX, "aclk_xiu_hevcx", "mout_aclk_hevc_400_user", 4303 ENABLE_ACLK_HEVC, 3, CLK_IGNORE_UNUSED, 0), 4304 GATE(CLK_ACLK_HEVCNP_100, "aclk_hevcnp_100", "div_pclk_hevc", 4305 ENABLE_ACLK_HEVC, 2, CLK_IGNORE_UNUSED, 0), 4306 GATE(CLK_ACLK_HEVCND_400, "aclk_hevcnd_400", "mout_aclk_hevc_400_user", 4307 ENABLE_ACLK_HEVC, 1, CLK_IGNORE_UNUSED, 0), 4308 GATE(CLK_ACLK_HEVC, "aclk_hevc", "mout_aclk_hevc_400_user", 4309 ENABLE_ACLK_HEVC, 0, 0, 0), 4310 4311 /* ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC */ 4312 GATE(CLK_ACLK_SMMU_HEVC_1, "aclk_smmu_hevc_1", 4313 "mout_aclk_hevc_400_user", 4314 ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC, 4315 1, CLK_IGNORE_UNUSED, 0), 4316 GATE(CLK_ACLK_SMMU_HEVC_0, "aclk_smmu_hevc_0", 4317 "mout_aclk_hevc_400_user", 4318 ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC, 4319 0, CLK_IGNORE_UNUSED, 0), 4320 4321 /* ENABLE_PCLK_HEVC */ 4322 GATE(CLK_PCLK_BTS_HEVC_1, "pclk_bts_hevc_1", "div_pclk_hevc", 4323 ENABLE_PCLK_HEVC, 4, 0, 0), 4324 GATE(CLK_PCLK_BTS_HEVC_0, "pclk_bts_hevc_0", "div_pclk_hevc", 4325 ENABLE_PCLK_HEVC, 3, 0, 0), 4326 GATE(CLK_PCLK_PMU_HEVC, "pclk_pmu_hevc", "div_pclk_hevc", 4327 ENABLE_PCLK_HEVC, 2, CLK_IGNORE_UNUSED, 0), 4328 GATE(CLK_PCLK_SYSREG_HEVC, "pclk_sysreg_hevc", "div_pclk_hevc", 4329 ENABLE_PCLK_HEVC, 1, CLK_IGNORE_UNUSED, 0), 4330 GATE(CLK_PCLK_HEVC, "pclk_hevc", "div_pclk_hevc", 4331 ENABLE_PCLK_HEVC, 4, CLK_IGNORE_UNUSED, 0), 4332 4333 /* ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC */ 4334 GATE(CLK_PCLK_SMMU_HEVC_1, "pclk_smmu_hevc_1", "div_pclk_hevc", 4335 ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC, 4336 1, CLK_IGNORE_UNUSED, 0), 4337 GATE(CLK_PCLK_SMMU_HEVC_0, "pclk_smmu_hevc_0", "div_pclk_hevc", 4338 ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC, 4339 0, CLK_IGNORE_UNUSED, 0), 4340 }; 4341 4342 static const struct samsung_cmu_info hevc_cmu_info __initconst = { 4343 .mux_clks = hevc_mux_clks, 4344 .nr_mux_clks = ARRAY_SIZE(hevc_mux_clks), 4345 .div_clks = hevc_div_clks, 4346 .nr_div_clks = ARRAY_SIZE(hevc_div_clks), 4347 .gate_clks = hevc_gate_clks, 4348 .nr_gate_clks = ARRAY_SIZE(hevc_gate_clks), 4349 .nr_clk_ids = HEVC_NR_CLK, 4350 .clk_regs = hevc_clk_regs, 4351 .nr_clk_regs = ARRAY_SIZE(hevc_clk_regs), 4352 .suspend_regs = hevc_suspend_regs, 4353 .nr_suspend_regs = ARRAY_SIZE(hevc_suspend_regs), 4354 .clk_name = "aclk_hevc_400", 4355 }; 4356 4357 /* 4358 * Register offset definitions for CMU_ISP 4359 */ 4360 #define MUX_SEL_ISP 0x0200 4361 #define MUX_ENABLE_ISP 0x0300 4362 #define MUX_STAT_ISP 0x0400 4363 #define DIV_ISP 0x0600 4364 #define DIV_STAT_ISP 0x0700 4365 #define ENABLE_ACLK_ISP0 0x0800 4366 #define ENABLE_ACLK_ISP1 0x0804 4367 #define ENABLE_ACLK_ISP2 0x0808 4368 #define ENABLE_PCLK_ISP 0x0900 4369 #define ENABLE_SCLK_ISP 0x0a00 4370 #define ENABLE_IP_ISP0 0x0b00 4371 #define ENABLE_IP_ISP1 0x0b04 4372 #define ENABLE_IP_ISP2 0x0b08 4373 #define ENABLE_IP_ISP3 0x0b0c 4374 4375 static const unsigned long isp_clk_regs[] __initconst = { 4376 MUX_SEL_ISP, 4377 MUX_ENABLE_ISP, 4378 DIV_ISP, 4379 ENABLE_ACLK_ISP0, 4380 ENABLE_ACLK_ISP1, 4381 ENABLE_ACLK_ISP2, 4382 ENABLE_PCLK_ISP, 4383 ENABLE_SCLK_ISP, 4384 ENABLE_IP_ISP0, 4385 ENABLE_IP_ISP1, 4386 ENABLE_IP_ISP2, 4387 ENABLE_IP_ISP3, 4388 }; 4389 4390 static const struct samsung_clk_reg_dump isp_suspend_regs[] = { 4391 { MUX_SEL_ISP, 0 }, 4392 }; 4393 4394 PNAME(mout_aclk_isp_dis_400_user_p) = { "oscclk", "aclk_isp_dis_400", }; 4395 PNAME(mout_aclk_isp_400_user_p) = { "oscclk", "aclk_isp_400", }; 4396 4397 static const struct samsung_mux_clock isp_mux_clks[] __initconst = { 4398 /* MUX_SEL_ISP */ 4399 MUX(CLK_MOUT_ACLK_ISP_DIS_400_USER, "mout_aclk_isp_dis_400_user", 4400 mout_aclk_isp_dis_400_user_p, MUX_SEL_ISP, 4, 0), 4401 MUX(CLK_MOUT_ACLK_ISP_400_USER, "mout_aclk_isp_400_user", 4402 mout_aclk_isp_400_user_p, MUX_SEL_ISP, 0, 0), 4403 }; 4404 4405 static const struct samsung_div_clock isp_div_clks[] __initconst = { 4406 /* DIV_ISP */ 4407 DIV(CLK_DIV_PCLK_ISP_DIS, "div_pclk_isp_dis", 4408 "mout_aclk_isp_dis_400_user", DIV_ISP, 12, 3), 4409 DIV(CLK_DIV_PCLK_ISP, "div_pclk_isp", "mout_aclk_isp_400_user", 4410 DIV_ISP, 8, 3), 4411 DIV(CLK_DIV_ACLK_ISP_D_200, "div_aclk_isp_d_200", 4412 "mout_aclk_isp_400_user", DIV_ISP, 4, 3), 4413 DIV(CLK_DIV_ACLK_ISP_C_200, "div_aclk_isp_c_200", 4414 "mout_aclk_isp_400_user", DIV_ISP, 0, 3), 4415 }; 4416 4417 static const struct samsung_gate_clock isp_gate_clks[] __initconst = { 4418 /* ENABLE_ACLK_ISP0 */ 4419 GATE(CLK_ACLK_ISP_D_GLUE, "aclk_isp_d_glue", "mout_aclk_isp_400_user", 4420 ENABLE_ACLK_ISP0, 6, CLK_IGNORE_UNUSED, 0), 4421 GATE(CLK_ACLK_SCALERP, "aclk_scalerp", "mout_aclk_isp_400_user", 4422 ENABLE_ACLK_ISP0, 5, 0, 0), 4423 GATE(CLK_ACLK_3DNR, "aclk_3dnr", "mout_aclk_isp_400_user", 4424 ENABLE_ACLK_ISP0, 4, 0, 0), 4425 GATE(CLK_ACLK_DIS, "aclk_dis", "mout_aclk_isp_dis_400_user", 4426 ENABLE_ACLK_ISP0, 3, 0, 0), 4427 GATE(CLK_ACLK_SCALERC, "aclk_scalerc", "mout_aclk_isp_400_user", 4428 ENABLE_ACLK_ISP0, 2, 0, 0), 4429 GATE(CLK_ACLK_DRC, "aclk_drc", "mout_aclk_isp_400_user", 4430 ENABLE_ACLK_ISP0, 1, 0, 0), 4431 GATE(CLK_ACLK_ISP, "aclk_isp", "mout_aclk_isp_400_user", 4432 ENABLE_ACLK_ISP0, 0, 0, 0), 4433 4434 /* ENABLE_ACLK_ISP1 */ 4435 GATE(CLK_ACLK_AXIUS_SCALERP, "aclk_axius_scalerp", 4436 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1, 4437 17, CLK_IGNORE_UNUSED, 0), 4438 GATE(CLK_ACLK_AXIUS_SCALERC, "aclk_axius_scalerc", 4439 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1, 4440 16, CLK_IGNORE_UNUSED, 0), 4441 GATE(CLK_ACLK_AXIUS_DRC, "aclk_axius_drc", 4442 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1, 4443 15, CLK_IGNORE_UNUSED, 0), 4444 GATE(CLK_ACLK_ASYNCAHBM_ISP2P, "aclk_asyncahbm_isp2p", 4445 "div_pclk_isp", ENABLE_ACLK_ISP1, 4446 14, CLK_IGNORE_UNUSED, 0), 4447 GATE(CLK_ACLK_ASYNCAHBM_ISP1P, "aclk_asyncahbm_isp1p", 4448 "div_pclk_isp", ENABLE_ACLK_ISP1, 4449 13, CLK_IGNORE_UNUSED, 0), 4450 GATE(CLK_ACLK_ASYNCAXIS_DIS1, "aclk_asyncaxis_dis1", 4451 "mout_aclk_isp_dis_400_user", ENABLE_ACLK_ISP1, 4452 12, CLK_IGNORE_UNUSED, 0), 4453 GATE(CLK_ACLK_ASYNCAXIS_DIS0, "aclk_asyncaxis_dis0", 4454 "mout_aclk_isp_dis_400_user", ENABLE_ACLK_ISP1, 4455 11, CLK_IGNORE_UNUSED, 0), 4456 GATE(CLK_ACLK_ASYNCAXIM_DIS1, "aclk_asyncaxim_dis1", 4457 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1, 4458 10, CLK_IGNORE_UNUSED, 0), 4459 GATE(CLK_ACLK_ASYNCAXIM_DIS0, "aclk_asyncaxim_dis0", 4460 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1, 4461 9, CLK_IGNORE_UNUSED, 0), 4462 GATE(CLK_ACLK_ASYNCAXIM_ISP2P, "aclk_asyncaxim_isp2p", 4463 "div_aclk_isp_d_200", ENABLE_ACLK_ISP1, 4464 8, CLK_IGNORE_UNUSED, 0), 4465 GATE(CLK_ACLK_ASYNCAXIM_ISP1P, "aclk_asyncaxim_isp1p", 4466 "div_aclk_isp_c_200", ENABLE_ACLK_ISP1, 4467 7, CLK_IGNORE_UNUSED, 0), 4468 GATE(CLK_ACLK_AHB2APB_ISP2P, "aclk_ahb2apb_isp2p", "div_pclk_isp", 4469 ENABLE_ACLK_ISP1, 6, CLK_IGNORE_UNUSED, 0), 4470 GATE(CLK_ACLK_AHB2APB_ISP1P, "aclk_ahb2apb_isp1p", "div_pclk_isp", 4471 ENABLE_ACLK_ISP1, 5, CLK_IGNORE_UNUSED, 0), 4472 GATE(CLK_ACLK_AXI2APB_ISP2P, "aclk_axi2apb_isp2p", 4473 "div_aclk_isp_d_200", ENABLE_ACLK_ISP1, 4474 4, CLK_IGNORE_UNUSED, 0), 4475 GATE(CLK_ACLK_AXI2APB_ISP1P, "aclk_axi2apb_isp1p", 4476 "div_aclk_isp_c_200", ENABLE_ACLK_ISP1, 4477 3, CLK_IGNORE_UNUSED, 0), 4478 GATE(CLK_ACLK_XIU_ISPEX1, "aclk_xiu_ispex1", "mout_aclk_isp_400_user", 4479 ENABLE_ACLK_ISP1, 2, CLK_IGNORE_UNUSED, 0), 4480 GATE(CLK_ACLK_XIU_ISPEX0, "aclk_xiu_ispex0", "mout_aclk_isp_400_user", 4481 ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0), 4482 GATE(CLK_ACLK_ISPND_400, "aclk_ispnd_400", "mout_aclk_isp_400_user", 4483 ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0), 4484 4485 /* ENABLE_ACLK_ISP2 */ 4486 GATE(CLK_ACLK_SMMU_SCALERP, "aclk_smmu_scalerp", 4487 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2, 4488 13, CLK_IGNORE_UNUSED, 0), 4489 GATE(CLK_ACLK_SMMU_3DNR, "aclk_smmu_3dnr", "mout_aclk_isp_400_user", 4490 ENABLE_ACLK_ISP2, 12, CLK_IGNORE_UNUSED, 0), 4491 GATE(CLK_ACLK_SMMU_DIS1, "aclk_smmu_dis1", "mout_aclk_isp_400_user", 4492 ENABLE_ACLK_ISP2, 11, CLK_IGNORE_UNUSED, 0), 4493 GATE(CLK_ACLK_SMMU_DIS0, "aclk_smmu_dis0", "mout_aclk_isp_400_user", 4494 ENABLE_ACLK_ISP2, 10, CLK_IGNORE_UNUSED, 0), 4495 GATE(CLK_ACLK_SMMU_SCALERC, "aclk_smmu_scalerc", 4496 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2, 4497 9, CLK_IGNORE_UNUSED, 0), 4498 GATE(CLK_ACLK_SMMU_DRC, "aclk_smmu_drc", "mout_aclk_isp_400_user", 4499 ENABLE_ACLK_ISP2, 8, CLK_IGNORE_UNUSED, 0), 4500 GATE(CLK_ACLK_SMMU_ISP, "aclk_smmu_isp", "mout_aclk_isp_400_user", 4501 ENABLE_ACLK_ISP2, 7, CLK_IGNORE_UNUSED, 0), 4502 GATE(CLK_ACLK_BTS_SCALERP, "aclk_bts_scalerp", 4503 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2, 4504 6, CLK_IGNORE_UNUSED, 0), 4505 GATE(CLK_ACLK_BTS_3DR, "aclk_bts_3dnr", "mout_aclk_isp_400_user", 4506 ENABLE_ACLK_ISP2, 5, CLK_IGNORE_UNUSED, 0), 4507 GATE(CLK_ACLK_BTS_DIS1, "aclk_bts_dis1", "mout_aclk_isp_400_user", 4508 ENABLE_ACLK_ISP2, 4, CLK_IGNORE_UNUSED, 0), 4509 GATE(CLK_ACLK_BTS_DIS0, "aclk_bts_dis0", "mout_aclk_isp_400_user", 4510 ENABLE_ACLK_ISP2, 3, CLK_IGNORE_UNUSED, 0), 4511 GATE(CLK_ACLK_BTS_SCALERC, "aclk_bts_scalerc", 4512 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2, 4513 2, CLK_IGNORE_UNUSED, 0), 4514 GATE(CLK_ACLK_BTS_DRC, "aclk_bts_drc", "mout_aclk_isp_400_user", 4515 ENABLE_ACLK_ISP2, 1, CLK_IGNORE_UNUSED, 0), 4516 GATE(CLK_ACLK_BTS_ISP, "aclk_bts_isp", "mout_aclk_isp_400_user", 4517 ENABLE_ACLK_ISP2, 0, CLK_IGNORE_UNUSED, 0), 4518 4519 /* ENABLE_PCLK_ISP */ 4520 GATE(CLK_PCLK_SMMU_SCALERP, "pclk_smmu_scalerp", "div_aclk_isp_d_200", 4521 ENABLE_PCLK_ISP, 25, CLK_IGNORE_UNUSED, 0), 4522 GATE(CLK_PCLK_SMMU_3DNR, "pclk_smmu_3dnr", "div_aclk_isp_d_200", 4523 ENABLE_PCLK_ISP, 24, CLK_IGNORE_UNUSED, 0), 4524 GATE(CLK_PCLK_SMMU_DIS1, "pclk_smmu_dis1", "div_aclk_isp_d_200", 4525 ENABLE_PCLK_ISP, 23, CLK_IGNORE_UNUSED, 0), 4526 GATE(CLK_PCLK_SMMU_DIS0, "pclk_smmu_dis0", "div_aclk_isp_d_200", 4527 ENABLE_PCLK_ISP, 22, CLK_IGNORE_UNUSED, 0), 4528 GATE(CLK_PCLK_SMMU_SCALERC, "pclk_smmu_scalerc", "div_aclk_isp_c_200", 4529 ENABLE_PCLK_ISP, 21, CLK_IGNORE_UNUSED, 0), 4530 GATE(CLK_PCLK_SMMU_DRC, "pclk_smmu_drc", "div_aclk_isp_c_200", 4531 ENABLE_PCLK_ISP, 20, CLK_IGNORE_UNUSED, 0), 4532 GATE(CLK_PCLK_SMMU_ISP, "pclk_smmu_isp", "div_aclk_isp_c_200", 4533 ENABLE_PCLK_ISP, 19, CLK_IGNORE_UNUSED, 0), 4534 GATE(CLK_PCLK_BTS_SCALERP, "pclk_bts_scalerp", "div_pclk_isp", 4535 ENABLE_PCLK_ISP, 18, CLK_IGNORE_UNUSED, 0), 4536 GATE(CLK_PCLK_BTS_3DNR, "pclk_bts_3dnr", "div_pclk_isp", 4537 ENABLE_PCLK_ISP, 17, CLK_IGNORE_UNUSED, 0), 4538 GATE(CLK_PCLK_BTS_DIS1, "pclk_bts_dis1", "div_pclk_isp", 4539 ENABLE_PCLK_ISP, 16, CLK_IGNORE_UNUSED, 0), 4540 GATE(CLK_PCLK_BTS_DIS0, "pclk_bts_dis0", "div_pclk_isp", 4541 ENABLE_PCLK_ISP, 15, CLK_IGNORE_UNUSED, 0), 4542 GATE(CLK_PCLK_BTS_SCALERC, "pclk_bts_scalerc", "div_pclk_isp", 4543 ENABLE_PCLK_ISP, 14, CLK_IGNORE_UNUSED, 0), 4544 GATE(CLK_PCLK_BTS_DRC, "pclk_bts_drc", "div_pclk_isp", 4545 ENABLE_PCLK_ISP, 13, CLK_IGNORE_UNUSED, 0), 4546 GATE(CLK_PCLK_BTS_ISP, "pclk_bts_isp", "div_pclk_isp", 4547 ENABLE_PCLK_ISP, 12, CLK_IGNORE_UNUSED, 0), 4548 GATE(CLK_PCLK_ASYNCAXI_DIS1, "pclk_asyncaxi_dis1", "div_pclk_isp", 4549 ENABLE_PCLK_ISP, 11, CLK_IGNORE_UNUSED, 0), 4550 GATE(CLK_PCLK_ASYNCAXI_DIS0, "pclk_asyncaxi_dis0", "div_pclk_isp", 4551 ENABLE_PCLK_ISP, 10, CLK_IGNORE_UNUSED, 0), 4552 GATE(CLK_PCLK_PMU_ISP, "pclk_pmu_isp", "div_pclk_isp", 4553 ENABLE_PCLK_ISP, 9, CLK_IGNORE_UNUSED, 0), 4554 GATE(CLK_PCLK_SYSREG_ISP, "pclk_sysreg_isp", "div_pclk_isp", 4555 ENABLE_PCLK_ISP, 8, CLK_IGNORE_UNUSED, 0), 4556 GATE(CLK_PCLK_CMU_ISP_LOCAL, "pclk_cmu_isp_local", 4557 "div_aclk_isp_c_200", ENABLE_PCLK_ISP, 4558 7, CLK_IGNORE_UNUSED, 0), 4559 GATE(CLK_PCLK_SCALERP, "pclk_scalerp", "div_aclk_isp_d_200", 4560 ENABLE_PCLK_ISP, 6, CLK_IGNORE_UNUSED, 0), 4561 GATE(CLK_PCLK_3DNR, "pclk_3dnr", "div_aclk_isp_d_200", 4562 ENABLE_PCLK_ISP, 5, CLK_IGNORE_UNUSED, 0), 4563 GATE(CLK_PCLK_DIS_CORE, "pclk_dis_core", "div_pclk_isp_dis", 4564 ENABLE_PCLK_ISP, 4, CLK_IGNORE_UNUSED, 0), 4565 GATE(CLK_PCLK_DIS, "pclk_dis", "div_aclk_isp_d_200", 4566 ENABLE_PCLK_ISP, 3, CLK_IGNORE_UNUSED, 0), 4567 GATE(CLK_PCLK_SCALERC, "pclk_scalerc", "div_aclk_isp_c_200", 4568 ENABLE_PCLK_ISP, 2, CLK_IGNORE_UNUSED, 0), 4569 GATE(CLK_PCLK_DRC, "pclk_drc", "div_aclk_isp_c_200", 4570 ENABLE_PCLK_ISP, 1, CLK_IGNORE_UNUSED, 0), 4571 GATE(CLK_PCLK_ISP, "pclk_isp", "div_aclk_isp_c_200", 4572 ENABLE_PCLK_ISP, 0, CLK_IGNORE_UNUSED, 0), 4573 4574 /* ENABLE_SCLK_ISP */ 4575 GATE(CLK_SCLK_PIXELASYNCS_DIS, "sclk_pixelasyncs_dis", 4576 "mout_aclk_isp_dis_400_user", ENABLE_SCLK_ISP, 4577 5, CLK_IGNORE_UNUSED, 0), 4578 GATE(CLK_SCLK_PIXELASYNCM_DIS, "sclk_pixelasyncm_dis", 4579 "mout_aclk_isp_dis_400_user", ENABLE_SCLK_ISP, 4580 4, CLK_IGNORE_UNUSED, 0), 4581 GATE(CLK_SCLK_PIXELASYNCS_SCALERP, "sclk_pixelasyncs_scalerp", 4582 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP, 4583 3, CLK_IGNORE_UNUSED, 0), 4584 GATE(CLK_SCLK_PIXELASYNCM_ISPD, "sclk_pixelasyncm_ispd", 4585 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP, 4586 2, CLK_IGNORE_UNUSED, 0), 4587 GATE(CLK_SCLK_PIXELASYNCS_ISPC, "sclk_pixelasyncs_ispc", 4588 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP, 4589 1, CLK_IGNORE_UNUSED, 0), 4590 GATE(CLK_SCLK_PIXELASYNCM_ISPC, "sclk_pixelasyncm_ispc", 4591 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP, 4592 0, CLK_IGNORE_UNUSED, 0), 4593 }; 4594 4595 static const struct samsung_cmu_info isp_cmu_info __initconst = { 4596 .mux_clks = isp_mux_clks, 4597 .nr_mux_clks = ARRAY_SIZE(isp_mux_clks), 4598 .div_clks = isp_div_clks, 4599 .nr_div_clks = ARRAY_SIZE(isp_div_clks), 4600 .gate_clks = isp_gate_clks, 4601 .nr_gate_clks = ARRAY_SIZE(isp_gate_clks), 4602 .nr_clk_ids = ISP_NR_CLK, 4603 .clk_regs = isp_clk_regs, 4604 .nr_clk_regs = ARRAY_SIZE(isp_clk_regs), 4605 .suspend_regs = isp_suspend_regs, 4606 .nr_suspend_regs = ARRAY_SIZE(isp_suspend_regs), 4607 .clk_name = "aclk_isp_400", 4608 }; 4609 4610 /* 4611 * Register offset definitions for CMU_CAM0 4612 */ 4613 #define MUX_SEL_CAM00 0x0200 4614 #define MUX_SEL_CAM01 0x0204 4615 #define MUX_SEL_CAM02 0x0208 4616 #define MUX_SEL_CAM03 0x020c 4617 #define MUX_SEL_CAM04 0x0210 4618 #define MUX_ENABLE_CAM00 0x0300 4619 #define MUX_ENABLE_CAM01 0x0304 4620 #define MUX_ENABLE_CAM02 0x0308 4621 #define MUX_ENABLE_CAM03 0x030c 4622 #define MUX_ENABLE_CAM04 0x0310 4623 #define MUX_STAT_CAM00 0x0400 4624 #define MUX_STAT_CAM01 0x0404 4625 #define MUX_STAT_CAM02 0x0408 4626 #define MUX_STAT_CAM03 0x040c 4627 #define MUX_STAT_CAM04 0x0410 4628 #define MUX_IGNORE_CAM01 0x0504 4629 #define DIV_CAM00 0x0600 4630 #define DIV_CAM01 0x0604 4631 #define DIV_CAM02 0x0608 4632 #define DIV_CAM03 0x060c 4633 #define DIV_STAT_CAM00 0x0700 4634 #define DIV_STAT_CAM01 0x0704 4635 #define DIV_STAT_CAM02 0x0708 4636 #define DIV_STAT_CAM03 0x070c 4637 #define ENABLE_ACLK_CAM00 0X0800 4638 #define ENABLE_ACLK_CAM01 0X0804 4639 #define ENABLE_ACLK_CAM02 0X0808 4640 #define ENABLE_PCLK_CAM0 0X0900 4641 #define ENABLE_SCLK_CAM0 0X0a00 4642 #define ENABLE_IP_CAM00 0X0b00 4643 #define ENABLE_IP_CAM01 0X0b04 4644 #define ENABLE_IP_CAM02 0X0b08 4645 #define ENABLE_IP_CAM03 0X0b0C 4646 4647 static const unsigned long cam0_clk_regs[] __initconst = { 4648 MUX_SEL_CAM00, 4649 MUX_SEL_CAM01, 4650 MUX_SEL_CAM02, 4651 MUX_SEL_CAM03, 4652 MUX_SEL_CAM04, 4653 MUX_ENABLE_CAM00, 4654 MUX_ENABLE_CAM01, 4655 MUX_ENABLE_CAM02, 4656 MUX_ENABLE_CAM03, 4657 MUX_ENABLE_CAM04, 4658 MUX_IGNORE_CAM01, 4659 DIV_CAM00, 4660 DIV_CAM01, 4661 DIV_CAM02, 4662 DIV_CAM03, 4663 ENABLE_ACLK_CAM00, 4664 ENABLE_ACLK_CAM01, 4665 ENABLE_ACLK_CAM02, 4666 ENABLE_PCLK_CAM0, 4667 ENABLE_SCLK_CAM0, 4668 ENABLE_IP_CAM00, 4669 ENABLE_IP_CAM01, 4670 ENABLE_IP_CAM02, 4671 ENABLE_IP_CAM03, 4672 }; 4673 4674 static const struct samsung_clk_reg_dump cam0_suspend_regs[] = { 4675 { MUX_SEL_CAM00, 0 }, 4676 { MUX_SEL_CAM01, 0 }, 4677 { MUX_SEL_CAM02, 0 }, 4678 { MUX_SEL_CAM03, 0 }, 4679 { MUX_SEL_CAM04, 0 }, 4680 }; 4681 4682 PNAME(mout_aclk_cam0_333_user_p) = { "oscclk", "aclk_cam0_333", }; 4683 PNAME(mout_aclk_cam0_400_user_p) = { "oscclk", "aclk_cam0_400", }; 4684 PNAME(mout_aclk_cam0_552_user_p) = { "oscclk", "aclk_cam0_552", }; 4685 4686 PNAME(mout_phyclk_rxbyteclkhs0_s4_user_p) = { "oscclk", 4687 "phyclk_rxbyteclkhs0_s4_phy", }; 4688 PNAME(mout_phyclk_rxbyteclkhs0_s2a_user_p) = { "oscclk", 4689 "phyclk_rxbyteclkhs0_s2a_phy", }; 4690 4691 PNAME(mout_aclk_lite_d_b_p) = { "mout_aclk_lite_d_a", 4692 "mout_aclk_cam0_333_user", }; 4693 PNAME(mout_aclk_lite_d_a_p) = { "mout_aclk_cam0_552_user", 4694 "mout_aclk_cam0_400_user", }; 4695 PNAME(mout_aclk_lite_b_b_p) = { "mout_aclk_lite_b_a", 4696 "mout_aclk_cam0_333_user", }; 4697 PNAME(mout_aclk_lite_b_a_p) = { "mout_aclk_cam0_552_user", 4698 "mout_aclk_cam0_400_user", }; 4699 PNAME(mout_aclk_lite_a_b_p) = { "mout_aclk_lite_a_a", 4700 "mout_aclk_cam0_333_user", }; 4701 PNAME(mout_aclk_lite_a_a_p) = { "mout_aclk_cam0_552_user", 4702 "mout_aclk_cam0_400_user", }; 4703 PNAME(mout_aclk_cam0_400_p) = { "mout_aclk_cam0_400_user", 4704 "mout_aclk_cam0_333_user", }; 4705 4706 PNAME(mout_aclk_csis1_b_p) = { "mout_aclk_csis1_a", 4707 "mout_aclk_cam0_333_user" }; 4708 PNAME(mout_aclk_csis1_a_p) = { "mout_aclk_cam0_552_user", 4709 "mout_aclk_cam0_400_user", }; 4710 PNAME(mout_aclk_csis0_b_p) = { "mout_aclk_csis0_a", 4711 "mout_aclk_cam0_333_user", }; 4712 PNAME(mout_aclk_csis0_a_p) = { "mout_aclk_cam0_552_user", 4713 "mout_aclk-cam0_400_user", }; 4714 PNAME(mout_aclk_3aa1_b_p) = { "mout_aclk_3aa1_a", 4715 "mout_aclk_cam0_333_user", }; 4716 PNAME(mout_aclk_3aa1_a_p) = { "mout_aclk_cam0_552_user", 4717 "mout_aclk_cam0_400_user", }; 4718 PNAME(mout_aclk_3aa0_b_p) = { "mout_aclk_3aa0_a", 4719 "mout_aclk_cam0_333_user", }; 4720 PNAME(mout_aclk_3aa0_a_p) = { "mout_aclk_cam0_552_user", 4721 "mout_aclk_cam0_400_user", }; 4722 4723 PNAME(mout_sclk_lite_freecnt_c_p) = { "mout_sclk_lite_freecnt_b", 4724 "div_pclk_lite_d", }; 4725 PNAME(mout_sclk_lite_freecnt_b_p) = { "mout_sclk_lite_freecnt_a", 4726 "div_pclk_pixelasync_lite_c", }; 4727 PNAME(mout_sclk_lite_freecnt_a_p) = { "div_pclk_lite_a", 4728 "div_pclk_lite_b", }; 4729 PNAME(mout_sclk_pixelasync_lite_c_b_p) = { "mout_sclk_pixelasync_lite_c_a", 4730 "mout_aclk_cam0_333_user", }; 4731 PNAME(mout_sclk_pixelasync_lite_c_a_p) = { "mout_aclk_cam0_552_user", 4732 "mout_aclk_cam0_400_user", }; 4733 PNAME(mout_sclk_pixelasync_lite_c_init_b_p) = { 4734 "mout_sclk_pixelasync_lite_c_init_a", 4735 "mout_aclk_cam0_400_user", }; 4736 PNAME(mout_sclk_pixelasync_lite_c_init_a_p) = { 4737 "mout_aclk_cam0_552_user", 4738 "mout_aclk_cam0_400_user", }; 4739 4740 static const struct samsung_fixed_rate_clock cam0_fixed_clks[] __initconst = { 4741 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY, "phyclk_rxbyteclkhs0_s4_phy", 4742 NULL, 0, 100000000), 4743 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY, "phyclk_rxbyteclkhs0_s2a_phy", 4744 NULL, 0, 100000000), 4745 }; 4746 4747 static const struct samsung_mux_clock cam0_mux_clks[] __initconst = { 4748 /* MUX_SEL_CAM00 */ 4749 MUX(CLK_MOUT_ACLK_CAM0_333_USER, "mout_aclk_cam0_333_user", 4750 mout_aclk_cam0_333_user_p, MUX_SEL_CAM00, 8, 1), 4751 MUX(CLK_MOUT_ACLK_CAM0_400_USER, "mout_aclk_cam0_400_user", 4752 mout_aclk_cam0_400_user_p, MUX_SEL_CAM00, 4, 1), 4753 MUX(CLK_MOUT_ACLK_CAM0_552_USER, "mout_aclk_cam0_552_user", 4754 mout_aclk_cam0_552_user_p, MUX_SEL_CAM00, 0, 1), 4755 4756 /* MUX_SEL_CAM01 */ 4757 MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S4_USER, 4758 "mout_phyclk_rxbyteclkhs0_s4_user", 4759 mout_phyclk_rxbyteclkhs0_s4_user_p, 4760 MUX_SEL_CAM01, 4, 1), 4761 MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2A_USER, 4762 "mout_phyclk_rxbyteclkhs0_s2a_user", 4763 mout_phyclk_rxbyteclkhs0_s2a_user_p, 4764 MUX_SEL_CAM01, 0, 1), 4765 4766 /* MUX_SEL_CAM02 */ 4767 MUX(CLK_MOUT_ACLK_LITE_D_B, "mout_aclk_lite_d_b", mout_aclk_lite_d_b_p, 4768 MUX_SEL_CAM02, 24, 1), 4769 MUX(CLK_MOUT_ACLK_LITE_D_A, "mout_aclk_lite_d_a", mout_aclk_lite_d_a_p, 4770 MUX_SEL_CAM02, 20, 1), 4771 MUX(CLK_MOUT_ACLK_LITE_B_B, "mout_aclk_lite_b_b", mout_aclk_lite_b_b_p, 4772 MUX_SEL_CAM02, 16, 1), 4773 MUX(CLK_MOUT_ACLK_LITE_B_A, "mout_aclk_lite_b_a", mout_aclk_lite_b_a_p, 4774 MUX_SEL_CAM02, 12, 1), 4775 MUX(CLK_MOUT_ACLK_LITE_A_B, "mout_aclk_lite_a_b", mout_aclk_lite_a_b_p, 4776 MUX_SEL_CAM02, 8, 1), 4777 MUX(CLK_MOUT_ACLK_LITE_A_A, "mout_aclk_lite_a_a", mout_aclk_lite_a_a_p, 4778 MUX_SEL_CAM02, 4, 1), 4779 MUX(CLK_MOUT_ACLK_CAM0_400, "mout_aclk_cam0_400", mout_aclk_cam0_400_p, 4780 MUX_SEL_CAM02, 0, 1), 4781 4782 /* MUX_SEL_CAM03 */ 4783 MUX(CLK_MOUT_ACLK_CSIS1_B, "mout_aclk_csis1_b", mout_aclk_csis1_b_p, 4784 MUX_SEL_CAM03, 28, 1), 4785 MUX(CLK_MOUT_ACLK_CSIS1_A, "mout_aclk_csis1_a", mout_aclk_csis1_a_p, 4786 MUX_SEL_CAM03, 24, 1), 4787 MUX(CLK_MOUT_ACLK_CSIS0_B, "mout_aclk_csis0_b", mout_aclk_csis0_b_p, 4788 MUX_SEL_CAM03, 20, 1), 4789 MUX(CLK_MOUT_ACLK_CSIS0_A, "mout_aclk_csis0_a", mout_aclk_csis0_a_p, 4790 MUX_SEL_CAM03, 16, 1), 4791 MUX(CLK_MOUT_ACLK_3AA1_B, "mout_aclk_3aa1_b", mout_aclk_3aa1_b_p, 4792 MUX_SEL_CAM03, 12, 1), 4793 MUX(CLK_MOUT_ACLK_3AA1_A, "mout_aclk_3aa1_a", mout_aclk_3aa1_a_p, 4794 MUX_SEL_CAM03, 8, 1), 4795 MUX(CLK_MOUT_ACLK_3AA0_B, "mout_aclk_3aa0_b", mout_aclk_3aa0_b_p, 4796 MUX_SEL_CAM03, 4, 1), 4797 MUX(CLK_MOUT_ACLK_3AA0_A, "mout_aclk_3aa0_a", mout_aclk_3aa0_a_p, 4798 MUX_SEL_CAM03, 0, 1), 4799 4800 /* MUX_SEL_CAM04 */ 4801 MUX(CLK_MOUT_SCLK_LITE_FREECNT_C, "mout_sclk_lite_freecnt_c", 4802 mout_sclk_lite_freecnt_c_p, MUX_SEL_CAM04, 24, 1), 4803 MUX(CLK_MOUT_SCLK_LITE_FREECNT_B, "mout_sclk_lite_freecnt_b", 4804 mout_sclk_lite_freecnt_b_p, MUX_SEL_CAM04, 20, 1), 4805 MUX(CLK_MOUT_SCLK_LITE_FREECNT_A, "mout_sclk_lite_freecnt_a", 4806 mout_sclk_lite_freecnt_a_p, MUX_SEL_CAM04, 16, 1), 4807 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_B, "mout_sclk_pixelasync_lite_c_b", 4808 mout_sclk_pixelasync_lite_c_b_p, MUX_SEL_CAM04, 12, 1), 4809 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_A, "mout_sclk_pixelasync_lite_c_a", 4810 mout_sclk_pixelasync_lite_c_a_p, MUX_SEL_CAM04, 8, 1), 4811 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_B, 4812 "mout_sclk_pixelasync_lite_c_init_b", 4813 mout_sclk_pixelasync_lite_c_init_b_p, 4814 MUX_SEL_CAM04, 4, 1), 4815 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_A, 4816 "mout_sclk_pixelasync_lite_c_init_a", 4817 mout_sclk_pixelasync_lite_c_init_a_p, 4818 MUX_SEL_CAM04, 0, 1), 4819 }; 4820 4821 static const struct samsung_div_clock cam0_div_clks[] __initconst = { 4822 /* DIV_CAM00 */ 4823 DIV(CLK_DIV_PCLK_CAM0_50, "div_pclk_cam0_50", "div_aclk_cam0_200", 4824 DIV_CAM00, 8, 2), 4825 DIV(CLK_DIV_ACLK_CAM0_200, "div_aclk_cam0_200", "mout_aclk_cam0_400", 4826 DIV_CAM00, 4, 3), 4827 DIV(CLK_DIV_ACLK_CAM0_BUS_400, "div_aclk_cam0_bus_400", 4828 "mout_aclk_cam0_400", DIV_CAM00, 0, 3), 4829 4830 /* DIV_CAM01 */ 4831 DIV(CLK_DIV_PCLK_LITE_D, "div_pclk_lite_d", "div_aclk_lite_d", 4832 DIV_CAM01, 20, 2), 4833 DIV(CLK_DIV_ACLK_LITE_D, "div_aclk_lite_d", "mout_aclk_lite_d_b", 4834 DIV_CAM01, 16, 3), 4835 DIV(CLK_DIV_PCLK_LITE_B, "div_pclk_lite_b", "div_aclk_lite_b", 4836 DIV_CAM01, 12, 2), 4837 DIV(CLK_DIV_ACLK_LITE_B, "div_aclk_lite_b", "mout_aclk_lite_b_b", 4838 DIV_CAM01, 8, 3), 4839 DIV(CLK_DIV_PCLK_LITE_A, "div_pclk_lite_a", "div_aclk_lite_a", 4840 DIV_CAM01, 4, 2), 4841 DIV(CLK_DIV_ACLK_LITE_A, "div_aclk_lite_a", "mout_aclk_lite_a_b", 4842 DIV_CAM01, 0, 3), 4843 4844 /* DIV_CAM02 */ 4845 DIV(CLK_DIV_ACLK_CSIS1, "div_aclk_csis1", "mout_aclk_csis1_b", 4846 DIV_CAM02, 20, 3), 4847 DIV(CLK_DIV_ACLK_CSIS0, "div_aclk_csis0", "mout_aclk_csis0_b", 4848 DIV_CAM02, 16, 3), 4849 DIV(CLK_DIV_PCLK_3AA1, "div_pclk_3aa1", "div_aclk_3aa1", 4850 DIV_CAM02, 12, 2), 4851 DIV(CLK_DIV_ACLK_3AA1, "div_aclk_3aa1", "mout_aclk_3aa1_b", 4852 DIV_CAM02, 8, 3), 4853 DIV(CLK_DIV_PCLK_3AA0, "div_pclk_3aa0", "div_aclk_3aa0", 4854 DIV_CAM02, 4, 2), 4855 DIV(CLK_DIV_ACLK_3AA0, "div_aclk_3aa0", "mout_aclk_3aa0_b", 4856 DIV_CAM02, 0, 3), 4857 4858 /* DIV_CAM03 */ 4859 DIV(CLK_DIV_SCLK_PIXELASYNC_LITE_C, "div_sclk_pixelasync_lite_c", 4860 "mout_sclk_pixelasync_lite_c_b", DIV_CAM03, 8, 3), 4861 DIV(CLK_DIV_PCLK_PIXELASYNC_LITE_C, "div_pclk_pixelasync_lite_c", 4862 "div_sclk_pixelasync_lite_c_init", DIV_CAM03, 4, 2), 4863 DIV(CLK_DIV_SCLK_PIXELASYNC_LITE_C_INIT, 4864 "div_sclk_pixelasync_lite_c_init", 4865 "mout_sclk_pixelasync_lite_c_init_b", DIV_CAM03, 0, 3), 4866 }; 4867 4868 static const struct samsung_gate_clock cam0_gate_clks[] __initconst = { 4869 /* ENABLE_ACLK_CAM00 */ 4870 GATE(CLK_ACLK_CSIS1, "aclk_csis1", "div_aclk_csis1", ENABLE_ACLK_CAM00, 4871 6, 0, 0), 4872 GATE(CLK_ACLK_CSIS0, "aclk_csis0", "div_aclk_csis0", ENABLE_ACLK_CAM00, 4873 5, 0, 0), 4874 GATE(CLK_ACLK_3AA1, "aclk_3aa1", "div_aclk_3aa1", ENABLE_ACLK_CAM00, 4875 4, 0, 0), 4876 GATE(CLK_ACLK_3AA0, "aclk_3aa0", "div_aclk_3aa0", ENABLE_ACLK_CAM00, 4877 3, 0, 0), 4878 GATE(CLK_ACLK_LITE_D, "aclk_lite_d", "div_aclk_lite_d", 4879 ENABLE_ACLK_CAM00, 2, 0, 0), 4880 GATE(CLK_ACLK_LITE_B, "aclk_lite_b", "div_aclk_lite_b", 4881 ENABLE_ACLK_CAM00, 1, 0, 0), 4882 GATE(CLK_ACLK_LITE_A, "aclk_lite_a", "div_aclk_lite_a", 4883 ENABLE_ACLK_CAM00, 0, 0, 0), 4884 4885 /* ENABLE_ACLK_CAM01 */ 4886 GATE(CLK_ACLK_AHBSYNCDN, "aclk_ahbsyncdn", "div_aclk_cam0_200", 4887 ENABLE_ACLK_CAM01, 31, CLK_IGNORE_UNUSED, 0), 4888 GATE(CLK_ACLK_AXIUS_LITE_D, "aclk_axius_lite_d", "div_aclk_cam0_bus_400", 4889 ENABLE_ACLK_CAM01, 30, CLK_IGNORE_UNUSED, 0), 4890 GATE(CLK_ACLK_AXIUS_LITE_B, "aclk_axius_lite_b", "div_aclk_cam0_bus_400", 4891 ENABLE_ACLK_CAM01, 29, CLK_IGNORE_UNUSED, 0), 4892 GATE(CLK_ACLK_AXIUS_LITE_A, "aclk_axius_lite_a", "div_aclk_cam0_bus_400", 4893 ENABLE_ACLK_CAM01, 28, CLK_IGNORE_UNUSED, 0), 4894 GATE(CLK_ACLK_ASYNCAPBM_3AA1, "aclk_asyncapbm_3aa1", "div_pclk_3aa1", 4895 ENABLE_ACLK_CAM01, 27, CLK_IGNORE_UNUSED, 0), 4896 GATE(CLK_ACLK_ASYNCAPBS_3AA1, "aclk_asyncapbs_3aa1", "div_aclk_3aa1", 4897 ENABLE_ACLK_CAM01, 26, CLK_IGNORE_UNUSED, 0), 4898 GATE(CLK_ACLK_ASYNCAPBM_3AA0, "aclk_asyncapbm_3aa0", "div_pclk_3aa0", 4899 ENABLE_ACLK_CAM01, 25, CLK_IGNORE_UNUSED, 0), 4900 GATE(CLK_ACLK_ASYNCAPBS_3AA0, "aclk_asyncapbs_3aa0", "div_aclk_3aa0", 4901 ENABLE_ACLK_CAM01, 24, CLK_IGNORE_UNUSED, 0), 4902 GATE(CLK_ACLK_ASYNCAPBM_LITE_D, "aclk_asyncapbm_lite_d", 4903 "div_pclk_lite_d", ENABLE_ACLK_CAM01, 4904 23, CLK_IGNORE_UNUSED, 0), 4905 GATE(CLK_ACLK_ASYNCAPBS_LITE_D, "aclk_asyncapbs_lite_d", 4906 "div_aclk_cam0_200", ENABLE_ACLK_CAM01, 4907 22, CLK_IGNORE_UNUSED, 0), 4908 GATE(CLK_ACLK_ASYNCAPBM_LITE_B, "aclk_asyncapbm_lite_b", 4909 "div_pclk_lite_b", ENABLE_ACLK_CAM01, 4910 21, CLK_IGNORE_UNUSED, 0), 4911 GATE(CLK_ACLK_ASYNCAPBS_LITE_B, "aclk_asyncapbs_lite_b", 4912 "div_aclk_cam0_200", ENABLE_ACLK_CAM01, 4913 20, CLK_IGNORE_UNUSED, 0), 4914 GATE(CLK_ACLK_ASYNCAPBM_LITE_A, "aclk_asyncapbm_lite_a", 4915 "div_pclk_lite_a", ENABLE_ACLK_CAM01, 4916 19, CLK_IGNORE_UNUSED, 0), 4917 GATE(CLK_ACLK_ASYNCAPBS_LITE_A, "aclk_asyncapbs_lite_a", 4918 "div_aclk_cam0_200", ENABLE_ACLK_CAM01, 4919 18, CLK_IGNORE_UNUSED, 0), 4920 GATE(CLK_ACLK_ASYNCAXIM_ISP0P, "aclk_asyncaxim_isp0p", 4921 "div_aclk_cam0_200", ENABLE_ACLK_CAM01, 4922 17, CLK_IGNORE_UNUSED, 0), 4923 GATE(CLK_ACLK_ASYNCAXIM_3AA1, "aclk_asyncaxim_3aa1", 4924 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01, 4925 16, CLK_IGNORE_UNUSED, 0), 4926 GATE(CLK_ACLK_ASYNCAXIS_3AA1, "aclk_asyncaxis_3aa1", 4927 "div_aclk_3aa1", ENABLE_ACLK_CAM01, 4928 15, CLK_IGNORE_UNUSED, 0), 4929 GATE(CLK_ACLK_ASYNCAXIM_3AA0, "aclk_asyncaxim_3aa0", 4930 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01, 4931 14, CLK_IGNORE_UNUSED, 0), 4932 GATE(CLK_ACLK_ASYNCAXIS_3AA0, "aclk_asyncaxis_3aa0", 4933 "div_aclk_3aa0", ENABLE_ACLK_CAM01, 4934 13, CLK_IGNORE_UNUSED, 0), 4935 GATE(CLK_ACLK_ASYNCAXIM_LITE_D, "aclk_asyncaxim_lite_d", 4936 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01, 4937 12, CLK_IGNORE_UNUSED, 0), 4938 GATE(CLK_ACLK_ASYNCAXIS_LITE_D, "aclk_asyncaxis_lite_d", 4939 "div_aclk_lite_d", ENABLE_ACLK_CAM01, 4940 11, CLK_IGNORE_UNUSED, 0), 4941 GATE(CLK_ACLK_ASYNCAXIM_LITE_B, "aclk_asyncaxim_lite_b", 4942 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01, 4943 10, CLK_IGNORE_UNUSED, 0), 4944 GATE(CLK_ACLK_ASYNCAXIS_LITE_B, "aclk_asyncaxis_lite_b", 4945 "div_aclk_lite_b", ENABLE_ACLK_CAM01, 4946 9, CLK_IGNORE_UNUSED, 0), 4947 GATE(CLK_ACLK_ASYNCAXIM_LITE_A, "aclk_asyncaxim_lite_a", 4948 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01, 4949 8, CLK_IGNORE_UNUSED, 0), 4950 GATE(CLK_ACLK_ASYNCAXIS_LITE_A, "aclk_asyncaxis_lite_a", 4951 "div_aclk_lite_a", ENABLE_ACLK_CAM01, 4952 7, CLK_IGNORE_UNUSED, 0), 4953 GATE(CLK_ACLK_AHB2APB_ISPSFRP, "aclk_ahb2apb_ispsfrp", 4954 "div_pclk_cam0_50", ENABLE_ACLK_CAM01, 4955 6, CLK_IGNORE_UNUSED, 0), 4956 GATE(CLK_ACLK_AXI2APB_ISP0P, "aclk_axi2apb_isp0p", "div_aclk_cam0_200", 4957 ENABLE_ACLK_CAM01, 5, CLK_IGNORE_UNUSED, 0), 4958 GATE(CLK_ACLK_AXI2AHB_ISP0P, "aclk_axi2ahb_isp0p", "div_aclk_cam0_200", 4959 ENABLE_ACLK_CAM01, 4, CLK_IGNORE_UNUSED, 0), 4960 GATE(CLK_ACLK_XIU_IS0X, "aclk_xiu_is0x", "div_aclk_cam0_200", 4961 ENABLE_ACLK_CAM01, 3, CLK_IGNORE_UNUSED, 0), 4962 GATE(CLK_ACLK_XIU_ISP0EX, "aclk_xiu_isp0ex", "div_aclk_cam0_bus_400", 4963 ENABLE_ACLK_CAM01, 2, CLK_IGNORE_UNUSED, 0), 4964 GATE(CLK_ACLK_CAM0NP_276, "aclk_cam0np_276", "div_aclk_cam0_200", 4965 ENABLE_ACLK_CAM01, 1, CLK_IGNORE_UNUSED, 0), 4966 GATE(CLK_ACLK_CAM0ND_400, "aclk_cam0nd_400", "div_aclk_cam0_bus_400", 4967 ENABLE_ACLK_CAM01, 0, CLK_IGNORE_UNUSED, 0), 4968 4969 /* ENABLE_ACLK_CAM02 */ 4970 GATE(CLK_ACLK_SMMU_3AA1, "aclk_smmu_3aa1", "div_aclk_cam0_bus_400", 4971 ENABLE_ACLK_CAM02, 9, CLK_IGNORE_UNUSED, 0), 4972 GATE(CLK_ACLK_SMMU_3AA0, "aclk_smmu_3aa0", "div_aclk_cam0_bus_400", 4973 ENABLE_ACLK_CAM02, 8, CLK_IGNORE_UNUSED, 0), 4974 GATE(CLK_ACLK_SMMU_LITE_D, "aclk_smmu_lite_d", "div_aclk_cam0_bus_400", 4975 ENABLE_ACLK_CAM02, 7, CLK_IGNORE_UNUSED, 0), 4976 GATE(CLK_ACLK_SMMU_LITE_B, "aclk_smmu_lite_b", "div_aclk_cam0_bus_400", 4977 ENABLE_ACLK_CAM02, 6, CLK_IGNORE_UNUSED, 0), 4978 GATE(CLK_ACLK_SMMU_LITE_A, "aclk_smmu_lite_a", "div_aclk_cam0_bus_400", 4979 ENABLE_ACLK_CAM02, 5, CLK_IGNORE_UNUSED, 0), 4980 GATE(CLK_ACLK_BTS_3AA1, "aclk_bts_3aa1", "div_aclk_cam0_bus_400", 4981 ENABLE_ACLK_CAM02, 4, CLK_IGNORE_UNUSED, 0), 4982 GATE(CLK_ACLK_BTS_3AA0, "aclk_bts_3aa0", "div_aclk_cam0_bus_400", 4983 ENABLE_ACLK_CAM02, 3, CLK_IGNORE_UNUSED, 0), 4984 GATE(CLK_ACLK_BTS_LITE_D, "aclk_bts_lite_d", "div_aclk_cam0_bus_400", 4985 ENABLE_ACLK_CAM02, 2, CLK_IGNORE_UNUSED, 0), 4986 GATE(CLK_ACLK_BTS_LITE_B, "aclk_bts_lite_b", "div_aclk_cam0_bus_400", 4987 ENABLE_ACLK_CAM02, 1, CLK_IGNORE_UNUSED, 0), 4988 GATE(CLK_ACLK_BTS_LITE_A, "aclk_bts_lite_a", "div_aclk_cam0_bus_400", 4989 ENABLE_ACLK_CAM02, 0, CLK_IGNORE_UNUSED, 0), 4990 4991 /* ENABLE_PCLK_CAM0 */ 4992 GATE(CLK_PCLK_SMMU_3AA1, "pclk_smmu_3aa1", "div_aclk_cam0_200", 4993 ENABLE_PCLK_CAM0, 25, CLK_IGNORE_UNUSED, 0), 4994 GATE(CLK_PCLK_SMMU_3AA0, "pclk_smmu_3aa0", "div_aclk_cam0_200", 4995 ENABLE_PCLK_CAM0, 24, CLK_IGNORE_UNUSED, 0), 4996 GATE(CLK_PCLK_SMMU_LITE_D, "pclk_smmu_lite_d", "div_aclk_cam0_200", 4997 ENABLE_PCLK_CAM0, 23, CLK_IGNORE_UNUSED, 0), 4998 GATE(CLK_PCLK_SMMU_LITE_B, "pclk_smmu_lite_b", "div_aclk_cam0_200", 4999 ENABLE_PCLK_CAM0, 22, CLK_IGNORE_UNUSED, 0), 5000 GATE(CLK_PCLK_SMMU_LITE_A, "pclk_smmu_lite_a", "div_aclk_cam0_200", 5001 ENABLE_PCLK_CAM0, 21, CLK_IGNORE_UNUSED, 0), 5002 GATE(CLK_PCLK_BTS_3AA1, "pclk_bts_3aa1", "div_pclk_cam0_50", 5003 ENABLE_PCLK_CAM0, 20, CLK_IGNORE_UNUSED, 0), 5004 GATE(CLK_PCLK_BTS_3AA0, "pclk_bts_3aa0", "div_pclk_cam0_50", 5005 ENABLE_PCLK_CAM0, 19, CLK_IGNORE_UNUSED, 0), 5006 GATE(CLK_PCLK_BTS_LITE_D, "pclk_bts_lite_d", "div_pclk_cam0_50", 5007 ENABLE_PCLK_CAM0, 18, CLK_IGNORE_UNUSED, 0), 5008 GATE(CLK_PCLK_BTS_LITE_B, "pclk_bts_lite_b", "div_pclk_cam0_50", 5009 ENABLE_PCLK_CAM0, 17, CLK_IGNORE_UNUSED, 0), 5010 GATE(CLK_PCLK_BTS_LITE_A, "pclk_bts_lite_a", "div_pclk_cam0_50", 5011 ENABLE_PCLK_CAM0, 16, CLK_IGNORE_UNUSED, 0), 5012 GATE(CLK_PCLK_ASYNCAXI_CAM1, "pclk_asyncaxi_cam1", "div_pclk_cam0_50", 5013 ENABLE_PCLK_CAM0, 15, CLK_IGNORE_UNUSED, 0), 5014 GATE(CLK_PCLK_ASYNCAXI_3AA1, "pclk_asyncaxi_3aa1", "div_pclk_cam0_50", 5015 ENABLE_PCLK_CAM0, 14, CLK_IGNORE_UNUSED, 0), 5016 GATE(CLK_PCLK_ASYNCAXI_3AA0, "pclk_asyncaxi_3aa0", "div_pclk_cam0_50", 5017 ENABLE_PCLK_CAM0, 13, CLK_IGNORE_UNUSED, 0), 5018 GATE(CLK_PCLK_ASYNCAXI_LITE_D, "pclk_asyncaxi_lite_d", 5019 "div_pclk_cam0_50", ENABLE_PCLK_CAM0, 5020 12, CLK_IGNORE_UNUSED, 0), 5021 GATE(CLK_PCLK_ASYNCAXI_LITE_B, "pclk_asyncaxi_lite_b", 5022 "div_pclk_cam0_50", ENABLE_PCLK_CAM0, 5023 11, CLK_IGNORE_UNUSED, 0), 5024 GATE(CLK_PCLK_ASYNCAXI_LITE_A, "pclk_asyncaxi_lite_a", 5025 "div_pclk_cam0_50", ENABLE_PCLK_CAM0, 5026 10, CLK_IGNORE_UNUSED, 0), 5027 GATE(CLK_PCLK_PMU_CAM0, "pclk_pmu_cam0", "div_pclk_cam0_50", 5028 ENABLE_PCLK_CAM0, 9, CLK_IGNORE_UNUSED, 0), 5029 GATE(CLK_PCLK_SYSREG_CAM0, "pclk_sysreg_cam0", "div_pclk_cam0_50", 5030 ENABLE_PCLK_CAM0, 8, CLK_IGNORE_UNUSED, 0), 5031 GATE(CLK_PCLK_CMU_CAM0_LOCAL, "pclk_cmu_cam0_local", 5032 "div_aclk_cam0_200", ENABLE_PCLK_CAM0, 5033 7, CLK_IGNORE_UNUSED, 0), 5034 GATE(CLK_PCLK_CSIS1, "pclk_csis1", "div_aclk_cam0_200", 5035 ENABLE_PCLK_CAM0, 6, CLK_IGNORE_UNUSED, 0), 5036 GATE(CLK_PCLK_CSIS0, "pclk_csis0", "div_aclk_cam0_200", 5037 ENABLE_PCLK_CAM0, 5, CLK_IGNORE_UNUSED, 0), 5038 GATE(CLK_PCLK_3AA1, "pclk_3aa1", "div_pclk_3aa1", 5039 ENABLE_PCLK_CAM0, 4, CLK_IGNORE_UNUSED, 0), 5040 GATE(CLK_PCLK_3AA0, "pclk_3aa0", "div_pclk_3aa0", 5041 ENABLE_PCLK_CAM0, 3, CLK_IGNORE_UNUSED, 0), 5042 GATE(CLK_PCLK_LITE_D, "pclk_lite_d", "div_pclk_lite_d", 5043 ENABLE_PCLK_CAM0, 2, CLK_IGNORE_UNUSED, 0), 5044 GATE(CLK_PCLK_LITE_B, "pclk_lite_b", "div_pclk_lite_b", 5045 ENABLE_PCLK_CAM0, 1, CLK_IGNORE_UNUSED, 0), 5046 GATE(CLK_PCLK_LITE_A, "pclk_lite_a", "div_pclk_lite_a", 5047 ENABLE_PCLK_CAM0, 0, CLK_IGNORE_UNUSED, 0), 5048 5049 /* ENABLE_SCLK_CAM0 */ 5050 GATE(CLK_PHYCLK_RXBYTECLKHS0_S4, "phyclk_rxbyteclkhs0_s4", 5051 "mout_phyclk_rxbyteclkhs0_s4_user", 5052 ENABLE_SCLK_CAM0, 8, 0, 0), 5053 GATE(CLK_PHYCLK_RXBYTECLKHS0_S2A, "phyclk_rxbyteclkhs0_s2a", 5054 "mout_phyclk_rxbyteclkhs0_s2a_user", 5055 ENABLE_SCLK_CAM0, 7, 0, 0), 5056 GATE(CLK_SCLK_LITE_FREECNT, "sclk_lite_freecnt", 5057 "mout_sclk_lite_freecnt_c", ENABLE_SCLK_CAM0, 6, 0, 0), 5058 GATE(CLK_SCLK_PIXELASYNCM_3AA1, "sclk_pixelasycm_3aa1", 5059 "div_aclk_3aa1", ENABLE_SCLK_CAM0, 5, 0, 0), 5060 GATE(CLK_SCLK_PIXELASYNCM_3AA0, "sclk_pixelasycm_3aa0", 5061 "div_aclk_3aa0", ENABLE_SCLK_CAM0, 4, 0, 0), 5062 GATE(CLK_SCLK_PIXELASYNCS_3AA0, "sclk_pixelasycs_3aa0", 5063 "div_aclk_3aa0", ENABLE_SCLK_CAM0, 3, 0, 0), 5064 GATE(CLK_SCLK_PIXELASYNCM_LITE_C, "sclk_pixelasyncm_lite_c", 5065 "div_sclk_pixelasync_lite_c", 5066 ENABLE_SCLK_CAM0, 2, 0, 0), 5067 GATE(CLK_SCLK_PIXELASYNCM_LITE_C_INIT, "sclk_pixelasyncm_lite_c_init", 5068 "div_sclk_pixelasync_lite_c_init", 5069 ENABLE_SCLK_CAM0, 1, 0, 0), 5070 GATE(CLK_SCLK_PIXELASYNCS_LITE_C_INIT, "sclk_pixelasyncs_lite_c_init", 5071 "div_sclk_pixelasync_lite_c", 5072 ENABLE_SCLK_CAM0, 0, 0, 0), 5073 }; 5074 5075 static const struct samsung_cmu_info cam0_cmu_info __initconst = { 5076 .mux_clks = cam0_mux_clks, 5077 .nr_mux_clks = ARRAY_SIZE(cam0_mux_clks), 5078 .div_clks = cam0_div_clks, 5079 .nr_div_clks = ARRAY_SIZE(cam0_div_clks), 5080 .gate_clks = cam0_gate_clks, 5081 .nr_gate_clks = ARRAY_SIZE(cam0_gate_clks), 5082 .fixed_clks = cam0_fixed_clks, 5083 .nr_fixed_clks = ARRAY_SIZE(cam0_fixed_clks), 5084 .nr_clk_ids = CAM0_NR_CLK, 5085 .clk_regs = cam0_clk_regs, 5086 .nr_clk_regs = ARRAY_SIZE(cam0_clk_regs), 5087 .suspend_regs = cam0_suspend_regs, 5088 .nr_suspend_regs = ARRAY_SIZE(cam0_suspend_regs), 5089 .clk_name = "aclk_cam0_400", 5090 }; 5091 5092 /* 5093 * Register offset definitions for CMU_CAM1 5094 */ 5095 #define MUX_SEL_CAM10 0x0200 5096 #define MUX_SEL_CAM11 0x0204 5097 #define MUX_SEL_CAM12 0x0208 5098 #define MUX_ENABLE_CAM10 0x0300 5099 #define MUX_ENABLE_CAM11 0x0304 5100 #define MUX_ENABLE_CAM12 0x0308 5101 #define MUX_STAT_CAM10 0x0400 5102 #define MUX_STAT_CAM11 0x0404 5103 #define MUX_STAT_CAM12 0x0408 5104 #define MUX_IGNORE_CAM11 0x0504 5105 #define DIV_CAM10 0x0600 5106 #define DIV_CAM11 0x0604 5107 #define DIV_STAT_CAM10 0x0700 5108 #define DIV_STAT_CAM11 0x0704 5109 #define ENABLE_ACLK_CAM10 0X0800 5110 #define ENABLE_ACLK_CAM11 0X0804 5111 #define ENABLE_ACLK_CAM12 0X0808 5112 #define ENABLE_PCLK_CAM1 0X0900 5113 #define ENABLE_SCLK_CAM1 0X0a00 5114 #define ENABLE_IP_CAM10 0X0b00 5115 #define ENABLE_IP_CAM11 0X0b04 5116 #define ENABLE_IP_CAM12 0X0b08 5117 5118 static const unsigned long cam1_clk_regs[] __initconst = { 5119 MUX_SEL_CAM10, 5120 MUX_SEL_CAM11, 5121 MUX_SEL_CAM12, 5122 MUX_ENABLE_CAM10, 5123 MUX_ENABLE_CAM11, 5124 MUX_ENABLE_CAM12, 5125 MUX_IGNORE_CAM11, 5126 DIV_CAM10, 5127 DIV_CAM11, 5128 ENABLE_ACLK_CAM10, 5129 ENABLE_ACLK_CAM11, 5130 ENABLE_ACLK_CAM12, 5131 ENABLE_PCLK_CAM1, 5132 ENABLE_SCLK_CAM1, 5133 ENABLE_IP_CAM10, 5134 ENABLE_IP_CAM11, 5135 ENABLE_IP_CAM12, 5136 }; 5137 5138 static const struct samsung_clk_reg_dump cam1_suspend_regs[] = { 5139 { MUX_SEL_CAM10, 0 }, 5140 { MUX_SEL_CAM11, 0 }, 5141 { MUX_SEL_CAM12, 0 }, 5142 }; 5143 5144 PNAME(mout_sclk_isp_uart_user_p) = { "oscclk", "sclk_isp_uart_cam1", }; 5145 PNAME(mout_sclk_isp_spi1_user_p) = { "oscclk", "sclk_isp_spi1_cam1", }; 5146 PNAME(mout_sclk_isp_spi0_user_p) = { "oscclk", "sclk_isp_spi0_cam1", }; 5147 5148 PNAME(mout_aclk_cam1_333_user_p) = { "oscclk", "aclk_cam1_333", }; 5149 PNAME(mout_aclk_cam1_400_user_p) = { "oscclk", "aclk_cam1_400", }; 5150 PNAME(mout_aclk_cam1_552_user_p) = { "oscclk", "aclk_cam1_552", }; 5151 5152 PNAME(mout_phyclk_rxbyteclkhs0_s2b_user_p) = { "oscclk", 5153 "phyclk_rxbyteclkhs0_s2b_phy", }; 5154 5155 PNAME(mout_aclk_csis2_b_p) = { "mout_aclk_csis2_a", 5156 "mout_aclk_cam1_333_user", }; 5157 PNAME(mout_aclk_csis2_a_p) = { "mout_aclk_cam1_552_user", 5158 "mout_aclk_cam1_400_user", }; 5159 5160 PNAME(mout_aclk_fd_b_p) = { "mout_aclk_fd_a", 5161 "mout_aclk_cam1_333_user", }; 5162 PNAME(mout_aclk_fd_a_p) = { "mout_aclk_cam1_552_user", 5163 "mout_aclk_cam1_400_user", }; 5164 5165 PNAME(mout_aclk_lite_c_b_p) = { "mout_aclk_lite_c_a", 5166 "mout_aclk_cam1_333_user", }; 5167 PNAME(mout_aclk_lite_c_a_p) = { "mout_aclk_cam1_552_user", 5168 "mout_aclk_cam1_400_user", }; 5169 5170 static const struct samsung_fixed_rate_clock cam1_fixed_clks[] __initconst = { 5171 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2B, "phyclk_rxbyteclkhs0_s2b_phy", NULL, 5172 0, 100000000), 5173 }; 5174 5175 static const struct samsung_mux_clock cam1_mux_clks[] __initconst = { 5176 /* MUX_SEL_CAM10 */ 5177 MUX(CLK_MOUT_SCLK_ISP_UART_USER, "mout_sclk_isp_uart_user", 5178 mout_sclk_isp_uart_user_p, MUX_SEL_CAM10, 20, 1), 5179 MUX(CLK_MOUT_SCLK_ISP_SPI1_USER, "mout_sclk_isp_spi1_user", 5180 mout_sclk_isp_spi1_user_p, MUX_SEL_CAM10, 16, 1), 5181 MUX(CLK_MOUT_SCLK_ISP_SPI0_USER, "mout_sclk_isp_spi0_user", 5182 mout_sclk_isp_spi0_user_p, MUX_SEL_CAM10, 12, 1), 5183 MUX(CLK_MOUT_ACLK_CAM1_333_USER, "mout_aclk_cam1_333_user", 5184 mout_aclk_cam1_333_user_p, MUX_SEL_CAM10, 8, 1), 5185 MUX(CLK_MOUT_ACLK_CAM1_400_USER, "mout_aclk_cam1_400_user", 5186 mout_aclk_cam1_400_user_p, MUX_SEL_CAM10, 4, 1), 5187 MUX(CLK_MOUT_ACLK_CAM1_552_USER, "mout_aclk_cam1_552_user", 5188 mout_aclk_cam1_552_user_p, MUX_SEL_CAM10, 0, 1), 5189 5190 /* MUX_SEL_CAM11 */ 5191 MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2B_USER, 5192 "mout_phyclk_rxbyteclkhs0_s2b_user", 5193 mout_phyclk_rxbyteclkhs0_s2b_user_p, 5194 MUX_SEL_CAM11, 0, 1), 5195 5196 /* MUX_SEL_CAM12 */ 5197 MUX(CLK_MOUT_ACLK_CSIS2_B, "mout_aclk_csis2_b", mout_aclk_csis2_b_p, 5198 MUX_SEL_CAM12, 20, 1), 5199 MUX(CLK_MOUT_ACLK_CSIS2_A, "mout_aclk_csis2_a", mout_aclk_csis2_a_p, 5200 MUX_SEL_CAM12, 16, 1), 5201 MUX(CLK_MOUT_ACLK_FD_B, "mout_aclk_fd_b", mout_aclk_fd_b_p, 5202 MUX_SEL_CAM12, 12, 1), 5203 MUX(CLK_MOUT_ACLK_FD_A, "mout_aclk_fd_a", mout_aclk_fd_a_p, 5204 MUX_SEL_CAM12, 8, 1), 5205 MUX(CLK_MOUT_ACLK_LITE_C_B, "mout_aclk_lite_c_b", mout_aclk_lite_c_b_p, 5206 MUX_SEL_CAM12, 4, 1), 5207 MUX(CLK_MOUT_ACLK_LITE_C_A, "mout_aclk_lite_c_a", mout_aclk_lite_c_a_p, 5208 MUX_SEL_CAM12, 0, 1), 5209 }; 5210 5211 static const struct samsung_div_clock cam1_div_clks[] __initconst = { 5212 /* DIV_CAM10 */ 5213 DIV(CLK_DIV_SCLK_ISP_MPWM, "div_sclk_isp_mpwm", 5214 "div_pclk_cam1_83", DIV_CAM10, 16, 2), 5215 DIV(CLK_DIV_PCLK_CAM1_83, "div_pclk_cam1_83", 5216 "mout_aclk_cam1_333_user", DIV_CAM10, 12, 2), 5217 DIV(CLK_DIV_PCLK_CAM1_166, "div_pclk_cam1_166", 5218 "mout_aclk_cam1_333_user", DIV_CAM10, 8, 2), 5219 DIV(CLK_DIV_PCLK_DBG_CAM1, "div_pclk_dbg_cam1", 5220 "mout_aclk_cam1_552_user", DIV_CAM10, 4, 3), 5221 DIV(CLK_DIV_ATCLK_CAM1, "div_atclk_cam1", "mout_aclk_cam1_552_user", 5222 DIV_CAM10, 0, 3), 5223 5224 /* DIV_CAM11 */ 5225 DIV(CLK_DIV_ACLK_CSIS2, "div_aclk_csis2", "mout_aclk_csis2_b", 5226 DIV_CAM11, 16, 3), 5227 DIV(CLK_DIV_PCLK_FD, "div_pclk_fd", "div_aclk_fd", DIV_CAM11, 12, 2), 5228 DIV(CLK_DIV_ACLK_FD, "div_aclk_fd", "mout_aclk_fd_b", DIV_CAM11, 8, 3), 5229 DIV(CLK_DIV_PCLK_LITE_C, "div_pclk_lite_c", "div_aclk_lite_c", 5230 DIV_CAM11, 4, 2), 5231 DIV(CLK_DIV_ACLK_LITE_C, "div_aclk_lite_c", "mout_aclk_lite_c_b", 5232 DIV_CAM11, 0, 3), 5233 }; 5234 5235 static const struct samsung_gate_clock cam1_gate_clks[] __initconst = { 5236 /* ENABLE_ACLK_CAM10 */ 5237 GATE(CLK_ACLK_ISP_GIC, "aclk_isp_gic", "mout_aclk_cam1_333_user", 5238 ENABLE_ACLK_CAM10, 4, 0, 0), 5239 GATE(CLK_ACLK_FD, "aclk_fd", "div_aclk_fd", 5240 ENABLE_ACLK_CAM10, 3, 0, 0), 5241 GATE(CLK_ACLK_LITE_C, "aclk_lite_c", "div_aclk_lite_c", 5242 ENABLE_ACLK_CAM10, 1, 0, 0), 5243 GATE(CLK_ACLK_CSIS2, "aclk_csis2", "div_aclk_csis2", 5244 ENABLE_ACLK_CAM10, 0, 0, 0), 5245 5246 /* ENABLE_ACLK_CAM11 */ 5247 GATE(CLK_ACLK_ASYNCAPBM_FD, "aclk_asyncapbm_fd", "div_pclk_fd", 5248 ENABLE_ACLK_CAM11, 29, CLK_IGNORE_UNUSED, 0), 5249 GATE(CLK_ACLK_ASYNCAPBS_FD, "aclk_asyncapbs_fd", "div_pclk_cam1_166", 5250 ENABLE_ACLK_CAM11, 28, CLK_IGNORE_UNUSED, 0), 5251 GATE(CLK_ACLK_ASYNCAPBM_LITE_C, "aclk_asyncapbm_lite_c", 5252 "div_pclk_lite_c", ENABLE_ACLK_CAM11, 5253 27, CLK_IGNORE_UNUSED, 0), 5254 GATE(CLK_ACLK_ASYNCAPBS_LITE_C, "aclk_asyncapbs_lite_c", 5255 "div_pclk_cam1_166", ENABLE_ACLK_CAM11, 5256 26, CLK_IGNORE_UNUSED, 0), 5257 GATE(CLK_ACLK_ASYNCAHBS_SFRISP2H2, "aclk_asyncahbs_sfrisp2h2", 5258 "div_pclk_cam1_83", ENABLE_ACLK_CAM11, 5259 25, CLK_IGNORE_UNUSED, 0), 5260 GATE(CLK_ACLK_ASYNCAHBS_SFRISP2H1, "aclk_asyncahbs_sfrisp2h1", 5261 "div_pclk_cam1_83", ENABLE_ACLK_CAM11, 5262 24, CLK_IGNORE_UNUSED, 0), 5263 GATE(CLK_ACLK_ASYNCAXIM_CA5, "aclk_asyncaxim_ca5", 5264 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11, 5265 23, CLK_IGNORE_UNUSED, 0), 5266 GATE(CLK_ACLK_ASYNCAXIS_CA5, "aclk_asyncaxis_ca5", 5267 "mout_aclk_cam1_552_user", ENABLE_ACLK_CAM11, 5268 22, CLK_IGNORE_UNUSED, 0), 5269 GATE(CLK_ACLK_ASYNCAXIS_ISPX2, "aclk_asyncaxis_ispx2", 5270 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11, 5271 21, CLK_IGNORE_UNUSED, 0), 5272 GATE(CLK_ACLK_ASYNCAXIS_ISPX1, "aclk_asyncaxis_ispx1", 5273 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11, 5274 20, CLK_IGNORE_UNUSED, 0), 5275 GATE(CLK_ACLK_ASYNCAXIS_ISPX0, "aclk_asyncaxis_ispx0", 5276 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11, 5277 19, CLK_IGNORE_UNUSED, 0), 5278 GATE(CLK_ACLK_ASYNCAXIM_ISPEX, "aclk_asyncaxim_ispex", 5279 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11, 5280 18, CLK_IGNORE_UNUSED, 0), 5281 GATE(CLK_ACLK_ASYNCAXIM_ISP3P, "aclk_asyncaxim_isp3p", 5282 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11, 5283 17, CLK_IGNORE_UNUSED, 0), 5284 GATE(CLK_ACLK_ASYNCAXIS_ISP3P, "aclk_asyncaxis_isp3p", 5285 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11, 5286 16, CLK_IGNORE_UNUSED, 0), 5287 GATE(CLK_ACLK_ASYNCAXIM_FD, "aclk_asyncaxim_fd", 5288 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11, 5289 15, CLK_IGNORE_UNUSED, 0), 5290 GATE(CLK_ACLK_ASYNCAXIS_FD, "aclk_asyncaxis_fd", "div_aclk_fd", 5291 ENABLE_ACLK_CAM11, 14, CLK_IGNORE_UNUSED, 0), 5292 GATE(CLK_ACLK_ASYNCAXIM_LITE_C, "aclk_asyncaxim_lite_c", 5293 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11, 5294 13, CLK_IGNORE_UNUSED, 0), 5295 GATE(CLK_ACLK_ASYNCAXIS_LITE_C, "aclk_asyncaxis_lite_c", 5296 "div_aclk_lite_c", ENABLE_ACLK_CAM11, 5297 12, CLK_IGNORE_UNUSED, 0), 5298 GATE(CLK_ACLK_AHB2APB_ISP5P, "aclk_ahb2apb_isp5p", "div_pclk_cam1_83", 5299 ENABLE_ACLK_CAM11, 11, CLK_IGNORE_UNUSED, 0), 5300 GATE(CLK_ACLK_AHB2APB_ISP3P, "aclk_ahb2apb_isp3p", "div_pclk_cam1_83", 5301 ENABLE_ACLK_CAM11, 10, CLK_IGNORE_UNUSED, 0), 5302 GATE(CLK_ACLK_AXI2APB_ISP3P, "aclk_axi2apb_isp3p", 5303 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11, 5304 9, CLK_IGNORE_UNUSED, 0), 5305 GATE(CLK_ACLK_AHB_SFRISP2H, "aclk_ahb_sfrisp2h", "div_pclk_cam1_83", 5306 ENABLE_ACLK_CAM11, 8, CLK_IGNORE_UNUSED, 0), 5307 GATE(CLK_ACLK_AXI_ISP_HX_R, "aclk_axi_isp_hx_r", "div_pclk_cam1_166", 5308 ENABLE_ACLK_CAM11, 7, CLK_IGNORE_UNUSED, 0), 5309 GATE(CLK_ACLK_AXI_ISP_CX_R, "aclk_axi_isp_cx_r", "div_pclk_cam1_166", 5310 ENABLE_ACLK_CAM11, 6, CLK_IGNORE_UNUSED, 0), 5311 GATE(CLK_ACLK_AXI_ISP_HX, "aclk_axi_isp_hx", "mout_aclk_cam1_333_user", 5312 ENABLE_ACLK_CAM11, 5, CLK_IGNORE_UNUSED, 0), 5313 GATE(CLK_ACLK_AXI_ISP_CX, "aclk_axi_isp_cx", "mout_aclk_cam1_333_user", 5314 ENABLE_ACLK_CAM11, 4, CLK_IGNORE_UNUSED, 0), 5315 GATE(CLK_ACLK_XIU_ISPX, "aclk_xiu_ispx", "mout_aclk_cam1_333_user", 5316 ENABLE_ACLK_CAM11, 3, CLK_IGNORE_UNUSED, 0), 5317 GATE(CLK_ACLK_XIU_ISPEX, "aclk_xiu_ispex", "mout_aclk_cam1_400_user", 5318 ENABLE_ACLK_CAM11, 2, CLK_IGNORE_UNUSED, 0), 5319 GATE(CLK_ACLK_CAM1NP_333, "aclk_cam1np_333", "mout_aclk_cam1_333_user", 5320 ENABLE_ACLK_CAM11, 1, CLK_IGNORE_UNUSED, 0), 5321 GATE(CLK_ACLK_CAM1ND_400, "aclk_cam1nd_400", "mout_aclk_cam1_400_user", 5322 ENABLE_ACLK_CAM11, 0, CLK_IGNORE_UNUSED, 0), 5323 5324 /* ENABLE_ACLK_CAM12 */ 5325 GATE(CLK_ACLK_SMMU_ISPCPU, "aclk_smmu_ispcpu", 5326 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12, 5327 10, CLK_IGNORE_UNUSED, 0), 5328 GATE(CLK_ACLK_SMMU_FD, "aclk_smmu_fd", "mout_aclk_cam1_400_user", 5329 ENABLE_ACLK_CAM12, 9, CLK_IGNORE_UNUSED, 0), 5330 GATE(CLK_ACLK_SMMU_LITE_C, "aclk_smmu_lite_c", 5331 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12, 5332 8, CLK_IGNORE_UNUSED, 0), 5333 GATE(CLK_ACLK_BTS_ISP3P, "aclk_bts_isp3p", "mout_aclk_cam1_400_user", 5334 ENABLE_ACLK_CAM12, 7, CLK_IGNORE_UNUSED, 0), 5335 GATE(CLK_ACLK_BTS_FD, "aclk_bts_fd", "mout_aclk_cam1_400_user", 5336 ENABLE_ACLK_CAM12, 6, CLK_IGNORE_UNUSED, 0), 5337 GATE(CLK_ACLK_BTS_LITE_C, "aclk_bts_lite_c", "mout_aclk_cam1_400_user", 5338 ENABLE_ACLK_CAM12, 5, CLK_IGNORE_UNUSED, 0), 5339 GATE(CLK_ACLK_AHBDN_SFRISP2H, "aclk_ahbdn_sfrisp2h", 5340 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM12, 5341 4, CLK_IGNORE_UNUSED, 0), 5342 GATE(CLK_ACLK_AHBDN_ISP5P, "aclk_aclk-shbdn_isp5p", 5343 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM12, 5344 3, CLK_IGNORE_UNUSED, 0), 5345 GATE(CLK_ACLK_AXIUS_ISP3P, "aclk_axius_isp3p", 5346 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12, 5347 2, CLK_IGNORE_UNUSED, 0), 5348 GATE(CLK_ACLK_AXIUS_FD, "aclk_axius_fd", "mout_aclk_cam1_400_user", 5349 ENABLE_ACLK_CAM12, 1, CLK_IGNORE_UNUSED, 0), 5350 GATE(CLK_ACLK_AXIUS_LITE_C, "aclk_axius_lite_c", 5351 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12, 5352 0, CLK_IGNORE_UNUSED, 0), 5353 5354 /* ENABLE_PCLK_CAM1 */ 5355 GATE(CLK_PCLK_SMMU_ISPCPU, "pclk_smmu_ispcpu", "div_pclk_cam1_166", 5356 ENABLE_PCLK_CAM1, 27, CLK_IGNORE_UNUSED, 0), 5357 GATE(CLK_PCLK_SMMU_FD, "pclk_smmu_fd", "div_pclk_cam1_166", 5358 ENABLE_PCLK_CAM1, 26, CLK_IGNORE_UNUSED, 0), 5359 GATE(CLK_PCLK_SMMU_LITE_C, "pclk_smmu_lite_c", "div_pclk_cam1_166", 5360 ENABLE_PCLK_CAM1, 25, CLK_IGNORE_UNUSED, 0), 5361 GATE(CLK_PCLK_BTS_ISP3P, "pclk_bts_isp3p", "div_pclk_cam1_83", 5362 ENABLE_PCLK_CAM1, 24, CLK_IGNORE_UNUSED, 0), 5363 GATE(CLK_PCLK_BTS_FD, "pclk_bts_fd", "div_pclk_cam1_83", 5364 ENABLE_PCLK_CAM1, 23, CLK_IGNORE_UNUSED, 0), 5365 GATE(CLK_PCLK_BTS_LITE_C, "pclk_bts_lite_c", "div_pclk_cam1_83", 5366 ENABLE_PCLK_CAM1, 22, CLK_IGNORE_UNUSED, 0), 5367 GATE(CLK_PCLK_ASYNCAXIM_CA5, "pclk_asyncaxim_ca5", "div_pclk_cam1_166", 5368 ENABLE_PCLK_CAM1, 21, CLK_IGNORE_UNUSED, 0), 5369 GATE(CLK_PCLK_ASYNCAXIM_ISPEX, "pclk_asyncaxim_ispex", 5370 "div_pclk_cam1_83", ENABLE_PCLK_CAM1, 5371 20, CLK_IGNORE_UNUSED, 0), 5372 GATE(CLK_PCLK_ASYNCAXIM_ISP3P, "pclk_asyncaxim_isp3p", 5373 "div_pclk_cam1_83", ENABLE_PCLK_CAM1, 5374 19, CLK_IGNORE_UNUSED, 0), 5375 GATE(CLK_PCLK_ASYNCAXIM_FD, "pclk_asyncaxim_fd", "div_pclk_cam1_83", 5376 ENABLE_PCLK_CAM1, 18, CLK_IGNORE_UNUSED, 0), 5377 GATE(CLK_PCLK_ASYNCAXIM_LITE_C, "pclk_asyncaxim_lite_c", 5378 "div_pclk_cam1_83", ENABLE_PCLK_CAM1, 5379 17, CLK_IGNORE_UNUSED, 0), 5380 GATE(CLK_PCLK_PMU_CAM1, "pclk_pmu_cam1", "div_pclk_cam1_83", 5381 ENABLE_PCLK_CAM1, 16, CLK_IGNORE_UNUSED, 0), 5382 GATE(CLK_PCLK_SYSREG_CAM1, "pclk_sysreg_cam1", "div_pclk_cam1_83", 5383 ENABLE_PCLK_CAM1, 15, CLK_IGNORE_UNUSED, 0), 5384 GATE(CLK_PCLK_CMU_CAM1_LOCAL, "pclk_cmu_cam1_local", 5385 "div_pclk_cam1_166", ENABLE_PCLK_CAM1, 5386 14, CLK_IGNORE_UNUSED, 0), 5387 GATE(CLK_PCLK_ISP_MCTADC, "pclk_isp_mctadc", "div_pclk_cam1_83", 5388 ENABLE_PCLK_CAM1, 13, CLK_IGNORE_UNUSED, 0), 5389 GATE(CLK_PCLK_ISP_WDT, "pclk_isp_wdt", "div_pclk_cam1_83", 5390 ENABLE_PCLK_CAM1, 12, CLK_IGNORE_UNUSED, 0), 5391 GATE(CLK_PCLK_ISP_PWM, "pclk_isp_pwm", "div_pclk_cam1_83", 5392 ENABLE_PCLK_CAM1, 11, CLK_IGNORE_UNUSED, 0), 5393 GATE(CLK_PCLK_ISP_UART, "pclk_isp_uart", "div_pclk_cam1_83", 5394 ENABLE_PCLK_CAM1, 10, CLK_IGNORE_UNUSED, 0), 5395 GATE(CLK_PCLK_ISP_MCUCTL, "pclk_isp_mcuctl", "div_pclk_cam1_83", 5396 ENABLE_PCLK_CAM1, 9, CLK_IGNORE_UNUSED, 0), 5397 GATE(CLK_PCLK_ISP_SPI1, "pclk_isp_spi1", "div_pclk_cam1_83", 5398 ENABLE_PCLK_CAM1, 8, CLK_IGNORE_UNUSED, 0), 5399 GATE(CLK_PCLK_ISP_SPI0, "pclk_isp_spi0", "div_pclk_cam1_83", 5400 ENABLE_PCLK_CAM1, 7, CLK_IGNORE_UNUSED, 0), 5401 GATE(CLK_PCLK_ISP_I2C2, "pclk_isp_i2c2", "div_pclk_cam1_83", 5402 ENABLE_PCLK_CAM1, 6, CLK_IGNORE_UNUSED, 0), 5403 GATE(CLK_PCLK_ISP_I2C1, "pclk_isp_i2c1", "div_pclk_cam1_83", 5404 ENABLE_PCLK_CAM1, 5, CLK_IGNORE_UNUSED, 0), 5405 GATE(CLK_PCLK_ISP_I2C0, "pclk_isp_i2c0", "div_pclk_cam1_83", 5406 ENABLE_PCLK_CAM1, 4, CLK_IGNORE_UNUSED, 0), 5407 GATE(CLK_PCLK_ISP_MPWM, "pclk_isp_mpwm", "div_pclk_cam1_83", 5408 ENABLE_PCLK_CAM1, 3, CLK_IGNORE_UNUSED, 0), 5409 GATE(CLK_PCLK_FD, "pclk_fd", "div_pclk_fd", 5410 ENABLE_PCLK_CAM1, 3, CLK_IGNORE_UNUSED, 0), 5411 GATE(CLK_PCLK_LITE_C, "pclk_lite_c", "div_pclk_lite_c", 5412 ENABLE_PCLK_CAM1, 1, CLK_IGNORE_UNUSED, 0), 5413 GATE(CLK_PCLK_CSIS2, "pclk_csis2", "div_pclk_cam1_166", 5414 ENABLE_PCLK_CAM1, 0, CLK_IGNORE_UNUSED, 0), 5415 5416 /* ENABLE_SCLK_CAM1 */ 5417 GATE(CLK_SCLK_ISP_I2C2, "sclk_isp_i2c2", "oscclk", ENABLE_SCLK_CAM1, 5418 15, 0, 0), 5419 GATE(CLK_SCLK_ISP_I2C1, "sclk_isp_i2c1", "oscclk", ENABLE_SCLK_CAM1, 5420 14, 0, 0), 5421 GATE(CLK_SCLK_ISP_I2C0, "sclk_isp_i2c0", "oscclk", ENABLE_SCLK_CAM1, 5422 13, 0, 0), 5423 GATE(CLK_SCLK_ISP_PWM, "sclk_isp_pwm", "oscclk", ENABLE_SCLK_CAM1, 5424 12, 0, 0), 5425 GATE(CLK_PHYCLK_RXBYTECLKHS0_S2B, "phyclk_rxbyteclkhs0_s2b", 5426 "mout_phyclk_rxbyteclkhs0_s2b_user", 5427 ENABLE_SCLK_CAM1, 11, 0, 0), 5428 GATE(CLK_SCLK_LITE_C_FREECNT, "sclk_lite_c_freecnt", "div_pclk_lite_c", 5429 ENABLE_SCLK_CAM1, 10, 0, 0), 5430 GATE(CLK_SCLK_PIXELASYNCM_FD, "sclk_pixelasyncm_fd", "div_aclk_fd", 5431 ENABLE_SCLK_CAM1, 9, 0, 0), 5432 GATE(CLK_SCLK_ISP_MCTADC, "sclk_isp_mctadc", "sclk_isp_mctadc_cam1", 5433 ENABLE_SCLK_CAM1, 7, 0, 0), 5434 GATE(CLK_SCLK_ISP_UART, "sclk_isp_uart", "mout_sclk_isp_uart_user", 5435 ENABLE_SCLK_CAM1, 6, 0, 0), 5436 GATE(CLK_SCLK_ISP_SPI1, "sclk_isp_spi1", "mout_sclk_isp_spi1_user", 5437 ENABLE_SCLK_CAM1, 5, 0, 0), 5438 GATE(CLK_SCLK_ISP_SPI0, "sclk_isp_spi0", "mout_sclk_isp_spi0_user", 5439 ENABLE_SCLK_CAM1, 4, 0, 0), 5440 GATE(CLK_SCLK_ISP_MPWM, "sclk_isp_mpwm", "div_sclk_isp_mpwm", 5441 ENABLE_SCLK_CAM1, 3, 0, 0), 5442 GATE(CLK_PCLK_DBG_ISP, "sclk_dbg_isp", "div_pclk_dbg_cam1", 5443 ENABLE_SCLK_CAM1, 2, 0, 0), 5444 GATE(CLK_ATCLK_ISP, "atclk_isp", "div_atclk_cam1", 5445 ENABLE_SCLK_CAM1, 1, 0, 0), 5446 GATE(CLK_SCLK_ISP_CA5, "sclk_isp_ca5", "mout_aclk_cam1_552_user", 5447 ENABLE_SCLK_CAM1, 0, 0, 0), 5448 }; 5449 5450 static const struct samsung_cmu_info cam1_cmu_info __initconst = { 5451 .mux_clks = cam1_mux_clks, 5452 .nr_mux_clks = ARRAY_SIZE(cam1_mux_clks), 5453 .div_clks = cam1_div_clks, 5454 .nr_div_clks = ARRAY_SIZE(cam1_div_clks), 5455 .gate_clks = cam1_gate_clks, 5456 .nr_gate_clks = ARRAY_SIZE(cam1_gate_clks), 5457 .fixed_clks = cam1_fixed_clks, 5458 .nr_fixed_clks = ARRAY_SIZE(cam1_fixed_clks), 5459 .nr_clk_ids = CAM1_NR_CLK, 5460 .clk_regs = cam1_clk_regs, 5461 .nr_clk_regs = ARRAY_SIZE(cam1_clk_regs), 5462 .suspend_regs = cam1_suspend_regs, 5463 .nr_suspend_regs = ARRAY_SIZE(cam1_suspend_regs), 5464 .clk_name = "aclk_cam1_400", 5465 }; 5466 5467 /* 5468 * Register offset definitions for CMU_IMEM 5469 */ 5470 #define ENABLE_ACLK_IMEM_SLIMSSS 0x080c 5471 #define ENABLE_PCLK_IMEM_SLIMSSS 0x0908 5472 5473 static const unsigned long imem_clk_regs[] __initconst = { 5474 ENABLE_ACLK_IMEM_SLIMSSS, 5475 ENABLE_PCLK_IMEM_SLIMSSS, 5476 }; 5477 5478 static const struct samsung_gate_clock imem_gate_clks[] __initconst = { 5479 /* ENABLE_ACLK_IMEM_SLIMSSS */ 5480 GATE(CLK_ACLK_SLIMSSS, "aclk_slimsss", "aclk_imem_sssx_266", 5481 ENABLE_ACLK_IMEM_SLIMSSS, 0, CLK_IGNORE_UNUSED, 0), 5482 5483 /* ENABLE_PCLK_IMEM_SLIMSSS */ 5484 GATE(CLK_PCLK_SLIMSSS, "pclk_slimsss", "aclk_imem_200", 5485 ENABLE_PCLK_IMEM_SLIMSSS, 0, CLK_IGNORE_UNUSED, 0), 5486 }; 5487 5488 static const struct samsung_cmu_info imem_cmu_info __initconst = { 5489 .gate_clks = imem_gate_clks, 5490 .nr_gate_clks = ARRAY_SIZE(imem_gate_clks), 5491 .nr_clk_ids = IMEM_NR_CLK, 5492 .clk_regs = imem_clk_regs, 5493 .nr_clk_regs = ARRAY_SIZE(imem_clk_regs), 5494 .clk_name = "aclk_imem_200", 5495 }; 5496 5497 struct exynos5433_cmu_data { 5498 struct samsung_clk_reg_dump *clk_save; 5499 unsigned int nr_clk_save; 5500 const struct samsung_clk_reg_dump *clk_suspend; 5501 unsigned int nr_clk_suspend; 5502 5503 struct clk *clk; 5504 struct clk **pclks; 5505 int nr_pclks; 5506 5507 /* must be the last entry */ 5508 struct samsung_clk_provider ctx; 5509 }; 5510 5511 static int __maybe_unused exynos5433_cmu_suspend(struct device *dev) 5512 { 5513 struct exynos5433_cmu_data *data = dev_get_drvdata(dev); 5514 int i; 5515 5516 samsung_clk_save(data->ctx.reg_base, data->clk_save, 5517 data->nr_clk_save); 5518 5519 for (i = 0; i < data->nr_pclks; i++) 5520 clk_prepare_enable(data->pclks[i]); 5521 5522 /* for suspend some registers have to be set to certain values */ 5523 samsung_clk_restore(data->ctx.reg_base, data->clk_suspend, 5524 data->nr_clk_suspend); 5525 5526 for (i = 0; i < data->nr_pclks; i++) 5527 clk_disable_unprepare(data->pclks[i]); 5528 5529 clk_disable_unprepare(data->clk); 5530 5531 return 0; 5532 } 5533 5534 static int __maybe_unused exynos5433_cmu_resume(struct device *dev) 5535 { 5536 struct exynos5433_cmu_data *data = dev_get_drvdata(dev); 5537 int i; 5538 5539 clk_prepare_enable(data->clk); 5540 5541 for (i = 0; i < data->nr_pclks; i++) 5542 clk_prepare_enable(data->pclks[i]); 5543 5544 samsung_clk_restore(data->ctx.reg_base, data->clk_save, 5545 data->nr_clk_save); 5546 5547 for (i = 0; i < data->nr_pclks; i++) 5548 clk_disable_unprepare(data->pclks[i]); 5549 5550 return 0; 5551 } 5552 5553 static int __init exynos5433_cmu_probe(struct platform_device *pdev) 5554 { 5555 const struct samsung_cmu_info *info; 5556 struct exynos5433_cmu_data *data; 5557 struct samsung_clk_provider *ctx; 5558 struct device *dev = &pdev->dev; 5559 struct resource *res; 5560 void __iomem *reg_base; 5561 int i; 5562 5563 info = of_device_get_match_data(dev); 5564 5565 data = devm_kzalloc(dev, 5566 struct_size(data, ctx.clk_data.hws, info->nr_clk_ids), 5567 GFP_KERNEL); 5568 if (!data) 5569 return -ENOMEM; 5570 ctx = &data->ctx; 5571 5572 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 5573 reg_base = devm_ioremap_resource(dev, res); 5574 if (IS_ERR(reg_base)) 5575 return PTR_ERR(reg_base); 5576 5577 for (i = 0; i < info->nr_clk_ids; ++i) 5578 ctx->clk_data.hws[i] = ERR_PTR(-ENOENT); 5579 5580 ctx->clk_data.num = info->nr_clk_ids; 5581 ctx->reg_base = reg_base; 5582 ctx->dev = dev; 5583 spin_lock_init(&ctx->lock); 5584 5585 data->clk_save = samsung_clk_alloc_reg_dump(info->clk_regs, 5586 info->nr_clk_regs); 5587 data->nr_clk_save = info->nr_clk_regs; 5588 data->clk_suspend = info->suspend_regs; 5589 data->nr_clk_suspend = info->nr_suspend_regs; 5590 data->nr_pclks = of_count_phandle_with_args(dev->of_node, "clocks", 5591 "#clock-cells"); 5592 if (data->nr_pclks > 0) { 5593 data->pclks = devm_kcalloc(dev, sizeof(struct clk *), 5594 data->nr_pclks, GFP_KERNEL); 5595 5596 for (i = 0; i < data->nr_pclks; i++) { 5597 struct clk *clk = of_clk_get(dev->of_node, i); 5598 5599 if (IS_ERR(clk)) 5600 return PTR_ERR(clk); 5601 data->pclks[i] = clk; 5602 } 5603 } 5604 5605 if (info->clk_name) 5606 data->clk = clk_get(dev, info->clk_name); 5607 clk_prepare_enable(data->clk); 5608 5609 platform_set_drvdata(pdev, data); 5610 5611 /* 5612 * Enable runtime PM here to allow the clock core using runtime PM 5613 * for the registered clocks. Additionally, we increase the runtime 5614 * PM usage count before registering the clocks, to prevent the 5615 * clock core from runtime suspending the device. 5616 */ 5617 pm_runtime_get_noresume(dev); 5618 pm_runtime_set_active(dev); 5619 pm_runtime_enable(dev); 5620 5621 if (info->pll_clks) 5622 samsung_clk_register_pll(ctx, info->pll_clks, info->nr_pll_clks, 5623 reg_base); 5624 if (info->mux_clks) 5625 samsung_clk_register_mux(ctx, info->mux_clks, 5626 info->nr_mux_clks); 5627 if (info->div_clks) 5628 samsung_clk_register_div(ctx, info->div_clks, 5629 info->nr_div_clks); 5630 if (info->gate_clks) 5631 samsung_clk_register_gate(ctx, info->gate_clks, 5632 info->nr_gate_clks); 5633 if (info->fixed_clks) 5634 samsung_clk_register_fixed_rate(ctx, info->fixed_clks, 5635 info->nr_fixed_clks); 5636 if (info->fixed_factor_clks) 5637 samsung_clk_register_fixed_factor(ctx, info->fixed_factor_clks, 5638 info->nr_fixed_factor_clks); 5639 5640 samsung_clk_of_add_provider(dev->of_node, ctx); 5641 pm_runtime_put_sync(dev); 5642 5643 return 0; 5644 } 5645 5646 static const struct of_device_id exynos5433_cmu_of_match[] = { 5647 { 5648 .compatible = "samsung,exynos5433-cmu-aud", 5649 .data = &aud_cmu_info, 5650 }, { 5651 .compatible = "samsung,exynos5433-cmu-cam0", 5652 .data = &cam0_cmu_info, 5653 }, { 5654 .compatible = "samsung,exynos5433-cmu-cam1", 5655 .data = &cam1_cmu_info, 5656 }, { 5657 .compatible = "samsung,exynos5433-cmu-disp", 5658 .data = &disp_cmu_info, 5659 }, { 5660 .compatible = "samsung,exynos5433-cmu-g2d", 5661 .data = &g2d_cmu_info, 5662 }, { 5663 .compatible = "samsung,exynos5433-cmu-g3d", 5664 .data = &g3d_cmu_info, 5665 }, { 5666 .compatible = "samsung,exynos5433-cmu-fsys", 5667 .data = &fsys_cmu_info, 5668 }, { 5669 .compatible = "samsung,exynos5433-cmu-gscl", 5670 .data = &gscl_cmu_info, 5671 }, { 5672 .compatible = "samsung,exynos5433-cmu-mfc", 5673 .data = &mfc_cmu_info, 5674 }, { 5675 .compatible = "samsung,exynos5433-cmu-hevc", 5676 .data = &hevc_cmu_info, 5677 }, { 5678 .compatible = "samsung,exynos5433-cmu-isp", 5679 .data = &isp_cmu_info, 5680 }, { 5681 .compatible = "samsung,exynos5433-cmu-mscl", 5682 .data = &mscl_cmu_info, 5683 }, { 5684 .compatible = "samsung,exynos5433-cmu-imem", 5685 .data = &imem_cmu_info, 5686 }, { 5687 }, 5688 }; 5689 5690 static const struct dev_pm_ops exynos5433_cmu_pm_ops = { 5691 SET_RUNTIME_PM_OPS(exynos5433_cmu_suspend, exynos5433_cmu_resume, 5692 NULL) 5693 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 5694 pm_runtime_force_resume) 5695 }; 5696 5697 static struct platform_driver exynos5433_cmu_driver __refdata = { 5698 .driver = { 5699 .name = "exynos5433-cmu", 5700 .of_match_table = exynos5433_cmu_of_match, 5701 .suppress_bind_attrs = true, 5702 .pm = &exynos5433_cmu_pm_ops, 5703 }, 5704 .probe = exynos5433_cmu_probe, 5705 }; 5706 5707 static int __init exynos5433_cmu_init(void) 5708 { 5709 return platform_driver_register(&exynos5433_cmu_driver); 5710 } 5711 core_initcall(exynos5433_cmu_init); 5712