1532abc3aSNaveen Krishna Ch /* 2532abc3aSNaveen Krishna Ch * Copyright (c) 2014 Samsung Electronics Co., Ltd. 3532abc3aSNaveen Krishna Ch * Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com> 4532abc3aSNaveen Krishna Ch * 5532abc3aSNaveen Krishna Ch * This program is free software; you can redistribute it and/or modify 6532abc3aSNaveen Krishna Ch * it under the terms of the GNU General Public License version 2 as 7532abc3aSNaveen Krishna Ch * published by the Free Software Foundation. 8532abc3aSNaveen Krishna Ch * 9532abc3aSNaveen Krishna Ch */ 10532abc3aSNaveen Krishna Ch 11532abc3aSNaveen Krishna Ch #include <linux/clk.h> 12532abc3aSNaveen Krishna Ch #include <linux/clkdev.h> 13532abc3aSNaveen Krishna Ch #include <linux/clk-provider.h> 14532abc3aSNaveen Krishna Ch #include <linux/of.h> 15532abc3aSNaveen Krishna Ch 16532abc3aSNaveen Krishna Ch #include "clk.h" 17532abc3aSNaveen Krishna Ch #include <dt-bindings/clock/exynos7-clk.h> 18532abc3aSNaveen Krishna Ch 19532abc3aSNaveen Krishna Ch /* Register Offset definitions for CMU_TOPC (0x10570000) */ 20532abc3aSNaveen Krishna Ch #define CC_PLL_LOCK 0x0000 21532abc3aSNaveen Krishna Ch #define BUS0_PLL_LOCK 0x0004 22532abc3aSNaveen Krishna Ch #define BUS1_DPLL_LOCK 0x0008 23532abc3aSNaveen Krishna Ch #define MFC_PLL_LOCK 0x000C 24532abc3aSNaveen Krishna Ch #define AUD_PLL_LOCK 0x0010 25532abc3aSNaveen Krishna Ch #define CC_PLL_CON0 0x0100 26532abc3aSNaveen Krishna Ch #define BUS0_PLL_CON0 0x0110 27532abc3aSNaveen Krishna Ch #define BUS1_DPLL_CON0 0x0120 28532abc3aSNaveen Krishna Ch #define MFC_PLL_CON0 0x0130 29532abc3aSNaveen Krishna Ch #define AUD_PLL_CON0 0x0140 30532abc3aSNaveen Krishna Ch #define MUX_SEL_TOPC0 0x0200 31532abc3aSNaveen Krishna Ch #define MUX_SEL_TOPC1 0x0204 32f5e127cdSNaveen Krishna Ch #define MUX_SEL_TOPC2 0x0208 33532abc3aSNaveen Krishna Ch #define MUX_SEL_TOPC3 0x020C 34f5e127cdSNaveen Krishna Ch #define DIV_TOPC0 0x0600 35532abc3aSNaveen Krishna Ch #define DIV_TOPC1 0x0604 36532abc3aSNaveen Krishna Ch #define DIV_TOPC3 0x060C 37532abc3aSNaveen Krishna Ch 38532abc3aSNaveen Krishna Ch static struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initdata = { 39532abc3aSNaveen Krishna Ch FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_bus0_pll_ctrl", 1, 2, 0), 40532abc3aSNaveen Krishna Ch FFACTOR(0, "ffac_topc_bus0_pll_div4", 41532abc3aSNaveen Krishna Ch "ffac_topc_bus0_pll_div2", 1, 2, 0), 42532abc3aSNaveen Krishna Ch FFACTOR(0, "ffac_topc_bus1_pll_div2", "mout_bus1_pll_ctrl", 1, 2, 0), 43532abc3aSNaveen Krishna Ch FFACTOR(0, "ffac_topc_cc_pll_div2", "mout_cc_pll_ctrl", 1, 2, 0), 44532abc3aSNaveen Krishna Ch FFACTOR(0, "ffac_topc_mfc_pll_div2", "mout_mfc_pll_ctrl", 1, 2, 0), 45532abc3aSNaveen Krishna Ch }; 46532abc3aSNaveen Krishna Ch 47532abc3aSNaveen Krishna Ch /* List of parent clocks for Muxes in CMU_TOPC */ 48532abc3aSNaveen Krishna Ch PNAME(mout_bus0_pll_ctrl_p) = { "fin_pll", "fout_bus0_pll" }; 49532abc3aSNaveen Krishna Ch PNAME(mout_bus1_pll_ctrl_p) = { "fin_pll", "fout_bus1_pll" }; 50532abc3aSNaveen Krishna Ch PNAME(mout_cc_pll_ctrl_p) = { "fin_pll", "fout_cc_pll" }; 51532abc3aSNaveen Krishna Ch PNAME(mout_mfc_pll_ctrl_p) = { "fin_pll", "fout_mfc_pll" }; 52532abc3aSNaveen Krishna Ch 53532abc3aSNaveen Krishna Ch PNAME(mout_topc_group2) = { "mout_sclk_bus0_pll_cmuc", 54532abc3aSNaveen Krishna Ch "mout_sclk_bus1_pll_cmuc", "mout_sclk_cc_pll_cmuc", 55532abc3aSNaveen Krishna Ch "mout_sclk_mfc_pll_cmuc" }; 56532abc3aSNaveen Krishna Ch 57532abc3aSNaveen Krishna Ch PNAME(mout_sclk_bus0_pll_cmuc_p) = { "mout_bus0_pll_ctrl", 58532abc3aSNaveen Krishna Ch "ffac_topc_bus0_pll_div2", "ffac_topc_bus0_pll_div4"}; 59532abc3aSNaveen Krishna Ch PNAME(mout_sclk_bus1_pll_cmuc_p) = { "mout_bus1_pll_ctrl", 60532abc3aSNaveen Krishna Ch "ffac_topc_bus1_pll_div2"}; 61532abc3aSNaveen Krishna Ch PNAME(mout_sclk_cc_pll_cmuc_p) = { "mout_cc_pll_ctrl", 62532abc3aSNaveen Krishna Ch "ffac_topc_cc_pll_div2"}; 63532abc3aSNaveen Krishna Ch PNAME(mout_sclk_mfc_pll_cmuc_p) = { "mout_mfc_pll_ctrl", 64532abc3aSNaveen Krishna Ch "ffac_topc_mfc_pll_div2"}; 65532abc3aSNaveen Krishna Ch 66532abc3aSNaveen Krishna Ch 67532abc3aSNaveen Krishna Ch PNAME(mout_sclk_bus0_pll_out_p) = {"mout_bus0_pll_ctrl", 68532abc3aSNaveen Krishna Ch "ffac_topc_bus0_pll_div2"}; 69532abc3aSNaveen Krishna Ch 70532abc3aSNaveen Krishna Ch static unsigned long topc_clk_regs[] __initdata = { 71532abc3aSNaveen Krishna Ch CC_PLL_LOCK, 72532abc3aSNaveen Krishna Ch BUS0_PLL_LOCK, 73532abc3aSNaveen Krishna Ch BUS1_DPLL_LOCK, 74532abc3aSNaveen Krishna Ch MFC_PLL_LOCK, 75532abc3aSNaveen Krishna Ch AUD_PLL_LOCK, 76532abc3aSNaveen Krishna Ch CC_PLL_CON0, 77532abc3aSNaveen Krishna Ch BUS0_PLL_CON0, 78532abc3aSNaveen Krishna Ch BUS1_DPLL_CON0, 79532abc3aSNaveen Krishna Ch MFC_PLL_CON0, 80532abc3aSNaveen Krishna Ch AUD_PLL_CON0, 81532abc3aSNaveen Krishna Ch MUX_SEL_TOPC0, 82532abc3aSNaveen Krishna Ch MUX_SEL_TOPC1, 83f5e127cdSNaveen Krishna Ch MUX_SEL_TOPC2, 84532abc3aSNaveen Krishna Ch MUX_SEL_TOPC3, 85f5e127cdSNaveen Krishna Ch DIV_TOPC0, 86532abc3aSNaveen Krishna Ch DIV_TOPC1, 87532abc3aSNaveen Krishna Ch DIV_TOPC3, 88532abc3aSNaveen Krishna Ch }; 89532abc3aSNaveen Krishna Ch 90532abc3aSNaveen Krishna Ch static struct samsung_mux_clock topc_mux_clks[] __initdata = { 91532abc3aSNaveen Krishna Ch MUX(0, "mout_bus0_pll_ctrl", mout_bus0_pll_ctrl_p, MUX_SEL_TOPC0, 0, 1), 92532abc3aSNaveen Krishna Ch MUX(0, "mout_bus1_pll_ctrl", mout_bus1_pll_ctrl_p, MUX_SEL_TOPC0, 4, 1), 93532abc3aSNaveen Krishna Ch MUX(0, "mout_cc_pll_ctrl", mout_cc_pll_ctrl_p, MUX_SEL_TOPC0, 8, 1), 94532abc3aSNaveen Krishna Ch MUX(0, "mout_mfc_pll_ctrl", mout_mfc_pll_ctrl_p, MUX_SEL_TOPC0, 12, 1), 95532abc3aSNaveen Krishna Ch 96532abc3aSNaveen Krishna Ch MUX(0, "mout_sclk_bus0_pll_cmuc", mout_sclk_bus0_pll_cmuc_p, 97532abc3aSNaveen Krishna Ch MUX_SEL_TOPC0, 16, 2), 98532abc3aSNaveen Krishna Ch MUX(0, "mout_sclk_bus1_pll_cmuc", mout_sclk_bus1_pll_cmuc_p, 99532abc3aSNaveen Krishna Ch MUX_SEL_TOPC0, 20, 1), 100532abc3aSNaveen Krishna Ch MUX(0, "mout_sclk_cc_pll_cmuc", mout_sclk_cc_pll_cmuc_p, 101532abc3aSNaveen Krishna Ch MUX_SEL_TOPC0, 24, 1), 102532abc3aSNaveen Krishna Ch MUX(0, "mout_sclk_mfc_pll_cmuc", mout_sclk_mfc_pll_cmuc_p, 103532abc3aSNaveen Krishna Ch MUX_SEL_TOPC0, 28, 1), 104532abc3aSNaveen Krishna Ch 105532abc3aSNaveen Krishna Ch MUX(0, "mout_sclk_bus0_pll_out", mout_sclk_bus0_pll_out_p, 106532abc3aSNaveen Krishna Ch MUX_SEL_TOPC1, 16, 1), 107532abc3aSNaveen Krishna Ch 108f5e127cdSNaveen Krishna Ch MUX(0, "mout_aclk_ccore_133", mout_topc_group2, MUX_SEL_TOPC2, 4, 2), 109f5e127cdSNaveen Krishna Ch 110532abc3aSNaveen Krishna Ch MUX(0, "mout_aclk_peris_66", mout_topc_group2, MUX_SEL_TOPC3, 24, 2), 111532abc3aSNaveen Krishna Ch }; 112532abc3aSNaveen Krishna Ch 113532abc3aSNaveen Krishna Ch static struct samsung_div_clock topc_div_clks[] __initdata = { 114f5e127cdSNaveen Krishna Ch DIV(DOUT_ACLK_CCORE_133, "dout_aclk_ccore_133", "mout_aclk_ccore_133", 115f5e127cdSNaveen Krishna Ch DIV_TOPC0, 4, 4), 116f5e127cdSNaveen Krishna Ch 117532abc3aSNaveen Krishna Ch DIV(DOUT_ACLK_PERIS, "dout_aclk_peris_66", "mout_aclk_peris_66", 118532abc3aSNaveen Krishna Ch DIV_TOPC1, 24, 4), 119532abc3aSNaveen Krishna Ch 120532abc3aSNaveen Krishna Ch DIV(DOUT_SCLK_BUS0_PLL, "dout_sclk_bus0_pll", "mout_sclk_bus0_pll_out", 121532abc3aSNaveen Krishna Ch DIV_TOPC3, 0, 3), 122532abc3aSNaveen Krishna Ch DIV(DOUT_SCLK_BUS1_PLL, "dout_sclk_bus1_pll", "mout_bus1_pll_ctrl", 123532abc3aSNaveen Krishna Ch DIV_TOPC3, 8, 3), 124532abc3aSNaveen Krishna Ch DIV(DOUT_SCLK_CC_PLL, "dout_sclk_cc_pll", "mout_cc_pll_ctrl", 125532abc3aSNaveen Krishna Ch DIV_TOPC3, 12, 3), 126532abc3aSNaveen Krishna Ch DIV(DOUT_SCLK_MFC_PLL, "dout_sclk_mfc_pll", "mout_mfc_pll_ctrl", 127532abc3aSNaveen Krishna Ch DIV_TOPC3, 16, 3), 128532abc3aSNaveen Krishna Ch }; 129532abc3aSNaveen Krishna Ch 130532abc3aSNaveen Krishna Ch static struct samsung_pll_clock topc_pll_clks[] __initdata = { 131532abc3aSNaveen Krishna Ch PLL(pll_1451x, 0, "fout_bus0_pll", "fin_pll", BUS0_PLL_LOCK, 132532abc3aSNaveen Krishna Ch BUS0_PLL_CON0, NULL), 133532abc3aSNaveen Krishna Ch PLL(pll_1452x, 0, "fout_cc_pll", "fin_pll", CC_PLL_LOCK, 134532abc3aSNaveen Krishna Ch CC_PLL_CON0, NULL), 135532abc3aSNaveen Krishna Ch PLL(pll_1452x, 0, "fout_bus1_pll", "fin_pll", BUS1_DPLL_LOCK, 136532abc3aSNaveen Krishna Ch BUS1_DPLL_CON0, NULL), 137532abc3aSNaveen Krishna Ch PLL(pll_1452x, 0, "fout_mfc_pll", "fin_pll", MFC_PLL_LOCK, 138532abc3aSNaveen Krishna Ch MFC_PLL_CON0, NULL), 139532abc3aSNaveen Krishna Ch PLL(pll_1460x, 0, "fout_aud_pll", "fin_pll", AUD_PLL_LOCK, 140532abc3aSNaveen Krishna Ch AUD_PLL_CON0, NULL), 141532abc3aSNaveen Krishna Ch }; 142532abc3aSNaveen Krishna Ch 143532abc3aSNaveen Krishna Ch static struct samsung_cmu_info topc_cmu_info __initdata = { 144532abc3aSNaveen Krishna Ch .pll_clks = topc_pll_clks, 145532abc3aSNaveen Krishna Ch .nr_pll_clks = ARRAY_SIZE(topc_pll_clks), 146532abc3aSNaveen Krishna Ch .mux_clks = topc_mux_clks, 147532abc3aSNaveen Krishna Ch .nr_mux_clks = ARRAY_SIZE(topc_mux_clks), 148532abc3aSNaveen Krishna Ch .div_clks = topc_div_clks, 149532abc3aSNaveen Krishna Ch .nr_div_clks = ARRAY_SIZE(topc_div_clks), 150532abc3aSNaveen Krishna Ch .fixed_factor_clks = topc_fixed_factor_clks, 151532abc3aSNaveen Krishna Ch .nr_fixed_factor_clks = ARRAY_SIZE(topc_fixed_factor_clks), 152532abc3aSNaveen Krishna Ch .nr_clk_ids = TOPC_NR_CLK, 153532abc3aSNaveen Krishna Ch .clk_regs = topc_clk_regs, 154532abc3aSNaveen Krishna Ch .nr_clk_regs = ARRAY_SIZE(topc_clk_regs), 155532abc3aSNaveen Krishna Ch }; 156532abc3aSNaveen Krishna Ch 157532abc3aSNaveen Krishna Ch static void __init exynos7_clk_topc_init(struct device_node *np) 158532abc3aSNaveen Krishna Ch { 159532abc3aSNaveen Krishna Ch samsung_cmu_register_one(np, &topc_cmu_info); 160532abc3aSNaveen Krishna Ch } 161532abc3aSNaveen Krishna Ch 162532abc3aSNaveen Krishna Ch CLK_OF_DECLARE(exynos7_clk_topc, "samsung,exynos7-clock-topc", 163532abc3aSNaveen Krishna Ch exynos7_clk_topc_init); 164532abc3aSNaveen Krishna Ch 165532abc3aSNaveen Krishna Ch /* Register Offset definitions for CMU_TOP0 (0x105D0000) */ 166532abc3aSNaveen Krishna Ch #define MUX_SEL_TOP00 0x0200 167532abc3aSNaveen Krishna Ch #define MUX_SEL_TOP01 0x0204 168532abc3aSNaveen Krishna Ch #define MUX_SEL_TOP03 0x020C 169532abc3aSNaveen Krishna Ch #define MUX_SEL_TOP0_PERIC3 0x023C 170532abc3aSNaveen Krishna Ch #define DIV_TOP03 0x060C 171532abc3aSNaveen Krishna Ch #define DIV_TOP0_PERIC3 0x063C 172532abc3aSNaveen Krishna Ch #define ENABLE_SCLK_TOP0_PERIC3 0x0A3C 173532abc3aSNaveen Krishna Ch 174532abc3aSNaveen Krishna Ch /* List of parent clocks for Muxes in CMU_TOP0 */ 175532abc3aSNaveen Krishna Ch PNAME(mout_bus0_pll_p) = { "fin_pll", "dout_sclk_bus0_pll" }; 176532abc3aSNaveen Krishna Ch PNAME(mout_bus1_pll_p) = { "fin_pll", "dout_sclk_bus1_pll" }; 177532abc3aSNaveen Krishna Ch PNAME(mout_cc_pll_p) = { "fin_pll", "dout_sclk_cc_pll" }; 178532abc3aSNaveen Krishna Ch PNAME(mout_mfc_pll_p) = { "fin_pll", "dout_sclk_mfc_pll" }; 179532abc3aSNaveen Krishna Ch 180532abc3aSNaveen Krishna Ch PNAME(mout_top0_half_bus0_pll_p) = {"mout_top0_bus0_pll", 181532abc3aSNaveen Krishna Ch "ffac_top0_bus0_pll_div2"}; 182532abc3aSNaveen Krishna Ch PNAME(mout_top0_half_bus1_pll_p) = {"mout_top0_bus1_pll", 183532abc3aSNaveen Krishna Ch "ffac_top0_bus1_pll_div2"}; 184532abc3aSNaveen Krishna Ch PNAME(mout_top0_half_cc_pll_p) = {"mout_top0_cc_pll", 185532abc3aSNaveen Krishna Ch "ffac_top0_cc_pll_div2"}; 186532abc3aSNaveen Krishna Ch PNAME(mout_top0_half_mfc_pll_p) = {"mout_top0_mfc_pll", 187532abc3aSNaveen Krishna Ch "ffac_top0_mfc_pll_div2"}; 188532abc3aSNaveen Krishna Ch 189532abc3aSNaveen Krishna Ch PNAME(mout_top0_group1) = {"mout_top0_half_bus0_pll", 190532abc3aSNaveen Krishna Ch "mout_top0_half_bus1_pll", "mout_top0_half_cc_pll", 191532abc3aSNaveen Krishna Ch "mout_top0_half_mfc_pll"}; 192532abc3aSNaveen Krishna Ch 193532abc3aSNaveen Krishna Ch static unsigned long top0_clk_regs[] __initdata = { 194532abc3aSNaveen Krishna Ch MUX_SEL_TOP00, 195532abc3aSNaveen Krishna Ch MUX_SEL_TOP01, 196532abc3aSNaveen Krishna Ch MUX_SEL_TOP03, 197532abc3aSNaveen Krishna Ch MUX_SEL_TOP0_PERIC3, 198532abc3aSNaveen Krishna Ch DIV_TOP03, 199532abc3aSNaveen Krishna Ch DIV_TOP0_PERIC3, 200532abc3aSNaveen Krishna Ch ENABLE_SCLK_TOP0_PERIC3, 201532abc3aSNaveen Krishna Ch }; 202532abc3aSNaveen Krishna Ch 203532abc3aSNaveen Krishna Ch static struct samsung_mux_clock top0_mux_clks[] __initdata = { 204532abc3aSNaveen Krishna Ch MUX(0, "mout_top0_mfc_pll", mout_mfc_pll_p, MUX_SEL_TOP00, 4, 1), 205532abc3aSNaveen Krishna Ch MUX(0, "mout_top0_cc_pll", mout_cc_pll_p, MUX_SEL_TOP00, 8, 1), 206532abc3aSNaveen Krishna Ch MUX(0, "mout_top0_bus1_pll", mout_bus1_pll_p, MUX_SEL_TOP00, 12, 1), 207532abc3aSNaveen Krishna Ch MUX(0, "mout_top0_bus0_pll", mout_bus0_pll_p, MUX_SEL_TOP00, 16, 1), 208532abc3aSNaveen Krishna Ch 209532abc3aSNaveen Krishna Ch MUX(0, "mout_top0_half_mfc_pll", mout_top0_half_mfc_pll_p, 210532abc3aSNaveen Krishna Ch MUX_SEL_TOP01, 4, 1), 211532abc3aSNaveen Krishna Ch MUX(0, "mout_top0_half_cc_pll", mout_top0_half_cc_pll_p, 212532abc3aSNaveen Krishna Ch MUX_SEL_TOP01, 8, 1), 213532abc3aSNaveen Krishna Ch MUX(0, "mout_top0_half_bus1_pll", mout_top0_half_bus1_pll_p, 214532abc3aSNaveen Krishna Ch MUX_SEL_TOP01, 12, 1), 215532abc3aSNaveen Krishna Ch MUX(0, "mout_top0_half_bus0_pll", mout_top0_half_bus0_pll_p, 216532abc3aSNaveen Krishna Ch MUX_SEL_TOP01, 16, 1), 217532abc3aSNaveen Krishna Ch 218532abc3aSNaveen Krishna Ch MUX(0, "mout_aclk_peric1_66", mout_top0_group1, MUX_SEL_TOP03, 12, 2), 219532abc3aSNaveen Krishna Ch MUX(0, "mout_aclk_peric0_66", mout_top0_group1, MUX_SEL_TOP03, 20, 2), 220532abc3aSNaveen Krishna Ch 221532abc3aSNaveen Krishna Ch MUX(0, "mout_sclk_uart3", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 4, 2), 222532abc3aSNaveen Krishna Ch MUX(0, "mout_sclk_uart2", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 8, 2), 223532abc3aSNaveen Krishna Ch MUX(0, "mout_sclk_uart1", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 12, 2), 224532abc3aSNaveen Krishna Ch MUX(0, "mout_sclk_uart0", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 16, 2), 225532abc3aSNaveen Krishna Ch }; 226532abc3aSNaveen Krishna Ch 227532abc3aSNaveen Krishna Ch static struct samsung_div_clock top0_div_clks[] __initdata = { 228532abc3aSNaveen Krishna Ch DIV(DOUT_ACLK_PERIC1, "dout_aclk_peric1_66", "mout_aclk_peric1_66", 229532abc3aSNaveen Krishna Ch DIV_TOP03, 12, 6), 230532abc3aSNaveen Krishna Ch DIV(DOUT_ACLK_PERIC0, "dout_aclk_peric0_66", "mout_aclk_peric0_66", 231532abc3aSNaveen Krishna Ch DIV_TOP03, 20, 6), 232532abc3aSNaveen Krishna Ch 233532abc3aSNaveen Krishna Ch DIV(0, "dout_sclk_uart3", "mout_sclk_uart3", DIV_TOP0_PERIC3, 4, 4), 234532abc3aSNaveen Krishna Ch DIV(0, "dout_sclk_uart2", "mout_sclk_uart2", DIV_TOP0_PERIC3, 8, 4), 235532abc3aSNaveen Krishna Ch DIV(0, "dout_sclk_uart1", "mout_sclk_uart1", DIV_TOP0_PERIC3, 12, 4), 236532abc3aSNaveen Krishna Ch DIV(0, "dout_sclk_uart0", "mout_sclk_uart0", DIV_TOP0_PERIC3, 16, 4), 237532abc3aSNaveen Krishna Ch }; 238532abc3aSNaveen Krishna Ch 239532abc3aSNaveen Krishna Ch static struct samsung_gate_clock top0_gate_clks[] __initdata = { 240532abc3aSNaveen Krishna Ch GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_sclk_uart3", 241532abc3aSNaveen Krishna Ch ENABLE_SCLK_TOP0_PERIC3, 4, 0, 0), 242532abc3aSNaveen Krishna Ch GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_sclk_uart2", 243532abc3aSNaveen Krishna Ch ENABLE_SCLK_TOP0_PERIC3, 8, 0, 0), 244532abc3aSNaveen Krishna Ch GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_sclk_uart1", 245532abc3aSNaveen Krishna Ch ENABLE_SCLK_TOP0_PERIC3, 12, 0, 0), 246532abc3aSNaveen Krishna Ch GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_sclk_uart0", 247532abc3aSNaveen Krishna Ch ENABLE_SCLK_TOP0_PERIC3, 16, 0, 0), 248532abc3aSNaveen Krishna Ch }; 249532abc3aSNaveen Krishna Ch 250532abc3aSNaveen Krishna Ch static struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initdata = { 251532abc3aSNaveen Krishna Ch FFACTOR(0, "ffac_top0_bus0_pll_div2", "mout_top0_bus0_pll", 1, 2, 0), 252532abc3aSNaveen Krishna Ch FFACTOR(0, "ffac_top0_bus1_pll_div2", "mout_top0_bus1_pll", 1, 2, 0), 253532abc3aSNaveen Krishna Ch FFACTOR(0, "ffac_top0_cc_pll_div2", "mout_top0_cc_pll", 1, 2, 0), 254532abc3aSNaveen Krishna Ch FFACTOR(0, "ffac_top0_mfc_pll_div2", "mout_top0_mfc_pll", 1, 2, 0), 255532abc3aSNaveen Krishna Ch }; 256532abc3aSNaveen Krishna Ch 257532abc3aSNaveen Krishna Ch static struct samsung_cmu_info top0_cmu_info __initdata = { 258532abc3aSNaveen Krishna Ch .mux_clks = top0_mux_clks, 259532abc3aSNaveen Krishna Ch .nr_mux_clks = ARRAY_SIZE(top0_mux_clks), 260532abc3aSNaveen Krishna Ch .div_clks = top0_div_clks, 261532abc3aSNaveen Krishna Ch .nr_div_clks = ARRAY_SIZE(top0_div_clks), 262532abc3aSNaveen Krishna Ch .gate_clks = top0_gate_clks, 263532abc3aSNaveen Krishna Ch .nr_gate_clks = ARRAY_SIZE(top0_gate_clks), 264532abc3aSNaveen Krishna Ch .fixed_factor_clks = top0_fixed_factor_clks, 265532abc3aSNaveen Krishna Ch .nr_fixed_factor_clks = ARRAY_SIZE(top0_fixed_factor_clks), 266532abc3aSNaveen Krishna Ch .nr_clk_ids = TOP0_NR_CLK, 267532abc3aSNaveen Krishna Ch .clk_regs = top0_clk_regs, 268532abc3aSNaveen Krishna Ch .nr_clk_regs = ARRAY_SIZE(top0_clk_regs), 269532abc3aSNaveen Krishna Ch }; 270532abc3aSNaveen Krishna Ch 271532abc3aSNaveen Krishna Ch static void __init exynos7_clk_top0_init(struct device_node *np) 272532abc3aSNaveen Krishna Ch { 273532abc3aSNaveen Krishna Ch samsung_cmu_register_one(np, &top0_cmu_info); 274532abc3aSNaveen Krishna Ch } 275532abc3aSNaveen Krishna Ch 276532abc3aSNaveen Krishna Ch CLK_OF_DECLARE(exynos7_clk_top0, "samsung,exynos7-clock-top0", 277532abc3aSNaveen Krishna Ch exynos7_clk_top0_init); 278532abc3aSNaveen Krishna Ch 2796d0c8c72SNaveen Krishna Ch /* Register Offset definitions for CMU_TOP1 (0x105E0000) */ 2806d0c8c72SNaveen Krishna Ch #define MUX_SEL_TOP10 0x0200 2816d0c8c72SNaveen Krishna Ch #define MUX_SEL_TOP11 0x0204 2826d0c8c72SNaveen Krishna Ch #define MUX_SEL_TOP13 0x020C 2836d0c8c72SNaveen Krishna Ch #define MUX_SEL_TOP1_FSYS0 0x0224 2846d0c8c72SNaveen Krishna Ch #define MUX_SEL_TOP1_FSYS1 0x0228 2856d0c8c72SNaveen Krishna Ch #define DIV_TOP13 0x060C 2866d0c8c72SNaveen Krishna Ch #define DIV_TOP1_FSYS0 0x0624 2876d0c8c72SNaveen Krishna Ch #define DIV_TOP1_FSYS1 0x0628 2886d0c8c72SNaveen Krishna Ch #define ENABLE_ACLK_TOP13 0x080C 2896d0c8c72SNaveen Krishna Ch #define ENABLE_SCLK_TOP1_FSYS0 0x0A24 2906d0c8c72SNaveen Krishna Ch #define ENABLE_SCLK_TOP1_FSYS1 0x0A28 2916d0c8c72SNaveen Krishna Ch 2926d0c8c72SNaveen Krishna Ch /* List of parent clocks for Muxes in CMU_TOP1 */ 2936d0c8c72SNaveen Krishna Ch PNAME(mout_top1_bus0_pll_p) = { "fin_pll", "dout_sclk_bus0_pll" }; 2946d0c8c72SNaveen Krishna Ch PNAME(mout_top1_bus1_pll_p) = { "fin_pll", "dout_sclk_bus1_pll_b" }; 2956d0c8c72SNaveen Krishna Ch PNAME(mout_top1_cc_pll_p) = { "fin_pll", "dout_sclk_cc_pll_b" }; 2966d0c8c72SNaveen Krishna Ch PNAME(mout_top1_mfc_pll_p) = { "fin_pll", "dout_sclk_mfc_pll_b" }; 2976d0c8c72SNaveen Krishna Ch 2986d0c8c72SNaveen Krishna Ch PNAME(mout_top1_half_bus0_pll_p) = {"mout_top1_bus0_pll", 2996d0c8c72SNaveen Krishna Ch "ffac_top1_bus0_pll_div2"}; 3006d0c8c72SNaveen Krishna Ch PNAME(mout_top1_half_bus1_pll_p) = {"mout_top1_bus1_pll", 3016d0c8c72SNaveen Krishna Ch "ffac_top1_bus1_pll_div2"}; 3026d0c8c72SNaveen Krishna Ch PNAME(mout_top1_half_cc_pll_p) = {"mout_top1_cc_pll", 3036d0c8c72SNaveen Krishna Ch "ffac_top1_cc_pll_div2"}; 3046d0c8c72SNaveen Krishna Ch PNAME(mout_top1_half_mfc_pll_p) = {"mout_top1_mfc_pll", 3056d0c8c72SNaveen Krishna Ch "ffac_top1_mfc_pll_div2"}; 3066d0c8c72SNaveen Krishna Ch 3076d0c8c72SNaveen Krishna Ch PNAME(mout_top1_group1) = {"mout_top1_half_bus0_pll", 3086d0c8c72SNaveen Krishna Ch "mout_top1_half_bus1_pll", "mout_top1_half_cc_pll", 3096d0c8c72SNaveen Krishna Ch "mout_top1_half_mfc_pll"}; 3106d0c8c72SNaveen Krishna Ch 3116d0c8c72SNaveen Krishna Ch static unsigned long top1_clk_regs[] __initdata = { 3126d0c8c72SNaveen Krishna Ch MUX_SEL_TOP10, 3136d0c8c72SNaveen Krishna Ch MUX_SEL_TOP11, 3146d0c8c72SNaveen Krishna Ch MUX_SEL_TOP13, 3156d0c8c72SNaveen Krishna Ch MUX_SEL_TOP1_FSYS0, 3166d0c8c72SNaveen Krishna Ch MUX_SEL_TOP1_FSYS1, 3176d0c8c72SNaveen Krishna Ch DIV_TOP13, 3186d0c8c72SNaveen Krishna Ch DIV_TOP1_FSYS0, 3196d0c8c72SNaveen Krishna Ch DIV_TOP1_FSYS1, 3206d0c8c72SNaveen Krishna Ch ENABLE_ACLK_TOP13, 3216d0c8c72SNaveen Krishna Ch ENABLE_SCLK_TOP1_FSYS0, 3226d0c8c72SNaveen Krishna Ch ENABLE_SCLK_TOP1_FSYS1, 3236d0c8c72SNaveen Krishna Ch }; 3246d0c8c72SNaveen Krishna Ch 3256d0c8c72SNaveen Krishna Ch static struct samsung_mux_clock top1_mux_clks[] __initdata = { 3266d0c8c72SNaveen Krishna Ch MUX(0, "mout_top1_mfc_pll", mout_top1_mfc_pll_p, MUX_SEL_TOP10, 4, 1), 3276d0c8c72SNaveen Krishna Ch MUX(0, "mout_top1_cc_pll", mout_top1_cc_pll_p, MUX_SEL_TOP10, 8, 1), 3286d0c8c72SNaveen Krishna Ch MUX(0, "mout_top1_bus1_pll", mout_top1_bus1_pll_p, 3296d0c8c72SNaveen Krishna Ch MUX_SEL_TOP10, 12, 1), 3306d0c8c72SNaveen Krishna Ch MUX(0, "mout_top1_bus0_pll", mout_top1_bus0_pll_p, 3316d0c8c72SNaveen Krishna Ch MUX_SEL_TOP10, 16, 1), 3326d0c8c72SNaveen Krishna Ch 3336d0c8c72SNaveen Krishna Ch MUX(0, "mout_top1_half_mfc_pll", mout_top1_half_mfc_pll_p, 3346d0c8c72SNaveen Krishna Ch MUX_SEL_TOP11, 4, 1), 3356d0c8c72SNaveen Krishna Ch MUX(0, "mout_top1_half_cc_pll", mout_top1_half_cc_pll_p, 3366d0c8c72SNaveen Krishna Ch MUX_SEL_TOP11, 8, 1), 3376d0c8c72SNaveen Krishna Ch MUX(0, "mout_top1_half_bus1_pll", mout_top1_half_bus1_pll_p, 3386d0c8c72SNaveen Krishna Ch MUX_SEL_TOP11, 12, 1), 3396d0c8c72SNaveen Krishna Ch MUX(0, "mout_top1_half_bus0_pll", mout_top1_half_bus0_pll_p, 3406d0c8c72SNaveen Krishna Ch MUX_SEL_TOP11, 16, 1), 3416d0c8c72SNaveen Krishna Ch 3426d0c8c72SNaveen Krishna Ch MUX(0, "mout_aclk_fsys1_200", mout_top1_group1, MUX_SEL_TOP13, 24, 2), 3436d0c8c72SNaveen Krishna Ch MUX(0, "mout_aclk_fsys0_200", mout_top1_group1, MUX_SEL_TOP13, 28, 2), 3446d0c8c72SNaveen Krishna Ch 3456d0c8c72SNaveen Krishna Ch MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 24, 2), 3466d0c8c72SNaveen Krishna Ch 3476d0c8c72SNaveen Krishna Ch MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 24, 2), 3486d0c8c72SNaveen Krishna Ch MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 28, 2), 3496d0c8c72SNaveen Krishna Ch }; 3506d0c8c72SNaveen Krishna Ch 3516d0c8c72SNaveen Krishna Ch static struct samsung_div_clock top1_div_clks[] __initdata = { 3526d0c8c72SNaveen Krishna Ch DIV(DOUT_ACLK_FSYS1_200, "dout_aclk_fsys1_200", "mout_aclk_fsys1_200", 3536d0c8c72SNaveen Krishna Ch DIV_TOP13, 24, 4), 3546d0c8c72SNaveen Krishna Ch DIV(DOUT_ACLK_FSYS0_200, "dout_aclk_fsys0_200", "mout_aclk_fsys0_200", 3556d0c8c72SNaveen Krishna Ch DIV_TOP13, 28, 4), 3566d0c8c72SNaveen Krishna Ch 3576d0c8c72SNaveen Krishna Ch DIV(DOUT_SCLK_MMC2, "dout_sclk_mmc2", "mout_sclk_mmc2", 3586d0c8c72SNaveen Krishna Ch DIV_TOP1_FSYS0, 24, 4), 3596d0c8c72SNaveen Krishna Ch 3606d0c8c72SNaveen Krishna Ch DIV(DOUT_SCLK_MMC1, "dout_sclk_mmc1", "mout_sclk_mmc1", 3616d0c8c72SNaveen Krishna Ch DIV_TOP1_FSYS1, 24, 4), 3626d0c8c72SNaveen Krishna Ch DIV(DOUT_SCLK_MMC0, "dout_sclk_mmc0", "mout_sclk_mmc0", 3636d0c8c72SNaveen Krishna Ch DIV_TOP1_FSYS1, 28, 4), 3646d0c8c72SNaveen Krishna Ch }; 3656d0c8c72SNaveen Krishna Ch 3666d0c8c72SNaveen Krishna Ch static struct samsung_gate_clock top1_gate_clks[] __initdata = { 3676d0c8c72SNaveen Krishna Ch GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_sclk_mmc2", 3686d0c8c72SNaveen Krishna Ch ENABLE_SCLK_TOP1_FSYS0, 24, CLK_SET_RATE_PARENT, 0), 3696d0c8c72SNaveen Krishna Ch 3706d0c8c72SNaveen Krishna Ch GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_sclk_mmc1", 3716d0c8c72SNaveen Krishna Ch ENABLE_SCLK_TOP1_FSYS1, 24, CLK_SET_RATE_PARENT, 0), 3726d0c8c72SNaveen Krishna Ch GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_sclk_mmc0", 3736d0c8c72SNaveen Krishna Ch ENABLE_SCLK_TOP1_FSYS1, 28, CLK_SET_RATE_PARENT, 0), 3746d0c8c72SNaveen Krishna Ch }; 3756d0c8c72SNaveen Krishna Ch 3766d0c8c72SNaveen Krishna Ch static struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initdata = { 3776d0c8c72SNaveen Krishna Ch FFACTOR(0, "ffac_top1_bus0_pll_div2", "mout_top1_bus0_pll", 1, 2, 0), 3786d0c8c72SNaveen Krishna Ch FFACTOR(0, "ffac_top1_bus1_pll_div2", "mout_top1_bus1_pll", 1, 2, 0), 3796d0c8c72SNaveen Krishna Ch FFACTOR(0, "ffac_top1_cc_pll_div2", "mout_top1_cc_pll", 1, 2, 0), 3806d0c8c72SNaveen Krishna Ch FFACTOR(0, "ffac_top1_mfc_pll_div2", "mout_top1_mfc_pll", 1, 2, 0), 3816d0c8c72SNaveen Krishna Ch }; 3826d0c8c72SNaveen Krishna Ch 3836d0c8c72SNaveen Krishna Ch static struct samsung_cmu_info top1_cmu_info __initdata = { 3846d0c8c72SNaveen Krishna Ch .mux_clks = top1_mux_clks, 3856d0c8c72SNaveen Krishna Ch .nr_mux_clks = ARRAY_SIZE(top1_mux_clks), 3866d0c8c72SNaveen Krishna Ch .div_clks = top1_div_clks, 3876d0c8c72SNaveen Krishna Ch .nr_div_clks = ARRAY_SIZE(top1_div_clks), 3886d0c8c72SNaveen Krishna Ch .gate_clks = top1_gate_clks, 3896d0c8c72SNaveen Krishna Ch .nr_gate_clks = ARRAY_SIZE(top1_gate_clks), 3906d0c8c72SNaveen Krishna Ch .fixed_factor_clks = top1_fixed_factor_clks, 3916d0c8c72SNaveen Krishna Ch .nr_fixed_factor_clks = ARRAY_SIZE(top1_fixed_factor_clks), 3926d0c8c72SNaveen Krishna Ch .nr_clk_ids = TOP1_NR_CLK, 3936d0c8c72SNaveen Krishna Ch .clk_regs = top1_clk_regs, 3946d0c8c72SNaveen Krishna Ch .nr_clk_regs = ARRAY_SIZE(top1_clk_regs), 3956d0c8c72SNaveen Krishna Ch }; 3966d0c8c72SNaveen Krishna Ch 3976d0c8c72SNaveen Krishna Ch static void __init exynos7_clk_top1_init(struct device_node *np) 3986d0c8c72SNaveen Krishna Ch { 3996d0c8c72SNaveen Krishna Ch samsung_cmu_register_one(np, &top1_cmu_info); 4006d0c8c72SNaveen Krishna Ch } 4016d0c8c72SNaveen Krishna Ch 4026d0c8c72SNaveen Krishna Ch CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1", 4036d0c8c72SNaveen Krishna Ch exynos7_clk_top1_init); 4046d0c8c72SNaveen Krishna Ch 405f5e127cdSNaveen Krishna Ch /* Register Offset definitions for CMU_CCORE (0x105B0000) */ 406f5e127cdSNaveen Krishna Ch #define MUX_SEL_CCORE 0x0200 407f5e127cdSNaveen Krishna Ch #define DIV_CCORE 0x0600 408f5e127cdSNaveen Krishna Ch #define ENABLE_ACLK_CCORE0 0x0800 409f5e127cdSNaveen Krishna Ch #define ENABLE_ACLK_CCORE1 0x0804 410f5e127cdSNaveen Krishna Ch #define ENABLE_PCLK_CCORE 0x0900 411f5e127cdSNaveen Krishna Ch 412f5e127cdSNaveen Krishna Ch /* 413f5e127cdSNaveen Krishna Ch * List of parent clocks for Muxes in CMU_CCORE 414f5e127cdSNaveen Krishna Ch */ 415f5e127cdSNaveen Krishna Ch PNAME(mout_aclk_ccore_133_p) = { "fin_pll", "dout_aclk_ccore_133" }; 416f5e127cdSNaveen Krishna Ch 417f5e127cdSNaveen Krishna Ch static unsigned long ccore_clk_regs[] __initdata = { 418f5e127cdSNaveen Krishna Ch MUX_SEL_CCORE, 419f5e127cdSNaveen Krishna Ch ENABLE_PCLK_CCORE, 420f5e127cdSNaveen Krishna Ch }; 421f5e127cdSNaveen Krishna Ch 422f5e127cdSNaveen Krishna Ch static struct samsung_mux_clock ccore_mux_clks[] __initdata = { 423f5e127cdSNaveen Krishna Ch MUX(0, "mout_aclk_ccore_133_user", mout_aclk_ccore_133_p, 424f5e127cdSNaveen Krishna Ch MUX_SEL_CCORE, 1, 1), 425f5e127cdSNaveen Krishna Ch }; 426f5e127cdSNaveen Krishna Ch 427f5e127cdSNaveen Krishna Ch static struct samsung_gate_clock ccore_gate_clks[] __initdata = { 428f5e127cdSNaveen Krishna Ch GATE(PCLK_RTC, "pclk_rtc", "mout_aclk_ccore_133_user", 429f5e127cdSNaveen Krishna Ch ENABLE_PCLK_CCORE, 8, 0, 0), 430f5e127cdSNaveen Krishna Ch }; 431f5e127cdSNaveen Krishna Ch 432f5e127cdSNaveen Krishna Ch static struct samsung_cmu_info ccore_cmu_info __initdata = { 433f5e127cdSNaveen Krishna Ch .mux_clks = ccore_mux_clks, 434f5e127cdSNaveen Krishna Ch .nr_mux_clks = ARRAY_SIZE(ccore_mux_clks), 435f5e127cdSNaveen Krishna Ch .gate_clks = ccore_gate_clks, 436f5e127cdSNaveen Krishna Ch .nr_gate_clks = ARRAY_SIZE(ccore_gate_clks), 437f5e127cdSNaveen Krishna Ch .nr_clk_ids = CCORE_NR_CLK, 438f5e127cdSNaveen Krishna Ch .clk_regs = ccore_clk_regs, 439f5e127cdSNaveen Krishna Ch .nr_clk_regs = ARRAY_SIZE(ccore_clk_regs), 440f5e127cdSNaveen Krishna Ch }; 441f5e127cdSNaveen Krishna Ch 442f5e127cdSNaveen Krishna Ch static void __init exynos7_clk_ccore_init(struct device_node *np) 443f5e127cdSNaveen Krishna Ch { 444f5e127cdSNaveen Krishna Ch samsung_cmu_register_one(np, &ccore_cmu_info); 445f5e127cdSNaveen Krishna Ch } 446f5e127cdSNaveen Krishna Ch 447f5e127cdSNaveen Krishna Ch CLK_OF_DECLARE(exynos7_clk_ccore, "samsung,exynos7-clock-ccore", 448f5e127cdSNaveen Krishna Ch exynos7_clk_ccore_init); 449f5e127cdSNaveen Krishna Ch 450532abc3aSNaveen Krishna Ch /* Register Offset definitions for CMU_PERIC0 (0x13610000) */ 451532abc3aSNaveen Krishna Ch #define MUX_SEL_PERIC0 0x0200 452532abc3aSNaveen Krishna Ch #define ENABLE_PCLK_PERIC0 0x0900 453532abc3aSNaveen Krishna Ch #define ENABLE_SCLK_PERIC0 0x0A00 454532abc3aSNaveen Krishna Ch 455532abc3aSNaveen Krishna Ch /* List of parent clocks for Muxes in CMU_PERIC0 */ 456532abc3aSNaveen Krishna Ch PNAME(mout_aclk_peric0_66_p) = { "fin_pll", "dout_aclk_peric0_66" }; 457532abc3aSNaveen Krishna Ch PNAME(mout_sclk_uart0_p) = { "fin_pll", "sclk_uart0" }; 458532abc3aSNaveen Krishna Ch 459532abc3aSNaveen Krishna Ch static unsigned long peric0_clk_regs[] __initdata = { 460532abc3aSNaveen Krishna Ch MUX_SEL_PERIC0, 461532abc3aSNaveen Krishna Ch ENABLE_PCLK_PERIC0, 462532abc3aSNaveen Krishna Ch ENABLE_SCLK_PERIC0, 463532abc3aSNaveen Krishna Ch }; 464532abc3aSNaveen Krishna Ch 465532abc3aSNaveen Krishna Ch static struct samsung_mux_clock peric0_mux_clks[] __initdata = { 466532abc3aSNaveen Krishna Ch MUX(0, "mout_aclk_peric0_66_user", mout_aclk_peric0_66_p, 467532abc3aSNaveen Krishna Ch MUX_SEL_PERIC0, 0, 1), 468532abc3aSNaveen Krishna Ch MUX(0, "mout_sclk_uart0_user", mout_sclk_uart0_p, 469532abc3aSNaveen Krishna Ch MUX_SEL_PERIC0, 16, 1), 470532abc3aSNaveen Krishna Ch }; 471532abc3aSNaveen Krishna Ch 472532abc3aSNaveen Krishna Ch static struct samsung_gate_clock peric0_gate_clks[] __initdata = { 47357a2b485SNaveen Krishna Ch GATE(PCLK_HSI2C0, "pclk_hsi2c0", "mout_aclk_peric0_66_user", 47457a2b485SNaveen Krishna Ch ENABLE_PCLK_PERIC0, 8, 0, 0), 47557a2b485SNaveen Krishna Ch GATE(PCLK_HSI2C1, "pclk_hsi2c1", "mout_aclk_peric0_66_user", 47657a2b485SNaveen Krishna Ch ENABLE_PCLK_PERIC0, 9, 0, 0), 47757a2b485SNaveen Krishna Ch GATE(PCLK_HSI2C4, "pclk_hsi2c4", "mout_aclk_peric0_66_user", 47857a2b485SNaveen Krishna Ch ENABLE_PCLK_PERIC0, 10, 0, 0), 47957a2b485SNaveen Krishna Ch GATE(PCLK_HSI2C5, "pclk_hsi2c5", "mout_aclk_peric0_66_user", 48057a2b485SNaveen Krishna Ch ENABLE_PCLK_PERIC0, 11, 0, 0), 48157a2b485SNaveen Krishna Ch GATE(PCLK_HSI2C9, "pclk_hsi2c9", "mout_aclk_peric0_66_user", 48257a2b485SNaveen Krishna Ch ENABLE_PCLK_PERIC0, 12, 0, 0), 48357a2b485SNaveen Krishna Ch GATE(PCLK_HSI2C10, "pclk_hsi2c10", "mout_aclk_peric0_66_user", 48457a2b485SNaveen Krishna Ch ENABLE_PCLK_PERIC0, 13, 0, 0), 48557a2b485SNaveen Krishna Ch GATE(PCLK_HSI2C11, "pclk_hsi2c11", "mout_aclk_peric0_66_user", 48657a2b485SNaveen Krishna Ch ENABLE_PCLK_PERIC0, 14, 0, 0), 487532abc3aSNaveen Krishna Ch GATE(PCLK_UART0, "pclk_uart0", "mout_aclk_peric0_66_user", 488532abc3aSNaveen Krishna Ch ENABLE_PCLK_PERIC0, 16, 0, 0), 489*2ab2dfe5SNaveen Krishna Ch GATE(PCLK_PWM, "pclk_pwm", "mout_aclk_peric0_66_user", 490*2ab2dfe5SNaveen Krishna Ch ENABLE_PCLK_PERIC0, 21, 0, 0), 491532abc3aSNaveen Krishna Ch 492532abc3aSNaveen Krishna Ch GATE(SCLK_UART0, "sclk_uart0_user", "mout_sclk_uart0_user", 493532abc3aSNaveen Krishna Ch ENABLE_SCLK_PERIC0, 16, 0, 0), 494*2ab2dfe5SNaveen Krishna Ch GATE(SCLK_PWM, "sclk_pwm", "fin_pll", ENABLE_SCLK_PERIC0, 21, 0, 0), 495532abc3aSNaveen Krishna Ch }; 496532abc3aSNaveen Krishna Ch 497532abc3aSNaveen Krishna Ch static struct samsung_cmu_info peric0_cmu_info __initdata = { 498532abc3aSNaveen Krishna Ch .mux_clks = peric0_mux_clks, 499532abc3aSNaveen Krishna Ch .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks), 500532abc3aSNaveen Krishna Ch .gate_clks = peric0_gate_clks, 501532abc3aSNaveen Krishna Ch .nr_gate_clks = ARRAY_SIZE(peric0_gate_clks), 502532abc3aSNaveen Krishna Ch .nr_clk_ids = PERIC0_NR_CLK, 503532abc3aSNaveen Krishna Ch .clk_regs = peric0_clk_regs, 504532abc3aSNaveen Krishna Ch .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs), 505532abc3aSNaveen Krishna Ch }; 506532abc3aSNaveen Krishna Ch 507532abc3aSNaveen Krishna Ch static void __init exynos7_clk_peric0_init(struct device_node *np) 508532abc3aSNaveen Krishna Ch { 509532abc3aSNaveen Krishna Ch samsung_cmu_register_one(np, &peric0_cmu_info); 510532abc3aSNaveen Krishna Ch } 511532abc3aSNaveen Krishna Ch 512532abc3aSNaveen Krishna Ch /* Register Offset definitions for CMU_PERIC1 (0x14C80000) */ 513532abc3aSNaveen Krishna Ch #define MUX_SEL_PERIC10 0x0200 514532abc3aSNaveen Krishna Ch #define MUX_SEL_PERIC11 0x0204 515532abc3aSNaveen Krishna Ch #define ENABLE_PCLK_PERIC1 0x0900 516532abc3aSNaveen Krishna Ch #define ENABLE_SCLK_PERIC10 0x0A00 517532abc3aSNaveen Krishna Ch 518532abc3aSNaveen Krishna Ch CLK_OF_DECLARE(exynos7_clk_peric0, "samsung,exynos7-clock-peric0", 519532abc3aSNaveen Krishna Ch exynos7_clk_peric0_init); 520532abc3aSNaveen Krishna Ch 521532abc3aSNaveen Krishna Ch /* List of parent clocks for Muxes in CMU_PERIC1 */ 522532abc3aSNaveen Krishna Ch PNAME(mout_aclk_peric1_66_p) = { "fin_pll", "dout_aclk_peric1_66" }; 523532abc3aSNaveen Krishna Ch PNAME(mout_sclk_uart1_p) = { "fin_pll", "sclk_uart1" }; 524532abc3aSNaveen Krishna Ch PNAME(mout_sclk_uart2_p) = { "fin_pll", "sclk_uart2" }; 525532abc3aSNaveen Krishna Ch PNAME(mout_sclk_uart3_p) = { "fin_pll", "sclk_uart3" }; 526532abc3aSNaveen Krishna Ch 527532abc3aSNaveen Krishna Ch static unsigned long peric1_clk_regs[] __initdata = { 528532abc3aSNaveen Krishna Ch MUX_SEL_PERIC10, 529532abc3aSNaveen Krishna Ch MUX_SEL_PERIC11, 530532abc3aSNaveen Krishna Ch ENABLE_PCLK_PERIC1, 531532abc3aSNaveen Krishna Ch ENABLE_SCLK_PERIC10, 532532abc3aSNaveen Krishna Ch }; 533532abc3aSNaveen Krishna Ch 534532abc3aSNaveen Krishna Ch static struct samsung_mux_clock peric1_mux_clks[] __initdata = { 535532abc3aSNaveen Krishna Ch MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_p, 536532abc3aSNaveen Krishna Ch MUX_SEL_PERIC10, 0, 1), 537532abc3aSNaveen Krishna Ch 538532abc3aSNaveen Krishna Ch MUX(0, "mout_sclk_uart1_user", mout_sclk_uart1_p, 539532abc3aSNaveen Krishna Ch MUX_SEL_PERIC11, 20, 1), 540532abc3aSNaveen Krishna Ch MUX(0, "mout_sclk_uart2_user", mout_sclk_uart2_p, 541532abc3aSNaveen Krishna Ch MUX_SEL_PERIC11, 24, 1), 542532abc3aSNaveen Krishna Ch MUX(0, "mout_sclk_uart3_user", mout_sclk_uart3_p, 543532abc3aSNaveen Krishna Ch MUX_SEL_PERIC11, 28, 1), 544532abc3aSNaveen Krishna Ch }; 545532abc3aSNaveen Krishna Ch 546532abc3aSNaveen Krishna Ch static struct samsung_gate_clock peric1_gate_clks[] __initdata = { 54757a2b485SNaveen Krishna Ch GATE(PCLK_HSI2C2, "pclk_hsi2c2", "mout_aclk_peric1_66_user", 54857a2b485SNaveen Krishna Ch ENABLE_PCLK_PERIC1, 4, 0, 0), 54957a2b485SNaveen Krishna Ch GATE(PCLK_HSI2C3, "pclk_hsi2c3", "mout_aclk_peric1_66_user", 55057a2b485SNaveen Krishna Ch ENABLE_PCLK_PERIC1, 5, 0, 0), 55157a2b485SNaveen Krishna Ch GATE(PCLK_HSI2C6, "pclk_hsi2c6", "mout_aclk_peric1_66_user", 55257a2b485SNaveen Krishna Ch ENABLE_PCLK_PERIC1, 6, 0, 0), 55357a2b485SNaveen Krishna Ch GATE(PCLK_HSI2C7, "pclk_hsi2c7", "mout_aclk_peric1_66_user", 55457a2b485SNaveen Krishna Ch ENABLE_PCLK_PERIC1, 7, 0, 0), 55557a2b485SNaveen Krishna Ch GATE(PCLK_HSI2C8, "pclk_hsi2c8", "mout_aclk_peric1_66_user", 55657a2b485SNaveen Krishna Ch ENABLE_PCLK_PERIC1, 8, 0, 0), 557532abc3aSNaveen Krishna Ch GATE(PCLK_UART1, "pclk_uart1", "mout_aclk_peric1_66_user", 558532abc3aSNaveen Krishna Ch ENABLE_PCLK_PERIC1, 9, 0, 0), 559532abc3aSNaveen Krishna Ch GATE(PCLK_UART2, "pclk_uart2", "mout_aclk_peric1_66_user", 560532abc3aSNaveen Krishna Ch ENABLE_PCLK_PERIC1, 10, 0, 0), 561532abc3aSNaveen Krishna Ch GATE(PCLK_UART3, "pclk_uart3", "mout_aclk_peric1_66_user", 562532abc3aSNaveen Krishna Ch ENABLE_PCLK_PERIC1, 11, 0, 0), 563532abc3aSNaveen Krishna Ch 564532abc3aSNaveen Krishna Ch GATE(SCLK_UART1, "sclk_uart1_user", "mout_sclk_uart1_user", 565532abc3aSNaveen Krishna Ch ENABLE_SCLK_PERIC10, 9, 0, 0), 566532abc3aSNaveen Krishna Ch GATE(SCLK_UART2, "sclk_uart2_user", "mout_sclk_uart2_user", 567532abc3aSNaveen Krishna Ch ENABLE_SCLK_PERIC10, 10, 0, 0), 568532abc3aSNaveen Krishna Ch GATE(SCLK_UART3, "sclk_uart3_user", "mout_sclk_uart3_user", 569532abc3aSNaveen Krishna Ch ENABLE_SCLK_PERIC10, 11, 0, 0), 570532abc3aSNaveen Krishna Ch }; 571532abc3aSNaveen Krishna Ch 572532abc3aSNaveen Krishna Ch static struct samsung_cmu_info peric1_cmu_info __initdata = { 573532abc3aSNaveen Krishna Ch .mux_clks = peric1_mux_clks, 574532abc3aSNaveen Krishna Ch .nr_mux_clks = ARRAY_SIZE(peric1_mux_clks), 575532abc3aSNaveen Krishna Ch .gate_clks = peric1_gate_clks, 576532abc3aSNaveen Krishna Ch .nr_gate_clks = ARRAY_SIZE(peric1_gate_clks), 577532abc3aSNaveen Krishna Ch .nr_clk_ids = PERIC1_NR_CLK, 578532abc3aSNaveen Krishna Ch .clk_regs = peric1_clk_regs, 579532abc3aSNaveen Krishna Ch .nr_clk_regs = ARRAY_SIZE(peric1_clk_regs), 580532abc3aSNaveen Krishna Ch }; 581532abc3aSNaveen Krishna Ch 582532abc3aSNaveen Krishna Ch static void __init exynos7_clk_peric1_init(struct device_node *np) 583532abc3aSNaveen Krishna Ch { 584532abc3aSNaveen Krishna Ch samsung_cmu_register_one(np, &peric1_cmu_info); 585532abc3aSNaveen Krishna Ch } 586532abc3aSNaveen Krishna Ch 587532abc3aSNaveen Krishna Ch CLK_OF_DECLARE(exynos7_clk_peric1, "samsung,exynos7-clock-peric1", 588532abc3aSNaveen Krishna Ch exynos7_clk_peric1_init); 589532abc3aSNaveen Krishna Ch 590532abc3aSNaveen Krishna Ch /* Register Offset definitions for CMU_PERIS (0x10040000) */ 591532abc3aSNaveen Krishna Ch #define MUX_SEL_PERIS 0x0200 592*2ab2dfe5SNaveen Krishna Ch #define ENABLE_PCLK_PERIS 0x0900 593532abc3aSNaveen Krishna Ch #define ENABLE_PCLK_PERIS_SECURE_CHIPID 0x0910 594*2ab2dfe5SNaveen Krishna Ch #define ENABLE_SCLK_PERIS 0x0A00 595532abc3aSNaveen Krishna Ch #define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0A10 596532abc3aSNaveen Krishna Ch 597532abc3aSNaveen Krishna Ch /* List of parent clocks for Muxes in CMU_PERIS */ 598532abc3aSNaveen Krishna Ch PNAME(mout_aclk_peris_66_p) = { "fin_pll", "dout_aclk_peris_66" }; 599532abc3aSNaveen Krishna Ch 600532abc3aSNaveen Krishna Ch static unsigned long peris_clk_regs[] __initdata = { 601532abc3aSNaveen Krishna Ch MUX_SEL_PERIS, 602*2ab2dfe5SNaveen Krishna Ch ENABLE_PCLK_PERIS, 603532abc3aSNaveen Krishna Ch ENABLE_PCLK_PERIS_SECURE_CHIPID, 604*2ab2dfe5SNaveen Krishna Ch ENABLE_SCLK_PERIS, 605532abc3aSNaveen Krishna Ch ENABLE_SCLK_PERIS_SECURE_CHIPID, 606532abc3aSNaveen Krishna Ch }; 607532abc3aSNaveen Krishna Ch 608532abc3aSNaveen Krishna Ch static struct samsung_mux_clock peris_mux_clks[] __initdata = { 609532abc3aSNaveen Krishna Ch MUX(0, "mout_aclk_peris_66_user", 610532abc3aSNaveen Krishna Ch mout_aclk_peris_66_p, MUX_SEL_PERIS, 0, 1), 611532abc3aSNaveen Krishna Ch }; 612532abc3aSNaveen Krishna Ch 613532abc3aSNaveen Krishna Ch static struct samsung_gate_clock peris_gate_clks[] __initdata = { 614*2ab2dfe5SNaveen Krishna Ch GATE(PCLK_WDT, "pclk_wdt", "mout_aclk_peris_66_user", 615*2ab2dfe5SNaveen Krishna Ch ENABLE_PCLK_PERIS, 6, 0, 0), 616*2ab2dfe5SNaveen Krishna Ch GATE(PCLK_TMU, "pclk_tmu_apbif", "mout_aclk_peris_66_user", 617*2ab2dfe5SNaveen Krishna Ch ENABLE_PCLK_PERIS, 10, 0, 0), 618*2ab2dfe5SNaveen Krishna Ch 619532abc3aSNaveen Krishna Ch GATE(PCLK_CHIPID, "pclk_chipid", "mout_aclk_peris_66_user", 620532abc3aSNaveen Krishna Ch ENABLE_PCLK_PERIS_SECURE_CHIPID, 0, 0, 0), 621532abc3aSNaveen Krishna Ch GATE(SCLK_CHIPID, "sclk_chipid", "fin_pll", 622532abc3aSNaveen Krishna Ch ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0), 623*2ab2dfe5SNaveen Krishna Ch 624*2ab2dfe5SNaveen Krishna Ch GATE(SCLK_TMU, "sclk_tmu", "fin_pll", ENABLE_SCLK_PERIS, 10, 0, 0), 625532abc3aSNaveen Krishna Ch }; 626532abc3aSNaveen Krishna Ch 627532abc3aSNaveen Krishna Ch static struct samsung_cmu_info peris_cmu_info __initdata = { 628532abc3aSNaveen Krishna Ch .mux_clks = peris_mux_clks, 629532abc3aSNaveen Krishna Ch .nr_mux_clks = ARRAY_SIZE(peris_mux_clks), 630532abc3aSNaveen Krishna Ch .gate_clks = peris_gate_clks, 631532abc3aSNaveen Krishna Ch .nr_gate_clks = ARRAY_SIZE(peris_gate_clks), 632532abc3aSNaveen Krishna Ch .nr_clk_ids = PERIS_NR_CLK, 633532abc3aSNaveen Krishna Ch .clk_regs = peris_clk_regs, 634532abc3aSNaveen Krishna Ch .nr_clk_regs = ARRAY_SIZE(peris_clk_regs), 635532abc3aSNaveen Krishna Ch }; 636532abc3aSNaveen Krishna Ch 637532abc3aSNaveen Krishna Ch static void __init exynos7_clk_peris_init(struct device_node *np) 638532abc3aSNaveen Krishna Ch { 639532abc3aSNaveen Krishna Ch samsung_cmu_register_one(np, &peris_cmu_info); 640532abc3aSNaveen Krishna Ch } 641532abc3aSNaveen Krishna Ch 642532abc3aSNaveen Krishna Ch CLK_OF_DECLARE(exynos7_clk_peris, "samsung,exynos7-clock-peris", 643532abc3aSNaveen Krishna Ch exynos7_clk_peris_init); 6446d0c8c72SNaveen Krishna Ch 6456d0c8c72SNaveen Krishna Ch /* Register Offset definitions for CMU_FSYS0 (0x10E90000) */ 6466d0c8c72SNaveen Krishna Ch #define MUX_SEL_FSYS00 0x0200 6476d0c8c72SNaveen Krishna Ch #define MUX_SEL_FSYS01 0x0204 6486d0c8c72SNaveen Krishna Ch #define ENABLE_ACLK_FSYS01 0x0804 6496d0c8c72SNaveen Krishna Ch 6506d0c8c72SNaveen Krishna Ch /* 6516d0c8c72SNaveen Krishna Ch * List of parent clocks for Muxes in CMU_FSYS0 6526d0c8c72SNaveen Krishna Ch */ 6536d0c8c72SNaveen Krishna Ch PNAME(mout_aclk_fsys0_200_p) = { "fin_pll", "dout_aclk_fsys0_200" }; 6546d0c8c72SNaveen Krishna Ch PNAME(mout_sclk_mmc2_p) = { "fin_pll", "sclk_mmc2" }; 6556d0c8c72SNaveen Krishna Ch 6566d0c8c72SNaveen Krishna Ch static unsigned long fsys0_clk_regs[] __initdata = { 6576d0c8c72SNaveen Krishna Ch MUX_SEL_FSYS00, 6586d0c8c72SNaveen Krishna Ch MUX_SEL_FSYS01, 6596d0c8c72SNaveen Krishna Ch ENABLE_ACLK_FSYS01, 6606d0c8c72SNaveen Krishna Ch }; 6616d0c8c72SNaveen Krishna Ch 6626d0c8c72SNaveen Krishna Ch static struct samsung_mux_clock fsys0_mux_clks[] __initdata = { 6636d0c8c72SNaveen Krishna Ch MUX(0, "mout_aclk_fsys0_200_user", mout_aclk_fsys0_200_p, 6646d0c8c72SNaveen Krishna Ch MUX_SEL_FSYS00, 24, 1), 6656d0c8c72SNaveen Krishna Ch 6666d0c8c72SNaveen Krishna Ch MUX(0, "mout_sclk_mmc2_user", mout_sclk_mmc2_p, MUX_SEL_FSYS01, 24, 1), 6676d0c8c72SNaveen Krishna Ch }; 6686d0c8c72SNaveen Krishna Ch 6696d0c8c72SNaveen Krishna Ch static struct samsung_gate_clock fsys0_gate_clks[] __initdata = { 6706d0c8c72SNaveen Krishna Ch GATE(ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys0_200_user", 6716d0c8c72SNaveen Krishna Ch ENABLE_ACLK_FSYS01, 31, 0, 0), 6726d0c8c72SNaveen Krishna Ch }; 6736d0c8c72SNaveen Krishna Ch 6746d0c8c72SNaveen Krishna Ch static struct samsung_cmu_info fsys0_cmu_info __initdata = { 6756d0c8c72SNaveen Krishna Ch .mux_clks = fsys0_mux_clks, 6766d0c8c72SNaveen Krishna Ch .nr_mux_clks = ARRAY_SIZE(fsys0_mux_clks), 6776d0c8c72SNaveen Krishna Ch .gate_clks = fsys0_gate_clks, 6786d0c8c72SNaveen Krishna Ch .nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks), 6796d0c8c72SNaveen Krishna Ch .nr_clk_ids = TOP1_NR_CLK, 6806d0c8c72SNaveen Krishna Ch .clk_regs = fsys0_clk_regs, 6816d0c8c72SNaveen Krishna Ch .nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs), 6826d0c8c72SNaveen Krishna Ch }; 6836d0c8c72SNaveen Krishna Ch 6846d0c8c72SNaveen Krishna Ch static void __init exynos7_clk_fsys0_init(struct device_node *np) 6856d0c8c72SNaveen Krishna Ch { 6866d0c8c72SNaveen Krishna Ch samsung_cmu_register_one(np, &fsys0_cmu_info); 6876d0c8c72SNaveen Krishna Ch } 6886d0c8c72SNaveen Krishna Ch 6896d0c8c72SNaveen Krishna Ch CLK_OF_DECLARE(exynos7_clk_fsys0, "samsung,exynos7-clock-fsys0", 6906d0c8c72SNaveen Krishna Ch exynos7_clk_fsys0_init); 6916d0c8c72SNaveen Krishna Ch 6926d0c8c72SNaveen Krishna Ch /* Register Offset definitions for CMU_FSYS1 (0x156E0000) */ 6936d0c8c72SNaveen Krishna Ch #define MUX_SEL_FSYS10 0x0200 6946d0c8c72SNaveen Krishna Ch #define MUX_SEL_FSYS11 0x0204 6956d0c8c72SNaveen Krishna Ch #define ENABLE_ACLK_FSYS1 0x0800 6966d0c8c72SNaveen Krishna Ch 6976d0c8c72SNaveen Krishna Ch /* 6986d0c8c72SNaveen Krishna Ch * List of parent clocks for Muxes in CMU_FSYS1 6996d0c8c72SNaveen Krishna Ch */ 7006d0c8c72SNaveen Krishna Ch PNAME(mout_aclk_fsys1_200_p) = { "fin_pll", "dout_aclk_fsys1_200" }; 7016d0c8c72SNaveen Krishna Ch PNAME(mout_sclk_mmc0_p) = { "fin_pll", "sclk_mmc0" }; 7026d0c8c72SNaveen Krishna Ch PNAME(mout_sclk_mmc1_p) = { "fin_pll", "sclk_mmc1" }; 7036d0c8c72SNaveen Krishna Ch 7046d0c8c72SNaveen Krishna Ch static unsigned long fsys1_clk_regs[] __initdata = { 7056d0c8c72SNaveen Krishna Ch MUX_SEL_FSYS10, 7066d0c8c72SNaveen Krishna Ch MUX_SEL_FSYS11, 7076d0c8c72SNaveen Krishna Ch ENABLE_ACLK_FSYS1, 7086d0c8c72SNaveen Krishna Ch }; 7096d0c8c72SNaveen Krishna Ch 7106d0c8c72SNaveen Krishna Ch static struct samsung_mux_clock fsys1_mux_clks[] __initdata = { 7116d0c8c72SNaveen Krishna Ch MUX(0, "mout_aclk_fsys1_200_user", mout_aclk_fsys1_200_p, 7126d0c8c72SNaveen Krishna Ch MUX_SEL_FSYS10, 28, 1), 7136d0c8c72SNaveen Krishna Ch 7146d0c8c72SNaveen Krishna Ch MUX(0, "mout_sclk_mmc1_user", mout_sclk_mmc1_p, MUX_SEL_FSYS11, 24, 1), 7156d0c8c72SNaveen Krishna Ch MUX(0, "mout_sclk_mmc0_user", mout_sclk_mmc0_p, MUX_SEL_FSYS11, 28, 1), 7166d0c8c72SNaveen Krishna Ch }; 7176d0c8c72SNaveen Krishna Ch 7186d0c8c72SNaveen Krishna Ch static struct samsung_gate_clock fsys1_gate_clks[] __initdata = { 7196d0c8c72SNaveen Krishna Ch GATE(ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys1_200_user", 7206d0c8c72SNaveen Krishna Ch ENABLE_ACLK_FSYS1, 29, 0, 0), 7216d0c8c72SNaveen Krishna Ch GATE(ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys1_200_user", 7226d0c8c72SNaveen Krishna Ch ENABLE_ACLK_FSYS1, 30, 0, 0), 7236d0c8c72SNaveen Krishna Ch }; 7246d0c8c72SNaveen Krishna Ch 7256d0c8c72SNaveen Krishna Ch static struct samsung_cmu_info fsys1_cmu_info __initdata = { 7266d0c8c72SNaveen Krishna Ch .mux_clks = fsys1_mux_clks, 7276d0c8c72SNaveen Krishna Ch .nr_mux_clks = ARRAY_SIZE(fsys1_mux_clks), 7286d0c8c72SNaveen Krishna Ch .gate_clks = fsys1_gate_clks, 7296d0c8c72SNaveen Krishna Ch .nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks), 7306d0c8c72SNaveen Krishna Ch .nr_clk_ids = TOP1_NR_CLK, 7316d0c8c72SNaveen Krishna Ch .clk_regs = fsys1_clk_regs, 7326d0c8c72SNaveen Krishna Ch .nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs), 7336d0c8c72SNaveen Krishna Ch }; 7346d0c8c72SNaveen Krishna Ch 7356d0c8c72SNaveen Krishna Ch static void __init exynos7_clk_fsys1_init(struct device_node *np) 7366d0c8c72SNaveen Krishna Ch { 7376d0c8c72SNaveen Krishna Ch samsung_cmu_register_one(np, &fsys1_cmu_info); 7386d0c8c72SNaveen Krishna Ch } 7396d0c8c72SNaveen Krishna Ch 7406d0c8c72SNaveen Krishna Ch CLK_OF_DECLARE(exynos7_clk_fsys1, "samsung,exynos7-clock-fsys1", 7416d0c8c72SNaveen Krishna Ch exynos7_clk_fsys1_init); 742