1*616bc1deSXingyu Wu // SPDX-License-Identifier: GPL-2.0
2*616bc1deSXingyu Wu /*
3*616bc1deSXingyu Wu * StarFive JH7110 PLL Clock Generator Driver
4*616bc1deSXingyu Wu *
5*616bc1deSXingyu Wu * Copyright (C) 2023 StarFive Technology Co., Ltd.
6*616bc1deSXingyu Wu * Copyright (C) 2023 Emil Renner Berthing <emil.renner.berthing@canonical.com>
7*616bc1deSXingyu Wu *
8*616bc1deSXingyu Wu * This driver is about to register JH7110 PLL clock generator and support ops.
9*616bc1deSXingyu Wu * The JH7110 have three PLL clock, PLL0, PLL1 and PLL2.
10*616bc1deSXingyu Wu * Each PLL clocks work in integer mode or fraction mode by some dividers,
11*616bc1deSXingyu Wu * and the configuration registers and dividers are set in several syscon registers.
12*616bc1deSXingyu Wu * The formula for calculating frequency is:
13*616bc1deSXingyu Wu * Fvco = Fref * (NI + NF) / M / Q1
14*616bc1deSXingyu Wu * Fref: OSC source clock rate
15*616bc1deSXingyu Wu * NI: integer frequency dividing ratio of feedback divider, set by fbdiv[11:0].
16*616bc1deSXingyu Wu * NF: fractional frequency dividing ratio, set by frac[23:0]. NF = frac[23:0] / 2^24 = 0 ~ 0.999.
17*616bc1deSXingyu Wu * M: frequency dividing ratio of pre-divider, set by prediv[5:0].
18*616bc1deSXingyu Wu * Q1: frequency dividing ratio of post divider, set by 2^postdiv1[1:0], eg. 1, 2, 4 or 8.
19*616bc1deSXingyu Wu */
20*616bc1deSXingyu Wu
21*616bc1deSXingyu Wu #include <linux/bits.h>
22*616bc1deSXingyu Wu #include <linux/clk-provider.h>
23*616bc1deSXingyu Wu #include <linux/debugfs.h>
24*616bc1deSXingyu Wu #include <linux/device.h>
25*616bc1deSXingyu Wu #include <linux/kernel.h>
26*616bc1deSXingyu Wu #include <linux/mfd/syscon.h>
27*616bc1deSXingyu Wu #include <linux/platform_device.h>
28*616bc1deSXingyu Wu #include <linux/regmap.h>
29*616bc1deSXingyu Wu
30*616bc1deSXingyu Wu #include <dt-bindings/clock/starfive,jh7110-crg.h>
31*616bc1deSXingyu Wu
32*616bc1deSXingyu Wu /* this driver expects a 24MHz input frequency from the oscillator */
33*616bc1deSXingyu Wu #define JH7110_PLL_OSC_RATE 24000000UL
34*616bc1deSXingyu Wu
35*616bc1deSXingyu Wu #define JH7110_PLL0_PD_OFFSET 0x18
36*616bc1deSXingyu Wu #define JH7110_PLL0_DACPD_SHIFT 24
37*616bc1deSXingyu Wu #define JH7110_PLL0_DACPD_MASK BIT(24)
38*616bc1deSXingyu Wu #define JH7110_PLL0_DSMPD_SHIFT 25
39*616bc1deSXingyu Wu #define JH7110_PLL0_DSMPD_MASK BIT(25)
40*616bc1deSXingyu Wu #define JH7110_PLL0_FBDIV_OFFSET 0x1c
41*616bc1deSXingyu Wu #define JH7110_PLL0_FBDIV_SHIFT 0
42*616bc1deSXingyu Wu #define JH7110_PLL0_FBDIV_MASK GENMASK(11, 0)
43*616bc1deSXingyu Wu #define JH7110_PLL0_FRAC_OFFSET 0x20
44*616bc1deSXingyu Wu #define JH7110_PLL0_PREDIV_OFFSET 0x24
45*616bc1deSXingyu Wu
46*616bc1deSXingyu Wu #define JH7110_PLL1_PD_OFFSET 0x24
47*616bc1deSXingyu Wu #define JH7110_PLL1_DACPD_SHIFT 15
48*616bc1deSXingyu Wu #define JH7110_PLL1_DACPD_MASK BIT(15)
49*616bc1deSXingyu Wu #define JH7110_PLL1_DSMPD_SHIFT 16
50*616bc1deSXingyu Wu #define JH7110_PLL1_DSMPD_MASK BIT(16)
51*616bc1deSXingyu Wu #define JH7110_PLL1_FBDIV_OFFSET 0x24
52*616bc1deSXingyu Wu #define JH7110_PLL1_FBDIV_SHIFT 17
53*616bc1deSXingyu Wu #define JH7110_PLL1_FBDIV_MASK GENMASK(28, 17)
54*616bc1deSXingyu Wu #define JH7110_PLL1_FRAC_OFFSET 0x28
55*616bc1deSXingyu Wu #define JH7110_PLL1_PREDIV_OFFSET 0x2c
56*616bc1deSXingyu Wu
57*616bc1deSXingyu Wu #define JH7110_PLL2_PD_OFFSET 0x2c
58*616bc1deSXingyu Wu #define JH7110_PLL2_DACPD_SHIFT 15
59*616bc1deSXingyu Wu #define JH7110_PLL2_DACPD_MASK BIT(15)
60*616bc1deSXingyu Wu #define JH7110_PLL2_DSMPD_SHIFT 16
61*616bc1deSXingyu Wu #define JH7110_PLL2_DSMPD_MASK BIT(16)
62*616bc1deSXingyu Wu #define JH7110_PLL2_FBDIV_OFFSET 0x2c
63*616bc1deSXingyu Wu #define JH7110_PLL2_FBDIV_SHIFT 17
64*616bc1deSXingyu Wu #define JH7110_PLL2_FBDIV_MASK GENMASK(28, 17)
65*616bc1deSXingyu Wu #define JH7110_PLL2_FRAC_OFFSET 0x30
66*616bc1deSXingyu Wu #define JH7110_PLL2_PREDIV_OFFSET 0x34
67*616bc1deSXingyu Wu
68*616bc1deSXingyu Wu #define JH7110_PLL_FRAC_SHIFT 0
69*616bc1deSXingyu Wu #define JH7110_PLL_FRAC_MASK GENMASK(23, 0)
70*616bc1deSXingyu Wu #define JH7110_PLL_POSTDIV1_SHIFT 28
71*616bc1deSXingyu Wu #define JH7110_PLL_POSTDIV1_MASK GENMASK(29, 28)
72*616bc1deSXingyu Wu #define JH7110_PLL_PREDIV_SHIFT 0
73*616bc1deSXingyu Wu #define JH7110_PLL_PREDIV_MASK GENMASK(5, 0)
74*616bc1deSXingyu Wu
75*616bc1deSXingyu Wu enum jh7110_pll_mode {
76*616bc1deSXingyu Wu JH7110_PLL_MODE_FRACTION,
77*616bc1deSXingyu Wu JH7110_PLL_MODE_INTEGER,
78*616bc1deSXingyu Wu };
79*616bc1deSXingyu Wu
80*616bc1deSXingyu Wu struct jh7110_pll_preset {
81*616bc1deSXingyu Wu unsigned long freq;
82*616bc1deSXingyu Wu u32 frac; /* frac value should be decimals multiplied by 2^24 */
83*616bc1deSXingyu Wu unsigned fbdiv : 12; /* fbdiv value should be 8 to 4095 */
84*616bc1deSXingyu Wu unsigned prediv : 6;
85*616bc1deSXingyu Wu unsigned postdiv1 : 2;
86*616bc1deSXingyu Wu unsigned mode : 1;
87*616bc1deSXingyu Wu };
88*616bc1deSXingyu Wu
89*616bc1deSXingyu Wu struct jh7110_pll_info {
90*616bc1deSXingyu Wu char *name;
91*616bc1deSXingyu Wu const struct jh7110_pll_preset *presets;
92*616bc1deSXingyu Wu unsigned int npresets;
93*616bc1deSXingyu Wu struct {
94*616bc1deSXingyu Wu unsigned int pd;
95*616bc1deSXingyu Wu unsigned int fbdiv;
96*616bc1deSXingyu Wu unsigned int frac;
97*616bc1deSXingyu Wu unsigned int prediv;
98*616bc1deSXingyu Wu } offsets;
99*616bc1deSXingyu Wu struct {
100*616bc1deSXingyu Wu u32 dacpd;
101*616bc1deSXingyu Wu u32 dsmpd;
102*616bc1deSXingyu Wu u32 fbdiv;
103*616bc1deSXingyu Wu } masks;
104*616bc1deSXingyu Wu struct {
105*616bc1deSXingyu Wu char dacpd;
106*616bc1deSXingyu Wu char dsmpd;
107*616bc1deSXingyu Wu char fbdiv;
108*616bc1deSXingyu Wu } shifts;
109*616bc1deSXingyu Wu };
110*616bc1deSXingyu Wu
111*616bc1deSXingyu Wu #define _JH7110_PLL(_idx, _name, _presets) \
112*616bc1deSXingyu Wu [_idx] = { \
113*616bc1deSXingyu Wu .name = _name, \
114*616bc1deSXingyu Wu .presets = _presets, \
115*616bc1deSXingyu Wu .npresets = ARRAY_SIZE(_presets), \
116*616bc1deSXingyu Wu .offsets = { \
117*616bc1deSXingyu Wu .pd = JH7110_PLL##_idx##_PD_OFFSET, \
118*616bc1deSXingyu Wu .fbdiv = JH7110_PLL##_idx##_FBDIV_OFFSET, \
119*616bc1deSXingyu Wu .frac = JH7110_PLL##_idx##_FRAC_OFFSET, \
120*616bc1deSXingyu Wu .prediv = JH7110_PLL##_idx##_PREDIV_OFFSET, \
121*616bc1deSXingyu Wu }, \
122*616bc1deSXingyu Wu .masks = { \
123*616bc1deSXingyu Wu .dacpd = JH7110_PLL##_idx##_DACPD_MASK, \
124*616bc1deSXingyu Wu .dsmpd = JH7110_PLL##_idx##_DSMPD_MASK, \
125*616bc1deSXingyu Wu .fbdiv = JH7110_PLL##_idx##_FBDIV_MASK, \
126*616bc1deSXingyu Wu }, \
127*616bc1deSXingyu Wu .shifts = { \
128*616bc1deSXingyu Wu .dacpd = JH7110_PLL##_idx##_DACPD_SHIFT, \
129*616bc1deSXingyu Wu .dsmpd = JH7110_PLL##_idx##_DSMPD_SHIFT, \
130*616bc1deSXingyu Wu .fbdiv = JH7110_PLL##_idx##_FBDIV_SHIFT, \
131*616bc1deSXingyu Wu }, \
132*616bc1deSXingyu Wu }
133*616bc1deSXingyu Wu #define JH7110_PLL(idx, name, presets) _JH7110_PLL(idx, name, presets)
134*616bc1deSXingyu Wu
135*616bc1deSXingyu Wu struct jh7110_pll_data {
136*616bc1deSXingyu Wu struct clk_hw hw;
137*616bc1deSXingyu Wu unsigned int idx;
138*616bc1deSXingyu Wu };
139*616bc1deSXingyu Wu
140*616bc1deSXingyu Wu struct jh7110_pll_priv {
141*616bc1deSXingyu Wu struct device *dev;
142*616bc1deSXingyu Wu struct regmap *regmap;
143*616bc1deSXingyu Wu struct jh7110_pll_data pll[JH7110_PLLCLK_END];
144*616bc1deSXingyu Wu };
145*616bc1deSXingyu Wu
146*616bc1deSXingyu Wu struct jh7110_pll_regvals {
147*616bc1deSXingyu Wu u32 dacpd;
148*616bc1deSXingyu Wu u32 dsmpd;
149*616bc1deSXingyu Wu u32 fbdiv;
150*616bc1deSXingyu Wu u32 frac;
151*616bc1deSXingyu Wu u32 postdiv1;
152*616bc1deSXingyu Wu u32 prediv;
153*616bc1deSXingyu Wu };
154*616bc1deSXingyu Wu
155*616bc1deSXingyu Wu /*
156*616bc1deSXingyu Wu * Because the pll frequency is relatively fixed,
157*616bc1deSXingyu Wu * it cannot be set arbitrarily, so it needs a specific configuration.
158*616bc1deSXingyu Wu * PLL0 frequency should be multiple of 125MHz (USB frequency).
159*616bc1deSXingyu Wu */
160*616bc1deSXingyu Wu static const struct jh7110_pll_preset jh7110_pll0_presets[] = {
161*616bc1deSXingyu Wu {
162*616bc1deSXingyu Wu .freq = 375000000,
163*616bc1deSXingyu Wu .fbdiv = 125,
164*616bc1deSXingyu Wu .prediv = 8,
165*616bc1deSXingyu Wu .postdiv1 = 0,
166*616bc1deSXingyu Wu .mode = JH7110_PLL_MODE_INTEGER,
167*616bc1deSXingyu Wu }, {
168*616bc1deSXingyu Wu .freq = 500000000,
169*616bc1deSXingyu Wu .fbdiv = 125,
170*616bc1deSXingyu Wu .prediv = 6,
171*616bc1deSXingyu Wu .postdiv1 = 0,
172*616bc1deSXingyu Wu .mode = JH7110_PLL_MODE_INTEGER,
173*616bc1deSXingyu Wu }, {
174*616bc1deSXingyu Wu .freq = 625000000,
175*616bc1deSXingyu Wu .fbdiv = 625,
176*616bc1deSXingyu Wu .prediv = 24,
177*616bc1deSXingyu Wu .postdiv1 = 0,
178*616bc1deSXingyu Wu .mode = JH7110_PLL_MODE_INTEGER,
179*616bc1deSXingyu Wu }, {
180*616bc1deSXingyu Wu .freq = 750000000,
181*616bc1deSXingyu Wu .fbdiv = 125,
182*616bc1deSXingyu Wu .prediv = 4,
183*616bc1deSXingyu Wu .postdiv1 = 0,
184*616bc1deSXingyu Wu .mode = JH7110_PLL_MODE_INTEGER,
185*616bc1deSXingyu Wu }, {
186*616bc1deSXingyu Wu .freq = 875000000,
187*616bc1deSXingyu Wu .fbdiv = 875,
188*616bc1deSXingyu Wu .prediv = 24,
189*616bc1deSXingyu Wu .postdiv1 = 0,
190*616bc1deSXingyu Wu .mode = JH7110_PLL_MODE_INTEGER,
191*616bc1deSXingyu Wu }, {
192*616bc1deSXingyu Wu .freq = 1000000000,
193*616bc1deSXingyu Wu .fbdiv = 125,
194*616bc1deSXingyu Wu .prediv = 3,
195*616bc1deSXingyu Wu .postdiv1 = 0,
196*616bc1deSXingyu Wu .mode = JH7110_PLL_MODE_INTEGER,
197*616bc1deSXingyu Wu }, {
198*616bc1deSXingyu Wu .freq = 1250000000,
199*616bc1deSXingyu Wu .fbdiv = 625,
200*616bc1deSXingyu Wu .prediv = 12,
201*616bc1deSXingyu Wu .postdiv1 = 0,
202*616bc1deSXingyu Wu .mode = JH7110_PLL_MODE_INTEGER,
203*616bc1deSXingyu Wu }, {
204*616bc1deSXingyu Wu .freq = 1375000000,
205*616bc1deSXingyu Wu .fbdiv = 1375,
206*616bc1deSXingyu Wu .prediv = 24,
207*616bc1deSXingyu Wu .postdiv1 = 0,
208*616bc1deSXingyu Wu .mode = JH7110_PLL_MODE_INTEGER,
209*616bc1deSXingyu Wu }, {
210*616bc1deSXingyu Wu .freq = 1500000000,
211*616bc1deSXingyu Wu .fbdiv = 125,
212*616bc1deSXingyu Wu .prediv = 2,
213*616bc1deSXingyu Wu .postdiv1 = 0,
214*616bc1deSXingyu Wu .mode = JH7110_PLL_MODE_INTEGER,
215*616bc1deSXingyu Wu },
216*616bc1deSXingyu Wu };
217*616bc1deSXingyu Wu
218*616bc1deSXingyu Wu static const struct jh7110_pll_preset jh7110_pll1_presets[] = {
219*616bc1deSXingyu Wu {
220*616bc1deSXingyu Wu .freq = 1066000000,
221*616bc1deSXingyu Wu .fbdiv = 533,
222*616bc1deSXingyu Wu .prediv = 12,
223*616bc1deSXingyu Wu .postdiv1 = 0,
224*616bc1deSXingyu Wu .mode = JH7110_PLL_MODE_INTEGER,
225*616bc1deSXingyu Wu }, {
226*616bc1deSXingyu Wu .freq = 1200000000,
227*616bc1deSXingyu Wu .fbdiv = 50,
228*616bc1deSXingyu Wu .prediv = 1,
229*616bc1deSXingyu Wu .postdiv1 = 0,
230*616bc1deSXingyu Wu .mode = JH7110_PLL_MODE_INTEGER,
231*616bc1deSXingyu Wu }, {
232*616bc1deSXingyu Wu .freq = 1400000000,
233*616bc1deSXingyu Wu .fbdiv = 350,
234*616bc1deSXingyu Wu .prediv = 6,
235*616bc1deSXingyu Wu .postdiv1 = 0,
236*616bc1deSXingyu Wu .mode = JH7110_PLL_MODE_INTEGER,
237*616bc1deSXingyu Wu }, {
238*616bc1deSXingyu Wu .freq = 1600000000,
239*616bc1deSXingyu Wu .fbdiv = 200,
240*616bc1deSXingyu Wu .prediv = 3,
241*616bc1deSXingyu Wu .postdiv1 = 0,
242*616bc1deSXingyu Wu .mode = JH7110_PLL_MODE_INTEGER,
243*616bc1deSXingyu Wu },
244*616bc1deSXingyu Wu };
245*616bc1deSXingyu Wu
246*616bc1deSXingyu Wu static const struct jh7110_pll_preset jh7110_pll2_presets[] = {
247*616bc1deSXingyu Wu {
248*616bc1deSXingyu Wu .freq = 1188000000,
249*616bc1deSXingyu Wu .fbdiv = 99,
250*616bc1deSXingyu Wu .prediv = 2,
251*616bc1deSXingyu Wu .postdiv1 = 0,
252*616bc1deSXingyu Wu .mode = JH7110_PLL_MODE_INTEGER,
253*616bc1deSXingyu Wu }, {
254*616bc1deSXingyu Wu .freq = 1228800000,
255*616bc1deSXingyu Wu .fbdiv = 256,
256*616bc1deSXingyu Wu .prediv = 5,
257*616bc1deSXingyu Wu .postdiv1 = 0,
258*616bc1deSXingyu Wu .mode = JH7110_PLL_MODE_INTEGER,
259*616bc1deSXingyu Wu },
260*616bc1deSXingyu Wu };
261*616bc1deSXingyu Wu
262*616bc1deSXingyu Wu static const struct jh7110_pll_info jh7110_plls[JH7110_PLLCLK_END] = {
263*616bc1deSXingyu Wu JH7110_PLL(JH7110_PLLCLK_PLL0_OUT, "pll0_out", jh7110_pll0_presets),
264*616bc1deSXingyu Wu JH7110_PLL(JH7110_PLLCLK_PLL1_OUT, "pll1_out", jh7110_pll1_presets),
265*616bc1deSXingyu Wu JH7110_PLL(JH7110_PLLCLK_PLL2_OUT, "pll2_out", jh7110_pll2_presets),
266*616bc1deSXingyu Wu };
267*616bc1deSXingyu Wu
jh7110_pll_data_from(struct clk_hw * hw)268*616bc1deSXingyu Wu static struct jh7110_pll_data *jh7110_pll_data_from(struct clk_hw *hw)
269*616bc1deSXingyu Wu {
270*616bc1deSXingyu Wu return container_of(hw, struct jh7110_pll_data, hw);
271*616bc1deSXingyu Wu }
272*616bc1deSXingyu Wu
jh7110_pll_priv_from(struct jh7110_pll_data * pll)273*616bc1deSXingyu Wu static struct jh7110_pll_priv *jh7110_pll_priv_from(struct jh7110_pll_data *pll)
274*616bc1deSXingyu Wu {
275*616bc1deSXingyu Wu return container_of(pll, struct jh7110_pll_priv, pll[pll->idx]);
276*616bc1deSXingyu Wu }
277*616bc1deSXingyu Wu
jh7110_pll_regvals_get(struct regmap * regmap,const struct jh7110_pll_info * info,struct jh7110_pll_regvals * ret)278*616bc1deSXingyu Wu static void jh7110_pll_regvals_get(struct regmap *regmap,
279*616bc1deSXingyu Wu const struct jh7110_pll_info *info,
280*616bc1deSXingyu Wu struct jh7110_pll_regvals *ret)
281*616bc1deSXingyu Wu {
282*616bc1deSXingyu Wu u32 val;
283*616bc1deSXingyu Wu
284*616bc1deSXingyu Wu regmap_read(regmap, info->offsets.pd, &val);
285*616bc1deSXingyu Wu ret->dacpd = (val & info->masks.dacpd) >> info->shifts.dacpd;
286*616bc1deSXingyu Wu ret->dsmpd = (val & info->masks.dsmpd) >> info->shifts.dsmpd;
287*616bc1deSXingyu Wu
288*616bc1deSXingyu Wu regmap_read(regmap, info->offsets.fbdiv, &val);
289*616bc1deSXingyu Wu ret->fbdiv = (val & info->masks.fbdiv) >> info->shifts.fbdiv;
290*616bc1deSXingyu Wu
291*616bc1deSXingyu Wu regmap_read(regmap, info->offsets.frac, &val);
292*616bc1deSXingyu Wu ret->frac = (val & JH7110_PLL_FRAC_MASK) >> JH7110_PLL_FRAC_SHIFT;
293*616bc1deSXingyu Wu ret->postdiv1 = (val & JH7110_PLL_POSTDIV1_MASK) >> JH7110_PLL_POSTDIV1_SHIFT;
294*616bc1deSXingyu Wu
295*616bc1deSXingyu Wu regmap_read(regmap, info->offsets.prediv, &val);
296*616bc1deSXingyu Wu ret->prediv = (val & JH7110_PLL_PREDIV_MASK) >> JH7110_PLL_PREDIV_SHIFT;
297*616bc1deSXingyu Wu }
298*616bc1deSXingyu Wu
jh7110_pll_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)299*616bc1deSXingyu Wu static unsigned long jh7110_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
300*616bc1deSXingyu Wu {
301*616bc1deSXingyu Wu struct jh7110_pll_data *pll = jh7110_pll_data_from(hw);
302*616bc1deSXingyu Wu struct jh7110_pll_priv *priv = jh7110_pll_priv_from(pll);
303*616bc1deSXingyu Wu struct jh7110_pll_regvals val;
304*616bc1deSXingyu Wu unsigned long rate;
305*616bc1deSXingyu Wu
306*616bc1deSXingyu Wu jh7110_pll_regvals_get(priv->regmap, &jh7110_plls[pll->idx], &val);
307*616bc1deSXingyu Wu
308*616bc1deSXingyu Wu /*
309*616bc1deSXingyu Wu * dacpd = dsmpd = 0: fraction mode
310*616bc1deSXingyu Wu * dacpd = dsmpd = 1: integer mode, frac value ignored
311*616bc1deSXingyu Wu *
312*616bc1deSXingyu Wu * rate = parent * (fbdiv + frac/2^24) / prediv / 2^postdiv1
313*616bc1deSXingyu Wu * = (parent * fbdiv + parent * frac / 2^24) / (prediv * 2^postdiv1)
314*616bc1deSXingyu Wu */
315*616bc1deSXingyu Wu if (val.dacpd == 0 && val.dsmpd == 0)
316*616bc1deSXingyu Wu rate = parent_rate * val.frac / (1UL << 24);
317*616bc1deSXingyu Wu else if (val.dacpd == 1 && val.dsmpd == 1)
318*616bc1deSXingyu Wu rate = 0;
319*616bc1deSXingyu Wu else
320*616bc1deSXingyu Wu return 0;
321*616bc1deSXingyu Wu
322*616bc1deSXingyu Wu rate += parent_rate * val.fbdiv;
323*616bc1deSXingyu Wu rate /= val.prediv << val.postdiv1;
324*616bc1deSXingyu Wu
325*616bc1deSXingyu Wu return rate;
326*616bc1deSXingyu Wu }
327*616bc1deSXingyu Wu
jh7110_pll_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)328*616bc1deSXingyu Wu static int jh7110_pll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
329*616bc1deSXingyu Wu {
330*616bc1deSXingyu Wu struct jh7110_pll_data *pll = jh7110_pll_data_from(hw);
331*616bc1deSXingyu Wu const struct jh7110_pll_info *info = &jh7110_plls[pll->idx];
332*616bc1deSXingyu Wu const struct jh7110_pll_preset *selected = &info->presets[0];
333*616bc1deSXingyu Wu unsigned int idx;
334*616bc1deSXingyu Wu
335*616bc1deSXingyu Wu /* if the parent rate doesn't match our expectations the presets won't work */
336*616bc1deSXingyu Wu if (req->best_parent_rate != JH7110_PLL_OSC_RATE) {
337*616bc1deSXingyu Wu req->rate = jh7110_pll_recalc_rate(hw, req->best_parent_rate);
338*616bc1deSXingyu Wu return 0;
339*616bc1deSXingyu Wu }
340*616bc1deSXingyu Wu
341*616bc1deSXingyu Wu /* find highest rate lower or equal to the requested rate */
342*616bc1deSXingyu Wu for (idx = 1; idx < info->npresets; idx++) {
343*616bc1deSXingyu Wu const struct jh7110_pll_preset *val = &info->presets[idx];
344*616bc1deSXingyu Wu
345*616bc1deSXingyu Wu if (req->rate < val->freq)
346*616bc1deSXingyu Wu break;
347*616bc1deSXingyu Wu
348*616bc1deSXingyu Wu selected = val;
349*616bc1deSXingyu Wu }
350*616bc1deSXingyu Wu
351*616bc1deSXingyu Wu req->rate = selected->freq;
352*616bc1deSXingyu Wu return 0;
353*616bc1deSXingyu Wu }
354*616bc1deSXingyu Wu
jh7110_pll_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)355*616bc1deSXingyu Wu static int jh7110_pll_set_rate(struct clk_hw *hw, unsigned long rate,
356*616bc1deSXingyu Wu unsigned long parent_rate)
357*616bc1deSXingyu Wu {
358*616bc1deSXingyu Wu struct jh7110_pll_data *pll = jh7110_pll_data_from(hw);
359*616bc1deSXingyu Wu struct jh7110_pll_priv *priv = jh7110_pll_priv_from(pll);
360*616bc1deSXingyu Wu const struct jh7110_pll_info *info = &jh7110_plls[pll->idx];
361*616bc1deSXingyu Wu const struct jh7110_pll_preset *val;
362*616bc1deSXingyu Wu unsigned int idx;
363*616bc1deSXingyu Wu
364*616bc1deSXingyu Wu /* if the parent rate doesn't match our expectations the presets won't work */
365*616bc1deSXingyu Wu if (parent_rate != JH7110_PLL_OSC_RATE)
366*616bc1deSXingyu Wu return -EINVAL;
367*616bc1deSXingyu Wu
368*616bc1deSXingyu Wu for (idx = 0, val = &info->presets[0]; idx < info->npresets; idx++, val++) {
369*616bc1deSXingyu Wu if (val->freq == rate)
370*616bc1deSXingyu Wu goto found;
371*616bc1deSXingyu Wu }
372*616bc1deSXingyu Wu return -EINVAL;
373*616bc1deSXingyu Wu
374*616bc1deSXingyu Wu found:
375*616bc1deSXingyu Wu if (val->mode == JH7110_PLL_MODE_FRACTION)
376*616bc1deSXingyu Wu regmap_update_bits(priv->regmap, info->offsets.frac, JH7110_PLL_FRAC_MASK,
377*616bc1deSXingyu Wu val->frac << JH7110_PLL_FRAC_SHIFT);
378*616bc1deSXingyu Wu
379*616bc1deSXingyu Wu regmap_update_bits(priv->regmap, info->offsets.pd, info->masks.dacpd,
380*616bc1deSXingyu Wu (u32)val->mode << info->shifts.dacpd);
381*616bc1deSXingyu Wu regmap_update_bits(priv->regmap, info->offsets.pd, info->masks.dsmpd,
382*616bc1deSXingyu Wu (u32)val->mode << info->shifts.dsmpd);
383*616bc1deSXingyu Wu regmap_update_bits(priv->regmap, info->offsets.prediv, JH7110_PLL_PREDIV_MASK,
384*616bc1deSXingyu Wu (u32)val->prediv << JH7110_PLL_PREDIV_SHIFT);
385*616bc1deSXingyu Wu regmap_update_bits(priv->regmap, info->offsets.fbdiv, info->masks.fbdiv,
386*616bc1deSXingyu Wu val->fbdiv << info->shifts.fbdiv);
387*616bc1deSXingyu Wu regmap_update_bits(priv->regmap, info->offsets.frac, JH7110_PLL_POSTDIV1_MASK,
388*616bc1deSXingyu Wu (u32)val->postdiv1 << JH7110_PLL_POSTDIV1_SHIFT);
389*616bc1deSXingyu Wu
390*616bc1deSXingyu Wu return 0;
391*616bc1deSXingyu Wu }
392*616bc1deSXingyu Wu
393*616bc1deSXingyu Wu #ifdef CONFIG_DEBUG_FS
jh7110_pll_registers_read(struct seq_file * s,void * unused)394*616bc1deSXingyu Wu static int jh7110_pll_registers_read(struct seq_file *s, void *unused)
395*616bc1deSXingyu Wu {
396*616bc1deSXingyu Wu struct jh7110_pll_data *pll = s->private;
397*616bc1deSXingyu Wu struct jh7110_pll_priv *priv = jh7110_pll_priv_from(pll);
398*616bc1deSXingyu Wu struct jh7110_pll_regvals val;
399*616bc1deSXingyu Wu
400*616bc1deSXingyu Wu jh7110_pll_regvals_get(priv->regmap, &jh7110_plls[pll->idx], &val);
401*616bc1deSXingyu Wu
402*616bc1deSXingyu Wu seq_printf(s, "fbdiv=%u\n"
403*616bc1deSXingyu Wu "frac=%u\n"
404*616bc1deSXingyu Wu "prediv=%u\n"
405*616bc1deSXingyu Wu "postdiv1=%u\n"
406*616bc1deSXingyu Wu "dacpd=%u\n"
407*616bc1deSXingyu Wu "dsmpd=%u\n",
408*616bc1deSXingyu Wu val.fbdiv, val.frac, val.prediv, val.postdiv1,
409*616bc1deSXingyu Wu val.dacpd, val.dsmpd);
410*616bc1deSXingyu Wu
411*616bc1deSXingyu Wu return 0;
412*616bc1deSXingyu Wu }
413*616bc1deSXingyu Wu
jh7110_pll_registers_open(struct inode * inode,struct file * f)414*616bc1deSXingyu Wu static int jh7110_pll_registers_open(struct inode *inode, struct file *f)
415*616bc1deSXingyu Wu {
416*616bc1deSXingyu Wu return single_open(f, jh7110_pll_registers_read, inode->i_private);
417*616bc1deSXingyu Wu }
418*616bc1deSXingyu Wu
419*616bc1deSXingyu Wu static const struct file_operations jh7110_pll_registers_ops = {
420*616bc1deSXingyu Wu .owner = THIS_MODULE,
421*616bc1deSXingyu Wu .open = jh7110_pll_registers_open,
422*616bc1deSXingyu Wu .release = single_release,
423*616bc1deSXingyu Wu .read = seq_read,
424*616bc1deSXingyu Wu .llseek = seq_lseek
425*616bc1deSXingyu Wu };
426*616bc1deSXingyu Wu
jh7110_pll_debug_init(struct clk_hw * hw,struct dentry * dentry)427*616bc1deSXingyu Wu static void jh7110_pll_debug_init(struct clk_hw *hw, struct dentry *dentry)
428*616bc1deSXingyu Wu {
429*616bc1deSXingyu Wu struct jh7110_pll_data *pll = jh7110_pll_data_from(hw);
430*616bc1deSXingyu Wu
431*616bc1deSXingyu Wu debugfs_create_file("registers", 0400, dentry, pll,
432*616bc1deSXingyu Wu &jh7110_pll_registers_ops);
433*616bc1deSXingyu Wu }
434*616bc1deSXingyu Wu #else
435*616bc1deSXingyu Wu #define jh7110_pll_debug_init NULL
436*616bc1deSXingyu Wu #endif
437*616bc1deSXingyu Wu
438*616bc1deSXingyu Wu static const struct clk_ops jh7110_pll_ops = {
439*616bc1deSXingyu Wu .recalc_rate = jh7110_pll_recalc_rate,
440*616bc1deSXingyu Wu .determine_rate = jh7110_pll_determine_rate,
441*616bc1deSXingyu Wu .set_rate = jh7110_pll_set_rate,
442*616bc1deSXingyu Wu .debug_init = jh7110_pll_debug_init,
443*616bc1deSXingyu Wu };
444*616bc1deSXingyu Wu
jh7110_pll_get(struct of_phandle_args * clkspec,void * data)445*616bc1deSXingyu Wu static struct clk_hw *jh7110_pll_get(struct of_phandle_args *clkspec, void *data)
446*616bc1deSXingyu Wu {
447*616bc1deSXingyu Wu struct jh7110_pll_priv *priv = data;
448*616bc1deSXingyu Wu unsigned int idx = clkspec->args[0];
449*616bc1deSXingyu Wu
450*616bc1deSXingyu Wu if (idx < JH7110_PLLCLK_END)
451*616bc1deSXingyu Wu return &priv->pll[idx].hw;
452*616bc1deSXingyu Wu
453*616bc1deSXingyu Wu return ERR_PTR(-EINVAL);
454*616bc1deSXingyu Wu }
455*616bc1deSXingyu Wu
jh7110_pll_probe(struct platform_device * pdev)456*616bc1deSXingyu Wu static int jh7110_pll_probe(struct platform_device *pdev)
457*616bc1deSXingyu Wu {
458*616bc1deSXingyu Wu struct jh7110_pll_priv *priv;
459*616bc1deSXingyu Wu unsigned int idx;
460*616bc1deSXingyu Wu int ret;
461*616bc1deSXingyu Wu
462*616bc1deSXingyu Wu priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
463*616bc1deSXingyu Wu if (!priv)
464*616bc1deSXingyu Wu return -ENOMEM;
465*616bc1deSXingyu Wu
466*616bc1deSXingyu Wu priv->dev = &pdev->dev;
467*616bc1deSXingyu Wu priv->regmap = syscon_node_to_regmap(priv->dev->of_node->parent);
468*616bc1deSXingyu Wu if (IS_ERR(priv->regmap))
469*616bc1deSXingyu Wu return PTR_ERR(priv->regmap);
470*616bc1deSXingyu Wu
471*616bc1deSXingyu Wu for (idx = 0; idx < JH7110_PLLCLK_END; idx++) {
472*616bc1deSXingyu Wu struct clk_parent_data parents = {
473*616bc1deSXingyu Wu .index = 0,
474*616bc1deSXingyu Wu };
475*616bc1deSXingyu Wu struct clk_init_data init = {
476*616bc1deSXingyu Wu .name = jh7110_plls[idx].name,
477*616bc1deSXingyu Wu .ops = &jh7110_pll_ops,
478*616bc1deSXingyu Wu .parent_data = &parents,
479*616bc1deSXingyu Wu .num_parents = 1,
480*616bc1deSXingyu Wu .flags = 0,
481*616bc1deSXingyu Wu };
482*616bc1deSXingyu Wu struct jh7110_pll_data *pll = &priv->pll[idx];
483*616bc1deSXingyu Wu
484*616bc1deSXingyu Wu pll->hw.init = &init;
485*616bc1deSXingyu Wu pll->idx = idx;
486*616bc1deSXingyu Wu
487*616bc1deSXingyu Wu ret = devm_clk_hw_register(&pdev->dev, &pll->hw);
488*616bc1deSXingyu Wu if (ret)
489*616bc1deSXingyu Wu return ret;
490*616bc1deSXingyu Wu }
491*616bc1deSXingyu Wu
492*616bc1deSXingyu Wu return devm_of_clk_add_hw_provider(&pdev->dev, jh7110_pll_get, priv);
493*616bc1deSXingyu Wu }
494*616bc1deSXingyu Wu
495*616bc1deSXingyu Wu static const struct of_device_id jh7110_pll_match[] = {
496*616bc1deSXingyu Wu { .compatible = "starfive,jh7110-pll" },
497*616bc1deSXingyu Wu { /* sentinel */ }
498*616bc1deSXingyu Wu };
499*616bc1deSXingyu Wu MODULE_DEVICE_TABLE(of, jh7110_pll_match);
500*616bc1deSXingyu Wu
501*616bc1deSXingyu Wu static struct platform_driver jh7110_pll_driver = {
502*616bc1deSXingyu Wu .driver = {
503*616bc1deSXingyu Wu .name = "clk-starfive-jh7110-pll",
504*616bc1deSXingyu Wu .of_match_table = jh7110_pll_match,
505*616bc1deSXingyu Wu },
506*616bc1deSXingyu Wu };
507*616bc1deSXingyu Wu builtin_platform_driver_probe(jh7110_pll_driver, jh7110_pll_probe);
508