1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.io> 4 * 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/of_address.h> 9 10 #include "ccu_common.h" 11 #include "ccu_reset.h" 12 13 #include "ccu_div.h" 14 #include "ccu_gate.h" 15 #include "ccu_mp.h" 16 #include "ccu_mult.h" 17 #include "ccu_nk.h" 18 #include "ccu_nkm.h" 19 #include "ccu_nkmp.h" 20 #include "ccu_nm.h" 21 #include "ccu_phase.h" 22 23 #include "ccu-suniv-f1c100s.h" 24 25 static struct ccu_nkmp pll_cpu_clk = { 26 .enable = BIT(31), 27 .lock = BIT(28), 28 29 .n = _SUNXI_CCU_MULT(8, 5), 30 .k = _SUNXI_CCU_MULT(4, 2), 31 .m = _SUNXI_CCU_DIV(0, 2), 32 /* MAX is guessed by the BSP table */ 33 .p = _SUNXI_CCU_DIV_MAX(16, 2, 4), 34 35 .common = { 36 .reg = 0x000, 37 .hw.init = CLK_HW_INIT("pll-cpu", "osc24M", 38 &ccu_nkmp_ops, 39 CLK_SET_RATE_UNGATE), 40 }, 41 }; 42 43 /* 44 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from 45 * the base (2x, 4x and 8x), and one variable divider (the one true 46 * pll audio). 47 * 48 * We don't have any need for the variable divider for now, so we just 49 * hardcode it to match with the clock names 50 */ 51 #define SUNIV_PLL_AUDIO_REG 0x008 52 53 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", 54 "osc24M", 0x008, 55 8, 7, /* N */ 56 0, 5, /* M */ 57 BIT(31), /* gate */ 58 BIT(28), /* lock */ 59 CLK_SET_RATE_UNGATE); 60 61 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video", 62 "osc24M", 0x010, 63 8, 7, /* N */ 64 0, 4, /* M */ 65 BIT(24), /* frac enable */ 66 BIT(25), /* frac select */ 67 270000000, /* frac rate 0 */ 68 297000000, /* frac rate 1 */ 69 BIT(31), /* gate */ 70 BIT(28), /* lock */ 71 CLK_SET_RATE_UNGATE); 72 73 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve", 74 "osc24M", 0x018, 75 8, 7, /* N */ 76 0, 4, /* M */ 77 BIT(24), /* frac enable */ 78 BIT(25), /* frac select */ 79 270000000, /* frac rate 0 */ 80 297000000, /* frac rate 1 */ 81 BIT(31), /* gate */ 82 BIT(28), /* lock */ 83 CLK_SET_RATE_UNGATE); 84 85 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr", 86 "osc24M", 0x020, 87 8, 5, /* N */ 88 4, 2, /* K */ 89 0, 2, /* M */ 90 BIT(31), /* gate */ 91 BIT(28), /* lock */ 92 CLK_IS_CRITICAL); 93 94 static struct ccu_nk pll_periph_clk = { 95 .enable = BIT(31), 96 .lock = BIT(28), 97 .k = _SUNXI_CCU_MULT(4, 2), 98 .n = _SUNXI_CCU_MULT(8, 5), 99 .common = { 100 .reg = 0x028, 101 .hw.init = CLK_HW_INIT("pll-periph", "osc24M", 102 &ccu_nk_ops, 0), 103 }, 104 }; 105 106 static const char * const cpu_parents[] = { "osc32k", "osc24M", 107 "pll-cpu", "pll-cpu" }; 108 static SUNXI_CCU_MUX(cpu_clk, "cpu", cpu_parents, 109 0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT); 110 111 static const char * const ahb_parents[] = { "osc32k", "osc24M", 112 "cpu", "pll-periph" }; 113 static const struct ccu_mux_var_prediv ahb_predivs[] = { 114 { .index = 3, .shift = 6, .width = 2 }, 115 }; 116 static struct ccu_div ahb_clk = { 117 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO), 118 119 .mux = { 120 .shift = 12, 121 .width = 2, 122 123 .var_predivs = ahb_predivs, 124 .n_var_predivs = ARRAY_SIZE(ahb_predivs), 125 }, 126 127 .common = { 128 .reg = 0x054, 129 .features = CCU_FEATURE_VARIABLE_PREDIV, 130 .hw.init = CLK_HW_INIT_PARENTS("ahb", 131 ahb_parents, 132 &ccu_div_ops, 133 0), 134 }, 135 }; 136 137 static struct clk_div_table apb_div_table[] = { 138 { .val = 0, .div = 2 }, 139 { .val = 1, .div = 2 }, 140 { .val = 2, .div = 4 }, 141 { .val = 3, .div = 8 }, 142 { /* Sentinel */ }, 143 }; 144 static SUNXI_CCU_DIV_TABLE(apb_clk, "apb", "ahb", 145 0x054, 8, 2, apb_div_table, 0); 146 147 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb", 148 0x060, BIT(6), 0); 149 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb", 150 0x060, BIT(8), 0); 151 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb", 152 0x060, BIT(9), 0); 153 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb", 154 0x060, BIT(14), 0); 155 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb", 156 0x060, BIT(20), 0); 157 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb", 158 0x060, BIT(21), 0); 159 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb", 160 0x060, BIT(24), 0); 161 162 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb", 163 0x064, BIT(0), 0); 164 static SUNXI_CCU_GATE(bus_lcd_clk, "bus-lcd", "ahb", 165 0x064, BIT(4), 0); 166 static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "ahb", 167 0x064, BIT(5), 0); 168 static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb", 169 0x064, BIT(8), 0); 170 static SUNXI_CCU_GATE(bus_tvd_clk, "bus-tvd", "ahb", 171 0x064, BIT(9), 0); 172 static SUNXI_CCU_GATE(bus_tve_clk, "bus-tve", "ahb", 173 0x064, BIT(10), 0); 174 static SUNXI_CCU_GATE(bus_de_be_clk, "bus-de-be", "ahb", 175 0x064, BIT(12), 0); 176 static SUNXI_CCU_GATE(bus_de_fe_clk, "bus-de-fe", "ahb", 177 0x064, BIT(14), 0); 178 179 static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb", 180 0x068, BIT(0), 0); 181 static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb", 182 0x068, BIT(1), 0); 183 static SUNXI_CCU_GATE(bus_ir_clk, "bus-ir", "apb", 184 0x068, BIT(2), 0); 185 static SUNXI_CCU_GATE(bus_rsb_clk, "bus-rsb", "apb", 186 0x068, BIT(3), 0); 187 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb", 188 0x068, BIT(12), 0); 189 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb", 190 0x068, BIT(16), 0); 191 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb", 192 0x068, BIT(17), 0); 193 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb", 194 0x068, BIT(18), 0); 195 static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb", 196 0x068, BIT(19), 0); 197 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb", 198 0x068, BIT(20), 0); 199 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb", 200 0x068, BIT(21), 0); 201 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb", 202 0x068, BIT(22), 0); 203 204 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" }; 205 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088, 206 0, 4, /* M */ 207 16, 2, /* P */ 208 24, 2, /* mux */ 209 BIT(31), /* gate */ 210 0); 211 212 static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0", 213 0x088, 20, 3, 0); 214 static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0", 215 0x088, 8, 3, 0); 216 217 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c, 218 0, 4, /* M */ 219 16, 2, /* P */ 220 24, 2, /* mux */ 221 BIT(31), /* gate */ 222 0); 223 224 static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1", 225 0x08c, 20, 3, 0); 226 static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1", 227 0x08c, 8, 3, 0); 228 229 static const char * const i2s_spdif_parents[] = { "pll-audio-8x", 230 "pll-audio-4x", 231 "pll-audio-2x", 232 "pll-audio" }; 233 234 static SUNXI_CCU_MUX_WITH_GATE(i2s_clk, "i2s", i2s_spdif_parents, 235 0x0b0, 16, 2, BIT(31), 0); 236 237 static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", i2s_spdif_parents, 238 0x0b4, 16, 2, BIT(31), 0); 239 240 /* The BSP header file has a CIR_CFG, but no mod clock uses this definition */ 241 242 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M", 243 0x0cc, BIT(1), 0); 244 245 static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "pll-ddr", 246 0x100, BIT(0), 0); 247 static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "pll-ddr", 248 0x100, BIT(1), 0); 249 static SUNXI_CCU_GATE(dram_deinterlace_clk, "dram-deinterlace", 250 "pll-ddr", 0x100, BIT(2), 0); 251 static SUNXI_CCU_GATE(dram_tvd_clk, "dram-tvd", "pll-ddr", 252 0x100, BIT(3), 0); 253 static SUNXI_CCU_GATE(dram_de_fe_clk, "dram-de-fe", "pll-ddr", 254 0x100, BIT(24), 0); 255 static SUNXI_CCU_GATE(dram_de_be_clk, "dram-de-be", "pll-ddr", 256 0x100, BIT(26), 0); 257 258 static const char * const de_parents[] = { "pll-video", "pll-periph" }; 259 static const u8 de_table[] = { 0, 2, }; 260 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_be_clk, "de-be", 261 de_parents, de_table, 262 0x104, 0, 4, 24, 3, BIT(31), 0); 263 264 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_fe_clk, "de-fe", 265 de_parents, de_table, 266 0x10c, 0, 4, 24, 3, BIT(31), 0); 267 268 static const char * const tcon_parents[] = { "pll-video", "pll-video-2x" }; 269 static const u8 tcon_table[] = { 0, 2, }; 270 static SUNXI_CCU_MUX_TABLE_WITH_GATE(tcon_clk, "tcon", 271 tcon_parents, tcon_table, 272 0x118, 24, 3, BIT(31), 273 CLK_SET_RATE_PARENT); 274 275 static const char * const deinterlace_parents[] = { "pll-video", 276 "pll-video-2x" }; 277 static const u8 deinterlace_table[] = { 0, 2, }; 278 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(deinterlace_clk, "deinterlace", 279 deinterlace_parents, deinterlace_table, 280 0x11c, 0, 4, 24, 3, BIT(31), 0); 281 282 static const char * const tve_clk2_parents[] = { "pll-video", 283 "pll-video-2x" }; 284 static const u8 tve_clk2_table[] = { 0, 2, }; 285 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(tve_clk2_clk, "tve-clk2", 286 tve_clk2_parents, tve_clk2_table, 287 0x120, 0, 4, 24, 3, BIT(31), 0); 288 static SUNXI_CCU_M_WITH_GATE(tve_clk1_clk, "tve-clk1", "tve-clk2", 289 0x120, 8, 1, BIT(15), 0); 290 291 static const char * const tvd_parents[] = { "pll-video", "osc24M", 292 "pll-video-2x" }; 293 static SUNXI_CCU_M_WITH_MUX_GATE(tvd_clk, "tvd", tvd_parents, 294 0x124, 0, 4, 24, 3, BIT(31), 0); 295 296 static const char * const csi_parents[] = { "pll-video", "osc24M" }; 297 static const u8 csi_table[] = { 0, 5, }; 298 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_clk, "csi", csi_parents, csi_table, 299 0x120, 0, 4, 8, 3, BIT(15), 0); 300 301 /* 302 * TODO: BSP says the parent is pll-audio, however common sense and experience 303 * told us it should be pll-ve. pll-ve is totally not used in BSP code. 304 */ 305 static SUNXI_CCU_GATE(ve_clk, "ve", "pll-audio", 0x13c, BIT(31), 0); 306 307 static SUNXI_CCU_GATE(codec_clk, "codec", "pll-audio", 0x140, BIT(31), 0); 308 309 static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 0x144, BIT(31), 0); 310 311 static struct ccu_common *suniv_ccu_clks[] = { 312 &pll_cpu_clk.common, 313 &pll_audio_base_clk.common, 314 &pll_video_clk.common, 315 &pll_ve_clk.common, 316 &pll_ddr0_clk.common, 317 &pll_periph_clk.common, 318 &cpu_clk.common, 319 &ahb_clk.common, 320 &apb_clk.common, 321 &bus_dma_clk.common, 322 &bus_mmc0_clk.common, 323 &bus_mmc1_clk.common, 324 &bus_dram_clk.common, 325 &bus_spi0_clk.common, 326 &bus_spi1_clk.common, 327 &bus_otg_clk.common, 328 &bus_ve_clk.common, 329 &bus_lcd_clk.common, 330 &bus_deinterlace_clk.common, 331 &bus_csi_clk.common, 332 &bus_tve_clk.common, 333 &bus_tvd_clk.common, 334 &bus_de_be_clk.common, 335 &bus_de_fe_clk.common, 336 &bus_codec_clk.common, 337 &bus_spdif_clk.common, 338 &bus_ir_clk.common, 339 &bus_rsb_clk.common, 340 &bus_i2s0_clk.common, 341 &bus_i2c0_clk.common, 342 &bus_i2c1_clk.common, 343 &bus_i2c2_clk.common, 344 &bus_pio_clk.common, 345 &bus_uart0_clk.common, 346 &bus_uart1_clk.common, 347 &bus_uart2_clk.common, 348 &mmc0_clk.common, 349 &mmc0_sample_clk.common, 350 &mmc0_output_clk.common, 351 &mmc1_clk.common, 352 &mmc1_sample_clk.common, 353 &mmc1_output_clk.common, 354 &i2s_clk.common, 355 &spdif_clk.common, 356 &usb_phy0_clk.common, 357 &dram_ve_clk.common, 358 &dram_csi_clk.common, 359 &dram_deinterlace_clk.common, 360 &dram_tvd_clk.common, 361 &dram_de_fe_clk.common, 362 &dram_de_be_clk.common, 363 &de_be_clk.common, 364 &de_fe_clk.common, 365 &tcon_clk.common, 366 &deinterlace_clk.common, 367 &tve_clk2_clk.common, 368 &tve_clk1_clk.common, 369 &tvd_clk.common, 370 &csi_clk.common, 371 &ve_clk.common, 372 &codec_clk.common, 373 &avs_clk.common, 374 }; 375 376 static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio", 377 "pll-audio-base", 4, 1, CLK_SET_RATE_PARENT); 378 static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x", 379 "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT); 380 static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x", 381 "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT); 382 static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x", 383 "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT); 384 static CLK_FIXED_FACTOR(pll_video_2x_clk, "pll-video-2x", 385 "pll-video", 1, 2, 0); 386 387 static struct clk_hw_onecell_data suniv_hw_clks = { 388 .hws = { 389 [CLK_PLL_CPU] = &pll_cpu_clk.common.hw, 390 [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw, 391 [CLK_PLL_AUDIO] = &pll_audio_clk.hw, 392 [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw, 393 [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw, 394 [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw, 395 [CLK_PLL_VIDEO] = &pll_video_clk.common.hw, 396 [CLK_PLL_VIDEO_2X] = &pll_video_2x_clk.hw, 397 [CLK_PLL_VE] = &pll_ve_clk.common.hw, 398 [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw, 399 [CLK_PLL_PERIPH] = &pll_periph_clk.common.hw, 400 [CLK_CPU] = &cpu_clk.common.hw, 401 [CLK_AHB] = &ahb_clk.common.hw, 402 [CLK_APB] = &apb_clk.common.hw, 403 [CLK_BUS_DMA] = &bus_dma_clk.common.hw, 404 [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw, 405 [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw, 406 [CLK_BUS_DRAM] = &bus_dram_clk.common.hw, 407 [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw, 408 [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw, 409 [CLK_BUS_OTG] = &bus_otg_clk.common.hw, 410 [CLK_BUS_VE] = &bus_ve_clk.common.hw, 411 [CLK_BUS_LCD] = &bus_lcd_clk.common.hw, 412 [CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw, 413 [CLK_BUS_CSI] = &bus_csi_clk.common.hw, 414 [CLK_BUS_TVD] = &bus_tvd_clk.common.hw, 415 [CLK_BUS_TVE] = &bus_tve_clk.common.hw, 416 [CLK_BUS_DE_BE] = &bus_de_be_clk.common.hw, 417 [CLK_BUS_DE_FE] = &bus_de_fe_clk.common.hw, 418 [CLK_BUS_CODEC] = &bus_codec_clk.common.hw, 419 [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw, 420 [CLK_BUS_IR] = &bus_ir_clk.common.hw, 421 [CLK_BUS_RSB] = &bus_rsb_clk.common.hw, 422 [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw, 423 [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw, 424 [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw, 425 [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw, 426 [CLK_BUS_PIO] = &bus_pio_clk.common.hw, 427 [CLK_BUS_UART0] = &bus_uart0_clk.common.hw, 428 [CLK_BUS_UART1] = &bus_uart1_clk.common.hw, 429 [CLK_BUS_UART2] = &bus_uart2_clk.common.hw, 430 [CLK_MMC0] = &mmc0_clk.common.hw, 431 [CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw, 432 [CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw, 433 [CLK_MMC1] = &mmc1_clk.common.hw, 434 [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw, 435 [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw, 436 [CLK_I2S] = &i2s_clk.common.hw, 437 [CLK_SPDIF] = &spdif_clk.common.hw, 438 [CLK_USB_PHY0] = &usb_phy0_clk.common.hw, 439 [CLK_DRAM_VE] = &dram_ve_clk.common.hw, 440 [CLK_DRAM_CSI] = &dram_csi_clk.common.hw, 441 [CLK_DRAM_DEINTERLACE] = &dram_deinterlace_clk.common.hw, 442 [CLK_DRAM_TVD] = &dram_tvd_clk.common.hw, 443 [CLK_DRAM_DE_FE] = &dram_de_fe_clk.common.hw, 444 [CLK_DRAM_DE_BE] = &dram_de_be_clk.common.hw, 445 [CLK_DE_BE] = &de_be_clk.common.hw, 446 [CLK_DE_FE] = &de_fe_clk.common.hw, 447 [CLK_TCON] = &tcon_clk.common.hw, 448 [CLK_DEINTERLACE] = &deinterlace_clk.common.hw, 449 [CLK_TVE2_CLK] = &tve_clk2_clk.common.hw, 450 [CLK_TVE1_CLK] = &tve_clk1_clk.common.hw, 451 [CLK_TVD] = &tvd_clk.common.hw, 452 [CLK_CSI] = &csi_clk.common.hw, 453 [CLK_VE] = &ve_clk.common.hw, 454 [CLK_CODEC] = &codec_clk.common.hw, 455 [CLK_AVS] = &avs_clk.common.hw, 456 }, 457 .num = CLK_NUMBER, 458 }; 459 460 static struct ccu_reset_map suniv_ccu_resets[] = { 461 [RST_USB_PHY0] = { 0x0cc, BIT(0) }, 462 463 [RST_BUS_DMA] = { 0x2c0, BIT(6) }, 464 [RST_BUS_MMC0] = { 0x2c0, BIT(8) }, 465 [RST_BUS_MMC1] = { 0x2c0, BIT(9) }, 466 [RST_BUS_DRAM] = { 0x2c0, BIT(14) }, 467 [RST_BUS_SPI0] = { 0x2c0, BIT(20) }, 468 [RST_BUS_SPI1] = { 0x2c0, BIT(21) }, 469 [RST_BUS_OTG] = { 0x2c0, BIT(24) }, 470 [RST_BUS_VE] = { 0x2c4, BIT(0) }, 471 [RST_BUS_LCD] = { 0x2c4, BIT(4) }, 472 [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) }, 473 [RST_BUS_CSI] = { 0x2c4, BIT(8) }, 474 [RST_BUS_TVD] = { 0x2c4, BIT(9) }, 475 [RST_BUS_TVE] = { 0x2c4, BIT(10) }, 476 [RST_BUS_DE_BE] = { 0x2c4, BIT(12) }, 477 [RST_BUS_DE_FE] = { 0x2c4, BIT(14) }, 478 [RST_BUS_CODEC] = { 0x2d0, BIT(0) }, 479 [RST_BUS_SPDIF] = { 0x2d0, BIT(1) }, 480 [RST_BUS_IR] = { 0x2d0, BIT(2) }, 481 [RST_BUS_RSB] = { 0x2d0, BIT(3) }, 482 [RST_BUS_I2S0] = { 0x2d0, BIT(12) }, 483 [RST_BUS_I2C0] = { 0x2d0, BIT(16) }, 484 [RST_BUS_I2C1] = { 0x2d0, BIT(17) }, 485 [RST_BUS_I2C2] = { 0x2d0, BIT(18) }, 486 [RST_BUS_UART0] = { 0x2d0, BIT(20) }, 487 [RST_BUS_UART1] = { 0x2d0, BIT(21) }, 488 [RST_BUS_UART2] = { 0x2d0, BIT(22) }, 489 }; 490 491 static const struct sunxi_ccu_desc suniv_ccu_desc = { 492 .ccu_clks = suniv_ccu_clks, 493 .num_ccu_clks = ARRAY_SIZE(suniv_ccu_clks), 494 495 .hw_clks = &suniv_hw_clks, 496 497 .resets = suniv_ccu_resets, 498 .num_resets = ARRAY_SIZE(suniv_ccu_resets), 499 }; 500 501 static struct ccu_pll_nb suniv_pll_cpu_nb = { 502 .common = &pll_cpu_clk.common, 503 /* copy from pll_cpu_clk */ 504 .enable = BIT(31), 505 .lock = BIT(28), 506 }; 507 508 static struct ccu_mux_nb suniv_cpu_nb = { 509 .common = &cpu_clk.common, 510 .cm = &cpu_clk.mux, 511 .delay_us = 1, /* > 8 clock cycles at 24 MHz */ 512 .bypass_index = 1, /* index of 24 MHz oscillator */ 513 }; 514 515 static void __init suniv_f1c100s_ccu_setup(struct device_node *node) 516 { 517 void __iomem *reg; 518 u32 val; 519 520 reg = of_io_request_and_map(node, 0, of_node_full_name(node)); 521 if (IS_ERR(reg)) { 522 pr_err("%pOF: Could not map the clock registers\n", node); 523 return; 524 } 525 526 /* Force the PLL-Audio-1x divider to 4 */ 527 val = readl(reg + SUNIV_PLL_AUDIO_REG); 528 val &= ~GENMASK(19, 16); 529 writel(val | (3 << 16), reg + SUNIV_PLL_AUDIO_REG); 530 531 sunxi_ccu_probe(node, reg, &suniv_ccu_desc); 532 533 /* Gate then ungate PLL CPU after any rate changes */ 534 ccu_pll_notifier_register(&suniv_pll_cpu_nb); 535 536 /* Reparent CPU during PLL CPU rate changes */ 537 ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk, 538 &suniv_cpu_nb); 539 } 540 CLK_OF_DECLARE(suniv_f1c100s_ccu, "allwinner,suniv-f1c100s-ccu", 541 suniv_f1c100s_ccu_setup); 542