1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 4 */ 5 6 #include <linux/io.h> 7 #include <linux/delay.h> 8 #include <linux/clk-provider.h> 9 #include <linux/clkdev.h> 10 #include <linux/of.h> 11 #include <linux/of_address.h> 12 #include <linux/clk/tegra.h> 13 14 #include <soc/tegra/pmc.h> 15 16 #include <dt-bindings/clock/tegra30-car.h> 17 18 #include "clk.h" 19 #include "clk-id.h" 20 21 #define OSC_CTRL 0x50 22 #define OSC_CTRL_OSC_FREQ_MASK (0xF<<28) 23 #define OSC_CTRL_OSC_FREQ_13MHZ (0X0<<28) 24 #define OSC_CTRL_OSC_FREQ_19_2MHZ (0X4<<28) 25 #define OSC_CTRL_OSC_FREQ_12MHZ (0X8<<28) 26 #define OSC_CTRL_OSC_FREQ_26MHZ (0XC<<28) 27 #define OSC_CTRL_OSC_FREQ_16_8MHZ (0X1<<28) 28 #define OSC_CTRL_OSC_FREQ_38_4MHZ (0X5<<28) 29 #define OSC_CTRL_OSC_FREQ_48MHZ (0X9<<28) 30 #define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK) 31 32 #define OSC_CTRL_PLL_REF_DIV_MASK (3<<26) 33 #define OSC_CTRL_PLL_REF_DIV_1 (0<<26) 34 #define OSC_CTRL_PLL_REF_DIV_2 (1<<26) 35 #define OSC_CTRL_PLL_REF_DIV_4 (2<<26) 36 37 #define OSC_FREQ_DET 0x58 38 #define OSC_FREQ_DET_TRIG BIT(31) 39 40 #define OSC_FREQ_DET_STATUS 0x5c 41 #define OSC_FREQ_DET_BUSY BIT(31) 42 #define OSC_FREQ_DET_CNT_MASK 0xffff 43 44 #define CCLKG_BURST_POLICY 0x368 45 #define SUPER_CCLKG_DIVIDER 0x36c 46 #define CCLKLP_BURST_POLICY 0x370 47 #define SUPER_CCLKLP_DIVIDER 0x374 48 #define SCLK_BURST_POLICY 0x028 49 #define SUPER_SCLK_DIVIDER 0x02c 50 51 #define SYSTEM_CLK_RATE 0x030 52 53 #define TEGRA30_CLK_PERIPH_BANKS 5 54 55 #define PLLC_BASE 0x80 56 #define PLLC_MISC 0x8c 57 #define PLLM_BASE 0x90 58 #define PLLM_MISC 0x9c 59 #define PLLP_BASE 0xa0 60 #define PLLP_MISC 0xac 61 #define PLLX_BASE 0xe0 62 #define PLLX_MISC 0xe4 63 #define PLLD_BASE 0xd0 64 #define PLLD_MISC 0xdc 65 #define PLLD2_BASE 0x4b8 66 #define PLLD2_MISC 0x4bc 67 #define PLLE_BASE 0xe8 68 #define PLLE_MISC 0xec 69 #define PLLA_BASE 0xb0 70 #define PLLA_MISC 0xbc 71 #define PLLU_BASE 0xc0 72 #define PLLU_MISC 0xcc 73 74 #define PLL_MISC_LOCK_ENABLE 18 75 #define PLLDU_MISC_LOCK_ENABLE 22 76 #define PLLE_MISC_LOCK_ENABLE 9 77 78 #define PLL_BASE_LOCK BIT(27) 79 #define PLLE_MISC_LOCK BIT(11) 80 81 #define PLLE_AUX 0x48c 82 #define PLLC_OUT 0x84 83 #define PLLM_OUT 0x94 84 #define PLLP_OUTA 0xa4 85 #define PLLP_OUTB 0xa8 86 #define PLLA_OUT 0xb4 87 88 #define AUDIO_SYNC_CLK_I2S0 0x4a0 89 #define AUDIO_SYNC_CLK_I2S1 0x4a4 90 #define AUDIO_SYNC_CLK_I2S2 0x4a8 91 #define AUDIO_SYNC_CLK_I2S3 0x4ac 92 #define AUDIO_SYNC_CLK_I2S4 0x4b0 93 #define AUDIO_SYNC_CLK_SPDIF 0x4b4 94 95 #define CLK_SOURCE_SPDIF_OUT 0x108 96 #define CLK_SOURCE_PWM 0x110 97 #define CLK_SOURCE_D_AUDIO 0x3d0 98 #define CLK_SOURCE_DAM0 0x3d8 99 #define CLK_SOURCE_DAM1 0x3dc 100 #define CLK_SOURCE_DAM2 0x3e0 101 #define CLK_SOURCE_3D2 0x3b0 102 #define CLK_SOURCE_2D 0x15c 103 #define CLK_SOURCE_HDMI 0x18c 104 #define CLK_SOURCE_DSIB 0xd0 105 #define CLK_SOURCE_SE 0x42c 106 #define CLK_SOURCE_EMC 0x19c 107 108 #define AUDIO_SYNC_DOUBLER 0x49c 109 110 /* Tegra CPU clock and reset control regs */ 111 #define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c 112 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340 113 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344 114 #define TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c 115 #define TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470 116 117 #define CPU_CLOCK(cpu) (0x1 << (8 + cpu)) 118 #define CPU_RESET(cpu) (0x1111ul << (cpu)) 119 120 #define CLK_RESET_CCLK_BURST 0x20 121 #define CLK_RESET_CCLK_DIVIDER 0x24 122 #define CLK_RESET_PLLX_BASE 0xe0 123 #define CLK_RESET_PLLX_MISC 0xe4 124 125 #define CLK_RESET_SOURCE_CSITE 0x1d4 126 127 #define CLK_RESET_CCLK_BURST_POLICY_SHIFT 28 128 #define CLK_RESET_CCLK_RUN_POLICY_SHIFT 4 129 #define CLK_RESET_CCLK_IDLE_POLICY_SHIFT 0 130 #define CLK_RESET_CCLK_IDLE_POLICY 1 131 #define CLK_RESET_CCLK_RUN_POLICY 2 132 #define CLK_RESET_CCLK_BURST_POLICY_PLLX 8 133 134 /* PLLM override registers */ 135 #define PMC_PLLM_WB0_OVERRIDE 0x1dc 136 137 #ifdef CONFIG_PM_SLEEP 138 static struct cpu_clk_suspend_context { 139 u32 pllx_misc; 140 u32 pllx_base; 141 142 u32 cpu_burst; 143 u32 clk_csite_src; 144 u32 cclk_divider; 145 } tegra30_cpu_clk_sctx; 146 #endif 147 148 static void __iomem *clk_base; 149 static void __iomem *pmc_base; 150 static unsigned long input_freq; 151 152 static DEFINE_SPINLOCK(cml_lock); 153 static DEFINE_SPINLOCK(pll_d_lock); 154 155 #define TEGRA_INIT_DATA_MUX(_name, _parents, _offset, \ 156 _clk_num, _gate_flags, _clk_id) \ 157 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \ 158 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \ 159 _clk_num, _gate_flags, _clk_id) 160 161 #define TEGRA_INIT_DATA_MUX8(_name, _parents, _offset, \ 162 _clk_num, _gate_flags, _clk_id) \ 163 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \ 164 29, 3, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \ 165 _clk_num, _gate_flags, _clk_id) 166 167 #define TEGRA_INIT_DATA_INT(_name, _parents, _offset, \ 168 _clk_num, _gate_flags, _clk_id) \ 169 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \ 170 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_INT | \ 171 TEGRA_DIVIDER_ROUND_UP, _clk_num, \ 172 _gate_flags, _clk_id) 173 174 #define TEGRA_INIT_DATA_NODIV(_name, _parents, _offset, \ 175 _mux_shift, _mux_width, _clk_num, \ 176 _gate_flags, _clk_id) \ 177 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \ 178 _mux_shift, _mux_width, 0, 0, 0, 0, 0,\ 179 _clk_num, _gate_flags, \ 180 _clk_id) 181 182 static struct clk **clks; 183 184 static struct tegra_clk_pll_freq_table pll_c_freq_table[] = { 185 { 12000000, 1040000000, 520, 6, 1, 8 }, 186 { 13000000, 1040000000, 480, 6, 1, 8 }, 187 { 16800000, 1040000000, 495, 8, 1, 8 }, /* actual: 1039.5 MHz */ 188 { 19200000, 1040000000, 325, 6, 1, 6 }, 189 { 26000000, 1040000000, 520, 13, 1, 8 }, 190 { 12000000, 832000000, 416, 6, 1, 8 }, 191 { 13000000, 832000000, 832, 13, 1, 8 }, 192 { 16800000, 832000000, 396, 8, 1, 8 }, /* actual: 831.6 MHz */ 193 { 19200000, 832000000, 260, 6, 1, 8 }, 194 { 26000000, 832000000, 416, 13, 1, 8 }, 195 { 12000000, 624000000, 624, 12, 1, 8 }, 196 { 13000000, 624000000, 624, 13, 1, 8 }, 197 { 16800000, 600000000, 520, 14, 1, 8 }, 198 { 19200000, 624000000, 520, 16, 1, 8 }, 199 { 26000000, 624000000, 624, 26, 1, 8 }, 200 { 12000000, 600000000, 600, 12, 1, 8 }, 201 { 13000000, 600000000, 600, 13, 1, 8 }, 202 { 16800000, 600000000, 500, 14, 1, 8 }, 203 { 19200000, 600000000, 375, 12, 1, 6 }, 204 { 26000000, 600000000, 600, 26, 1, 8 }, 205 { 12000000, 520000000, 520, 12, 1, 8 }, 206 { 13000000, 520000000, 520, 13, 1, 8 }, 207 { 16800000, 520000000, 495, 16, 1, 8 }, /* actual: 519.75 MHz */ 208 { 19200000, 520000000, 325, 12, 1, 6 }, 209 { 26000000, 520000000, 520, 26, 1, 8 }, 210 { 12000000, 416000000, 416, 12, 1, 8 }, 211 { 13000000, 416000000, 416, 13, 1, 8 }, 212 { 16800000, 416000000, 396, 16, 1, 8 }, /* actual: 415.8 MHz */ 213 { 19200000, 416000000, 260, 12, 1, 6 }, 214 { 26000000, 416000000, 416, 26, 1, 8 }, 215 { 0, 0, 0, 0, 0, 0 }, 216 }; 217 218 static struct tegra_clk_pll_freq_table pll_m_freq_table[] = { 219 { 12000000, 666000000, 666, 12, 1, 8 }, 220 { 13000000, 666000000, 666, 13, 1, 8 }, 221 { 16800000, 666000000, 555, 14, 1, 8 }, 222 { 19200000, 666000000, 555, 16, 1, 8 }, 223 { 26000000, 666000000, 666, 26, 1, 8 }, 224 { 12000000, 600000000, 600, 12, 1, 8 }, 225 { 13000000, 600000000, 600, 13, 1, 8 }, 226 { 16800000, 600000000, 500, 14, 1, 8 }, 227 { 19200000, 600000000, 375, 12, 1, 6 }, 228 { 26000000, 600000000, 600, 26, 1, 8 }, 229 { 0, 0, 0, 0, 0, 0 }, 230 }; 231 232 static struct tegra_clk_pll_freq_table pll_p_freq_table[] = { 233 { 12000000, 216000000, 432, 12, 2, 8 }, 234 { 13000000, 216000000, 432, 13, 2, 8 }, 235 { 16800000, 216000000, 360, 14, 2, 8 }, 236 { 19200000, 216000000, 360, 16, 2, 8 }, 237 { 26000000, 216000000, 432, 26, 2, 8 }, 238 { 0, 0, 0, 0, 0, 0 }, 239 }; 240 241 static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { 242 { 9600000, 564480000, 294, 5, 1, 4 }, 243 { 9600000, 552960000, 288, 5, 1, 4 }, 244 { 9600000, 24000000, 5, 2, 1, 1 }, 245 { 28800000, 56448000, 49, 25, 1, 1 }, 246 { 28800000, 73728000, 64, 25, 1, 1 }, 247 { 28800000, 24000000, 5, 6, 1, 1 }, 248 { 0, 0, 0, 0, 0, 0 }, 249 }; 250 251 static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { 252 { 12000000, 216000000, 216, 12, 1, 4 }, 253 { 13000000, 216000000, 216, 13, 1, 4 }, 254 { 16800000, 216000000, 180, 14, 1, 4 }, 255 { 19200000, 216000000, 180, 16, 1, 4 }, 256 { 26000000, 216000000, 216, 26, 1, 4 }, 257 { 12000000, 594000000, 594, 12, 1, 8 }, 258 { 13000000, 594000000, 594, 13, 1, 8 }, 259 { 16800000, 594000000, 495, 14, 1, 8 }, 260 { 19200000, 594000000, 495, 16, 1, 8 }, 261 { 26000000, 594000000, 594, 26, 1, 8 }, 262 { 12000000, 1000000000, 1000, 12, 1, 12 }, 263 { 13000000, 1000000000, 1000, 13, 1, 12 }, 264 { 19200000, 1000000000, 625, 12, 1, 8 }, 265 { 26000000, 1000000000, 1000, 26, 1, 12 }, 266 { 0, 0, 0, 0, 0, 0 }, 267 }; 268 269 static const struct pdiv_map pllu_p[] = { 270 { .pdiv = 1, .hw_val = 1 }, 271 { .pdiv = 2, .hw_val = 0 }, 272 { .pdiv = 0, .hw_val = 0 }, 273 }; 274 275 static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { 276 { 12000000, 480000000, 960, 12, 2, 12 }, 277 { 13000000, 480000000, 960, 13, 2, 12 }, 278 { 16800000, 480000000, 400, 7, 2, 5 }, 279 { 19200000, 480000000, 200, 4, 2, 3 }, 280 { 26000000, 480000000, 960, 26, 2, 12 }, 281 { 0, 0, 0, 0, 0, 0 }, 282 }; 283 284 static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { 285 /* 1.7 GHz */ 286 { 12000000, 1700000000, 850, 6, 1, 8 }, 287 { 13000000, 1700000000, 915, 7, 1, 8 }, /* actual: 1699.2 MHz */ 288 { 16800000, 1700000000, 708, 7, 1, 8 }, /* actual: 1699.2 MHz */ 289 { 19200000, 1700000000, 885, 10, 1, 8 }, /* actual: 1699.2 MHz */ 290 { 26000000, 1700000000, 850, 13, 1, 8 }, 291 /* 1.6 GHz */ 292 { 12000000, 1600000000, 800, 6, 1, 8 }, 293 { 13000000, 1600000000, 738, 6, 1, 8 }, /* actual: 1599.0 MHz */ 294 { 16800000, 1600000000, 857, 9, 1, 8 }, /* actual: 1599.7 MHz */ 295 { 19200000, 1600000000, 500, 6, 1, 8 }, 296 { 26000000, 1600000000, 800, 13, 1, 8 }, 297 /* 1.5 GHz */ 298 { 12000000, 1500000000, 750, 6, 1, 8 }, 299 { 13000000, 1500000000, 923, 8, 1, 8 }, /* actual: 1499.8 MHz */ 300 { 16800000, 1500000000, 625, 7, 1, 8 }, 301 { 19200000, 1500000000, 625, 8, 1, 8 }, 302 { 26000000, 1500000000, 750, 13, 1, 8 }, 303 /* 1.4 GHz */ 304 { 12000000, 1400000000, 700, 6, 1, 8 }, 305 { 13000000, 1400000000, 969, 9, 1, 8 }, /* actual: 1399.7 MHz */ 306 { 16800000, 1400000000, 1000, 12, 1, 8 }, 307 { 19200000, 1400000000, 875, 12, 1, 8 }, 308 { 26000000, 1400000000, 700, 13, 1, 8 }, 309 /* 1.3 GHz */ 310 { 12000000, 1300000000, 975, 9, 1, 8 }, 311 { 13000000, 1300000000, 1000, 10, 1, 8 }, 312 { 16800000, 1300000000, 928, 12, 1, 8 }, /* actual: 1299.2 MHz */ 313 { 19200000, 1300000000, 812, 12, 1, 8 }, /* actual: 1299.2 MHz */ 314 { 26000000, 1300000000, 650, 13, 1, 8 }, 315 /* 1.2 GHz */ 316 { 12000000, 1200000000, 1000, 10, 1, 8 }, 317 { 13000000, 1200000000, 923, 10, 1, 8 }, /* actual: 1199.9 MHz */ 318 { 16800000, 1200000000, 1000, 14, 1, 8 }, 319 { 19200000, 1200000000, 1000, 16, 1, 8 }, 320 { 26000000, 1200000000, 600, 13, 1, 8 }, 321 /* 1.1 GHz */ 322 { 12000000, 1100000000, 825, 9, 1, 8 }, 323 { 13000000, 1100000000, 846, 10, 1, 8 }, /* actual: 1099.8 MHz */ 324 { 16800000, 1100000000, 982, 15, 1, 8 }, /* actual: 1099.8 MHz */ 325 { 19200000, 1100000000, 859, 15, 1, 8 }, /* actual: 1099.5 MHz */ 326 { 26000000, 1100000000, 550, 13, 1, 8 }, 327 /* 1 GHz */ 328 { 12000000, 1000000000, 1000, 12, 1, 8 }, 329 { 13000000, 1000000000, 1000, 13, 1, 8 }, 330 { 16800000, 1000000000, 833, 14, 1, 8 }, /* actual: 999.6 MHz */ 331 { 19200000, 1000000000, 625, 12, 1, 8 }, 332 { 26000000, 1000000000, 1000, 26, 1, 8 }, 333 { 0, 0, 0, 0, 0, 0 }, 334 }; 335 336 static const struct pdiv_map plle_p[] = { 337 { .pdiv = 18, .hw_val = 18 }, 338 { .pdiv = 24, .hw_val = 24 }, 339 { .pdiv = 0, .hw_val = 0 }, 340 }; 341 342 static struct tegra_clk_pll_freq_table pll_e_freq_table[] = { 343 /* PLLE special case: use cpcon field to store cml divider value */ 344 { 12000000, 100000000, 150, 1, 18, 11 }, 345 { 216000000, 100000000, 200, 18, 24, 13 }, 346 { 0, 0, 0, 0, 0, 0 }, 347 }; 348 349 /* PLL parameters */ 350 static struct tegra_clk_pll_params pll_c_params __ro_after_init = { 351 .input_min = 2000000, 352 .input_max = 31000000, 353 .cf_min = 1000000, 354 .cf_max = 6000000, 355 .vco_min = 20000000, 356 .vco_max = 1400000000, 357 .base_reg = PLLC_BASE, 358 .misc_reg = PLLC_MISC, 359 .lock_mask = PLL_BASE_LOCK, 360 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 361 .lock_delay = 300, 362 .freq_table = pll_c_freq_table, 363 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK | 364 TEGRA_PLL_HAS_LOCK_ENABLE, 365 }; 366 367 static struct div_nmp pllm_nmp = { 368 .divn_shift = 8, 369 .divn_width = 10, 370 .override_divn_shift = 5, 371 .divm_shift = 0, 372 .divm_width = 5, 373 .override_divm_shift = 0, 374 .divp_shift = 20, 375 .divp_width = 3, 376 .override_divp_shift = 15, 377 }; 378 379 static struct tegra_clk_pll_params pll_m_params __ro_after_init = { 380 .input_min = 2000000, 381 .input_max = 31000000, 382 .cf_min = 1000000, 383 .cf_max = 6000000, 384 .vco_min = 20000000, 385 .vco_max = 1200000000, 386 .base_reg = PLLM_BASE, 387 .misc_reg = PLLM_MISC, 388 .lock_mask = PLL_BASE_LOCK, 389 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 390 .lock_delay = 300, 391 .div_nmp = &pllm_nmp, 392 .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE, 393 .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE, 394 .freq_table = pll_m_freq_table, 395 .flags = TEGRA_PLLM | TEGRA_PLL_HAS_CPCON | 396 TEGRA_PLL_SET_DCCON | TEGRA_PLL_USE_LOCK | 397 TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_FIXED, 398 }; 399 400 static struct tegra_clk_pll_params pll_p_params __ro_after_init = { 401 .input_min = 2000000, 402 .input_max = 31000000, 403 .cf_min = 1000000, 404 .cf_max = 6000000, 405 .vco_min = 20000000, 406 .vco_max = 1400000000, 407 .base_reg = PLLP_BASE, 408 .misc_reg = PLLP_MISC, 409 .lock_mask = PLL_BASE_LOCK, 410 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 411 .lock_delay = 300, 412 .freq_table = pll_p_freq_table, 413 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK | 414 TEGRA_PLL_HAS_LOCK_ENABLE, 415 .fixed_rate = 408000000, 416 }; 417 418 static struct tegra_clk_pll_params pll_a_params = { 419 .input_min = 2000000, 420 .input_max = 31000000, 421 .cf_min = 1000000, 422 .cf_max = 6000000, 423 .vco_min = 20000000, 424 .vco_max = 1400000000, 425 .base_reg = PLLA_BASE, 426 .misc_reg = PLLA_MISC, 427 .lock_mask = PLL_BASE_LOCK, 428 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 429 .lock_delay = 300, 430 .freq_table = pll_a_freq_table, 431 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK | 432 TEGRA_PLL_HAS_LOCK_ENABLE, 433 }; 434 435 static struct tegra_clk_pll_params pll_d_params __ro_after_init = { 436 .input_min = 2000000, 437 .input_max = 40000000, 438 .cf_min = 1000000, 439 .cf_max = 6000000, 440 .vco_min = 40000000, 441 .vco_max = 1000000000, 442 .base_reg = PLLD_BASE, 443 .misc_reg = PLLD_MISC, 444 .lock_mask = PLL_BASE_LOCK, 445 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 446 .lock_delay = 1000, 447 .freq_table = pll_d_freq_table, 448 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | 449 TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, 450 }; 451 452 static struct tegra_clk_pll_params pll_d2_params __ro_after_init = { 453 .input_min = 2000000, 454 .input_max = 40000000, 455 .cf_min = 1000000, 456 .cf_max = 6000000, 457 .vco_min = 40000000, 458 .vco_max = 1000000000, 459 .base_reg = PLLD2_BASE, 460 .misc_reg = PLLD2_MISC, 461 .lock_mask = PLL_BASE_LOCK, 462 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 463 .lock_delay = 1000, 464 .freq_table = pll_d_freq_table, 465 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | 466 TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, 467 }; 468 469 static struct tegra_clk_pll_params pll_u_params __ro_after_init = { 470 .input_min = 2000000, 471 .input_max = 40000000, 472 .cf_min = 1000000, 473 .cf_max = 6000000, 474 .vco_min = 48000000, 475 .vco_max = 960000000, 476 .base_reg = PLLU_BASE, 477 .misc_reg = PLLU_MISC, 478 .lock_mask = PLL_BASE_LOCK, 479 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 480 .lock_delay = 1000, 481 .pdiv_tohw = pllu_p, 482 .freq_table = pll_u_freq_table, 483 .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | 484 TEGRA_PLL_HAS_LOCK_ENABLE, 485 }; 486 487 static struct tegra_clk_pll_params pll_x_params __ro_after_init = { 488 .input_min = 2000000, 489 .input_max = 31000000, 490 .cf_min = 1000000, 491 .cf_max = 6000000, 492 .vco_min = 20000000, 493 .vco_max = 1700000000, 494 .base_reg = PLLX_BASE, 495 .misc_reg = PLLX_MISC, 496 .lock_mask = PLL_BASE_LOCK, 497 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 498 .lock_delay = 300, 499 .freq_table = pll_x_freq_table, 500 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_DCCON | 501 TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, 502 }; 503 504 static struct tegra_clk_pll_params pll_e_params __ro_after_init = { 505 .input_min = 12000000, 506 .input_max = 216000000, 507 .cf_min = 12000000, 508 .cf_max = 12000000, 509 .vco_min = 1200000000, 510 .vco_max = 2400000000U, 511 .base_reg = PLLE_BASE, 512 .misc_reg = PLLE_MISC, 513 .lock_mask = PLLE_MISC_LOCK, 514 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, 515 .lock_delay = 300, 516 .pdiv_tohw = plle_p, 517 .freq_table = pll_e_freq_table, 518 .flags = TEGRA_PLLE_CONFIGURE | TEGRA_PLL_FIXED | 519 TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_LOCK_MISC, 520 .fixed_rate = 100000000, 521 }; 522 523 static unsigned long tegra30_input_freq[] = { 524 [ 0] = 13000000, 525 [ 1] = 16800000, 526 [ 4] = 19200000, 527 [ 5] = 38400000, 528 [ 8] = 12000000, 529 [ 9] = 48000000, 530 [12] = 26000000, 531 }; 532 533 static struct tegra_devclk devclks[] __initdata = { 534 { .con_id = "pll_c", .dt_id = TEGRA30_CLK_PLL_C }, 535 { .con_id = "pll_c_out1", .dt_id = TEGRA30_CLK_PLL_C_OUT1 }, 536 { .con_id = "pll_p", .dt_id = TEGRA30_CLK_PLL_P }, 537 { .con_id = "pll_p_out1", .dt_id = TEGRA30_CLK_PLL_P_OUT1 }, 538 { .con_id = "pll_p_out2", .dt_id = TEGRA30_CLK_PLL_P_OUT2 }, 539 { .con_id = "pll_p_out3", .dt_id = TEGRA30_CLK_PLL_P_OUT3 }, 540 { .con_id = "pll_p_out4", .dt_id = TEGRA30_CLK_PLL_P_OUT4 }, 541 { .con_id = "pll_m", .dt_id = TEGRA30_CLK_PLL_M }, 542 { .con_id = "pll_m_out1", .dt_id = TEGRA30_CLK_PLL_M_OUT1 }, 543 { .con_id = "pll_x", .dt_id = TEGRA30_CLK_PLL_X }, 544 { .con_id = "pll_x_out0", .dt_id = TEGRA30_CLK_PLL_X_OUT0 }, 545 { .con_id = "pll_u", .dt_id = TEGRA30_CLK_PLL_U }, 546 { .con_id = "pll_d", .dt_id = TEGRA30_CLK_PLL_D }, 547 { .con_id = "pll_d_out0", .dt_id = TEGRA30_CLK_PLL_D_OUT0 }, 548 { .con_id = "pll_d2", .dt_id = TEGRA30_CLK_PLL_D2 }, 549 { .con_id = "pll_d2_out0", .dt_id = TEGRA30_CLK_PLL_D2_OUT0 }, 550 { .con_id = "pll_a", .dt_id = TEGRA30_CLK_PLL_A }, 551 { .con_id = "pll_a_out0", .dt_id = TEGRA30_CLK_PLL_A_OUT0 }, 552 { .con_id = "pll_e", .dt_id = TEGRA30_CLK_PLL_E }, 553 { .con_id = "spdif_in_sync", .dt_id = TEGRA30_CLK_SPDIF_IN_SYNC }, 554 { .con_id = "i2s0_sync", .dt_id = TEGRA30_CLK_I2S0_SYNC }, 555 { .con_id = "i2s1_sync", .dt_id = TEGRA30_CLK_I2S1_SYNC }, 556 { .con_id = "i2s2_sync", .dt_id = TEGRA30_CLK_I2S2_SYNC }, 557 { .con_id = "i2s3_sync", .dt_id = TEGRA30_CLK_I2S3_SYNC }, 558 { .con_id = "i2s4_sync", .dt_id = TEGRA30_CLK_I2S4_SYNC }, 559 { .con_id = "vimclk_sync", .dt_id = TEGRA30_CLK_VIMCLK_SYNC }, 560 { .con_id = "audio0", .dt_id = TEGRA30_CLK_AUDIO0 }, 561 { .con_id = "audio1", .dt_id = TEGRA30_CLK_AUDIO1 }, 562 { .con_id = "audio2", .dt_id = TEGRA30_CLK_AUDIO2 }, 563 { .con_id = "audio3", .dt_id = TEGRA30_CLK_AUDIO3 }, 564 { .con_id = "audio4", .dt_id = TEGRA30_CLK_AUDIO4 }, 565 { .con_id = "spdif", .dt_id = TEGRA30_CLK_SPDIF }, 566 { .con_id = "audio0_2x", .dt_id = TEGRA30_CLK_AUDIO0_2X }, 567 { .con_id = "audio1_2x", .dt_id = TEGRA30_CLK_AUDIO1_2X }, 568 { .con_id = "audio2_2x", .dt_id = TEGRA30_CLK_AUDIO2_2X }, 569 { .con_id = "audio3_2x", .dt_id = TEGRA30_CLK_AUDIO3_2X }, 570 { .con_id = "audio4_2x", .dt_id = TEGRA30_CLK_AUDIO4_2X }, 571 { .con_id = "spdif_2x", .dt_id = TEGRA30_CLK_SPDIF_2X }, 572 { .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA30_CLK_EXTERN1 }, 573 { .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA30_CLK_EXTERN2 }, 574 { .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA30_CLK_EXTERN3 }, 575 { .con_id = "blink", .dt_id = TEGRA30_CLK_BLINK }, 576 { .con_id = "cclk_g", .dt_id = TEGRA30_CLK_CCLK_G }, 577 { .con_id = "cclk_lp", .dt_id = TEGRA30_CLK_CCLK_LP }, 578 { .con_id = "sclk", .dt_id = TEGRA30_CLK_SCLK }, 579 { .con_id = "hclk", .dt_id = TEGRA30_CLK_HCLK }, 580 { .con_id = "pclk", .dt_id = TEGRA30_CLK_PCLK }, 581 { .con_id = "twd", .dt_id = TEGRA30_CLK_TWD }, 582 { .con_id = "emc", .dt_id = TEGRA30_CLK_EMC }, 583 { .con_id = "clk_32k", .dt_id = TEGRA30_CLK_CLK_32K }, 584 { .con_id = "clk_m_div2", .dt_id = TEGRA30_CLK_CLK_M_DIV2 }, 585 { .con_id = "clk_m_div4", .dt_id = TEGRA30_CLK_CLK_M_DIV4 }, 586 { .con_id = "cml0", .dt_id = TEGRA30_CLK_CML0 }, 587 { .con_id = "cml1", .dt_id = TEGRA30_CLK_CML1 }, 588 { .con_id = "clk_m", .dt_id = TEGRA30_CLK_CLK_M }, 589 { .con_id = "pll_ref", .dt_id = TEGRA30_CLK_PLL_REF }, 590 { .con_id = "csus", .dev_id = "tengra_camera", .dt_id = TEGRA30_CLK_CSUS }, 591 { .con_id = "vcp", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_VCP }, 592 { .con_id = "bsea", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_BSEA }, 593 { .con_id = "bsev", .dev_id = "tegra-aes", .dt_id = TEGRA30_CLK_BSEV }, 594 { .con_id = "dsia", .dev_id = "tegradc.0", .dt_id = TEGRA30_CLK_DSIA }, 595 { .con_id = "csi", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_CSI }, 596 { .con_id = "isp", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_ISP }, 597 { .con_id = "pcie", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_PCIE }, 598 { .con_id = "afi", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_AFI }, 599 { .con_id = "fuse", .dt_id = TEGRA30_CLK_FUSE }, 600 { .con_id = "fuse_burn", .dev_id = "fuse-tegra", .dt_id = TEGRA30_CLK_FUSE_BURN }, 601 { .con_id = "apbif", .dev_id = "tegra30-ahub", .dt_id = TEGRA30_CLK_APBIF }, 602 { .con_id = "hda2hdmi", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA2HDMI }, 603 { .dev_id = "tegra-apbdma", .dt_id = TEGRA30_CLK_APBDMA }, 604 { .dev_id = "rtc-tegra", .dt_id = TEGRA30_CLK_RTC }, 605 { .dev_id = "timer", .dt_id = TEGRA30_CLK_TIMER }, 606 { .dev_id = "tegra-kbc", .dt_id = TEGRA30_CLK_KBC }, 607 { .dev_id = "fsl-tegra-udc", .dt_id = TEGRA30_CLK_USBD }, 608 { .dev_id = "tegra-ehci.1", .dt_id = TEGRA30_CLK_USB2 }, 609 { .dev_id = "tegra-ehci.2", .dt_id = TEGRA30_CLK_USB2 }, 610 { .dev_id = "kfuse-tegra", .dt_id = TEGRA30_CLK_KFUSE }, 611 { .dev_id = "tegra_sata_cold", .dt_id = TEGRA30_CLK_SATA_COLD }, 612 { .dev_id = "dtv", .dt_id = TEGRA30_CLK_DTV }, 613 { .dev_id = "tegra30-i2s.0", .dt_id = TEGRA30_CLK_I2S0 }, 614 { .dev_id = "tegra30-i2s.1", .dt_id = TEGRA30_CLK_I2S1 }, 615 { .dev_id = "tegra30-i2s.2", .dt_id = TEGRA30_CLK_I2S2 }, 616 { .dev_id = "tegra30-i2s.3", .dt_id = TEGRA30_CLK_I2S3 }, 617 { .dev_id = "tegra30-i2s.4", .dt_id = TEGRA30_CLK_I2S4 }, 618 { .con_id = "spdif_out", .dev_id = "tegra30-spdif", .dt_id = TEGRA30_CLK_SPDIF_OUT }, 619 { .con_id = "spdif_in", .dev_id = "tegra30-spdif", .dt_id = TEGRA30_CLK_SPDIF_IN }, 620 { .con_id = "d_audio", .dev_id = "tegra30-ahub", .dt_id = TEGRA30_CLK_D_AUDIO }, 621 { .dev_id = "tegra30-dam.0", .dt_id = TEGRA30_CLK_DAM0 }, 622 { .dev_id = "tegra30-dam.1", .dt_id = TEGRA30_CLK_DAM1 }, 623 { .dev_id = "tegra30-dam.2", .dt_id = TEGRA30_CLK_DAM2 }, 624 { .con_id = "hda", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA }, 625 { .con_id = "hda2codec_2x", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA2CODEC_2X }, 626 { .dev_id = "spi_tegra.0", .dt_id = TEGRA30_CLK_SBC1 }, 627 { .dev_id = "spi_tegra.1", .dt_id = TEGRA30_CLK_SBC2 }, 628 { .dev_id = "spi_tegra.2", .dt_id = TEGRA30_CLK_SBC3 }, 629 { .dev_id = "spi_tegra.3", .dt_id = TEGRA30_CLK_SBC4 }, 630 { .dev_id = "spi_tegra.4", .dt_id = TEGRA30_CLK_SBC5 }, 631 { .dev_id = "spi_tegra.5", .dt_id = TEGRA30_CLK_SBC6 }, 632 { .dev_id = "tegra_sata_oob", .dt_id = TEGRA30_CLK_SATA_OOB }, 633 { .dev_id = "tegra_sata", .dt_id = TEGRA30_CLK_SATA }, 634 { .dev_id = "tegra_nand", .dt_id = TEGRA30_CLK_NDFLASH }, 635 { .dev_id = "tegra_nand_speed", .dt_id = TEGRA30_CLK_NDSPEED }, 636 { .dev_id = "vfir", .dt_id = TEGRA30_CLK_VFIR }, 637 { .dev_id = "csite", .dt_id = TEGRA30_CLK_CSITE }, 638 { .dev_id = "la", .dt_id = TEGRA30_CLK_LA }, 639 { .dev_id = "tegra_w1", .dt_id = TEGRA30_CLK_OWR }, 640 { .dev_id = "mipi", .dt_id = TEGRA30_CLK_MIPI }, 641 { .dev_id = "tegra-tsensor", .dt_id = TEGRA30_CLK_TSENSOR }, 642 { .dev_id = "i2cslow", .dt_id = TEGRA30_CLK_I2CSLOW }, 643 { .dev_id = "vde", .dt_id = TEGRA30_CLK_VDE }, 644 { .con_id = "vi", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_VI }, 645 { .dev_id = "epp", .dt_id = TEGRA30_CLK_EPP }, 646 { .dev_id = "mpe", .dt_id = TEGRA30_CLK_MPE }, 647 { .dev_id = "host1x", .dt_id = TEGRA30_CLK_HOST1X }, 648 { .dev_id = "3d", .dt_id = TEGRA30_CLK_GR3D }, 649 { .dev_id = "3d2", .dt_id = TEGRA30_CLK_GR3D2 }, 650 { .dev_id = "2d", .dt_id = TEGRA30_CLK_GR2D }, 651 { .dev_id = "se", .dt_id = TEGRA30_CLK_SE }, 652 { .dev_id = "mselect", .dt_id = TEGRA30_CLK_MSELECT }, 653 { .dev_id = "tegra-nor", .dt_id = TEGRA30_CLK_NOR }, 654 { .dev_id = "sdhci-tegra.0", .dt_id = TEGRA30_CLK_SDMMC1 }, 655 { .dev_id = "sdhci-tegra.1", .dt_id = TEGRA30_CLK_SDMMC2 }, 656 { .dev_id = "sdhci-tegra.2", .dt_id = TEGRA30_CLK_SDMMC3 }, 657 { .dev_id = "sdhci-tegra.3", .dt_id = TEGRA30_CLK_SDMMC4 }, 658 { .dev_id = "cve", .dt_id = TEGRA30_CLK_CVE }, 659 { .dev_id = "tvo", .dt_id = TEGRA30_CLK_TVO }, 660 { .dev_id = "tvdac", .dt_id = TEGRA30_CLK_TVDAC }, 661 { .dev_id = "actmon", .dt_id = TEGRA30_CLK_ACTMON }, 662 { .con_id = "vi_sensor", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_VI_SENSOR }, 663 { .con_id = "div-clk", .dev_id = "tegra-i2c.0", .dt_id = TEGRA30_CLK_I2C1 }, 664 { .con_id = "div-clk", .dev_id = "tegra-i2c.1", .dt_id = TEGRA30_CLK_I2C2 }, 665 { .con_id = "div-clk", .dev_id = "tegra-i2c.2", .dt_id = TEGRA30_CLK_I2C3 }, 666 { .con_id = "div-clk", .dev_id = "tegra-i2c.3", .dt_id = TEGRA30_CLK_I2C4 }, 667 { .con_id = "div-clk", .dev_id = "tegra-i2c.4", .dt_id = TEGRA30_CLK_I2C5 }, 668 { .dev_id = "tegra_uart.0", .dt_id = TEGRA30_CLK_UARTA }, 669 { .dev_id = "tegra_uart.1", .dt_id = TEGRA30_CLK_UARTB }, 670 { .dev_id = "tegra_uart.2", .dt_id = TEGRA30_CLK_UARTC }, 671 { .dev_id = "tegra_uart.3", .dt_id = TEGRA30_CLK_UARTD }, 672 { .dev_id = "tegra_uart.4", .dt_id = TEGRA30_CLK_UARTE }, 673 { .dev_id = "hdmi", .dt_id = TEGRA30_CLK_HDMI }, 674 { .dev_id = "extern1", .dt_id = TEGRA30_CLK_EXTERN1 }, 675 { .dev_id = "extern2", .dt_id = TEGRA30_CLK_EXTERN2 }, 676 { .dev_id = "extern3", .dt_id = TEGRA30_CLK_EXTERN3 }, 677 { .dev_id = "pwm", .dt_id = TEGRA30_CLK_PWM }, 678 { .dev_id = "tegradc.0", .dt_id = TEGRA30_CLK_DISP1 }, 679 { .dev_id = "tegradc.1", .dt_id = TEGRA30_CLK_DISP2 }, 680 { .dev_id = "tegradc.1", .dt_id = TEGRA30_CLK_DSIB }, 681 }; 682 683 static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = { 684 [tegra_clk_clk_32k] = { .dt_id = TEGRA30_CLK_CLK_32K, .present = true }, 685 [tegra_clk_clk_m] = { .dt_id = TEGRA30_CLK_CLK_M, .present = true }, 686 [tegra_clk_clk_m_div2] = { .dt_id = TEGRA30_CLK_CLK_M_DIV2, .present = true }, 687 [tegra_clk_clk_m_div4] = { .dt_id = TEGRA30_CLK_CLK_M_DIV4, .present = true }, 688 [tegra_clk_pll_ref] = { .dt_id = TEGRA30_CLK_PLL_REF, .present = true }, 689 [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA30_CLK_SPDIF_IN_SYNC, .present = true }, 690 [tegra_clk_i2s0_sync] = { .dt_id = TEGRA30_CLK_I2S0_SYNC, .present = true }, 691 [tegra_clk_i2s1_sync] = { .dt_id = TEGRA30_CLK_I2S1_SYNC, .present = true }, 692 [tegra_clk_i2s2_sync] = { .dt_id = TEGRA30_CLK_I2S2_SYNC, .present = true }, 693 [tegra_clk_i2s3_sync] = { .dt_id = TEGRA30_CLK_I2S3_SYNC, .present = true }, 694 [tegra_clk_i2s4_sync] = { .dt_id = TEGRA30_CLK_I2S4_SYNC, .present = true }, 695 [tegra_clk_vimclk_sync] = { .dt_id = TEGRA30_CLK_VIMCLK_SYNC, .present = true }, 696 [tegra_clk_audio0] = { .dt_id = TEGRA30_CLK_AUDIO0, .present = true }, 697 [tegra_clk_audio1] = { .dt_id = TEGRA30_CLK_AUDIO1, .present = true }, 698 [tegra_clk_audio2] = { .dt_id = TEGRA30_CLK_AUDIO2, .present = true }, 699 [tegra_clk_audio3] = { .dt_id = TEGRA30_CLK_AUDIO3, .present = true }, 700 [tegra_clk_audio4] = { .dt_id = TEGRA30_CLK_AUDIO4, .present = true }, 701 [tegra_clk_spdif] = { .dt_id = TEGRA30_CLK_SPDIF, .present = true }, 702 [tegra_clk_audio0_mux] = { .dt_id = TEGRA30_CLK_AUDIO0_MUX, .present = true }, 703 [tegra_clk_audio1_mux] = { .dt_id = TEGRA30_CLK_AUDIO1_MUX, .present = true }, 704 [tegra_clk_audio2_mux] = { .dt_id = TEGRA30_CLK_AUDIO2_MUX, .present = true }, 705 [tegra_clk_audio3_mux] = { .dt_id = TEGRA30_CLK_AUDIO3_MUX, .present = true }, 706 [tegra_clk_audio4_mux] = { .dt_id = TEGRA30_CLK_AUDIO4_MUX, .present = true }, 707 [tegra_clk_spdif_mux] = { .dt_id = TEGRA30_CLK_SPDIF_MUX, .present = true }, 708 [tegra_clk_audio0_2x] = { .dt_id = TEGRA30_CLK_AUDIO0_2X, .present = true }, 709 [tegra_clk_audio1_2x] = { .dt_id = TEGRA30_CLK_AUDIO1_2X, .present = true }, 710 [tegra_clk_audio2_2x] = { .dt_id = TEGRA30_CLK_AUDIO2_2X, .present = true }, 711 [tegra_clk_audio3_2x] = { .dt_id = TEGRA30_CLK_AUDIO3_2X, .present = true }, 712 [tegra_clk_audio4_2x] = { .dt_id = TEGRA30_CLK_AUDIO4_2X, .present = true }, 713 [tegra_clk_spdif_2x] = { .dt_id = TEGRA30_CLK_SPDIF_2X, .present = true }, 714 [tegra_clk_clk_out_1] = { .dt_id = TEGRA30_CLK_CLK_OUT_1, .present = true }, 715 [tegra_clk_clk_out_2] = { .dt_id = TEGRA30_CLK_CLK_OUT_2, .present = true }, 716 [tegra_clk_clk_out_3] = { .dt_id = TEGRA30_CLK_CLK_OUT_3, .present = true }, 717 [tegra_clk_blink] = { .dt_id = TEGRA30_CLK_BLINK, .present = true }, 718 [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA30_CLK_CLK_OUT_1_MUX, .present = true }, 719 [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA30_CLK_CLK_OUT_2_MUX, .present = true }, 720 [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA30_CLK_CLK_OUT_3_MUX, .present = true }, 721 [tegra_clk_hclk] = { .dt_id = TEGRA30_CLK_HCLK, .present = true }, 722 [tegra_clk_pclk] = { .dt_id = TEGRA30_CLK_PCLK, .present = true }, 723 [tegra_clk_i2s0] = { .dt_id = TEGRA30_CLK_I2S0, .present = true }, 724 [tegra_clk_i2s1] = { .dt_id = TEGRA30_CLK_I2S1, .present = true }, 725 [tegra_clk_i2s2] = { .dt_id = TEGRA30_CLK_I2S2, .present = true }, 726 [tegra_clk_i2s3] = { .dt_id = TEGRA30_CLK_I2S3, .present = true }, 727 [tegra_clk_i2s4] = { .dt_id = TEGRA30_CLK_I2S4, .present = true }, 728 [tegra_clk_spdif_in] = { .dt_id = TEGRA30_CLK_SPDIF_IN, .present = true }, 729 [tegra_clk_hda] = { .dt_id = TEGRA30_CLK_HDA, .present = true }, 730 [tegra_clk_hda2codec_2x] = { .dt_id = TEGRA30_CLK_HDA2CODEC_2X, .present = true }, 731 [tegra_clk_sbc1] = { .dt_id = TEGRA30_CLK_SBC1, .present = true }, 732 [tegra_clk_sbc2] = { .dt_id = TEGRA30_CLK_SBC2, .present = true }, 733 [tegra_clk_sbc3] = { .dt_id = TEGRA30_CLK_SBC3, .present = true }, 734 [tegra_clk_sbc4] = { .dt_id = TEGRA30_CLK_SBC4, .present = true }, 735 [tegra_clk_sbc5] = { .dt_id = TEGRA30_CLK_SBC5, .present = true }, 736 [tegra_clk_sbc6] = { .dt_id = TEGRA30_CLK_SBC6, .present = true }, 737 [tegra_clk_ndflash] = { .dt_id = TEGRA30_CLK_NDFLASH, .present = true }, 738 [tegra_clk_ndspeed] = { .dt_id = TEGRA30_CLK_NDSPEED, .present = true }, 739 [tegra_clk_vfir] = { .dt_id = TEGRA30_CLK_VFIR, .present = true }, 740 [tegra_clk_la] = { .dt_id = TEGRA30_CLK_LA, .present = true }, 741 [tegra_clk_csite] = { .dt_id = TEGRA30_CLK_CSITE, .present = true }, 742 [tegra_clk_owr] = { .dt_id = TEGRA30_CLK_OWR, .present = true }, 743 [tegra_clk_mipi] = { .dt_id = TEGRA30_CLK_MIPI, .present = true }, 744 [tegra_clk_tsensor] = { .dt_id = TEGRA30_CLK_TSENSOR, .present = true }, 745 [tegra_clk_i2cslow] = { .dt_id = TEGRA30_CLK_I2CSLOW, .present = true }, 746 [tegra_clk_vde] = { .dt_id = TEGRA30_CLK_VDE, .present = true }, 747 [tegra_clk_vi] = { .dt_id = TEGRA30_CLK_VI, .present = true }, 748 [tegra_clk_epp] = { .dt_id = TEGRA30_CLK_EPP, .present = true }, 749 [tegra_clk_mpe] = { .dt_id = TEGRA30_CLK_MPE, .present = true }, 750 [tegra_clk_host1x] = { .dt_id = TEGRA30_CLK_HOST1X, .present = true }, 751 [tegra_clk_gr2d] = { .dt_id = TEGRA30_CLK_GR2D, .present = true }, 752 [tegra_clk_gr3d] = { .dt_id = TEGRA30_CLK_GR3D, .present = true }, 753 [tegra_clk_mselect] = { .dt_id = TEGRA30_CLK_MSELECT, .present = true }, 754 [tegra_clk_nor] = { .dt_id = TEGRA30_CLK_NOR, .present = true }, 755 [tegra_clk_sdmmc1] = { .dt_id = TEGRA30_CLK_SDMMC1, .present = true }, 756 [tegra_clk_sdmmc2] = { .dt_id = TEGRA30_CLK_SDMMC2, .present = true }, 757 [tegra_clk_sdmmc3] = { .dt_id = TEGRA30_CLK_SDMMC3, .present = true }, 758 [tegra_clk_sdmmc4] = { .dt_id = TEGRA30_CLK_SDMMC4, .present = true }, 759 [tegra_clk_cve] = { .dt_id = TEGRA30_CLK_CVE, .present = true }, 760 [tegra_clk_tvo] = { .dt_id = TEGRA30_CLK_TVO, .present = true }, 761 [tegra_clk_tvdac] = { .dt_id = TEGRA30_CLK_TVDAC, .present = true }, 762 [tegra_clk_actmon] = { .dt_id = TEGRA30_CLK_ACTMON, .present = true }, 763 [tegra_clk_vi_sensor] = { .dt_id = TEGRA30_CLK_VI_SENSOR, .present = true }, 764 [tegra_clk_i2c1] = { .dt_id = TEGRA30_CLK_I2C1, .present = true }, 765 [tegra_clk_i2c2] = { .dt_id = TEGRA30_CLK_I2C2, .present = true }, 766 [tegra_clk_i2c3] = { .dt_id = TEGRA30_CLK_I2C3, .present = true }, 767 [tegra_clk_i2c4] = { .dt_id = TEGRA30_CLK_I2C4, .present = true }, 768 [tegra_clk_i2c5] = { .dt_id = TEGRA30_CLK_I2C5, .present = true }, 769 [tegra_clk_uarta] = { .dt_id = TEGRA30_CLK_UARTA, .present = true }, 770 [tegra_clk_uartb] = { .dt_id = TEGRA30_CLK_UARTB, .present = true }, 771 [tegra_clk_uartc] = { .dt_id = TEGRA30_CLK_UARTC, .present = true }, 772 [tegra_clk_uartd] = { .dt_id = TEGRA30_CLK_UARTD, .present = true }, 773 [tegra_clk_uarte] = { .dt_id = TEGRA30_CLK_UARTE, .present = true }, 774 [tegra_clk_extern1] = { .dt_id = TEGRA30_CLK_EXTERN1, .present = true }, 775 [tegra_clk_extern2] = { .dt_id = TEGRA30_CLK_EXTERN2, .present = true }, 776 [tegra_clk_extern3] = { .dt_id = TEGRA30_CLK_EXTERN3, .present = true }, 777 [tegra_clk_disp1] = { .dt_id = TEGRA30_CLK_DISP1, .present = true }, 778 [tegra_clk_disp2] = { .dt_id = TEGRA30_CLK_DISP2, .present = true }, 779 [tegra_clk_ahbdma] = { .dt_id = TEGRA30_CLK_AHBDMA, .present = true }, 780 [tegra_clk_apbdma] = { .dt_id = TEGRA30_CLK_APBDMA, .present = true }, 781 [tegra_clk_rtc] = { .dt_id = TEGRA30_CLK_RTC, .present = true }, 782 [tegra_clk_timer] = { .dt_id = TEGRA30_CLK_TIMER, .present = true }, 783 [tegra_clk_kbc] = { .dt_id = TEGRA30_CLK_KBC, .present = true }, 784 [tegra_clk_csus] = { .dt_id = TEGRA30_CLK_CSUS, .present = true }, 785 [tegra_clk_vcp] = { .dt_id = TEGRA30_CLK_VCP, .present = true }, 786 [tegra_clk_bsea] = { .dt_id = TEGRA30_CLK_BSEA, .present = true }, 787 [tegra_clk_bsev] = { .dt_id = TEGRA30_CLK_BSEV, .present = true }, 788 [tegra_clk_usbd] = { .dt_id = TEGRA30_CLK_USBD, .present = true }, 789 [tegra_clk_usb2] = { .dt_id = TEGRA30_CLK_USB2, .present = true }, 790 [tegra_clk_usb3] = { .dt_id = TEGRA30_CLK_USB3, .present = true }, 791 [tegra_clk_csi] = { .dt_id = TEGRA30_CLK_CSI, .present = true }, 792 [tegra_clk_isp] = { .dt_id = TEGRA30_CLK_ISP, .present = true }, 793 [tegra_clk_kfuse] = { .dt_id = TEGRA30_CLK_KFUSE, .present = true }, 794 [tegra_clk_fuse] = { .dt_id = TEGRA30_CLK_FUSE, .present = true }, 795 [tegra_clk_fuse_burn] = { .dt_id = TEGRA30_CLK_FUSE_BURN, .present = true }, 796 [tegra_clk_apbif] = { .dt_id = TEGRA30_CLK_APBIF, .present = true }, 797 [tegra_clk_hda2hdmi] = { .dt_id = TEGRA30_CLK_HDA2HDMI, .present = true }, 798 [tegra_clk_sata_cold] = { .dt_id = TEGRA30_CLK_SATA_COLD, .present = true }, 799 [tegra_clk_sata_oob] = { .dt_id = TEGRA30_CLK_SATA_OOB, .present = true }, 800 [tegra_clk_sata] = { .dt_id = TEGRA30_CLK_SATA, .present = true }, 801 [tegra_clk_dtv] = { .dt_id = TEGRA30_CLK_DTV, .present = true }, 802 [tegra_clk_pll_p] = { .dt_id = TEGRA30_CLK_PLL_P, .present = true }, 803 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA30_CLK_PLL_P_OUT1, .present = true }, 804 [tegra_clk_pll_p_out2] = { .dt_id = TEGRA30_CLK_PLL_P_OUT2, .present = true }, 805 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA30_CLK_PLL_P_OUT3, .present = true }, 806 [tegra_clk_pll_p_out4] = { .dt_id = TEGRA30_CLK_PLL_P_OUT4, .present = true }, 807 [tegra_clk_pll_a] = { .dt_id = TEGRA30_CLK_PLL_A, .present = true }, 808 [tegra_clk_pll_a_out0] = { .dt_id = TEGRA30_CLK_PLL_A_OUT0, .present = true }, 809 [tegra_clk_cec] = { .dt_id = TEGRA30_CLK_CEC, .present = true }, 810 [tegra_clk_emc] = { .dt_id = TEGRA30_CLK_EMC, .present = false }, 811 }; 812 813 static const char *pll_e_parents[] = { "pll_ref", "pll_p" }; 814 815 static void __init tegra30_pll_init(void) 816 { 817 struct clk *clk; 818 819 /* PLLC */ 820 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0, 821 &pll_c_params, NULL); 822 clks[TEGRA30_CLK_PLL_C] = clk; 823 824 /* PLLC_OUT1 */ 825 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c", 826 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 827 8, 8, 1, NULL); 828 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div", 829 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT, 830 0, NULL); 831 clks[TEGRA30_CLK_PLL_C_OUT1] = clk; 832 833 /* PLLM */ 834 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base, 835 CLK_SET_RATE_GATE, &pll_m_params, NULL); 836 clks[TEGRA30_CLK_PLL_M] = clk; 837 838 /* PLLM_OUT1 */ 839 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m", 840 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 841 8, 8, 1, NULL); 842 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div", 843 clk_base + PLLM_OUT, 1, 0, 844 CLK_SET_RATE_PARENT, 0, NULL); 845 clks[TEGRA30_CLK_PLL_M_OUT1] = clk; 846 847 /* PLLX */ 848 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, pmc_base, 0, 849 &pll_x_params, NULL); 850 clks[TEGRA30_CLK_PLL_X] = clk; 851 852 /* PLLX_OUT0 */ 853 clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x", 854 CLK_SET_RATE_PARENT, 1, 2); 855 clks[TEGRA30_CLK_PLL_X_OUT0] = clk; 856 857 /* PLLU */ 858 clk = tegra_clk_register_pllu("pll_u", "pll_ref", clk_base, 0, 859 &pll_u_params, NULL); 860 clks[TEGRA30_CLK_PLL_U] = clk; 861 862 /* PLLD */ 863 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc_base, 0, 864 &pll_d_params, &pll_d_lock); 865 clks[TEGRA30_CLK_PLL_D] = clk; 866 867 /* PLLD_OUT0 */ 868 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d", 869 CLK_SET_RATE_PARENT, 1, 2); 870 clks[TEGRA30_CLK_PLL_D_OUT0] = clk; 871 872 /* PLLD2 */ 873 clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc_base, 0, 874 &pll_d2_params, NULL); 875 clks[TEGRA30_CLK_PLL_D2] = clk; 876 877 /* PLLD2_OUT0 */ 878 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2", 879 CLK_SET_RATE_PARENT, 1, 2); 880 clks[TEGRA30_CLK_PLL_D2_OUT0] = clk; 881 882 /* PLLE */ 883 clk = clk_register_mux(NULL, "pll_e_mux", pll_e_parents, 884 ARRAY_SIZE(pll_e_parents), 885 CLK_SET_RATE_NO_REPARENT, 886 clk_base + PLLE_AUX, 2, 1, 0, NULL); 887 clk = tegra_clk_register_plle("pll_e", "pll_e_mux", clk_base, pmc_base, 888 CLK_GET_RATE_NOCACHE, &pll_e_params, NULL); 889 clks[TEGRA30_CLK_PLL_E] = clk; 890 } 891 892 static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", 893 "pll_p_cclkg", "pll_p_out4_cclkg", 894 "pll_p_out3_cclkg", "unused", "pll_x" }; 895 static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", 896 "pll_p_cclklp", "pll_p_out4_cclklp", 897 "pll_p_out3_cclklp", "unused", "pll_x", 898 "pll_x_out0" }; 899 static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4", 900 "pll_p_out3", "pll_p_out2", "unused", 901 "clk_32k", "pll_m_out1" }; 902 903 static void __init tegra30_super_clk_init(void) 904 { 905 struct clk *clk; 906 907 /* 908 * Clock input to cclk_g divided from pll_p using 909 * U71 divider of cclk_g. 910 */ 911 clk = tegra_clk_register_divider("pll_p_cclkg", "pll_p", 912 clk_base + SUPER_CCLKG_DIVIDER, 0, 913 TEGRA_DIVIDER_INT, 16, 8, 1, NULL); 914 clk_register_clkdev(clk, "pll_p_cclkg", NULL); 915 916 /* 917 * Clock input to cclk_g divided from pll_p_out3 using 918 * U71 divider of cclk_g. 919 */ 920 clk = tegra_clk_register_divider("pll_p_out3_cclkg", "pll_p_out3", 921 clk_base + SUPER_CCLKG_DIVIDER, 0, 922 TEGRA_DIVIDER_INT, 16, 8, 1, NULL); 923 clk_register_clkdev(clk, "pll_p_out3_cclkg", NULL); 924 925 /* 926 * Clock input to cclk_g divided from pll_p_out4 using 927 * U71 divider of cclk_g. 928 */ 929 clk = tegra_clk_register_divider("pll_p_out4_cclkg", "pll_p_out4", 930 clk_base + SUPER_CCLKG_DIVIDER, 0, 931 TEGRA_DIVIDER_INT, 16, 8, 1, NULL); 932 clk_register_clkdev(clk, "pll_p_out4_cclkg", NULL); 933 934 /* CCLKG */ 935 clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents, 936 ARRAY_SIZE(cclk_g_parents), 937 CLK_SET_RATE_PARENT, 938 clk_base + CCLKG_BURST_POLICY, 939 0, 4, 0, 0, NULL); 940 clks[TEGRA30_CLK_CCLK_G] = clk; 941 942 /* 943 * Clock input to cclk_lp divided from pll_p using 944 * U71 divider of cclk_lp. 945 */ 946 clk = tegra_clk_register_divider("pll_p_cclklp", "pll_p", 947 clk_base + SUPER_CCLKLP_DIVIDER, 0, 948 TEGRA_DIVIDER_INT, 16, 8, 1, NULL); 949 clk_register_clkdev(clk, "pll_p_cclklp", NULL); 950 951 /* 952 * Clock input to cclk_lp divided from pll_p_out3 using 953 * U71 divider of cclk_lp. 954 */ 955 clk = tegra_clk_register_divider("pll_p_out3_cclklp", "pll_p_out3", 956 clk_base + SUPER_CCLKLP_DIVIDER, 0, 957 TEGRA_DIVIDER_INT, 16, 8, 1, NULL); 958 clk_register_clkdev(clk, "pll_p_out3_cclklp", NULL); 959 960 /* 961 * Clock input to cclk_lp divided from pll_p_out4 using 962 * U71 divider of cclk_lp. 963 */ 964 clk = tegra_clk_register_divider("pll_p_out4_cclklp", "pll_p_out4", 965 clk_base + SUPER_CCLKLP_DIVIDER, 0, 966 TEGRA_DIVIDER_INT, 16, 8, 1, NULL); 967 clk_register_clkdev(clk, "pll_p_out4_cclklp", NULL); 968 969 /* CCLKLP */ 970 clk = tegra_clk_register_super_mux("cclk_lp", cclk_lp_parents, 971 ARRAY_SIZE(cclk_lp_parents), 972 CLK_SET_RATE_PARENT, 973 clk_base + CCLKLP_BURST_POLICY, 974 TEGRA_DIVIDER_2, 4, 8, 9, 975 NULL); 976 clks[TEGRA30_CLK_CCLK_LP] = clk; 977 978 /* SCLK */ 979 clk = tegra_clk_register_super_mux("sclk", sclk_parents, 980 ARRAY_SIZE(sclk_parents), 981 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 982 clk_base + SCLK_BURST_POLICY, 983 0, 4, 0, 0, NULL); 984 clks[TEGRA30_CLK_SCLK] = clk; 985 986 /* twd */ 987 clk = clk_register_fixed_factor(NULL, "twd", "cclk_g", 988 CLK_SET_RATE_PARENT, 1, 2); 989 clks[TEGRA30_CLK_TWD] = clk; 990 991 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra30_clks, NULL); 992 } 993 994 static const char *mux_pllacp_clkm[] = { "pll_a_out0", "unused", "pll_p", 995 "clk_m" }; 996 static const char *mux_pllpcm_clkm[] = { "pll_p", "pll_c", "pll_m", "clk_m" }; 997 static const char *spdif_out_parents[] = { "pll_a_out0", "spdif_2x", "pll_p", 998 "clk_m" }; 999 static const char *mux_pllmcpa[] = { "pll_m", "pll_c", "pll_p", "pll_a_out0" }; 1000 static const char *mux_pllpmdacd2_clkm[] = { "pll_p", "pll_m", "pll_d_out0", 1001 "pll_a_out0", "pll_c", 1002 "pll_d2_out0", "clk_m" }; 1003 static const char *mux_plld_out0_plld2_out0[] = { "pll_d_out0", 1004 "pll_d2_out0" }; 1005 static const char *pwm_parents[] = { "pll_p", "pll_c", "clk_32k", "clk_m" }; 1006 1007 static struct tegra_periph_init_data tegra_periph_clk_list[] = { 1008 TEGRA_INIT_DATA_MUX("spdif_out", spdif_out_parents, CLK_SOURCE_SPDIF_OUT, 10, TEGRA_PERIPH_ON_APB, TEGRA30_CLK_SPDIF_OUT), 1009 TEGRA_INIT_DATA_MUX("d_audio", mux_pllacp_clkm, CLK_SOURCE_D_AUDIO, 106, 0, TEGRA30_CLK_D_AUDIO), 1010 TEGRA_INIT_DATA_MUX("dam0", mux_pllacp_clkm, CLK_SOURCE_DAM0, 108, 0, TEGRA30_CLK_DAM0), 1011 TEGRA_INIT_DATA_MUX("dam1", mux_pllacp_clkm, CLK_SOURCE_DAM1, 109, 0, TEGRA30_CLK_DAM1), 1012 TEGRA_INIT_DATA_MUX("dam2", mux_pllacp_clkm, CLK_SOURCE_DAM2, 110, 0, TEGRA30_CLK_DAM2), 1013 TEGRA_INIT_DATA_INT("3d2", mux_pllmcpa, CLK_SOURCE_3D2, 98, TEGRA_PERIPH_MANUAL_RESET, TEGRA30_CLK_GR3D2), 1014 TEGRA_INIT_DATA_INT("se", mux_pllpcm_clkm, CLK_SOURCE_SE, 127, 0, TEGRA30_CLK_SE), 1015 TEGRA_INIT_DATA_MUX8("hdmi", mux_pllpmdacd2_clkm, CLK_SOURCE_HDMI, 51, 0, TEGRA30_CLK_HDMI), 1016 TEGRA_INIT_DATA("pwm", NULL, NULL, pwm_parents, CLK_SOURCE_PWM, 28, 2, 0, 0, 8, 1, 0, 17, TEGRA_PERIPH_ON_APB, TEGRA30_CLK_PWM), 1017 }; 1018 1019 static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = { 1020 TEGRA_INIT_DATA_NODIV("dsib", mux_plld_out0_plld2_out0, CLK_SOURCE_DSIB, 25, 1, 82, 0, TEGRA30_CLK_DSIB), 1021 }; 1022 1023 static void __init tegra30_periph_clk_init(void) 1024 { 1025 struct tegra_periph_init_data *data; 1026 struct clk *clk; 1027 unsigned int i; 1028 1029 /* dsia */ 1030 clk = tegra_clk_register_periph_gate("dsia", "pll_d_out0", 0, clk_base, 1031 0, 48, periph_clk_enb_refcnt); 1032 clks[TEGRA30_CLK_DSIA] = clk; 1033 1034 /* pcie */ 1035 clk = tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0, 1036 70, periph_clk_enb_refcnt); 1037 clks[TEGRA30_CLK_PCIE] = clk; 1038 1039 /* afi */ 1040 clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72, 1041 periph_clk_enb_refcnt); 1042 clks[TEGRA30_CLK_AFI] = clk; 1043 1044 /* emc */ 1045 clk = tegra20_clk_register_emc(clk_base + CLK_SOURCE_EMC, true); 1046 1047 clks[TEGRA30_CLK_EMC] = clk; 1048 1049 clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC, 1050 NULL); 1051 clks[TEGRA30_CLK_MC] = clk; 1052 1053 /* cml0 */ 1054 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX, 1055 0, 0, &cml_lock); 1056 clks[TEGRA30_CLK_CML0] = clk; 1057 1058 /* cml1 */ 1059 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX, 1060 1, 0, &cml_lock); 1061 clks[TEGRA30_CLK_CML1] = clk; 1062 1063 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) { 1064 data = &tegra_periph_clk_list[i]; 1065 clk = tegra_clk_register_periph_data(clk_base, data); 1066 clks[data->clk_id] = clk; 1067 } 1068 1069 for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) { 1070 data = &tegra_periph_nodiv_clk_list[i]; 1071 clk = tegra_clk_register_periph_nodiv(data->name, 1072 data->p.parent_names, 1073 data->num_parents, &data->periph, 1074 clk_base, data->offset); 1075 clks[data->clk_id] = clk; 1076 } 1077 1078 tegra_periph_clk_init(clk_base, pmc_base, tegra30_clks, &pll_p_params); 1079 } 1080 1081 /* Tegra30 CPU clock and reset control functions */ 1082 static void tegra30_wait_cpu_in_reset(u32 cpu) 1083 { 1084 unsigned int reg; 1085 1086 do { 1087 reg = readl(clk_base + 1088 TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS); 1089 cpu_relax(); 1090 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */ 1091 1092 return; 1093 } 1094 1095 static void tegra30_put_cpu_in_reset(u32 cpu) 1096 { 1097 writel(CPU_RESET(cpu), 1098 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET); 1099 dmb(); 1100 } 1101 1102 static void tegra30_cpu_out_of_reset(u32 cpu) 1103 { 1104 writel(CPU_RESET(cpu), 1105 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR); 1106 wmb(); 1107 } 1108 1109 static void tegra30_enable_cpu_clock(u32 cpu) 1110 { 1111 unsigned int reg; 1112 1113 writel(CPU_CLOCK(cpu), 1114 clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR); 1115 reg = readl(clk_base + 1116 TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR); 1117 } 1118 1119 static void tegra30_disable_cpu_clock(u32 cpu) 1120 { 1121 unsigned int reg; 1122 1123 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 1124 writel(reg | CPU_CLOCK(cpu), 1125 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 1126 } 1127 1128 #ifdef CONFIG_PM_SLEEP 1129 static bool tegra30_cpu_rail_off_ready(void) 1130 { 1131 unsigned int cpu_rst_status; 1132 int cpu_pwr_status; 1133 1134 cpu_rst_status = readl(clk_base + 1135 TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS); 1136 cpu_pwr_status = tegra_pmc_cpu_is_powered(1) || 1137 tegra_pmc_cpu_is_powered(2) || 1138 tegra_pmc_cpu_is_powered(3); 1139 1140 if (((cpu_rst_status & 0xE) != 0xE) || cpu_pwr_status) 1141 return false; 1142 1143 return true; 1144 } 1145 1146 static void tegra30_cpu_clock_suspend(void) 1147 { 1148 /* switch coresite to clk_m, save off original source */ 1149 tegra30_cpu_clk_sctx.clk_csite_src = 1150 readl(clk_base + CLK_RESET_SOURCE_CSITE); 1151 writel(3 << 30, clk_base + CLK_RESET_SOURCE_CSITE); 1152 1153 tegra30_cpu_clk_sctx.cpu_burst = 1154 readl(clk_base + CLK_RESET_CCLK_BURST); 1155 tegra30_cpu_clk_sctx.pllx_base = 1156 readl(clk_base + CLK_RESET_PLLX_BASE); 1157 tegra30_cpu_clk_sctx.pllx_misc = 1158 readl(clk_base + CLK_RESET_PLLX_MISC); 1159 tegra30_cpu_clk_sctx.cclk_divider = 1160 readl(clk_base + CLK_RESET_CCLK_DIVIDER); 1161 } 1162 1163 static void tegra30_cpu_clock_resume(void) 1164 { 1165 unsigned int reg, policy; 1166 u32 misc, base; 1167 1168 /* Is CPU complex already running on PLLX? */ 1169 reg = readl(clk_base + CLK_RESET_CCLK_BURST); 1170 policy = (reg >> CLK_RESET_CCLK_BURST_POLICY_SHIFT) & 0xF; 1171 1172 if (policy == CLK_RESET_CCLK_IDLE_POLICY) 1173 reg = (reg >> CLK_RESET_CCLK_IDLE_POLICY_SHIFT) & 0xF; 1174 else if (policy == CLK_RESET_CCLK_RUN_POLICY) 1175 reg = (reg >> CLK_RESET_CCLK_RUN_POLICY_SHIFT) & 0xF; 1176 else 1177 BUG(); 1178 1179 if (reg != CLK_RESET_CCLK_BURST_POLICY_PLLX) { 1180 misc = readl_relaxed(clk_base + CLK_RESET_PLLX_MISC); 1181 base = readl_relaxed(clk_base + CLK_RESET_PLLX_BASE); 1182 1183 if (misc != tegra30_cpu_clk_sctx.pllx_misc || 1184 base != tegra30_cpu_clk_sctx.pllx_base) { 1185 /* restore PLLX settings if CPU is on different PLL */ 1186 writel(tegra30_cpu_clk_sctx.pllx_misc, 1187 clk_base + CLK_RESET_PLLX_MISC); 1188 writel(tegra30_cpu_clk_sctx.pllx_base, 1189 clk_base + CLK_RESET_PLLX_BASE); 1190 1191 /* wait for PLL stabilization if PLLX was enabled */ 1192 if (tegra30_cpu_clk_sctx.pllx_base & (1 << 30)) 1193 udelay(300); 1194 } 1195 } 1196 1197 /* 1198 * Restore original burst policy setting for calls resulting from CPU 1199 * LP2 in idle or system suspend. 1200 */ 1201 writel(tegra30_cpu_clk_sctx.cclk_divider, 1202 clk_base + CLK_RESET_CCLK_DIVIDER); 1203 writel(tegra30_cpu_clk_sctx.cpu_burst, 1204 clk_base + CLK_RESET_CCLK_BURST); 1205 1206 writel(tegra30_cpu_clk_sctx.clk_csite_src, 1207 clk_base + CLK_RESET_SOURCE_CSITE); 1208 } 1209 #endif 1210 1211 static struct tegra_cpu_car_ops tegra30_cpu_car_ops = { 1212 .wait_for_reset = tegra30_wait_cpu_in_reset, 1213 .put_in_reset = tegra30_put_cpu_in_reset, 1214 .out_of_reset = tegra30_cpu_out_of_reset, 1215 .enable_clock = tegra30_enable_cpu_clock, 1216 .disable_clock = tegra30_disable_cpu_clock, 1217 #ifdef CONFIG_PM_SLEEP 1218 .rail_off_ready = tegra30_cpu_rail_off_ready, 1219 .suspend = tegra30_cpu_clock_suspend, 1220 .resume = tegra30_cpu_clock_resume, 1221 #endif 1222 }; 1223 1224 static struct tegra_clk_init_table init_table[] __initdata = { 1225 { TEGRA30_CLK_UARTA, TEGRA30_CLK_PLL_P, 408000000, 0 }, 1226 { TEGRA30_CLK_UARTB, TEGRA30_CLK_PLL_P, 408000000, 0 }, 1227 { TEGRA30_CLK_UARTC, TEGRA30_CLK_PLL_P, 408000000, 0 }, 1228 { TEGRA30_CLK_UARTD, TEGRA30_CLK_PLL_P, 408000000, 0 }, 1229 { TEGRA30_CLK_UARTE, TEGRA30_CLK_PLL_P, 408000000, 0 }, 1230 { TEGRA30_CLK_PLL_A, TEGRA30_CLK_CLK_MAX, 564480000, 1 }, 1231 { TEGRA30_CLK_PLL_A_OUT0, TEGRA30_CLK_CLK_MAX, 11289600, 1 }, 1232 { TEGRA30_CLK_EXTERN1, TEGRA30_CLK_PLL_A_OUT0, 0, 1 }, 1233 { TEGRA30_CLK_CLK_OUT_1_MUX, TEGRA30_CLK_EXTERN1, 0, 0 }, 1234 { TEGRA30_CLK_CLK_OUT_1, TEGRA30_CLK_CLK_MAX, 0, 1 }, 1235 { TEGRA30_CLK_BLINK, TEGRA30_CLK_CLK_MAX, 0, 1 }, 1236 { TEGRA30_CLK_I2S0, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 }, 1237 { TEGRA30_CLK_I2S1, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 }, 1238 { TEGRA30_CLK_I2S2, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 }, 1239 { TEGRA30_CLK_I2S3, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 }, 1240 { TEGRA30_CLK_I2S4, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 }, 1241 { TEGRA30_CLK_SDMMC1, TEGRA30_CLK_PLL_P, 48000000, 0 }, 1242 { TEGRA30_CLK_SDMMC2, TEGRA30_CLK_PLL_P, 48000000, 0 }, 1243 { TEGRA30_CLK_SDMMC3, TEGRA30_CLK_PLL_P, 48000000, 0 }, 1244 { TEGRA30_CLK_CSITE, TEGRA30_CLK_CLK_MAX, 0, 1 }, 1245 { TEGRA30_CLK_MSELECT, TEGRA30_CLK_CLK_MAX, 0, 1 }, 1246 { TEGRA30_CLK_SBC1, TEGRA30_CLK_PLL_P, 100000000, 0 }, 1247 { TEGRA30_CLK_SBC2, TEGRA30_CLK_PLL_P, 100000000, 0 }, 1248 { TEGRA30_CLK_SBC3, TEGRA30_CLK_PLL_P, 100000000, 0 }, 1249 { TEGRA30_CLK_SBC4, TEGRA30_CLK_PLL_P, 100000000, 0 }, 1250 { TEGRA30_CLK_SBC5, TEGRA30_CLK_PLL_P, 100000000, 0 }, 1251 { TEGRA30_CLK_SBC6, TEGRA30_CLK_PLL_P, 100000000, 0 }, 1252 { TEGRA30_CLK_PLL_C, TEGRA30_CLK_CLK_MAX, 600000000, 0 }, 1253 { TEGRA30_CLK_HOST1X, TEGRA30_CLK_PLL_C, 150000000, 0 }, 1254 { TEGRA30_CLK_DISP1, TEGRA30_CLK_PLL_P, 600000000, 0 }, 1255 { TEGRA30_CLK_DISP2, TEGRA30_CLK_PLL_P, 600000000, 0 }, 1256 { TEGRA30_CLK_TWD, TEGRA30_CLK_CLK_MAX, 0, 1 }, 1257 { TEGRA30_CLK_GR2D, TEGRA30_CLK_PLL_C, 300000000, 0 }, 1258 { TEGRA30_CLK_GR3D, TEGRA30_CLK_PLL_C, 300000000, 0 }, 1259 { TEGRA30_CLK_GR3D2, TEGRA30_CLK_PLL_C, 300000000, 0 }, 1260 { TEGRA30_CLK_PLL_U, TEGRA30_CLK_CLK_MAX, 480000000, 0 }, 1261 { TEGRA30_CLK_VDE, TEGRA30_CLK_CLK_MAX, 600000000, 0 }, 1262 { TEGRA30_CLK_SPDIF_IN_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 }, 1263 { TEGRA30_CLK_I2S0_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 }, 1264 { TEGRA30_CLK_I2S1_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 }, 1265 { TEGRA30_CLK_I2S2_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 }, 1266 { TEGRA30_CLK_I2S3_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 }, 1267 { TEGRA30_CLK_I2S4_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 }, 1268 { TEGRA30_CLK_VIMCLK_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 }, 1269 /* must be the last entry */ 1270 { TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0 }, 1271 }; 1272 1273 static void __init tegra30_clock_apply_init_table(void) 1274 { 1275 tegra_init_from_table(init_table, clks, TEGRA30_CLK_CLK_MAX); 1276 } 1277 1278 /* 1279 * Some clocks may be used by different drivers depending on the board 1280 * configuration. List those here to register them twice in the clock lookup 1281 * table under two names. 1282 */ 1283 static struct tegra_clk_duplicate tegra_clk_duplicates[] = { 1284 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_USBD, "utmip-pad", NULL), 1285 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_USBD, "tegra-ehci.0", NULL), 1286 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_USBD, "tegra-otg", NULL), 1287 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEV, "tegra-avp", "bsev"), 1288 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEV, "nvavp", "bsev"), 1289 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_VDE, "tegra-aes", "vde"), 1290 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEA, "tegra-aes", "bsea"), 1291 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEA, "nvavp", "bsea"), 1292 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CML1, "tegra_sata_cml", NULL), 1293 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CML0, "tegra_pcie", "cml"), 1294 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_VCP, "nvavp", "vcp"), 1295 /* must be the last entry */ 1296 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CLK_MAX, NULL, NULL), 1297 }; 1298 1299 static const struct of_device_id pmc_match[] __initconst = { 1300 { .compatible = "nvidia,tegra30-pmc" }, 1301 { }, 1302 }; 1303 1304 static struct tegra_audio_clk_info tegra30_audio_plls[] = { 1305 { "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_p_out1" }, 1306 }; 1307 1308 static struct clk *tegra30_clk_src_onecell_get(struct of_phandle_args *clkspec, 1309 void *data) 1310 { 1311 struct clk_hw *hw; 1312 struct clk *clk; 1313 1314 clk = of_clk_src_onecell_get(clkspec, data); 1315 if (IS_ERR(clk)) 1316 return clk; 1317 1318 hw = __clk_get_hw(clk); 1319 1320 if (clkspec->args[0] == TEGRA30_CLK_EMC) { 1321 if (!tegra20_clk_emc_driver_available(hw)) 1322 return ERR_PTR(-EPROBE_DEFER); 1323 } 1324 1325 return clk; 1326 } 1327 1328 static void __init tegra30_clock_init(struct device_node *np) 1329 { 1330 struct device_node *node; 1331 1332 clk_base = of_iomap(np, 0); 1333 if (!clk_base) { 1334 pr_err("ioremap tegra30 CAR failed\n"); 1335 return; 1336 } 1337 1338 node = of_find_matching_node(NULL, pmc_match); 1339 if (!node) { 1340 pr_err("Failed to find pmc node\n"); 1341 BUG(); 1342 } 1343 1344 pmc_base = of_iomap(node, 0); 1345 if (!pmc_base) { 1346 pr_err("Can't map pmc registers\n"); 1347 BUG(); 1348 } 1349 1350 clks = tegra_clk_init(clk_base, TEGRA30_CLK_CLK_MAX, 1351 TEGRA30_CLK_PERIPH_BANKS); 1352 if (!clks) 1353 return; 1354 1355 if (tegra_osc_clk_init(clk_base, tegra30_clks, tegra30_input_freq, 1356 ARRAY_SIZE(tegra30_input_freq), 1, &input_freq, 1357 NULL) < 0) 1358 return; 1359 1360 tegra_fixed_clk_init(tegra30_clks); 1361 tegra30_pll_init(); 1362 tegra30_super_clk_init(); 1363 tegra30_periph_clk_init(); 1364 tegra_audio_clk_init(clk_base, pmc_base, tegra30_clks, 1365 tegra30_audio_plls, 1366 ARRAY_SIZE(tegra30_audio_plls), 24000000); 1367 tegra_pmc_clk_init(pmc_base, tegra30_clks); 1368 1369 tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA30_CLK_CLK_MAX); 1370 1371 tegra_add_of_provider(np, tegra30_clk_src_onecell_get); 1372 tegra_register_devclks(devclks, ARRAY_SIZE(devclks)); 1373 1374 tegra_clk_apply_init_table = tegra30_clock_apply_init_table; 1375 1376 tegra_cpu_car_ops = &tegra30_cpu_car_ops; 1377 } 1378 CLK_OF_DECLARE(tegra30, "nvidia,tegra30-car", tegra30_clock_init); 1379