1*b4cbe606SNobuhiro Iwamatsu // SPDX-License-Identifier: GPL-2.0-only
2*b4cbe606SNobuhiro Iwamatsu /*
3*b4cbe606SNobuhiro Iwamatsu * Toshiba Visconti ARM SoC reset controller
4*b4cbe606SNobuhiro Iwamatsu *
5*b4cbe606SNobuhiro Iwamatsu * Copyright (c) 2021 TOSHIBA CORPORATION
6*b4cbe606SNobuhiro Iwamatsu * Copyright (c) 2021 Toshiba Electronic Devices & Storage Corporation
7*b4cbe606SNobuhiro Iwamatsu *
8*b4cbe606SNobuhiro Iwamatsu * Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
9*b4cbe606SNobuhiro Iwamatsu */
10*b4cbe606SNobuhiro Iwamatsu #include <linux/delay.h>
11*b4cbe606SNobuhiro Iwamatsu #include <linux/device.h>
12*b4cbe606SNobuhiro Iwamatsu #include <linux/mfd/syscon.h>
13*b4cbe606SNobuhiro Iwamatsu #include <linux/regmap.h>
14*b4cbe606SNobuhiro Iwamatsu #include <linux/slab.h>
15*b4cbe606SNobuhiro Iwamatsu
16*b4cbe606SNobuhiro Iwamatsu #include "reset.h"
17*b4cbe606SNobuhiro Iwamatsu
to_visconti_reset(struct reset_controller_dev * rcdev)18*b4cbe606SNobuhiro Iwamatsu static inline struct visconti_reset *to_visconti_reset(struct reset_controller_dev *rcdev)
19*b4cbe606SNobuhiro Iwamatsu {
20*b4cbe606SNobuhiro Iwamatsu return container_of(rcdev, struct visconti_reset, rcdev);
21*b4cbe606SNobuhiro Iwamatsu }
22*b4cbe606SNobuhiro Iwamatsu
visconti_reset_assert(struct reset_controller_dev * rcdev,unsigned long id)23*b4cbe606SNobuhiro Iwamatsu static int visconti_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
24*b4cbe606SNobuhiro Iwamatsu {
25*b4cbe606SNobuhiro Iwamatsu struct visconti_reset *reset = to_visconti_reset(rcdev);
26*b4cbe606SNobuhiro Iwamatsu const struct visconti_reset_data *data = &reset->resets[id];
27*b4cbe606SNobuhiro Iwamatsu u32 rst = BIT(data->rs_idx);
28*b4cbe606SNobuhiro Iwamatsu unsigned long flags;
29*b4cbe606SNobuhiro Iwamatsu int ret;
30*b4cbe606SNobuhiro Iwamatsu
31*b4cbe606SNobuhiro Iwamatsu spin_lock_irqsave(reset->lock, flags);
32*b4cbe606SNobuhiro Iwamatsu ret = regmap_update_bits(reset->regmap, data->rson_offset, rst, rst);
33*b4cbe606SNobuhiro Iwamatsu spin_unlock_irqrestore(reset->lock, flags);
34*b4cbe606SNobuhiro Iwamatsu
35*b4cbe606SNobuhiro Iwamatsu return ret;
36*b4cbe606SNobuhiro Iwamatsu }
37*b4cbe606SNobuhiro Iwamatsu
visconti_reset_deassert(struct reset_controller_dev * rcdev,unsigned long id)38*b4cbe606SNobuhiro Iwamatsu static int visconti_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
39*b4cbe606SNobuhiro Iwamatsu {
40*b4cbe606SNobuhiro Iwamatsu struct visconti_reset *reset = to_visconti_reset(rcdev);
41*b4cbe606SNobuhiro Iwamatsu const struct visconti_reset_data *data = &reset->resets[id];
42*b4cbe606SNobuhiro Iwamatsu u32 rst = BIT(data->rs_idx);
43*b4cbe606SNobuhiro Iwamatsu unsigned long flags;
44*b4cbe606SNobuhiro Iwamatsu int ret;
45*b4cbe606SNobuhiro Iwamatsu
46*b4cbe606SNobuhiro Iwamatsu spin_lock_irqsave(reset->lock, flags);
47*b4cbe606SNobuhiro Iwamatsu ret = regmap_update_bits(reset->regmap, data->rsoff_offset, rst, rst);
48*b4cbe606SNobuhiro Iwamatsu spin_unlock_irqrestore(reset->lock, flags);
49*b4cbe606SNobuhiro Iwamatsu
50*b4cbe606SNobuhiro Iwamatsu return ret;
51*b4cbe606SNobuhiro Iwamatsu }
52*b4cbe606SNobuhiro Iwamatsu
visconti_reset_reset(struct reset_controller_dev * rcdev,unsigned long id)53*b4cbe606SNobuhiro Iwamatsu static int visconti_reset_reset(struct reset_controller_dev *rcdev, unsigned long id)
54*b4cbe606SNobuhiro Iwamatsu {
55*b4cbe606SNobuhiro Iwamatsu visconti_reset_assert(rcdev, id);
56*b4cbe606SNobuhiro Iwamatsu udelay(1);
57*b4cbe606SNobuhiro Iwamatsu visconti_reset_deassert(rcdev, id);
58*b4cbe606SNobuhiro Iwamatsu
59*b4cbe606SNobuhiro Iwamatsu return 0;
60*b4cbe606SNobuhiro Iwamatsu }
61*b4cbe606SNobuhiro Iwamatsu
visconti_reset_status(struct reset_controller_dev * rcdev,unsigned long id)62*b4cbe606SNobuhiro Iwamatsu static int visconti_reset_status(struct reset_controller_dev *rcdev, unsigned long id)
63*b4cbe606SNobuhiro Iwamatsu {
64*b4cbe606SNobuhiro Iwamatsu struct visconti_reset *reset = to_visconti_reset(rcdev);
65*b4cbe606SNobuhiro Iwamatsu const struct visconti_reset_data *data = &reset->resets[id];
66*b4cbe606SNobuhiro Iwamatsu unsigned long flags;
67*b4cbe606SNobuhiro Iwamatsu u32 reg;
68*b4cbe606SNobuhiro Iwamatsu int ret;
69*b4cbe606SNobuhiro Iwamatsu
70*b4cbe606SNobuhiro Iwamatsu spin_lock_irqsave(reset->lock, flags);
71*b4cbe606SNobuhiro Iwamatsu ret = regmap_read(reset->regmap, data->rson_offset, ®);
72*b4cbe606SNobuhiro Iwamatsu spin_unlock_irqrestore(reset->lock, flags);
73*b4cbe606SNobuhiro Iwamatsu if (ret)
74*b4cbe606SNobuhiro Iwamatsu return ret;
75*b4cbe606SNobuhiro Iwamatsu
76*b4cbe606SNobuhiro Iwamatsu return !(reg & data->rs_idx);
77*b4cbe606SNobuhiro Iwamatsu }
78*b4cbe606SNobuhiro Iwamatsu
79*b4cbe606SNobuhiro Iwamatsu const struct reset_control_ops visconti_reset_ops = {
80*b4cbe606SNobuhiro Iwamatsu .assert = visconti_reset_assert,
81*b4cbe606SNobuhiro Iwamatsu .deassert = visconti_reset_deassert,
82*b4cbe606SNobuhiro Iwamatsu .reset = visconti_reset_reset,
83*b4cbe606SNobuhiro Iwamatsu .status = visconti_reset_status,
84*b4cbe606SNobuhiro Iwamatsu };
85*b4cbe606SNobuhiro Iwamatsu
visconti_register_reset_controller(struct device * dev,struct regmap * regmap,const struct visconti_reset_data * resets,unsigned int num_resets,const struct reset_control_ops * reset_ops,spinlock_t * lock)86*b4cbe606SNobuhiro Iwamatsu int visconti_register_reset_controller(struct device *dev,
87*b4cbe606SNobuhiro Iwamatsu struct regmap *regmap,
88*b4cbe606SNobuhiro Iwamatsu const struct visconti_reset_data *resets,
89*b4cbe606SNobuhiro Iwamatsu unsigned int num_resets,
90*b4cbe606SNobuhiro Iwamatsu const struct reset_control_ops *reset_ops,
91*b4cbe606SNobuhiro Iwamatsu spinlock_t *lock)
92*b4cbe606SNobuhiro Iwamatsu {
93*b4cbe606SNobuhiro Iwamatsu struct visconti_reset *reset;
94*b4cbe606SNobuhiro Iwamatsu
95*b4cbe606SNobuhiro Iwamatsu reset = devm_kzalloc(dev, sizeof(*reset), GFP_KERNEL);
96*b4cbe606SNobuhiro Iwamatsu if (!reset)
97*b4cbe606SNobuhiro Iwamatsu return -ENOMEM;
98*b4cbe606SNobuhiro Iwamatsu
99*b4cbe606SNobuhiro Iwamatsu reset->regmap = regmap;
100*b4cbe606SNobuhiro Iwamatsu reset->resets = resets;
101*b4cbe606SNobuhiro Iwamatsu reset->rcdev.ops = reset_ops;
102*b4cbe606SNobuhiro Iwamatsu reset->rcdev.nr_resets = num_resets;
103*b4cbe606SNobuhiro Iwamatsu reset->rcdev.of_node = dev->of_node;
104*b4cbe606SNobuhiro Iwamatsu reset->lock = lock;
105*b4cbe606SNobuhiro Iwamatsu
106*b4cbe606SNobuhiro Iwamatsu return devm_reset_controller_register(dev, &reset->rcdev);
107*b4cbe606SNobuhiro Iwamatsu }
108