1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SuperH Timer Support - CMT 4 * 5 * Copyright (C) 2008 Magnus Damm 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/clockchips.h> 10 #include <linux/clocksource.h> 11 #include <linux/delay.h> 12 #include <linux/err.h> 13 #include <linux/init.h> 14 #include <linux/interrupt.h> 15 #include <linux/io.h> 16 #include <linux/ioport.h> 17 #include <linux/irq.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/of_device.h> 21 #include <linux/platform_device.h> 22 #include <linux/pm_domain.h> 23 #include <linux/pm_runtime.h> 24 #include <linux/sh_timer.h> 25 #include <linux/slab.h> 26 #include <linux/spinlock.h> 27 28 #ifdef CONFIG_SUPERH 29 #include <asm/platform_early.h> 30 #endif 31 32 struct sh_cmt_device; 33 34 /* 35 * The CMT comes in 5 different identified flavours, depending not only on the 36 * SoC but also on the particular instance. The following table lists the main 37 * characteristics of those flavours. 38 * 39 * 16B 32B 32B-F 48B R-Car Gen2 40 * ----------------------------------------------------------------------------- 41 * Channels 2 1/4 1 6 2/8 42 * Control Width 16 16 16 16 32 43 * Counter Width 16 32 32 32/48 32/48 44 * Shared Start/Stop Y Y Y Y N 45 * 46 * The r8a73a4 / R-Car Gen2 version has a per-channel start/stop register 47 * located in the channel registers block. All other versions have a shared 48 * start/stop register located in the global space. 49 * 50 * Channels are indexed from 0 to N-1 in the documentation. The channel index 51 * infers the start/stop bit position in the control register and the channel 52 * registers block address. Some CMT instances have a subset of channels 53 * available, in which case the index in the documentation doesn't match the 54 * "real" index as implemented in hardware. This is for instance the case with 55 * CMT0 on r8a7740, which is a 32-bit variant with a single channel numbered 0 56 * in the documentation but using start/stop bit 5 and having its registers 57 * block at 0x60. 58 * 59 * Similarly CMT0 on r8a73a4, r8a7790 and r8a7791, while implementing 32-bit 60 * channels only, is a 48-bit gen2 CMT with the 48-bit channels unavailable. 61 */ 62 63 enum sh_cmt_model { 64 SH_CMT_16BIT, 65 SH_CMT_32BIT, 66 SH_CMT_48BIT, 67 SH_CMT0_RCAR_GEN2, 68 SH_CMT1_RCAR_GEN2, 69 }; 70 71 struct sh_cmt_info { 72 enum sh_cmt_model model; 73 74 unsigned int channels_mask; 75 76 unsigned long width; /* 16 or 32 bit version of hardware block */ 77 u32 overflow_bit; 78 u32 clear_bits; 79 80 /* callbacks for CMSTR and CMCSR access */ 81 u32 (*read_control)(void __iomem *base, unsigned long offs); 82 void (*write_control)(void __iomem *base, unsigned long offs, 83 u32 value); 84 85 /* callbacks for CMCNT and CMCOR access */ 86 u32 (*read_count)(void __iomem *base, unsigned long offs); 87 void (*write_count)(void __iomem *base, unsigned long offs, u32 value); 88 }; 89 90 struct sh_cmt_channel { 91 struct sh_cmt_device *cmt; 92 93 unsigned int index; /* Index in the documentation */ 94 unsigned int hwidx; /* Real hardware index */ 95 96 void __iomem *iostart; 97 void __iomem *ioctrl; 98 99 unsigned int timer_bit; 100 unsigned long flags; 101 u32 match_value; 102 u32 next_match_value; 103 u32 max_match_value; 104 raw_spinlock_t lock; 105 struct clock_event_device ced; 106 struct clocksource cs; 107 u64 total_cycles; 108 bool cs_enabled; 109 }; 110 111 struct sh_cmt_device { 112 struct platform_device *pdev; 113 114 const struct sh_cmt_info *info; 115 116 void __iomem *mapbase; 117 struct clk *clk; 118 unsigned long rate; 119 120 raw_spinlock_t lock; /* Protect the shared start/stop register */ 121 122 struct sh_cmt_channel *channels; 123 unsigned int num_channels; 124 unsigned int hw_channels; 125 126 bool has_clockevent; 127 bool has_clocksource; 128 }; 129 130 #define SH_CMT16_CMCSR_CMF (1 << 7) 131 #define SH_CMT16_CMCSR_CMIE (1 << 6) 132 #define SH_CMT16_CMCSR_CKS8 (0 << 0) 133 #define SH_CMT16_CMCSR_CKS32 (1 << 0) 134 #define SH_CMT16_CMCSR_CKS128 (2 << 0) 135 #define SH_CMT16_CMCSR_CKS512 (3 << 0) 136 #define SH_CMT16_CMCSR_CKS_MASK (3 << 0) 137 138 #define SH_CMT32_CMCSR_CMF (1 << 15) 139 #define SH_CMT32_CMCSR_OVF (1 << 14) 140 #define SH_CMT32_CMCSR_WRFLG (1 << 13) 141 #define SH_CMT32_CMCSR_STTF (1 << 12) 142 #define SH_CMT32_CMCSR_STPF (1 << 11) 143 #define SH_CMT32_CMCSR_SSIE (1 << 10) 144 #define SH_CMT32_CMCSR_CMS (1 << 9) 145 #define SH_CMT32_CMCSR_CMM (1 << 8) 146 #define SH_CMT32_CMCSR_CMTOUT_IE (1 << 7) 147 #define SH_CMT32_CMCSR_CMR_NONE (0 << 4) 148 #define SH_CMT32_CMCSR_CMR_DMA (1 << 4) 149 #define SH_CMT32_CMCSR_CMR_IRQ (2 << 4) 150 #define SH_CMT32_CMCSR_CMR_MASK (3 << 4) 151 #define SH_CMT32_CMCSR_DBGIVD (1 << 3) 152 #define SH_CMT32_CMCSR_CKS_RCLK8 (4 << 0) 153 #define SH_CMT32_CMCSR_CKS_RCLK32 (5 << 0) 154 #define SH_CMT32_CMCSR_CKS_RCLK128 (6 << 0) 155 #define SH_CMT32_CMCSR_CKS_RCLK1 (7 << 0) 156 #define SH_CMT32_CMCSR_CKS_MASK (7 << 0) 157 158 static u32 sh_cmt_read16(void __iomem *base, unsigned long offs) 159 { 160 return ioread16(base + (offs << 1)); 161 } 162 163 static u32 sh_cmt_read32(void __iomem *base, unsigned long offs) 164 { 165 return ioread32(base + (offs << 2)); 166 } 167 168 static void sh_cmt_write16(void __iomem *base, unsigned long offs, u32 value) 169 { 170 iowrite16(value, base + (offs << 1)); 171 } 172 173 static void sh_cmt_write32(void __iomem *base, unsigned long offs, u32 value) 174 { 175 iowrite32(value, base + (offs << 2)); 176 } 177 178 static const struct sh_cmt_info sh_cmt_info[] = { 179 [SH_CMT_16BIT] = { 180 .model = SH_CMT_16BIT, 181 .width = 16, 182 .overflow_bit = SH_CMT16_CMCSR_CMF, 183 .clear_bits = ~SH_CMT16_CMCSR_CMF, 184 .read_control = sh_cmt_read16, 185 .write_control = sh_cmt_write16, 186 .read_count = sh_cmt_read16, 187 .write_count = sh_cmt_write16, 188 }, 189 [SH_CMT_32BIT] = { 190 .model = SH_CMT_32BIT, 191 .width = 32, 192 .overflow_bit = SH_CMT32_CMCSR_CMF, 193 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), 194 .read_control = sh_cmt_read16, 195 .write_control = sh_cmt_write16, 196 .read_count = sh_cmt_read32, 197 .write_count = sh_cmt_write32, 198 }, 199 [SH_CMT_48BIT] = { 200 .model = SH_CMT_48BIT, 201 .channels_mask = 0x3f, 202 .width = 32, 203 .overflow_bit = SH_CMT32_CMCSR_CMF, 204 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), 205 .read_control = sh_cmt_read32, 206 .write_control = sh_cmt_write32, 207 .read_count = sh_cmt_read32, 208 .write_count = sh_cmt_write32, 209 }, 210 [SH_CMT0_RCAR_GEN2] = { 211 .model = SH_CMT0_RCAR_GEN2, 212 .channels_mask = 0x60, 213 .width = 32, 214 .overflow_bit = SH_CMT32_CMCSR_CMF, 215 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), 216 .read_control = sh_cmt_read32, 217 .write_control = sh_cmt_write32, 218 .read_count = sh_cmt_read32, 219 .write_count = sh_cmt_write32, 220 }, 221 [SH_CMT1_RCAR_GEN2] = { 222 .model = SH_CMT1_RCAR_GEN2, 223 .channels_mask = 0xff, 224 .width = 32, 225 .overflow_bit = SH_CMT32_CMCSR_CMF, 226 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), 227 .read_control = sh_cmt_read32, 228 .write_control = sh_cmt_write32, 229 .read_count = sh_cmt_read32, 230 .write_count = sh_cmt_write32, 231 }, 232 }; 233 234 #define CMCSR 0 /* channel register */ 235 #define CMCNT 1 /* channel register */ 236 #define CMCOR 2 /* channel register */ 237 238 #define CMCLKE 0x1000 /* CLK Enable Register (R-Car Gen2) */ 239 240 static inline u32 sh_cmt_read_cmstr(struct sh_cmt_channel *ch) 241 { 242 if (ch->iostart) 243 return ch->cmt->info->read_control(ch->iostart, 0); 244 else 245 return ch->cmt->info->read_control(ch->cmt->mapbase, 0); 246 } 247 248 static inline void sh_cmt_write_cmstr(struct sh_cmt_channel *ch, u32 value) 249 { 250 if (ch->iostart) 251 ch->cmt->info->write_control(ch->iostart, 0, value); 252 else 253 ch->cmt->info->write_control(ch->cmt->mapbase, 0, value); 254 } 255 256 static inline u32 sh_cmt_read_cmcsr(struct sh_cmt_channel *ch) 257 { 258 return ch->cmt->info->read_control(ch->ioctrl, CMCSR); 259 } 260 261 static inline void sh_cmt_write_cmcsr(struct sh_cmt_channel *ch, u32 value) 262 { 263 ch->cmt->info->write_control(ch->ioctrl, CMCSR, value); 264 } 265 266 static inline u32 sh_cmt_read_cmcnt(struct sh_cmt_channel *ch) 267 { 268 return ch->cmt->info->read_count(ch->ioctrl, CMCNT); 269 } 270 271 static inline void sh_cmt_write_cmcnt(struct sh_cmt_channel *ch, u32 value) 272 { 273 ch->cmt->info->write_count(ch->ioctrl, CMCNT, value); 274 } 275 276 static inline void sh_cmt_write_cmcor(struct sh_cmt_channel *ch, u32 value) 277 { 278 ch->cmt->info->write_count(ch->ioctrl, CMCOR, value); 279 } 280 281 static u32 sh_cmt_get_counter(struct sh_cmt_channel *ch, u32 *has_wrapped) 282 { 283 u32 v1, v2, v3; 284 u32 o1, o2; 285 286 o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit; 287 288 /* Make sure the timer value is stable. Stolen from acpi_pm.c */ 289 do { 290 o2 = o1; 291 v1 = sh_cmt_read_cmcnt(ch); 292 v2 = sh_cmt_read_cmcnt(ch); 293 v3 = sh_cmt_read_cmcnt(ch); 294 o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit; 295 } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3) 296 || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2))); 297 298 *has_wrapped = o1; 299 return v2; 300 } 301 302 static void sh_cmt_start_stop_ch(struct sh_cmt_channel *ch, int start) 303 { 304 unsigned long flags; 305 u32 value; 306 307 /* start stop register shared by multiple timer channels */ 308 raw_spin_lock_irqsave(&ch->cmt->lock, flags); 309 value = sh_cmt_read_cmstr(ch); 310 311 if (start) 312 value |= 1 << ch->timer_bit; 313 else 314 value &= ~(1 << ch->timer_bit); 315 316 sh_cmt_write_cmstr(ch, value); 317 raw_spin_unlock_irqrestore(&ch->cmt->lock, flags); 318 } 319 320 static int sh_cmt_enable(struct sh_cmt_channel *ch) 321 { 322 int k, ret; 323 324 dev_pm_syscore_device(&ch->cmt->pdev->dev, true); 325 326 /* enable clock */ 327 ret = clk_enable(ch->cmt->clk); 328 if (ret) { 329 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot enable clock\n", 330 ch->index); 331 goto err0; 332 } 333 334 /* make sure channel is disabled */ 335 sh_cmt_start_stop_ch(ch, 0); 336 337 /* configure channel, periodic mode and maximum timeout */ 338 if (ch->cmt->info->width == 16) { 339 sh_cmt_write_cmcsr(ch, SH_CMT16_CMCSR_CMIE | 340 SH_CMT16_CMCSR_CKS512); 341 } else { 342 u32 cmtout = ch->cmt->info->model <= SH_CMT_48BIT ? 343 SH_CMT32_CMCSR_CMTOUT_IE : 0; 344 sh_cmt_write_cmcsr(ch, cmtout | SH_CMT32_CMCSR_CMM | 345 SH_CMT32_CMCSR_CMR_IRQ | 346 SH_CMT32_CMCSR_CKS_RCLK8); 347 } 348 349 sh_cmt_write_cmcor(ch, 0xffffffff); 350 sh_cmt_write_cmcnt(ch, 0); 351 352 /* 353 * According to the sh73a0 user's manual, as CMCNT can be operated 354 * only by the RCLK (Pseudo 32 kHz), there's one restriction on 355 * modifying CMCNT register; two RCLK cycles are necessary before 356 * this register is either read or any modification of the value 357 * it holds is reflected in the LSI's actual operation. 358 * 359 * While at it, we're supposed to clear out the CMCNT as of this 360 * moment, so make sure it's processed properly here. This will 361 * take RCLKx2 at maximum. 362 */ 363 for (k = 0; k < 100; k++) { 364 if (!sh_cmt_read_cmcnt(ch)) 365 break; 366 udelay(1); 367 } 368 369 if (sh_cmt_read_cmcnt(ch)) { 370 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot clear CMCNT\n", 371 ch->index); 372 ret = -ETIMEDOUT; 373 goto err1; 374 } 375 376 /* enable channel */ 377 sh_cmt_start_stop_ch(ch, 1); 378 return 0; 379 err1: 380 /* stop clock */ 381 clk_disable(ch->cmt->clk); 382 383 err0: 384 return ret; 385 } 386 387 static void sh_cmt_disable(struct sh_cmt_channel *ch) 388 { 389 /* disable channel */ 390 sh_cmt_start_stop_ch(ch, 0); 391 392 /* disable interrupts in CMT block */ 393 sh_cmt_write_cmcsr(ch, 0); 394 395 /* stop clock */ 396 clk_disable(ch->cmt->clk); 397 398 dev_pm_syscore_device(&ch->cmt->pdev->dev, false); 399 } 400 401 /* private flags */ 402 #define FLAG_CLOCKEVENT (1 << 0) 403 #define FLAG_CLOCKSOURCE (1 << 1) 404 #define FLAG_REPROGRAM (1 << 2) 405 #define FLAG_SKIPEVENT (1 << 3) 406 #define FLAG_IRQCONTEXT (1 << 4) 407 408 static void sh_cmt_clock_event_program_verify(struct sh_cmt_channel *ch, 409 int absolute) 410 { 411 u32 value = ch->next_match_value; 412 u32 new_match; 413 u32 delay = 0; 414 u32 now = 0; 415 u32 has_wrapped; 416 417 now = sh_cmt_get_counter(ch, &has_wrapped); 418 ch->flags |= FLAG_REPROGRAM; /* force reprogram */ 419 420 if (has_wrapped) { 421 /* we're competing with the interrupt handler. 422 * -> let the interrupt handler reprogram the timer. 423 * -> interrupt number two handles the event. 424 */ 425 ch->flags |= FLAG_SKIPEVENT; 426 return; 427 } 428 429 if (absolute) 430 now = 0; 431 432 do { 433 /* reprogram the timer hardware, 434 * but don't save the new match value yet. 435 */ 436 new_match = now + value + delay; 437 if (new_match > ch->max_match_value) 438 new_match = ch->max_match_value; 439 440 sh_cmt_write_cmcor(ch, new_match); 441 442 now = sh_cmt_get_counter(ch, &has_wrapped); 443 if (has_wrapped && (new_match > ch->match_value)) { 444 /* we are changing to a greater match value, 445 * so this wrap must be caused by the counter 446 * matching the old value. 447 * -> first interrupt reprograms the timer. 448 * -> interrupt number two handles the event. 449 */ 450 ch->flags |= FLAG_SKIPEVENT; 451 break; 452 } 453 454 if (has_wrapped) { 455 /* we are changing to a smaller match value, 456 * so the wrap must be caused by the counter 457 * matching the new value. 458 * -> save programmed match value. 459 * -> let isr handle the event. 460 */ 461 ch->match_value = new_match; 462 break; 463 } 464 465 /* be safe: verify hardware settings */ 466 if (now < new_match) { 467 /* timer value is below match value, all good. 468 * this makes sure we won't miss any match events. 469 * -> save programmed match value. 470 * -> let isr handle the event. 471 */ 472 ch->match_value = new_match; 473 break; 474 } 475 476 /* the counter has reached a value greater 477 * than our new match value. and since the 478 * has_wrapped flag isn't set we must have 479 * programmed a too close event. 480 * -> increase delay and retry. 481 */ 482 if (delay) 483 delay <<= 1; 484 else 485 delay = 1; 486 487 if (!delay) 488 dev_warn(&ch->cmt->pdev->dev, "ch%u: too long delay\n", 489 ch->index); 490 491 } while (delay); 492 } 493 494 static void __sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta) 495 { 496 if (delta > ch->max_match_value) 497 dev_warn(&ch->cmt->pdev->dev, "ch%u: delta out of range\n", 498 ch->index); 499 500 ch->next_match_value = delta; 501 sh_cmt_clock_event_program_verify(ch, 0); 502 } 503 504 static void sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta) 505 { 506 unsigned long flags; 507 508 raw_spin_lock_irqsave(&ch->lock, flags); 509 __sh_cmt_set_next(ch, delta); 510 raw_spin_unlock_irqrestore(&ch->lock, flags); 511 } 512 513 static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id) 514 { 515 struct sh_cmt_channel *ch = dev_id; 516 517 /* clear flags */ 518 sh_cmt_write_cmcsr(ch, sh_cmt_read_cmcsr(ch) & 519 ch->cmt->info->clear_bits); 520 521 /* update clock source counter to begin with if enabled 522 * the wrap flag should be cleared by the timer specific 523 * isr before we end up here. 524 */ 525 if (ch->flags & FLAG_CLOCKSOURCE) 526 ch->total_cycles += ch->match_value + 1; 527 528 if (!(ch->flags & FLAG_REPROGRAM)) 529 ch->next_match_value = ch->max_match_value; 530 531 ch->flags |= FLAG_IRQCONTEXT; 532 533 if (ch->flags & FLAG_CLOCKEVENT) { 534 if (!(ch->flags & FLAG_SKIPEVENT)) { 535 if (clockevent_state_oneshot(&ch->ced)) { 536 ch->next_match_value = ch->max_match_value; 537 ch->flags |= FLAG_REPROGRAM; 538 } 539 540 ch->ced.event_handler(&ch->ced); 541 } 542 } 543 544 ch->flags &= ~FLAG_SKIPEVENT; 545 546 if (ch->flags & FLAG_REPROGRAM) { 547 ch->flags &= ~FLAG_REPROGRAM; 548 sh_cmt_clock_event_program_verify(ch, 1); 549 550 if (ch->flags & FLAG_CLOCKEVENT) 551 if ((clockevent_state_shutdown(&ch->ced)) 552 || (ch->match_value == ch->next_match_value)) 553 ch->flags &= ~FLAG_REPROGRAM; 554 } 555 556 ch->flags &= ~FLAG_IRQCONTEXT; 557 558 return IRQ_HANDLED; 559 } 560 561 static int sh_cmt_start(struct sh_cmt_channel *ch, unsigned long flag) 562 { 563 int ret = 0; 564 unsigned long flags; 565 566 if (flag & FLAG_CLOCKSOURCE) 567 pm_runtime_get_sync(&ch->cmt->pdev->dev); 568 569 raw_spin_lock_irqsave(&ch->lock, flags); 570 571 if (!(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) { 572 if (flag & FLAG_CLOCKEVENT) 573 pm_runtime_get_sync(&ch->cmt->pdev->dev); 574 ret = sh_cmt_enable(ch); 575 } 576 577 if (ret) 578 goto out; 579 ch->flags |= flag; 580 581 /* setup timeout if no clockevent */ 582 if (ch->cmt->num_channels == 1 && 583 flag == FLAG_CLOCKSOURCE && (!(ch->flags & FLAG_CLOCKEVENT))) 584 __sh_cmt_set_next(ch, ch->max_match_value); 585 out: 586 raw_spin_unlock_irqrestore(&ch->lock, flags); 587 588 return ret; 589 } 590 591 static void sh_cmt_stop(struct sh_cmt_channel *ch, unsigned long flag) 592 { 593 unsigned long flags; 594 unsigned long f; 595 596 raw_spin_lock_irqsave(&ch->lock, flags); 597 598 f = ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE); 599 ch->flags &= ~flag; 600 601 if (f && !(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) { 602 sh_cmt_disable(ch); 603 if (flag & FLAG_CLOCKEVENT) 604 pm_runtime_put(&ch->cmt->pdev->dev); 605 } 606 607 /* adjust the timeout to maximum if only clocksource left */ 608 if ((flag == FLAG_CLOCKEVENT) && (ch->flags & FLAG_CLOCKSOURCE)) 609 __sh_cmt_set_next(ch, ch->max_match_value); 610 611 raw_spin_unlock_irqrestore(&ch->lock, flags); 612 613 if (flag & FLAG_CLOCKSOURCE) 614 pm_runtime_put(&ch->cmt->pdev->dev); 615 } 616 617 static struct sh_cmt_channel *cs_to_sh_cmt(struct clocksource *cs) 618 { 619 return container_of(cs, struct sh_cmt_channel, cs); 620 } 621 622 static u64 sh_cmt_clocksource_read(struct clocksource *cs) 623 { 624 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); 625 u32 has_wrapped; 626 627 if (ch->cmt->num_channels == 1) { 628 unsigned long flags; 629 u64 value; 630 u32 raw; 631 632 raw_spin_lock_irqsave(&ch->lock, flags); 633 value = ch->total_cycles; 634 raw = sh_cmt_get_counter(ch, &has_wrapped); 635 636 if (unlikely(has_wrapped)) 637 raw += ch->match_value + 1; 638 raw_spin_unlock_irqrestore(&ch->lock, flags); 639 640 return value + raw; 641 } 642 643 return sh_cmt_get_counter(ch, &has_wrapped); 644 } 645 646 static int sh_cmt_clocksource_enable(struct clocksource *cs) 647 { 648 int ret; 649 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); 650 651 WARN_ON(ch->cs_enabled); 652 653 ch->total_cycles = 0; 654 655 ret = sh_cmt_start(ch, FLAG_CLOCKSOURCE); 656 if (!ret) 657 ch->cs_enabled = true; 658 659 return ret; 660 } 661 662 static void sh_cmt_clocksource_disable(struct clocksource *cs) 663 { 664 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); 665 666 WARN_ON(!ch->cs_enabled); 667 668 sh_cmt_stop(ch, FLAG_CLOCKSOURCE); 669 ch->cs_enabled = false; 670 } 671 672 static void sh_cmt_clocksource_suspend(struct clocksource *cs) 673 { 674 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); 675 676 if (!ch->cs_enabled) 677 return; 678 679 sh_cmt_stop(ch, FLAG_CLOCKSOURCE); 680 dev_pm_genpd_suspend(&ch->cmt->pdev->dev); 681 } 682 683 static void sh_cmt_clocksource_resume(struct clocksource *cs) 684 { 685 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); 686 687 if (!ch->cs_enabled) 688 return; 689 690 dev_pm_genpd_resume(&ch->cmt->pdev->dev); 691 sh_cmt_start(ch, FLAG_CLOCKSOURCE); 692 } 693 694 static int sh_cmt_register_clocksource(struct sh_cmt_channel *ch, 695 const char *name) 696 { 697 struct clocksource *cs = &ch->cs; 698 699 cs->name = name; 700 cs->rating = 125; 701 cs->read = sh_cmt_clocksource_read; 702 cs->enable = sh_cmt_clocksource_enable; 703 cs->disable = sh_cmt_clocksource_disable; 704 cs->suspend = sh_cmt_clocksource_suspend; 705 cs->resume = sh_cmt_clocksource_resume; 706 cs->mask = CLOCKSOURCE_MASK(ch->cmt->info->width); 707 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS; 708 709 dev_info(&ch->cmt->pdev->dev, "ch%u: used as clock source\n", 710 ch->index); 711 712 clocksource_register_hz(cs, ch->cmt->rate); 713 return 0; 714 } 715 716 static struct sh_cmt_channel *ced_to_sh_cmt(struct clock_event_device *ced) 717 { 718 return container_of(ced, struct sh_cmt_channel, ced); 719 } 720 721 static void sh_cmt_clock_event_start(struct sh_cmt_channel *ch, int periodic) 722 { 723 sh_cmt_start(ch, FLAG_CLOCKEVENT); 724 725 if (periodic) 726 sh_cmt_set_next(ch, ((ch->cmt->rate + HZ/2) / HZ) - 1); 727 else 728 sh_cmt_set_next(ch, ch->max_match_value); 729 } 730 731 static int sh_cmt_clock_event_shutdown(struct clock_event_device *ced) 732 { 733 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); 734 735 sh_cmt_stop(ch, FLAG_CLOCKEVENT); 736 return 0; 737 } 738 739 static int sh_cmt_clock_event_set_state(struct clock_event_device *ced, 740 int periodic) 741 { 742 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); 743 744 /* deal with old setting first */ 745 if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced)) 746 sh_cmt_stop(ch, FLAG_CLOCKEVENT); 747 748 dev_info(&ch->cmt->pdev->dev, "ch%u: used for %s clock events\n", 749 ch->index, periodic ? "periodic" : "oneshot"); 750 sh_cmt_clock_event_start(ch, periodic); 751 return 0; 752 } 753 754 static int sh_cmt_clock_event_set_oneshot(struct clock_event_device *ced) 755 { 756 return sh_cmt_clock_event_set_state(ced, 0); 757 } 758 759 static int sh_cmt_clock_event_set_periodic(struct clock_event_device *ced) 760 { 761 return sh_cmt_clock_event_set_state(ced, 1); 762 } 763 764 static int sh_cmt_clock_event_next(unsigned long delta, 765 struct clock_event_device *ced) 766 { 767 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); 768 769 BUG_ON(!clockevent_state_oneshot(ced)); 770 if (likely(ch->flags & FLAG_IRQCONTEXT)) 771 ch->next_match_value = delta - 1; 772 else 773 sh_cmt_set_next(ch, delta - 1); 774 775 return 0; 776 } 777 778 static void sh_cmt_clock_event_suspend(struct clock_event_device *ced) 779 { 780 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); 781 782 dev_pm_genpd_suspend(&ch->cmt->pdev->dev); 783 clk_unprepare(ch->cmt->clk); 784 } 785 786 static void sh_cmt_clock_event_resume(struct clock_event_device *ced) 787 { 788 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); 789 790 clk_prepare(ch->cmt->clk); 791 dev_pm_genpd_resume(&ch->cmt->pdev->dev); 792 } 793 794 static int sh_cmt_register_clockevent(struct sh_cmt_channel *ch, 795 const char *name) 796 { 797 struct clock_event_device *ced = &ch->ced; 798 int irq; 799 int ret; 800 801 irq = platform_get_irq(ch->cmt->pdev, ch->index); 802 if (irq < 0) 803 return irq; 804 805 ret = request_irq(irq, sh_cmt_interrupt, 806 IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING, 807 dev_name(&ch->cmt->pdev->dev), ch); 808 if (ret) { 809 dev_err(&ch->cmt->pdev->dev, "ch%u: failed to request irq %d\n", 810 ch->index, irq); 811 return ret; 812 } 813 814 ced->name = name; 815 ced->features = CLOCK_EVT_FEAT_PERIODIC; 816 ced->features |= CLOCK_EVT_FEAT_ONESHOT; 817 ced->rating = 125; 818 ced->cpumask = cpu_possible_mask; 819 ced->set_next_event = sh_cmt_clock_event_next; 820 ced->set_state_shutdown = sh_cmt_clock_event_shutdown; 821 ced->set_state_periodic = sh_cmt_clock_event_set_periodic; 822 ced->set_state_oneshot = sh_cmt_clock_event_set_oneshot; 823 ced->suspend = sh_cmt_clock_event_suspend; 824 ced->resume = sh_cmt_clock_event_resume; 825 826 /* TODO: calculate good shift from rate and counter bit width */ 827 ced->shift = 32; 828 ced->mult = div_sc(ch->cmt->rate, NSEC_PER_SEC, ced->shift); 829 ced->max_delta_ns = clockevent_delta2ns(ch->max_match_value, ced); 830 ced->max_delta_ticks = ch->max_match_value; 831 ced->min_delta_ns = clockevent_delta2ns(0x1f, ced); 832 ced->min_delta_ticks = 0x1f; 833 834 dev_info(&ch->cmt->pdev->dev, "ch%u: used for clock events\n", 835 ch->index); 836 clockevents_register_device(ced); 837 838 return 0; 839 } 840 841 static int sh_cmt_register(struct sh_cmt_channel *ch, const char *name, 842 bool clockevent, bool clocksource) 843 { 844 int ret; 845 846 if (clockevent) { 847 ch->cmt->has_clockevent = true; 848 ret = sh_cmt_register_clockevent(ch, name); 849 if (ret < 0) 850 return ret; 851 } 852 853 if (clocksource) { 854 ch->cmt->has_clocksource = true; 855 sh_cmt_register_clocksource(ch, name); 856 } 857 858 return 0; 859 } 860 861 static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index, 862 unsigned int hwidx, bool clockevent, 863 bool clocksource, struct sh_cmt_device *cmt) 864 { 865 u32 value; 866 int ret; 867 868 /* Skip unused channels. */ 869 if (!clockevent && !clocksource) 870 return 0; 871 872 ch->cmt = cmt; 873 ch->index = index; 874 ch->hwidx = hwidx; 875 ch->timer_bit = hwidx; 876 877 /* 878 * Compute the address of the channel control register block. For the 879 * timers with a per-channel start/stop register, compute its address 880 * as well. 881 */ 882 switch (cmt->info->model) { 883 case SH_CMT_16BIT: 884 ch->ioctrl = cmt->mapbase + 2 + ch->hwidx * 6; 885 break; 886 case SH_CMT_32BIT: 887 case SH_CMT_48BIT: 888 ch->ioctrl = cmt->mapbase + 0x10 + ch->hwidx * 0x10; 889 break; 890 case SH_CMT0_RCAR_GEN2: 891 case SH_CMT1_RCAR_GEN2: 892 ch->iostart = cmt->mapbase + ch->hwidx * 0x100; 893 ch->ioctrl = ch->iostart + 0x10; 894 ch->timer_bit = 0; 895 896 /* Enable the clock supply to the channel */ 897 value = ioread32(cmt->mapbase + CMCLKE); 898 value |= BIT(hwidx); 899 iowrite32(value, cmt->mapbase + CMCLKE); 900 break; 901 } 902 903 if (cmt->info->width == (sizeof(ch->max_match_value) * 8)) 904 ch->max_match_value = ~0; 905 else 906 ch->max_match_value = (1 << cmt->info->width) - 1; 907 908 ch->match_value = ch->max_match_value; 909 raw_spin_lock_init(&ch->lock); 910 911 ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev), 912 clockevent, clocksource); 913 if (ret) { 914 dev_err(&cmt->pdev->dev, "ch%u: registration failed\n", 915 ch->index); 916 return ret; 917 } 918 ch->cs_enabled = false; 919 920 return 0; 921 } 922 923 static int sh_cmt_map_memory(struct sh_cmt_device *cmt) 924 { 925 struct resource *mem; 926 927 mem = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 0); 928 if (!mem) { 929 dev_err(&cmt->pdev->dev, "failed to get I/O memory\n"); 930 return -ENXIO; 931 } 932 933 cmt->mapbase = ioremap(mem->start, resource_size(mem)); 934 if (cmt->mapbase == NULL) { 935 dev_err(&cmt->pdev->dev, "failed to remap I/O memory\n"); 936 return -ENXIO; 937 } 938 939 return 0; 940 } 941 942 static const struct platform_device_id sh_cmt_id_table[] = { 943 { "sh-cmt-16", (kernel_ulong_t)&sh_cmt_info[SH_CMT_16BIT] }, 944 { "sh-cmt-32", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT] }, 945 { } 946 }; 947 MODULE_DEVICE_TABLE(platform, sh_cmt_id_table); 948 949 static const struct of_device_id sh_cmt_of_table[] __maybe_unused = { 950 { 951 /* deprecated, preserved for backward compatibility */ 952 .compatible = "renesas,cmt-48", 953 .data = &sh_cmt_info[SH_CMT_48BIT] 954 }, 955 { 956 /* deprecated, preserved for backward compatibility */ 957 .compatible = "renesas,cmt-48-gen2", 958 .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2] 959 }, 960 { 961 .compatible = "renesas,r8a7740-cmt1", 962 .data = &sh_cmt_info[SH_CMT_48BIT] 963 }, 964 { 965 .compatible = "renesas,sh73a0-cmt1", 966 .data = &sh_cmt_info[SH_CMT_48BIT] 967 }, 968 { 969 .compatible = "renesas,rcar-gen2-cmt0", 970 .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2] 971 }, 972 { 973 .compatible = "renesas,rcar-gen2-cmt1", 974 .data = &sh_cmt_info[SH_CMT1_RCAR_GEN2] 975 }, 976 { 977 .compatible = "renesas,rcar-gen3-cmt0", 978 .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2] 979 }, 980 { 981 .compatible = "renesas,rcar-gen3-cmt1", 982 .data = &sh_cmt_info[SH_CMT1_RCAR_GEN2] 983 }, 984 { 985 .compatible = "renesas,rcar-gen4-cmt0", 986 .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2] 987 }, 988 { 989 .compatible = "renesas,rcar-gen4-cmt1", 990 .data = &sh_cmt_info[SH_CMT1_RCAR_GEN2] 991 }, 992 { } 993 }; 994 MODULE_DEVICE_TABLE(of, sh_cmt_of_table); 995 996 static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev) 997 { 998 unsigned int mask; 999 unsigned int i; 1000 int ret; 1001 1002 cmt->pdev = pdev; 1003 raw_spin_lock_init(&cmt->lock); 1004 1005 if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) { 1006 cmt->info = of_device_get_match_data(&pdev->dev); 1007 cmt->hw_channels = cmt->info->channels_mask; 1008 } else if (pdev->dev.platform_data) { 1009 struct sh_timer_config *cfg = pdev->dev.platform_data; 1010 const struct platform_device_id *id = pdev->id_entry; 1011 1012 cmt->info = (const struct sh_cmt_info *)id->driver_data; 1013 cmt->hw_channels = cfg->channels_mask; 1014 } else { 1015 dev_err(&cmt->pdev->dev, "missing platform data\n"); 1016 return -ENXIO; 1017 } 1018 1019 /* Get hold of clock. */ 1020 cmt->clk = clk_get(&cmt->pdev->dev, "fck"); 1021 if (IS_ERR(cmt->clk)) { 1022 dev_err(&cmt->pdev->dev, "cannot get clock\n"); 1023 return PTR_ERR(cmt->clk); 1024 } 1025 1026 ret = clk_prepare(cmt->clk); 1027 if (ret < 0) 1028 goto err_clk_put; 1029 1030 /* Determine clock rate. */ 1031 ret = clk_enable(cmt->clk); 1032 if (ret < 0) 1033 goto err_clk_unprepare; 1034 1035 if (cmt->info->width == 16) 1036 cmt->rate = clk_get_rate(cmt->clk) / 512; 1037 else 1038 cmt->rate = clk_get_rate(cmt->clk) / 8; 1039 1040 /* Map the memory resource(s). */ 1041 ret = sh_cmt_map_memory(cmt); 1042 if (ret < 0) 1043 goto err_clk_disable; 1044 1045 /* Allocate and setup the channels. */ 1046 cmt->num_channels = hweight8(cmt->hw_channels); 1047 cmt->channels = kcalloc(cmt->num_channels, sizeof(*cmt->channels), 1048 GFP_KERNEL); 1049 if (cmt->channels == NULL) { 1050 ret = -ENOMEM; 1051 goto err_unmap; 1052 } 1053 1054 /* 1055 * Use the first channel as a clock event device and the second channel 1056 * as a clock source. If only one channel is available use it for both. 1057 */ 1058 for (i = 0, mask = cmt->hw_channels; i < cmt->num_channels; ++i) { 1059 unsigned int hwidx = ffs(mask) - 1; 1060 bool clocksource = i == 1 || cmt->num_channels == 1; 1061 bool clockevent = i == 0; 1062 1063 ret = sh_cmt_setup_channel(&cmt->channels[i], i, hwidx, 1064 clockevent, clocksource, cmt); 1065 if (ret < 0) 1066 goto err_unmap; 1067 1068 mask &= ~(1 << hwidx); 1069 } 1070 1071 clk_disable(cmt->clk); 1072 1073 platform_set_drvdata(pdev, cmt); 1074 1075 return 0; 1076 1077 err_unmap: 1078 kfree(cmt->channels); 1079 iounmap(cmt->mapbase); 1080 err_clk_disable: 1081 clk_disable(cmt->clk); 1082 err_clk_unprepare: 1083 clk_unprepare(cmt->clk); 1084 err_clk_put: 1085 clk_put(cmt->clk); 1086 return ret; 1087 } 1088 1089 static int sh_cmt_probe(struct platform_device *pdev) 1090 { 1091 struct sh_cmt_device *cmt = platform_get_drvdata(pdev); 1092 int ret; 1093 1094 if (!is_sh_early_platform_device(pdev)) { 1095 pm_runtime_set_active(&pdev->dev); 1096 pm_runtime_enable(&pdev->dev); 1097 } 1098 1099 if (cmt) { 1100 dev_info(&pdev->dev, "kept as earlytimer\n"); 1101 goto out; 1102 } 1103 1104 cmt = kzalloc(sizeof(*cmt), GFP_KERNEL); 1105 if (cmt == NULL) 1106 return -ENOMEM; 1107 1108 ret = sh_cmt_setup(cmt, pdev); 1109 if (ret) { 1110 kfree(cmt); 1111 pm_runtime_idle(&pdev->dev); 1112 return ret; 1113 } 1114 if (is_sh_early_platform_device(pdev)) 1115 return 0; 1116 1117 out: 1118 if (cmt->has_clockevent || cmt->has_clocksource) 1119 pm_runtime_irq_safe(&pdev->dev); 1120 else 1121 pm_runtime_idle(&pdev->dev); 1122 1123 return 0; 1124 } 1125 1126 static int sh_cmt_remove(struct platform_device *pdev) 1127 { 1128 return -EBUSY; /* cannot unregister clockevent and clocksource */ 1129 } 1130 1131 static struct platform_driver sh_cmt_device_driver = { 1132 .probe = sh_cmt_probe, 1133 .remove = sh_cmt_remove, 1134 .driver = { 1135 .name = "sh_cmt", 1136 .of_match_table = of_match_ptr(sh_cmt_of_table), 1137 }, 1138 .id_table = sh_cmt_id_table, 1139 }; 1140 1141 static int __init sh_cmt_init(void) 1142 { 1143 return platform_driver_register(&sh_cmt_device_driver); 1144 } 1145 1146 static void __exit sh_cmt_exit(void) 1147 { 1148 platform_driver_unregister(&sh_cmt_device_driver); 1149 } 1150 1151 #ifdef CONFIG_SUPERH 1152 sh_early_platform_init("earlytimer", &sh_cmt_device_driver); 1153 #endif 1154 1155 subsys_initcall(sh_cmt_init); 1156 module_exit(sh_cmt_exit); 1157 1158 MODULE_AUTHOR("Magnus Damm"); 1159 MODULE_DESCRIPTION("SuperH CMT Timer Driver"); 1160 MODULE_LICENSE("GPL v2"); 1161