1*8ffdff6aSGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0+ */ 2*8ffdff6aSGreg Kroah-Hartman /* 3*8ffdff6aSGreg Kroah-Hartman * Register descriptions for NI DAQ-STC chip 4*8ffdff6aSGreg Kroah-Hartman * 5*8ffdff6aSGreg Kroah-Hartman * COMEDI - Linux Control and Measurement Device Interface 6*8ffdff6aSGreg Kroah-Hartman * Copyright (C) 1998-9 David A. Schleef <ds@schleef.org> 7*8ffdff6aSGreg Kroah-Hartman */ 8*8ffdff6aSGreg Kroah-Hartman 9*8ffdff6aSGreg Kroah-Hartman /* 10*8ffdff6aSGreg Kroah-Hartman * References: 11*8ffdff6aSGreg Kroah-Hartman * DAQ-STC Technical Reference Manual 12*8ffdff6aSGreg Kroah-Hartman */ 13*8ffdff6aSGreg Kroah-Hartman 14*8ffdff6aSGreg Kroah-Hartman #ifndef _COMEDI_NI_STC_H 15*8ffdff6aSGreg Kroah-Hartman #define _COMEDI_NI_STC_H 16*8ffdff6aSGreg Kroah-Hartman 17*8ffdff6aSGreg Kroah-Hartman #include "ni_tio.h" 18*8ffdff6aSGreg Kroah-Hartman #include "ni_routes.h" 19*8ffdff6aSGreg Kroah-Hartman 20*8ffdff6aSGreg Kroah-Hartman /* 21*8ffdff6aSGreg Kroah-Hartman * Registers in the National Instruments DAQ-STC chip 22*8ffdff6aSGreg Kroah-Hartman */ 23*8ffdff6aSGreg Kroah-Hartman 24*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTA_ACK_REG 2 25*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTA_ACK_G0_GATE BIT(15) 26*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTA_ACK_G0_TC BIT(14) 27*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTA_ACK_AI_ERR BIT(13) 28*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTA_ACK_AI_STOP BIT(12) 29*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTA_ACK_AI_START BIT(11) 30*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTA_ACK_AI_START2 BIT(10) 31*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTA_ACK_AI_START1 BIT(9) 32*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTA_ACK_AI_SC_TC BIT(8) 33*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTA_ACK_AI_SC_TC_ERR BIT(7) 34*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTA_ACK_G0_TC_ERR BIT(6) 35*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTA_ACK_G0_GATE_ERR BIT(5) 36*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTA_ACK_AI_ALL (NISTC_INTA_ACK_AI_ERR | \ 37*8ffdff6aSGreg Kroah-Hartman NISTC_INTA_ACK_AI_STOP | \ 38*8ffdff6aSGreg Kroah-Hartman NISTC_INTA_ACK_AI_START | \ 39*8ffdff6aSGreg Kroah-Hartman NISTC_INTA_ACK_AI_START2 | \ 40*8ffdff6aSGreg Kroah-Hartman NISTC_INTA_ACK_AI_START1 | \ 41*8ffdff6aSGreg Kroah-Hartman NISTC_INTA_ACK_AI_SC_TC | \ 42*8ffdff6aSGreg Kroah-Hartman NISTC_INTA_ACK_AI_SC_TC_ERR) 43*8ffdff6aSGreg Kroah-Hartman 44*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTB_ACK_REG 3 45*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTB_ACK_G1_GATE BIT(15) 46*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTB_ACK_G1_TC BIT(14) 47*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTB_ACK_AO_ERR BIT(13) 48*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTB_ACK_AO_STOP BIT(12) 49*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTB_ACK_AO_START BIT(11) 50*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTB_ACK_AO_UPDATE BIT(10) 51*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTB_ACK_AO_START1 BIT(9) 52*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTB_ACK_AO_BC_TC BIT(8) 53*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTB_ACK_AO_UC_TC BIT(7) 54*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTB_ACK_AO_UI2_TC BIT(6) 55*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTB_ACK_AO_UI2_TC_ERR BIT(5) 56*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTB_ACK_AO_BC_TC_ERR BIT(4) 57*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTB_ACK_AO_BC_TC_TRIG_ERR BIT(3) 58*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTB_ACK_G1_TC_ERR BIT(2) 59*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTB_ACK_G1_GATE_ERR BIT(1) 60*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTB_ACK_AO_ALL (NISTC_INTB_ACK_AO_ERR | \ 61*8ffdff6aSGreg Kroah-Hartman NISTC_INTB_ACK_AO_STOP | \ 62*8ffdff6aSGreg Kroah-Hartman NISTC_INTB_ACK_AO_START | \ 63*8ffdff6aSGreg Kroah-Hartman NISTC_INTB_ACK_AO_UPDATE | \ 64*8ffdff6aSGreg Kroah-Hartman NISTC_INTB_ACK_AO_START1 | \ 65*8ffdff6aSGreg Kroah-Hartman NISTC_INTB_ACK_AO_BC_TC | \ 66*8ffdff6aSGreg Kroah-Hartman NISTC_INTB_ACK_AO_UC_TC | \ 67*8ffdff6aSGreg Kroah-Hartman NISTC_INTB_ACK_AO_BC_TC_ERR | \ 68*8ffdff6aSGreg Kroah-Hartman NISTC_INTB_ACK_AO_BC_TC_TRIG_ERR) 69*8ffdff6aSGreg Kroah-Hartman 70*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_CMD2_REG 4 71*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_CMD2_END_ON_SC_TC BIT(15) 72*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_CMD2_END_ON_EOS BIT(14) 73*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_CMD2_START1_DISABLE BIT(11) 74*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_CMD2_SC_SAVE_TRACE BIT(10) 75*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_CMD2_SI_SW_ON_SC_TC BIT(9) 76*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_CMD2_SI_SW_ON_STOP BIT(8) 77*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_CMD2_SI_SW_ON_TC BIT(7) 78*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_CMD2_SC_SW_ON_TC BIT(4) 79*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_CMD2_STOP_PULSE BIT(3) 80*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_CMD2_START_PULSE BIT(2) 81*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_CMD2_START2_PULSE BIT(1) 82*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_CMD2_START1_PULSE BIT(0) 83*8ffdff6aSGreg Kroah-Hartman 84*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_CMD2_REG 5 85*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_CMD2_END_ON_BC_TC(x) (((x) & 0x3) << 14) 86*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_CMD2_START_STOP_GATE_ENA BIT(13) 87*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_CMD2_UC_SAVE_TRACE BIT(12) 88*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_CMD2_BC_GATE_ENA BIT(11) 89*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_CMD2_BC_SAVE_TRACE BIT(10) 90*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_CMD2_UI_SW_ON_BC_TC BIT(9) 91*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_CMD2_UI_SW_ON_STOP BIT(8) 92*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_CMD2_UI_SW_ON_TC BIT(7) 93*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_CMD2_UC_SW_ON_BC_TC BIT(6) 94*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_CMD2_UC_SW_ON_TC BIT(5) 95*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_CMD2_BC_SW_ON_TC BIT(4) 96*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_CMD2_MUTE_B BIT(3) 97*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_CMD2_MUTE_A BIT(2) 98*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_CMD2_UPDATE2_PULSE BIT(1) 99*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_CMD2_START1_PULSE BIT(0) 100*8ffdff6aSGreg Kroah-Hartman 101*8ffdff6aSGreg Kroah-Hartman #define NISTC_G0_CMD_REG 6 102*8ffdff6aSGreg Kroah-Hartman #define NISTC_G1_CMD_REG 7 103*8ffdff6aSGreg Kroah-Hartman 104*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_CMD1_REG 8 105*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_CMD1_ATRIG_RESET BIT(14) 106*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_CMD1_DISARM BIT(13) 107*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_CMD1_SI2_ARM BIT(12) 108*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_CMD1_SI2_LOAD BIT(11) 109*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_CMD1_SI_ARM BIT(10) 110*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_CMD1_SI_LOAD BIT(9) 111*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_CMD1_DIV_ARM BIT(8) 112*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_CMD1_DIV_LOAD BIT(7) 113*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_CMD1_SC_ARM BIT(6) 114*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_CMD1_SC_LOAD BIT(5) 115*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_CMD1_SCAN_IN_PROG_PULSE BIT(4) 116*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_CMD1_EXTMUX_CLK_PULSE BIT(3) 117*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_CMD1_LOCALMUX_CLK_PULSE BIT(2) 118*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_CMD1_SC_TC_PULSE BIT(1) 119*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_CMD1_CONVERT_PULSE BIT(0) 120*8ffdff6aSGreg Kroah-Hartman 121*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_CMD1_REG 9 122*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_CMD1_ATRIG_RESET BIT(15) 123*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_CMD1_START_PULSE BIT(14) 124*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_CMD1_DISARM BIT(13) 125*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_CMD1_UI2_ARM_DISARM BIT(12) 126*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_CMD1_UI2_LOAD BIT(11) 127*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_CMD1_UI_ARM BIT(10) 128*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_CMD1_UI_LOAD BIT(9) 129*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_CMD1_UC_ARM BIT(8) 130*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_CMD1_UC_LOAD BIT(7) 131*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_CMD1_BC_ARM BIT(6) 132*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_CMD1_BC_LOAD BIT(5) 133*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_CMD1_DAC1_UPDATE_MODE BIT(4) 134*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_CMD1_LDAC1_SRC_SEL BIT(3) 135*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_CMD1_DAC0_UPDATE_MODE BIT(2) 136*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_CMD1_LDAC0_SRC_SEL BIT(1) 137*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_CMD1_UPDATE_PULSE BIT(0) 138*8ffdff6aSGreg Kroah-Hartman 139*8ffdff6aSGreg Kroah-Hartman #define NISTC_DIO_OUT_REG 10 140*8ffdff6aSGreg Kroah-Hartman #define NISTC_DIO_OUT_SERIAL(x) (((x) & 0xff) << 8) 141*8ffdff6aSGreg Kroah-Hartman #define NISTC_DIO_OUT_SERIAL_MASK NISTC_DIO_OUT_SERIAL(0xff) 142*8ffdff6aSGreg Kroah-Hartman #define NISTC_DIO_OUT_PARALLEL(x) ((x) & 0xff) 143*8ffdff6aSGreg Kroah-Hartman #define NISTC_DIO_OUT_PARALLEL_MASK NISTC_DIO_OUT_PARALLEL(0xff) 144*8ffdff6aSGreg Kroah-Hartman #define NISTC_DIO_SDIN BIT(4) 145*8ffdff6aSGreg Kroah-Hartman #define NISTC_DIO_SDOUT BIT(0) 146*8ffdff6aSGreg Kroah-Hartman 147*8ffdff6aSGreg Kroah-Hartman #define NISTC_DIO_CTRL_REG 11 148*8ffdff6aSGreg Kroah-Hartman #define NISTC_DIO_SDCLK BIT(11) 149*8ffdff6aSGreg Kroah-Hartman #define NISTC_DIO_CTRL_HW_SER_TIMEBASE BIT(10) 150*8ffdff6aSGreg Kroah-Hartman #define NISTC_DIO_CTRL_HW_SER_ENA BIT(9) 151*8ffdff6aSGreg Kroah-Hartman #define NISTC_DIO_CTRL_HW_SER_START BIT(8) 152*8ffdff6aSGreg Kroah-Hartman #define NISTC_DIO_CTRL_DIR(x) ((x) & 0xff) 153*8ffdff6aSGreg Kroah-Hartman #define NISTC_DIO_CTRL_DIR_MASK NISTC_DIO_CTRL_DIR(0xff) 154*8ffdff6aSGreg Kroah-Hartman 155*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_MODE1_REG 12 156*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_MODE1_CONVERT_SRC(x) (((x) & 0x1f) << 11) 157*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_MODE1_SI_SRC(x) (((x) & 0x1f) << 6) 158*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_MODE1_CONVERT_POLARITY BIT(5) 159*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_MODE1_SI_POLARITY BIT(4) 160*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_MODE1_START_STOP BIT(3) 161*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_MODE1_RSVD BIT(2) 162*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_MODE1_CONTINUOUS BIT(1) 163*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_MODE1_TRIGGER_ONCE BIT(0) 164*8ffdff6aSGreg Kroah-Hartman 165*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_MODE2_REG 13 166*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_MODE2_SC_GATE_ENA BIT(15) 167*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_MODE2_START_STOP_GATE_ENA BIT(14) 168*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_MODE2_PRE_TRIGGER BIT(13) 169*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_MODE2_EXTMUX_PRESENT BIT(12) 170*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_MODE2_SI2_INIT_LOAD_SRC BIT(9) 171*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_MODE2_SI2_RELOAD_MODE BIT(8) 172*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_MODE2_SI_INIT_LOAD_SRC BIT(7) 173*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_MODE2_SI_RELOAD_MODE(x) (((x) & 0x7) << 4) 174*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_MODE2_SI_WR_SWITCH BIT(3) 175*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_MODE2_SC_INIT_LOAD_SRC BIT(2) 176*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_MODE2_SC_RELOAD_MODE BIT(1) 177*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_MODE2_SC_WR_SWITCH BIT(0) 178*8ffdff6aSGreg Kroah-Hartman 179*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_SI_LOADA_REG 14 180*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_SI_LOADB_REG 16 181*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_SC_LOADA_REG 18 182*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_SC_LOADB_REG 20 183*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_SI2_LOADA_REG 23 184*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_SI2_LOADB_REG 25 185*8ffdff6aSGreg Kroah-Hartman 186*8ffdff6aSGreg Kroah-Hartman #define NISTC_G0_MODE_REG 26 187*8ffdff6aSGreg Kroah-Hartman #define NISTC_G1_MODE_REG 27 188*8ffdff6aSGreg Kroah-Hartman #define NISTC_G0_LOADA_REG 28 189*8ffdff6aSGreg Kroah-Hartman #define NISTC_G0_LOADB_REG 30 190*8ffdff6aSGreg Kroah-Hartman #define NISTC_G1_LOADA_REG 32 191*8ffdff6aSGreg Kroah-Hartman #define NISTC_G1_LOADB_REG 34 192*8ffdff6aSGreg Kroah-Hartman #define NISTC_G0_INPUT_SEL_REG 36 193*8ffdff6aSGreg Kroah-Hartman #define NISTC_G1_INPUT_SEL_REG 37 194*8ffdff6aSGreg Kroah-Hartman 195*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_MODE1_REG 38 196*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_MODE1_UPDATE_SRC(x) (((x) & 0x1f) << 11) 197*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_MODE1_UPDATE_SRC_MASK NISTC_AO_MODE1_UPDATE_SRC(0x1f) 198*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_MODE1_UI_SRC(x) (((x) & 0x1f) << 6) 199*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_MODE1_UI_SRC_MASK NISTC_AO_MODE1_UI_SRC(0x1f) 200*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_MODE1_MULTI_CHAN BIT(5) 201*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_MODE1_UPDATE_SRC_POLARITY BIT(4) 202*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_MODE1_UI_SRC_POLARITY BIT(3) 203*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_MODE1_UC_SW_EVERY_TC BIT(2) 204*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_MODE1_CONTINUOUS BIT(1) 205*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_MODE1_TRIGGER_ONCE BIT(0) 206*8ffdff6aSGreg Kroah-Hartman 207*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_MODE2_REG 39 208*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_MODE2_FIFO_MODE(x) (((x) & 0x3) << 14) 209*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_MODE2_FIFO_MODE_MASK NISTC_AO_MODE2_FIFO_MODE(3) 210*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_MODE2_FIFO_MODE_E NISTC_AO_MODE2_FIFO_MODE(0) 211*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_MODE2_FIFO_MODE_HF NISTC_AO_MODE2_FIFO_MODE(1) 212*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_MODE2_FIFO_MODE_F NISTC_AO_MODE2_FIFO_MODE(2) 213*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_MODE2_FIFO_MODE_HF_F NISTC_AO_MODE2_FIFO_MODE(3) 214*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_MODE2_FIFO_REXMIT_ENA BIT(13) 215*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_MODE2_START1_DISABLE BIT(12) 216*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_MODE2_UC_INIT_LOAD_SRC BIT(11) 217*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_MODE2_UC_WR_SWITCH BIT(10) 218*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_MODE2_UI2_INIT_LOAD_SRC BIT(9) 219*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_MODE2_UI2_RELOAD_MODE BIT(8) 220*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_MODE2_UI_INIT_LOAD_SRC BIT(7) 221*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_MODE2_UI_RELOAD_MODE(x) (((x) & 0x7) << 4) 222*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_MODE2_UI_WR_SWITCH BIT(3) 223*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_MODE2_BC_INIT_LOAD_SRC BIT(2) 224*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_MODE2_BC_RELOAD_MODE BIT(1) 225*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_MODE2_BC_WR_SWITCH BIT(0) 226*8ffdff6aSGreg Kroah-Hartman 227*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_UI_LOADA_REG 40 228*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_UI_LOADB_REG 42 229*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_BC_LOADA_REG 44 230*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_BC_LOADB_REG 46 231*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_UC_LOADA_REG 48 232*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_UC_LOADB_REG 50 233*8ffdff6aSGreg Kroah-Hartman 234*8ffdff6aSGreg Kroah-Hartman #define NISTC_CLK_FOUT_REG 56 235*8ffdff6aSGreg Kroah-Hartman #define NISTC_CLK_FOUT_ENA BIT(15) 236*8ffdff6aSGreg Kroah-Hartman #define NISTC_CLK_FOUT_TIMEBASE_SEL BIT(14) 237*8ffdff6aSGreg Kroah-Hartman #define NISTC_CLK_FOUT_DIO_SER_OUT_DIV2 BIT(13) 238*8ffdff6aSGreg Kroah-Hartman #define NISTC_CLK_FOUT_SLOW_DIV2 BIT(12) 239*8ffdff6aSGreg Kroah-Hartman #define NISTC_CLK_FOUT_SLOW_TIMEBASE BIT(11) 240*8ffdff6aSGreg Kroah-Hartman #define NISTC_CLK_FOUT_G_SRC_DIV2 BIT(10) 241*8ffdff6aSGreg Kroah-Hartman #define NISTC_CLK_FOUT_TO_BOARD_DIV2 BIT(9) 242*8ffdff6aSGreg Kroah-Hartman #define NISTC_CLK_FOUT_TO_BOARD BIT(8) 243*8ffdff6aSGreg Kroah-Hartman #define NISTC_CLK_FOUT_AI_OUT_DIV2 BIT(7) 244*8ffdff6aSGreg Kroah-Hartman #define NISTC_CLK_FOUT_AI_SRC_DIV2 BIT(6) 245*8ffdff6aSGreg Kroah-Hartman #define NISTC_CLK_FOUT_AO_OUT_DIV2 BIT(5) 246*8ffdff6aSGreg Kroah-Hartman #define NISTC_CLK_FOUT_AO_SRC_DIV2 BIT(4) 247*8ffdff6aSGreg Kroah-Hartman #define NISTC_CLK_FOUT_DIVIDER(x) (((x) & 0xf) << 0) 248*8ffdff6aSGreg Kroah-Hartman #define NISTC_CLK_FOUT_TO_DIVIDER(x) (((x) >> 0) & 0xf) 249*8ffdff6aSGreg Kroah-Hartman #define NISTC_CLK_FOUT_DIVIDER_MASK NISTC_CLK_FOUT_DIVIDER(0xf) 250*8ffdff6aSGreg Kroah-Hartman 251*8ffdff6aSGreg Kroah-Hartman #define NISTC_IO_BIDIR_PIN_REG 57 252*8ffdff6aSGreg Kroah-Hartman 253*8ffdff6aSGreg Kroah-Hartman #define NISTC_RTSI_TRIG_DIR_REG 58 254*8ffdff6aSGreg Kroah-Hartman #define NISTC_RTSI_TRIG_OLD_CLK_CHAN 7 255*8ffdff6aSGreg Kroah-Hartman #define NISTC_RTSI_TRIG_NUM_CHAN(_m) ((_m) ? 8 : 7) 256*8ffdff6aSGreg Kroah-Hartman #define NISTC_RTSI_TRIG_DIR(_c, _m) ((_m) ? BIT(8 + (_c)) : BIT(7 + (_c))) 257*8ffdff6aSGreg Kroah-Hartman #define NISTC_RTSI_TRIG_DIR_SUB_SEL1 BIT(2) /* only for M-Series */ 258*8ffdff6aSGreg Kroah-Hartman #define NISTC_RTSI_TRIG_DIR_SUB_SEL1_SHIFT 2 /* only for M-Series */ 259*8ffdff6aSGreg Kroah-Hartman #define NISTC_RTSI_TRIG_USE_CLK BIT(1) 260*8ffdff6aSGreg Kroah-Hartman #define NISTC_RTSI_TRIG_DRV_CLK BIT(0) 261*8ffdff6aSGreg Kroah-Hartman 262*8ffdff6aSGreg Kroah-Hartman #define NISTC_INT_CTRL_REG 59 263*8ffdff6aSGreg Kroah-Hartman #define NISTC_INT_CTRL_INTB_ENA BIT(15) 264*8ffdff6aSGreg Kroah-Hartman #define NISTC_INT_CTRL_INTB_SEL(x) (((x) & 0x7) << 12) 265*8ffdff6aSGreg Kroah-Hartman #define NISTC_INT_CTRL_INTA_ENA BIT(11) 266*8ffdff6aSGreg Kroah-Hartman #define NISTC_INT_CTRL_INTA_SEL(x) (((x) & 0x7) << 8) 267*8ffdff6aSGreg Kroah-Hartman #define NISTC_INT_CTRL_PASSTHRU0_POL BIT(3) 268*8ffdff6aSGreg Kroah-Hartman #define NISTC_INT_CTRL_PASSTHRU1_POL BIT(2) 269*8ffdff6aSGreg Kroah-Hartman #define NISTC_INT_CTRL_3PIN_INT BIT(1) 270*8ffdff6aSGreg Kroah-Hartman #define NISTC_INT_CTRL_INT_POL BIT(0) 271*8ffdff6aSGreg Kroah-Hartman 272*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_OUT_CTRL_REG 60 273*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_OUT_CTRL_START_SEL BIT(10) 274*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_OUT_CTRL_SCAN_IN_PROG_SEL(x) (((x) & 0x3) << 8) 275*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_OUT_CTRL_EXTMUX_CLK_SEL(x) (((x) & 0x3) << 6) 276*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_OUT_CTRL_LOCALMUX_CLK_SEL(x) (((x) & 0x3) << 4) 277*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_OUT_CTRL_SC_TC_SEL(x) (((x) & 0x3) << 2) 278*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_OUT_CTRL_CONVERT_SEL(x) (((x) & 0x3) << 0) 279*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_OUT_CTRL_CONVERT_HIGH_Z NISTC_AI_OUT_CTRL_CONVERT_SEL(0) 280*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_OUT_CTRL_CONVERT_GND NISTC_AI_OUT_CTRL_CONVERT_SEL(1) 281*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_OUT_CTRL_CONVERT_LOW NISTC_AI_OUT_CTRL_CONVERT_SEL(2) 282*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_OUT_CTRL_CONVERT_HIGH NISTC_AI_OUT_CTRL_CONVERT_SEL(3) 283*8ffdff6aSGreg Kroah-Hartman 284*8ffdff6aSGreg Kroah-Hartman #define NISTC_ATRIG_ETC_REG 61 285*8ffdff6aSGreg Kroah-Hartman #define NISTC_ATRIG_ETC_GPFO_1_ENA BIT(15) 286*8ffdff6aSGreg Kroah-Hartman #define NISTC_ATRIG_ETC_GPFO_0_ENA BIT(14) 287*8ffdff6aSGreg Kroah-Hartman #define NISTC_ATRIG_ETC_GPFO_0_SEL(x) (((x) & 0x7) << 11) 288*8ffdff6aSGreg Kroah-Hartman #define NISTC_ATRIG_ETC_GPFO_0_SEL_TO_SRC(x) (((x) >> 11) & 0x7) 289*8ffdff6aSGreg Kroah-Hartman #define NISTC_ATRIG_ETC_GPFO_1_SEL BIT(7) 290*8ffdff6aSGreg Kroah-Hartman #define NISTC_ATRIG_ETC_GPFO_1_SEL_TO_SRC(x) (((x) >> 7) & 0x1) 291*8ffdff6aSGreg Kroah-Hartman #define NISTC_ATRIG_ETC_DRV BIT(4) 292*8ffdff6aSGreg Kroah-Hartman #define NISTC_ATRIG_ETC_ENA BIT(3) 293*8ffdff6aSGreg Kroah-Hartman #define NISTC_ATRIG_ETC_MODE(x) (((x) & 0x7) << 0) 294*8ffdff6aSGreg Kroah-Hartman #define NISTC_GPFO_0_G_OUT 0 /* input to GPFO_0_SEL for Ctr0Out */ 295*8ffdff6aSGreg Kroah-Hartman #define NISTC_GPFO_1_G_OUT 0 /* input to GPFO_1_SEL for Ctr1Out */ 296*8ffdff6aSGreg Kroah-Hartman 297*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_START_STOP_REG 62 298*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_START_POLARITY BIT(15) 299*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_STOP_POLARITY BIT(14) 300*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_STOP_SYNC BIT(13) 301*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_STOP_EDGE BIT(12) 302*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_STOP_SEL(x) (((x) & 0x1f) << 7) 303*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_START_SYNC BIT(6) 304*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_START_EDGE BIT(5) 305*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_START_SEL(x) (((x) & 0x1f) << 0) 306*8ffdff6aSGreg Kroah-Hartman 307*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_TRIG_SEL_REG 63 308*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_TRIG_START1_POLARITY BIT(15) 309*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_TRIG_START2_POLARITY BIT(14) 310*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_TRIG_START2_SYNC BIT(13) 311*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_TRIG_START2_EDGE BIT(12) 312*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_TRIG_START2_SEL(x) (((x) & 0x1f) << 7) 313*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_TRIG_START1_SYNC BIT(6) 314*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_TRIG_START1_EDGE BIT(5) 315*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_TRIG_START1_SEL(x) (((x) & 0x1f) << 0) 316*8ffdff6aSGreg Kroah-Hartman 317*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_DIV_LOADA_REG 64 318*8ffdff6aSGreg Kroah-Hartman 319*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_START_SEL_REG 66 320*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_START_UI2_SW_GATE BIT(15) 321*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_START_UI2_EXT_GATE_POL BIT(14) 322*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_START_POLARITY BIT(13) 323*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_START_AOFREQ_ENA BIT(12) 324*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_START_UI2_EXT_GATE_SEL(x) (((x) & 0x1f) << 7) 325*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_START_SYNC BIT(6) 326*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_START_EDGE BIT(5) 327*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_START_SEL(x) (((x) & 0x1f) << 0) 328*8ffdff6aSGreg Kroah-Hartman 329*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_TRIG_SEL_REG 67 330*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_TRIG_UI2_EXT_GATE_ENA BIT(15) 331*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_TRIG_DELAYED_START1 BIT(14) 332*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_TRIG_START1_POLARITY BIT(13) 333*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_TRIG_UI2_SRC_POLARITY BIT(12) 334*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_TRIG_UI2_SRC_SEL(x) (((x) & 0x1f) << 7) 335*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_TRIG_START1_SYNC BIT(6) 336*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_TRIG_START1_EDGE BIT(5) 337*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_TRIG_START1_SEL(x) (((x) & 0x1f) << 0) 338*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_TRIG_START1_SEL_MASK NISTC_AO_TRIG_START1_SEL(0x1f) 339*8ffdff6aSGreg Kroah-Hartman 340*8ffdff6aSGreg Kroah-Hartman #define NISTC_G0_AUTOINC_REG 68 341*8ffdff6aSGreg Kroah-Hartman #define NISTC_G1_AUTOINC_REG 69 342*8ffdff6aSGreg Kroah-Hartman 343*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_MODE3_REG 70 344*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_MODE3_UI2_SW_NEXT_TC BIT(13) 345*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_MODE3_UC_SW_EVERY_BC_TC BIT(12) 346*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_MODE3_TRIG_LEN BIT(11) 347*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_MODE3_STOP_ON_OVERRUN_ERR BIT(5) 348*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_MODE3_STOP_ON_BC_TC_TRIG_ERR BIT(4) 349*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_MODE3_STOP_ON_BC_TC_ERR BIT(3) 350*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_MODE3_NOT_AN_UPDATE BIT(2) 351*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_MODE3_SW_GATE BIT(1) 352*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_MODE3_LAST_GATE_DISABLE BIT(0) /* M-Series only */ 353*8ffdff6aSGreg Kroah-Hartman 354*8ffdff6aSGreg Kroah-Hartman #define NISTC_RESET_REG 72 355*8ffdff6aSGreg Kroah-Hartman #define NISTC_RESET_SOFTWARE BIT(11) 356*8ffdff6aSGreg Kroah-Hartman #define NISTC_RESET_AO_CFG_END BIT(9) 357*8ffdff6aSGreg Kroah-Hartman #define NISTC_RESET_AI_CFG_END BIT(8) 358*8ffdff6aSGreg Kroah-Hartman #define NISTC_RESET_AO_CFG_START BIT(5) 359*8ffdff6aSGreg Kroah-Hartman #define NISTC_RESET_AI_CFG_START BIT(4) 360*8ffdff6aSGreg Kroah-Hartman #define NISTC_RESET_G1 BIT(3) 361*8ffdff6aSGreg Kroah-Hartman #define NISTC_RESET_G0 BIT(2) 362*8ffdff6aSGreg Kroah-Hartman #define NISTC_RESET_AO BIT(1) 363*8ffdff6aSGreg Kroah-Hartman #define NISTC_RESET_AI BIT(0) 364*8ffdff6aSGreg Kroah-Hartman 365*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTA_ENA_REG 73 366*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTA2_ENA_REG 74 367*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTA_ENA_PASSTHRU0 BIT(9) 368*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTA_ENA_G0_GATE BIT(8) 369*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTA_ENA_AI_FIFO BIT(7) 370*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTA_ENA_G0_TC BIT(6) 371*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTA_ENA_AI_ERR BIT(5) 372*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTA_ENA_AI_STOP BIT(4) 373*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTA_ENA_AI_START BIT(3) 374*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTA_ENA_AI_START2 BIT(2) 375*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTA_ENA_AI_START1 BIT(1) 376*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTA_ENA_AI_SC_TC BIT(0) 377*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTA_ENA_AI_MASK (NISTC_INTA_ENA_AI_FIFO | \ 378*8ffdff6aSGreg Kroah-Hartman NISTC_INTA_ENA_AI_ERR | \ 379*8ffdff6aSGreg Kroah-Hartman NISTC_INTA_ENA_AI_STOP | \ 380*8ffdff6aSGreg Kroah-Hartman NISTC_INTA_ENA_AI_START | \ 381*8ffdff6aSGreg Kroah-Hartman NISTC_INTA_ENA_AI_START2 | \ 382*8ffdff6aSGreg Kroah-Hartman NISTC_INTA_ENA_AI_START1 | \ 383*8ffdff6aSGreg Kroah-Hartman NISTC_INTA_ENA_AI_SC_TC) 384*8ffdff6aSGreg Kroah-Hartman 385*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTB_ENA_REG 75 386*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTB2_ENA_REG 76 387*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTB_ENA_PASSTHRU1 BIT(11) 388*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTB_ENA_G1_GATE BIT(10) 389*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTB_ENA_G1_TC BIT(9) 390*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTB_ENA_AO_FIFO BIT(8) 391*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTB_ENA_AO_UI2_TC BIT(7) 392*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTB_ENA_AO_UC_TC BIT(6) 393*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTB_ENA_AO_ERR BIT(5) 394*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTB_ENA_AO_STOP BIT(4) 395*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTB_ENA_AO_START BIT(3) 396*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTB_ENA_AO_UPDATE BIT(2) 397*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTB_ENA_AO_START1 BIT(1) 398*8ffdff6aSGreg Kroah-Hartman #define NISTC_INTB_ENA_AO_BC_TC BIT(0) 399*8ffdff6aSGreg Kroah-Hartman 400*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_PERSONAL_REG 77 401*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_PERSONAL_SHIFTIN_PW BIT(15) 402*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_PERSONAL_EOC_POLARITY BIT(14) 403*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_PERSONAL_SOC_POLARITY BIT(13) 404*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_PERSONAL_SHIFTIN_POL BIT(12) 405*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_PERSONAL_CONVERT_TIMEBASE BIT(11) 406*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_PERSONAL_CONVERT_PW BIT(10) 407*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_PERSONAL_CONVERT_ORIG_PULSE BIT(9) 408*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_PERSONAL_FIFO_FLAGS_POL BIT(8) 409*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_PERSONAL_OVERRUN_MODE BIT(7) 410*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_PERSONAL_EXTMUX_CLK_PW BIT(6) 411*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_PERSONAL_LOCALMUX_CLK_PW BIT(5) 412*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_PERSONAL_AIFREQ_POL BIT(4) 413*8ffdff6aSGreg Kroah-Hartman 414*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_PERSONAL_REG 78 415*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_PERSONAL_MULTI_DACS BIT(15) /* M-Series only */ 416*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_PERSONAL_NUM_DAC BIT(14) /* 1:single; 0:dual */ 417*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_PERSONAL_FAST_CPU BIT(13) /* M-Series reserved */ 418*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_PERSONAL_TMRDACWR_PW BIT(12) 419*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_PERSONAL_FIFO_FLAGS_POL BIT(11) /* M-Series reserved */ 420*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_PERSONAL_FIFO_ENA BIT(10) 421*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_PERSONAL_AOFREQ_POL BIT(9) /* M-Series reserved */ 422*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_PERSONAL_DMA_PIO_CTRL BIT(8) /* M-Series reserved */ 423*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_PERSONAL_UPDATE_ORIG_PULSE BIT(7) 424*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_PERSONAL_UPDATE_TIMEBASE BIT(6) 425*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_PERSONAL_UPDATE_PW BIT(5) 426*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_PERSONAL_BC_SRC_SEL BIT(4) 427*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_PERSONAL_INTERVAL_BUFFER_MODE BIT(3) 428*8ffdff6aSGreg Kroah-Hartman 429*8ffdff6aSGreg Kroah-Hartman #define NISTC_RTSI_TRIGA_OUT_REG 79 430*8ffdff6aSGreg Kroah-Hartman #define NISTC_RTSI_TRIGB_OUT_REG 80 431*8ffdff6aSGreg Kroah-Hartman #define NISTC_RTSI_TRIGB_SUB_SEL1 BIT(15) /* not for M-Series */ 432*8ffdff6aSGreg Kroah-Hartman #define NISTC_RTSI_TRIGB_SUB_SEL1_SHIFT 15 /* not for M-Series */ 433*8ffdff6aSGreg Kroah-Hartman #define NISTC_RTSI_TRIG(_c, _s) (((_s) & 0xf) << (((_c) % 4) * 4)) 434*8ffdff6aSGreg Kroah-Hartman #define NISTC_RTSI_TRIG_MASK(_c) NISTC_RTSI_TRIG((_c), 0xf) 435*8ffdff6aSGreg Kroah-Hartman #define NISTC_RTSI_TRIG_TO_SRC(_c, _b) (((_b) >> (((_c) % 4) * 4)) & 0xf) 436*8ffdff6aSGreg Kroah-Hartman 437*8ffdff6aSGreg Kroah-Hartman #define NISTC_RTSI_BOARD_REG 81 438*8ffdff6aSGreg Kroah-Hartman 439*8ffdff6aSGreg Kroah-Hartman #define NISTC_CFG_MEM_CLR_REG 82 440*8ffdff6aSGreg Kroah-Hartman #define NISTC_ADC_FIFO_CLR_REG 83 441*8ffdff6aSGreg Kroah-Hartman #define NISTC_DAC_FIFO_CLR_REG 84 442*8ffdff6aSGreg Kroah-Hartman #define NISTC_WR_STROBE3_REG 85 443*8ffdff6aSGreg Kroah-Hartman 444*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_OUT_CTRL_REG 86 445*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_OUT_CTRL_EXT_GATE_ENA BIT(15) 446*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_OUT_CTRL_EXT_GATE_SEL(x) (((x) & 0x1f) << 10) 447*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_OUT_CTRL_CHANS(x) (((x) & 0xf) << 6) 448*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_OUT_CTRL_UPDATE2_SEL(x) (((x) & 0x3) << 4) 449*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_OUT_CTRL_EXT_GATE_POL BIT(3) 450*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_OUT_CTRL_UPDATE2_TOGGLE BIT(2) 451*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_OUT_CTRL_UPDATE_SEL(x) (((x) & 0x3) << 0) 452*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ NISTC_AO_OUT_CTRL_UPDATE_SEL(0) 453*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_OUT_CTRL_UPDATE_SEL_GND NISTC_AO_OUT_CTRL_UPDATE_SEL(1) 454*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_OUT_CTRL_UPDATE_SEL_LOW NISTC_AO_OUT_CTRL_UPDATE_SEL(2) 455*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGH NISTC_AO_OUT_CTRL_UPDATE_SEL(3) 456*8ffdff6aSGreg Kroah-Hartman 457*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_MODE3_REG 87 458*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_MODE3_TRIG_LEN BIT(15) 459*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_MODE3_DELAY_START BIT(14) 460*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_MODE3_SOFTWARE_GATE BIT(13) 461*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_MODE3_SI_TRIG_DELAY BIT(12) 462*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_MODE3_SI2_SRC_SEL BIT(11) 463*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_MODE3_DELAYED_START2 BIT(10) 464*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_MODE3_DELAYED_START1 BIT(9) 465*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_MODE3_EXT_GATE_MODE BIT(8) 466*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_MODE3_FIFO_MODE(x) (((x) & 0x3) << 6) 467*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_MODE3_FIFO_MODE_NE NISTC_AI_MODE3_FIFO_MODE(0) 468*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_MODE3_FIFO_MODE_HF NISTC_AI_MODE3_FIFO_MODE(1) 469*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_MODE3_FIFO_MODE_F NISTC_AI_MODE3_FIFO_MODE(2) 470*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_MODE3_FIFO_MODE_HF_E NISTC_AI_MODE3_FIFO_MODE(3) 471*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_MODE3_EXT_GATE_POL BIT(5) 472*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_MODE3_EXT_GATE_SEL(x) (((x) & 0x1f) << 0) 473*8ffdff6aSGreg Kroah-Hartman 474*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_STATUS1_REG 2 475*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_STATUS1_INTA BIT(15) 476*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_STATUS1_FIFO_F BIT(14) 477*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_STATUS1_FIFO_HF BIT(13) 478*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_STATUS1_FIFO_E BIT(12) 479*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_STATUS1_OVERRUN BIT(11) 480*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_STATUS1_OVERFLOW BIT(10) 481*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_STATUS1_SC_TC_ERR BIT(9) 482*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_STATUS1_OVER (NISTC_AI_STATUS1_OVERRUN | \ 483*8ffdff6aSGreg Kroah-Hartman NISTC_AI_STATUS1_OVERFLOW) 484*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_STATUS1_ERR (NISTC_AI_STATUS1_OVER | \ 485*8ffdff6aSGreg Kroah-Hartman NISTC_AI_STATUS1_SC_TC_ERR) 486*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_STATUS1_START2 BIT(8) 487*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_STATUS1_START1 BIT(7) 488*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_STATUS1_SC_TC BIT(6) 489*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_STATUS1_START BIT(5) 490*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_STATUS1_STOP BIT(4) 491*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_STATUS1_G0_TC BIT(3) 492*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_STATUS1_G0_GATE BIT(2) 493*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_STATUS1_FIFO_REQ BIT(1) 494*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_STATUS1_PASSTHRU0 BIT(0) 495*8ffdff6aSGreg Kroah-Hartman 496*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_STATUS1_REG 3 497*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_STATUS1_INTB BIT(15) 498*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_STATUS1_FIFO_F BIT(14) 499*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_STATUS1_FIFO_HF BIT(13) 500*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_STATUS1_FIFO_E BIT(12) 501*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_STATUS1_BC_TC_ERR BIT(11) 502*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_STATUS1_START BIT(10) 503*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_STATUS1_OVERRUN BIT(9) 504*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_STATUS1_START1 BIT(8) 505*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_STATUS1_BC_TC BIT(7) 506*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_STATUS1_UC_TC BIT(6) 507*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_STATUS1_UPDATE BIT(5) 508*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_STATUS1_UI2_TC BIT(4) 509*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_STATUS1_G1_TC BIT(3) 510*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_STATUS1_G1_GATE BIT(2) 511*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_STATUS1_FIFO_REQ BIT(1) 512*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_STATUS1_PASSTHRU1 BIT(0) 513*8ffdff6aSGreg Kroah-Hartman 514*8ffdff6aSGreg Kroah-Hartman #define NISTC_G01_STATUS_REG 4 515*8ffdff6aSGreg Kroah-Hartman 516*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_STATUS2_REG 5 517*8ffdff6aSGreg Kroah-Hartman 518*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_STATUS2_REG 6 519*8ffdff6aSGreg Kroah-Hartman 520*8ffdff6aSGreg Kroah-Hartman #define NISTC_DIO_IN_REG 7 521*8ffdff6aSGreg Kroah-Hartman 522*8ffdff6aSGreg Kroah-Hartman #define NISTC_G0_HW_SAVE_REG 8 523*8ffdff6aSGreg Kroah-Hartman #define NISTC_G1_HW_SAVE_REG 10 524*8ffdff6aSGreg Kroah-Hartman 525*8ffdff6aSGreg Kroah-Hartman #define NISTC_G0_SAVE_REG 12 526*8ffdff6aSGreg Kroah-Hartman #define NISTC_G1_SAVE_REG 14 527*8ffdff6aSGreg Kroah-Hartman 528*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_UI_SAVE_REG 16 529*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_BC_SAVE_REG 18 530*8ffdff6aSGreg Kroah-Hartman #define NISTC_AO_UC_SAVE_REG 20 531*8ffdff6aSGreg Kroah-Hartman 532*8ffdff6aSGreg Kroah-Hartman #define NISTC_STATUS1_REG 27 533*8ffdff6aSGreg Kroah-Hartman #define NISTC_STATUS1_SERIO_IN_PROG BIT(12) 534*8ffdff6aSGreg Kroah-Hartman 535*8ffdff6aSGreg Kroah-Hartman #define NISTC_DIO_SERIAL_IN_REG 28 536*8ffdff6aSGreg Kroah-Hartman 537*8ffdff6aSGreg Kroah-Hartman #define NISTC_STATUS2_REG 29 538*8ffdff6aSGreg Kroah-Hartman #define NISTC_STATUS2_AO_TMRDACWRS_IN_PROGRESS BIT(5) 539*8ffdff6aSGreg Kroah-Hartman 540*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_SI_SAVE_REG 64 541*8ffdff6aSGreg Kroah-Hartman #define NISTC_AI_SC_SAVE_REG 66 542*8ffdff6aSGreg Kroah-Hartman 543*8ffdff6aSGreg Kroah-Hartman /* 544*8ffdff6aSGreg Kroah-Hartman * PCI E Series Registers 545*8ffdff6aSGreg Kroah-Hartman */ 546*8ffdff6aSGreg Kroah-Hartman #define NI_E_STC_WINDOW_ADDR_REG 0x00 /* rw16 */ 547*8ffdff6aSGreg Kroah-Hartman #define NI_E_STC_WINDOW_DATA_REG 0x02 /* rw16 */ 548*8ffdff6aSGreg Kroah-Hartman 549*8ffdff6aSGreg Kroah-Hartman #define NI_E_STATUS_REG 0x01 /* r8 */ 550*8ffdff6aSGreg Kroah-Hartman #define NI_E_STATUS_AI_FIFO_LOWER_NE BIT(3) 551*8ffdff6aSGreg Kroah-Hartman #define NI_E_STATUS_PROMOUT BIT(0) 552*8ffdff6aSGreg Kroah-Hartman 553*8ffdff6aSGreg Kroah-Hartman #define NI_E_DMA_AI_AO_SEL_REG 0x09 /* w8 */ 554*8ffdff6aSGreg Kroah-Hartman #define NI_E_DMA_AI_SEL(x) (((x) & 0xf) << 0) 555*8ffdff6aSGreg Kroah-Hartman #define NI_E_DMA_AI_SEL_MASK NI_E_DMA_AI_SEL(0xf) 556*8ffdff6aSGreg Kroah-Hartman #define NI_E_DMA_AO_SEL(x) (((x) & 0xf) << 4) 557*8ffdff6aSGreg Kroah-Hartman #define NI_E_DMA_AO_SEL_MASK NI_E_DMA_AO_SEL(0xf) 558*8ffdff6aSGreg Kroah-Hartman 559*8ffdff6aSGreg Kroah-Hartman #define NI_E_DMA_G0_G1_SEL_REG 0x0b /* w8 */ 560*8ffdff6aSGreg Kroah-Hartman #define NI_E_DMA_G0_G1_SEL(_g, _c) (((_c) & 0xf) << ((_g) * 4)) 561*8ffdff6aSGreg Kroah-Hartman #define NI_E_DMA_G0_G1_SEL_MASK(_g) NI_E_DMA_G0_G1_SEL((_g), 0xf) 562*8ffdff6aSGreg Kroah-Hartman 563*8ffdff6aSGreg Kroah-Hartman #define NI_E_SERIAL_CMD_REG 0x0d /* w8 */ 564*8ffdff6aSGreg Kroah-Hartman #define NI_E_SERIAL_CMD_DAC_LD(x) BIT(3 + (x)) 565*8ffdff6aSGreg Kroah-Hartman #define NI_E_SERIAL_CMD_EEPROM_CS BIT(2) 566*8ffdff6aSGreg Kroah-Hartman #define NI_E_SERIAL_CMD_SDATA BIT(1) 567*8ffdff6aSGreg Kroah-Hartman #define NI_E_SERIAL_CMD_SCLK BIT(0) 568*8ffdff6aSGreg Kroah-Hartman 569*8ffdff6aSGreg Kroah-Hartman #define NI_E_MISC_CMD_REG 0x0f /* w8 */ 570*8ffdff6aSGreg Kroah-Hartman #define NI_E_MISC_CMD_INTEXT_ATRIG(x) (((x) & 0x1) << 7) 571*8ffdff6aSGreg Kroah-Hartman #define NI_E_MISC_CMD_EXT_ATRIG NI_E_MISC_CMD_INTEXT_ATRIG(0) 572*8ffdff6aSGreg Kroah-Hartman #define NI_E_MISC_CMD_INT_ATRIG NI_E_MISC_CMD_INTEXT_ATRIG(1) 573*8ffdff6aSGreg Kroah-Hartman 574*8ffdff6aSGreg Kroah-Hartman #define NI_E_AI_CFG_LO_REG 0x10 /* w16 */ 575*8ffdff6aSGreg Kroah-Hartman #define NI_E_AI_CFG_LO_LAST_CHAN BIT(15) 576*8ffdff6aSGreg Kroah-Hartman #define NI_E_AI_CFG_LO_GEN_TRIG BIT(12) 577*8ffdff6aSGreg Kroah-Hartman #define NI_E_AI_CFG_LO_DITHER BIT(9) 578*8ffdff6aSGreg Kroah-Hartman #define NI_E_AI_CFG_LO_UNI BIT(8) 579*8ffdff6aSGreg Kroah-Hartman #define NI_E_AI_CFG_LO_GAIN(x) ((x) << 0) 580*8ffdff6aSGreg Kroah-Hartman 581*8ffdff6aSGreg Kroah-Hartman #define NI_E_AI_CFG_HI_REG 0x12 /* w16 */ 582*8ffdff6aSGreg Kroah-Hartman #define NI_E_AI_CFG_HI_TYPE(x) (((x) & 0x7) << 12) 583*8ffdff6aSGreg Kroah-Hartman #define NI_E_AI_CFG_HI_TYPE_DIFF NI_E_AI_CFG_HI_TYPE(1) 584*8ffdff6aSGreg Kroah-Hartman #define NI_E_AI_CFG_HI_TYPE_COMMON NI_E_AI_CFG_HI_TYPE(2) 585*8ffdff6aSGreg Kroah-Hartman #define NI_E_AI_CFG_HI_TYPE_GROUND NI_E_AI_CFG_HI_TYPE(3) 586*8ffdff6aSGreg Kroah-Hartman #define NI_E_AI_CFG_HI_AC_COUPLE BIT(11) 587*8ffdff6aSGreg Kroah-Hartman #define NI_E_AI_CFG_HI_CHAN(x) (((x) & 0x3f) << 0) 588*8ffdff6aSGreg Kroah-Hartman 589*8ffdff6aSGreg Kroah-Hartman #define NI_E_AO_CFG_REG 0x16 /* w16 */ 590*8ffdff6aSGreg Kroah-Hartman #define NI_E_AO_DACSEL(x) ((x) << 8) 591*8ffdff6aSGreg Kroah-Hartman #define NI_E_AO_GROUND_REF BIT(3) 592*8ffdff6aSGreg Kroah-Hartman #define NI_E_AO_EXT_REF BIT(2) 593*8ffdff6aSGreg Kroah-Hartman #define NI_E_AO_DEGLITCH BIT(1) 594*8ffdff6aSGreg Kroah-Hartman #define NI_E_AO_CFG_BIP BIT(0) 595*8ffdff6aSGreg Kroah-Hartman 596*8ffdff6aSGreg Kroah-Hartman #define NI_E_DAC_DIRECT_DATA_REG(x) (0x18 + ((x) * 2)) /* w16 */ 597*8ffdff6aSGreg Kroah-Hartman 598*8ffdff6aSGreg Kroah-Hartman #define NI_E_8255_BASE 0x19 /* rw8 */ 599*8ffdff6aSGreg Kroah-Hartman 600*8ffdff6aSGreg Kroah-Hartman #define NI_E_AI_FIFO_DATA_REG 0x1c /* r16 */ 601*8ffdff6aSGreg Kroah-Hartman 602*8ffdff6aSGreg Kroah-Hartman #define NI_E_AO_FIFO_DATA_REG 0x1e /* w16 */ 603*8ffdff6aSGreg Kroah-Hartman 604*8ffdff6aSGreg Kroah-Hartman /* 605*8ffdff6aSGreg Kroah-Hartman * 611x registers (these boards differ from the e-series) 606*8ffdff6aSGreg Kroah-Hartman */ 607*8ffdff6aSGreg Kroah-Hartman #define NI611X_MAGIC_REG 0x19 /* w8 (new) */ 608*8ffdff6aSGreg Kroah-Hartman #define NI611X_CALIB_CHAN_SEL_REG 0x1a /* w16 (new) */ 609*8ffdff6aSGreg Kroah-Hartman #define NI611X_AI_FIFO_DATA_REG 0x1c /* r32 (incompatible) */ 610*8ffdff6aSGreg Kroah-Hartman #define NI611X_AI_FIFO_OFFSET_LOAD_REG 0x05 /* r8 (new) */ 611*8ffdff6aSGreg Kroah-Hartman #define NI611X_AO_FIFO_DATA_REG 0x14 /* w32 (incompatible) */ 612*8ffdff6aSGreg Kroah-Hartman #define NI611X_CAL_GAIN_SEL_REG 0x05 /* w8 (new) */ 613*8ffdff6aSGreg Kroah-Hartman 614*8ffdff6aSGreg Kroah-Hartman #define NI611X_AO_WINDOW_ADDR_REG 0x18 615*8ffdff6aSGreg Kroah-Hartman #define NI611X_AO_WINDOW_DATA_REG 0x1e 616*8ffdff6aSGreg Kroah-Hartman 617*8ffdff6aSGreg Kroah-Hartman /* 618*8ffdff6aSGreg Kroah-Hartman * 6143 registers 619*8ffdff6aSGreg Kroah-Hartman */ 620*8ffdff6aSGreg Kroah-Hartman #define NI6143_MAGIC_REG 0x19 /* w8 */ 621*8ffdff6aSGreg Kroah-Hartman #define NI6143_DMA_G0_G1_SEL_REG 0x0b /* w8 */ 622*8ffdff6aSGreg Kroah-Hartman #define NI6143_PIPELINE_DELAY_REG 0x1f /* w8 */ 623*8ffdff6aSGreg Kroah-Hartman #define NI6143_EOC_SET_REG 0x1d /* w8 */ 624*8ffdff6aSGreg Kroah-Hartman #define NI6143_DMA_AI_SEL_REG 0x09 /* w8 */ 625*8ffdff6aSGreg Kroah-Hartman #define NI6143_AI_FIFO_DATA_REG 0x8c /* r32 */ 626*8ffdff6aSGreg Kroah-Hartman #define NI6143_AI_FIFO_FLAG_REG 0x84 /* w32 */ 627*8ffdff6aSGreg Kroah-Hartman #define NI6143_AI_FIFO_CTRL_REG 0x88 /* w32 */ 628*8ffdff6aSGreg Kroah-Hartman #define NI6143_AI_FIFO_STATUS_REG 0x88 /* r32 */ 629*8ffdff6aSGreg Kroah-Hartman #define NI6143_AI_FIFO_DMA_THRESH_REG 0x90 /* w32 */ 630*8ffdff6aSGreg Kroah-Hartman #define NI6143_AI_FIFO_WORDS_AVAIL_REG 0x94 /* w32 */ 631*8ffdff6aSGreg Kroah-Hartman 632*8ffdff6aSGreg Kroah-Hartman #define NI6143_CALIB_CHAN_REG 0x42 /* w16 */ 633*8ffdff6aSGreg Kroah-Hartman #define NI6143_CALIB_CHAN_RELAY_ON BIT(15) 634*8ffdff6aSGreg Kroah-Hartman #define NI6143_CALIB_CHAN_RELAY_OFF BIT(14) 635*8ffdff6aSGreg Kroah-Hartman #define NI6143_CALIB_CHAN(x) (((x) & 0xf) << 0) 636*8ffdff6aSGreg Kroah-Hartman #define NI6143_CALIB_CHAN_GND_GND NI6143_CALIB_CHAN(0) /* Offset Cal */ 637*8ffdff6aSGreg Kroah-Hartman #define NI6143_CALIB_CHAN_2V5_GND NI6143_CALIB_CHAN(2) /* 2.5V ref */ 638*8ffdff6aSGreg Kroah-Hartman #define NI6143_CALIB_CHAN_PWM_GND NI6143_CALIB_CHAN(5) /* +-5V Self Cal */ 639*8ffdff6aSGreg Kroah-Hartman #define NI6143_CALIB_CHAN_2V5_PWM NI6143_CALIB_CHAN(10) /* PWM Cal */ 640*8ffdff6aSGreg Kroah-Hartman #define NI6143_CALIB_CHAN_PWM_PWM NI6143_CALIB_CHAN(13) /* CMRR */ 641*8ffdff6aSGreg Kroah-Hartman #define NI6143_CALIB_CHAN_GND_PWM NI6143_CALIB_CHAN(14) /* PWM Cal */ 642*8ffdff6aSGreg Kroah-Hartman #define NI6143_CALIB_LO_TIME_REG 0x20 /* w16 */ 643*8ffdff6aSGreg Kroah-Hartman #define NI6143_CALIB_HI_TIME_REG 0x22 /* w16 */ 644*8ffdff6aSGreg Kroah-Hartman #define NI6143_RELAY_COUNTER_LOAD_REG 0x4c /* w32 */ 645*8ffdff6aSGreg Kroah-Hartman #define NI6143_SIGNATURE_REG 0x50 /* w32 */ 646*8ffdff6aSGreg Kroah-Hartman #define NI6143_RELEASE_DATE_REG 0x54 /* w32 */ 647*8ffdff6aSGreg Kroah-Hartman #define NI6143_RELEASE_OLDEST_DATE_REG 0x58 /* w32 */ 648*8ffdff6aSGreg Kroah-Hartman 649*8ffdff6aSGreg Kroah-Hartman /* 650*8ffdff6aSGreg Kroah-Hartman * 671x, 611x windowed ao registers 651*8ffdff6aSGreg Kroah-Hartman */ 652*8ffdff6aSGreg Kroah-Hartman #define NI671X_DAC_DIRECT_DATA_REG(x) (0x00 + (x)) /* w16 */ 653*8ffdff6aSGreg Kroah-Hartman #define NI611X_AO_TIMED_REG 0x10 /* w16 */ 654*8ffdff6aSGreg Kroah-Hartman #define NI671X_AO_IMMEDIATE_REG 0x11 /* w16 */ 655*8ffdff6aSGreg Kroah-Hartman #define NI611X_AO_FIFO_OFFSET_LOAD_REG 0x13 /* w32 */ 656*8ffdff6aSGreg Kroah-Hartman #define NI67XX_AO_SP_UPDATES_REG 0x14 /* w16 */ 657*8ffdff6aSGreg Kroah-Hartman #define NI611X_AO_WAVEFORM_GEN_REG 0x15 /* w16 */ 658*8ffdff6aSGreg Kroah-Hartman #define NI611X_AO_MISC_REG 0x16 /* w16 */ 659*8ffdff6aSGreg Kroah-Hartman #define NI611X_AO_MISC_CLEAR_WG BIT(0) 660*8ffdff6aSGreg Kroah-Hartman #define NI67XX_AO_CAL_CHAN_SEL_REG 0x17 /* w16 */ 661*8ffdff6aSGreg Kroah-Hartman #define NI67XX_AO_CFG2_REG 0x18 /* w16 */ 662*8ffdff6aSGreg Kroah-Hartman #define NI67XX_CAL_CMD_REG 0x19 /* w16 */ 663*8ffdff6aSGreg Kroah-Hartman #define NI67XX_CAL_STATUS_REG 0x1a /* r8 */ 664*8ffdff6aSGreg Kroah-Hartman #define NI67XX_CAL_STATUS_BUSY BIT(0) 665*8ffdff6aSGreg Kroah-Hartman #define NI67XX_CAL_STATUS_OSC_DETECT BIT(1) 666*8ffdff6aSGreg Kroah-Hartman #define NI67XX_CAL_STATUS_OVERRANGE BIT(2) 667*8ffdff6aSGreg Kroah-Hartman #define NI67XX_CAL_DATA_REG 0x1b /* r16 */ 668*8ffdff6aSGreg Kroah-Hartman #define NI67XX_CAL_CFG_HI_REG 0x1c /* rw16 */ 669*8ffdff6aSGreg Kroah-Hartman #define NI67XX_CAL_CFG_LO_REG 0x1d /* rw16 */ 670*8ffdff6aSGreg Kroah-Hartman 671*8ffdff6aSGreg Kroah-Hartman #define CS5529_CMD_CB BIT(7) 672*8ffdff6aSGreg Kroah-Hartman #define CS5529_CMD_SINGLE_CONV BIT(6) 673*8ffdff6aSGreg Kroah-Hartman #define CS5529_CMD_CONT_CONV BIT(5) 674*8ffdff6aSGreg Kroah-Hartman #define CS5529_CMD_READ BIT(4) 675*8ffdff6aSGreg Kroah-Hartman #define CS5529_CMD_REG(x) (((x) & 0x7) << 1) 676*8ffdff6aSGreg Kroah-Hartman #define CS5529_CMD_REG_MASK CS5529_CMD_REG(7) 677*8ffdff6aSGreg Kroah-Hartman #define CS5529_CMD_PWR_SAVE BIT(0) 678*8ffdff6aSGreg Kroah-Hartman 679*8ffdff6aSGreg Kroah-Hartman #define CS5529_OFFSET_REG CS5529_CMD_REG(0) 680*8ffdff6aSGreg Kroah-Hartman #define CS5529_GAIN_REG CS5529_CMD_REG(1) 681*8ffdff6aSGreg Kroah-Hartman #define CS5529_CONV_DATA_REG CS5529_CMD_REG(3) 682*8ffdff6aSGreg Kroah-Hartman #define CS5529_SETUP_REG CS5529_CMD_REG(4) 683*8ffdff6aSGreg Kroah-Hartman 684*8ffdff6aSGreg Kroah-Hartman #define CS5529_CFG_REG CS5529_CMD_REG(2) 685*8ffdff6aSGreg Kroah-Hartman #define CS5529_CFG_AOUT(x) BIT(22 + (x)) 686*8ffdff6aSGreg Kroah-Hartman #define CS5529_CFG_DOUT(x) BIT(18 + (x)) 687*8ffdff6aSGreg Kroah-Hartman #define CS5529_CFG_LOW_PWR_MODE BIT(16) 688*8ffdff6aSGreg Kroah-Hartman #define CS5529_CFG_WORD_RATE(x) (((x) & 0x7) << 13) 689*8ffdff6aSGreg Kroah-Hartman #define CS5529_CFG_WORD_RATE_MASK CS5529_CFG_WORD_RATE(0x7) 690*8ffdff6aSGreg Kroah-Hartman #define CS5529_CFG_WORD_RATE_2180 CS5529_CFG_WORD_RATE(0) 691*8ffdff6aSGreg Kroah-Hartman #define CS5529_CFG_WORD_RATE_1092 CS5529_CFG_WORD_RATE(1) 692*8ffdff6aSGreg Kroah-Hartman #define CS5529_CFG_WORD_RATE_532 CS5529_CFG_WORD_RATE(2) 693*8ffdff6aSGreg Kroah-Hartman #define CS5529_CFG_WORD_RATE_388 CS5529_CFG_WORD_RATE(3) 694*8ffdff6aSGreg Kroah-Hartman #define CS5529_CFG_WORD_RATE_324 CS5529_CFG_WORD_RATE(4) 695*8ffdff6aSGreg Kroah-Hartman #define CS5529_CFG_WORD_RATE_17444 CS5529_CFG_WORD_RATE(5) 696*8ffdff6aSGreg Kroah-Hartman #define CS5529_CFG_WORD_RATE_8724 CS5529_CFG_WORD_RATE(6) 697*8ffdff6aSGreg Kroah-Hartman #define CS5529_CFG_WORD_RATE_4364 CS5529_CFG_WORD_RATE(7) 698*8ffdff6aSGreg Kroah-Hartman #define CS5529_CFG_UNIPOLAR BIT(12) 699*8ffdff6aSGreg Kroah-Hartman #define CS5529_CFG_RESET BIT(7) 700*8ffdff6aSGreg Kroah-Hartman #define CS5529_CFG_RESET_VALID BIT(6) 701*8ffdff6aSGreg Kroah-Hartman #define CS5529_CFG_PORT_FLAG BIT(5) 702*8ffdff6aSGreg Kroah-Hartman #define CS5529_CFG_PWR_SAVE_SEL BIT(4) 703*8ffdff6aSGreg Kroah-Hartman #define CS5529_CFG_DONE_FLAG BIT(3) 704*8ffdff6aSGreg Kroah-Hartman #define CS5529_CFG_CALIB(x) (((x) & 0x7) << 0) 705*8ffdff6aSGreg Kroah-Hartman #define CS5529_CFG_CALIB_NONE CS5529_CFG_CALIB(0) 706*8ffdff6aSGreg Kroah-Hartman #define CS5529_CFG_CALIB_OFFSET_SELF CS5529_CFG_CALIB(1) 707*8ffdff6aSGreg Kroah-Hartman #define CS5529_CFG_CALIB_GAIN_SELF CS5529_CFG_CALIB(2) 708*8ffdff6aSGreg Kroah-Hartman #define CS5529_CFG_CALIB_BOTH_SELF CS5529_CFG_CALIB(3) 709*8ffdff6aSGreg Kroah-Hartman #define CS5529_CFG_CALIB_OFFSET_SYS CS5529_CFG_CALIB(5) 710*8ffdff6aSGreg Kroah-Hartman #define CS5529_CFG_CALIB_GAIN_SYS CS5529_CFG_CALIB(6) 711*8ffdff6aSGreg Kroah-Hartman 712*8ffdff6aSGreg Kroah-Hartman /* 713*8ffdff6aSGreg Kroah-Hartman * M-Series specific registers not handled by the DAQ-STC and GPCT register 714*8ffdff6aSGreg Kroah-Hartman * remapping. 715*8ffdff6aSGreg Kroah-Hartman */ 716*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDIO_DMA_SEL_REG 0x007 717*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDIO_DMA_SEL_CDO(x) (((x) & 0xf) << 4) 718*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDIO_DMA_SEL_CDO_MASK NI_M_CDIO_DMA_SEL_CDO(0xf) 719*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDIO_DMA_SEL_CDI(x) (((x) & 0xf) << 0) 720*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDIO_DMA_SEL_CDI_MASK NI_M_CDIO_DMA_SEL_CDI(0xf) 721*8ffdff6aSGreg Kroah-Hartman #define NI_M_SCXI_STATUS_REG 0x007 722*8ffdff6aSGreg Kroah-Hartman #define NI_M_AI_AO_SEL_REG 0x009 723*8ffdff6aSGreg Kroah-Hartman #define NI_M_G0_G1_SEL_REG 0x00b 724*8ffdff6aSGreg Kroah-Hartman #define NI_M_MISC_CMD_REG 0x00f 725*8ffdff6aSGreg Kroah-Hartman #define NI_M_SCXI_SER_DO_REG 0x011 726*8ffdff6aSGreg Kroah-Hartman #define NI_M_SCXI_CTRL_REG 0x013 727*8ffdff6aSGreg Kroah-Hartman #define NI_M_SCXI_OUT_ENA_REG 0x015 728*8ffdff6aSGreg Kroah-Hartman #define NI_M_AI_FIFO_DATA_REG 0x01c 729*8ffdff6aSGreg Kroah-Hartman #define NI_M_DIO_REG 0x024 730*8ffdff6aSGreg Kroah-Hartman #define NI_M_DIO_DIR_REG 0x028 731*8ffdff6aSGreg Kroah-Hartman #define NI_M_CAL_PWM_REG 0x040 732*8ffdff6aSGreg Kroah-Hartman #define NI_M_CAL_PWM_HIGH_TIME(x) (((x) & 0xffff) << 16) 733*8ffdff6aSGreg Kroah-Hartman #define NI_M_CAL_PWM_LOW_TIME(x) (((x) & 0xffff) << 0) 734*8ffdff6aSGreg Kroah-Hartman #define NI_M_GEN_PWM_REG(x) (0x044 + ((x) * 2)) 735*8ffdff6aSGreg Kroah-Hartman #define NI_M_AI_CFG_FIFO_DATA_REG 0x05e 736*8ffdff6aSGreg Kroah-Hartman #define NI_M_AI_CFG_LAST_CHAN BIT(14) 737*8ffdff6aSGreg Kroah-Hartman #define NI_M_AI_CFG_DITHER BIT(13) 738*8ffdff6aSGreg Kroah-Hartman #define NI_M_AI_CFG_POLARITY BIT(12) 739*8ffdff6aSGreg Kroah-Hartman #define NI_M_AI_CFG_GAIN(x) (((x) & 0x7) << 9) 740*8ffdff6aSGreg Kroah-Hartman #define NI_M_AI_CFG_CHAN_TYPE(x) (((x) & 0x7) << 6) 741*8ffdff6aSGreg Kroah-Hartman #define NI_M_AI_CFG_CHAN_TYPE_MASK NI_M_AI_CFG_CHAN_TYPE(7) 742*8ffdff6aSGreg Kroah-Hartman #define NI_M_AI_CFG_CHAN_TYPE_CALIB NI_M_AI_CFG_CHAN_TYPE(0) 743*8ffdff6aSGreg Kroah-Hartman #define NI_M_AI_CFG_CHAN_TYPE_DIFF NI_M_AI_CFG_CHAN_TYPE(1) 744*8ffdff6aSGreg Kroah-Hartman #define NI_M_AI_CFG_CHAN_TYPE_COMMON NI_M_AI_CFG_CHAN_TYPE(2) 745*8ffdff6aSGreg Kroah-Hartman #define NI_M_AI_CFG_CHAN_TYPE_GROUND NI_M_AI_CFG_CHAN_TYPE(3) 746*8ffdff6aSGreg Kroah-Hartman #define NI_M_AI_CFG_CHAN_TYPE_AUX NI_M_AI_CFG_CHAN_TYPE(5) 747*8ffdff6aSGreg Kroah-Hartman #define NI_M_AI_CFG_CHAN_TYPE_GHOST NI_M_AI_CFG_CHAN_TYPE(7) 748*8ffdff6aSGreg Kroah-Hartman #define NI_M_AI_CFG_BANK_SEL(x) ((((x) & 0x40) << 4) | ((x) & 0x30)) 749*8ffdff6aSGreg Kroah-Hartman #define NI_M_AI_CFG_CHAN_SEL(x) (((x) & 0xf) << 0) 750*8ffdff6aSGreg Kroah-Hartman #define NI_M_INTC_ENA_REG 0x088 751*8ffdff6aSGreg Kroah-Hartman #define NI_M_INTC_ENA BIT(0) 752*8ffdff6aSGreg Kroah-Hartman #define NI_M_INTC_STATUS_REG 0x088 753*8ffdff6aSGreg Kroah-Hartman #define NI_M_INTC_STATUS BIT(0) 754*8ffdff6aSGreg Kroah-Hartman #define NI_M_ATRIG_CTRL_REG 0x08c 755*8ffdff6aSGreg Kroah-Hartman #define NI_M_AO_SER_INT_ENA_REG 0x0a0 756*8ffdff6aSGreg Kroah-Hartman #define NI_M_AO_SER_INT_ACK_REG 0x0a1 757*8ffdff6aSGreg Kroah-Hartman #define NI_M_AO_SER_INT_STATUS_REG 0x0a1 758*8ffdff6aSGreg Kroah-Hartman #define NI_M_AO_CALIB_REG 0x0a3 759*8ffdff6aSGreg Kroah-Hartman #define NI_M_AO_FIFO_DATA_REG 0x0a4 760*8ffdff6aSGreg Kroah-Hartman #define NI_M_PFI_FILTER_REG 0x0b0 761*8ffdff6aSGreg Kroah-Hartman #define NI_M_PFI_FILTER_SEL(_c, _f) (((_f) & 0x3) << ((_c) * 2)) 762*8ffdff6aSGreg Kroah-Hartman #define NI_M_PFI_FILTER_SEL_MASK(_c) NI_M_PFI_FILTER_SEL((_c), 0x3) 763*8ffdff6aSGreg Kroah-Hartman #define NI_M_RTSI_FILTER_REG 0x0b4 764*8ffdff6aSGreg Kroah-Hartman #define NI_M_SCXI_LEGACY_COMPAT_REG 0x0bc 765*8ffdff6aSGreg Kroah-Hartman #define NI_M_DAC_DIRECT_DATA_REG(x) (0x0c0 + ((x) * 4)) 766*8ffdff6aSGreg Kroah-Hartman #define NI_M_AO_WAVEFORM_ORDER_REG(x) (0x0c2 + ((x) * 4)) 767*8ffdff6aSGreg Kroah-Hartman #define NI_M_AO_CFG_BANK_REG(x) (0x0c3 + ((x) * 4)) 768*8ffdff6aSGreg Kroah-Hartman #define NI_M_AO_CFG_BANK_BIPOLAR BIT(7) 769*8ffdff6aSGreg Kroah-Hartman #define NI_M_AO_CFG_BANK_UPDATE_TIMED BIT(6) 770*8ffdff6aSGreg Kroah-Hartman #define NI_M_AO_CFG_BANK_REF(x) (((x) & 0x7) << 3) 771*8ffdff6aSGreg Kroah-Hartman #define NI_M_AO_CFG_BANK_REF_MASK NI_M_AO_CFG_BANK_REF(7) 772*8ffdff6aSGreg Kroah-Hartman #define NI_M_AO_CFG_BANK_REF_INT_10V NI_M_AO_CFG_BANK_REF(0) 773*8ffdff6aSGreg Kroah-Hartman #define NI_M_AO_CFG_BANK_REF_INT_5V NI_M_AO_CFG_BANK_REF(1) 774*8ffdff6aSGreg Kroah-Hartman #define NI_M_AO_CFG_BANK_OFFSET(x) (((x) & 0x7) << 0) 775*8ffdff6aSGreg Kroah-Hartman #define NI_M_AO_CFG_BANK_OFFSET_MASK NI_M_AO_CFG_BANK_OFFSET(7) 776*8ffdff6aSGreg Kroah-Hartman #define NI_M_AO_CFG_BANK_OFFSET_0V NI_M_AO_CFG_BANK_OFFSET(0) 777*8ffdff6aSGreg Kroah-Hartman #define NI_M_AO_CFG_BANK_OFFSET_5V NI_M_AO_CFG_BANK_OFFSET(1) 778*8ffdff6aSGreg Kroah-Hartman #define NI_M_RTSI_SHARED_MUX_REG 0x1a2 779*8ffdff6aSGreg Kroah-Hartman #define NI_M_CLK_FOUT2_REG 0x1c4 780*8ffdff6aSGreg Kroah-Hartman #define NI_M_CLK_FOUT2_RTSI_10MHZ BIT(7) 781*8ffdff6aSGreg Kroah-Hartman #define NI_M_CLK_FOUT2_TIMEBASE3_PLL BIT(6) 782*8ffdff6aSGreg Kroah-Hartman #define NI_M_CLK_FOUT2_TIMEBASE1_PLL BIT(5) 783*8ffdff6aSGreg Kroah-Hartman #define NI_M_CLK_FOUT2_PLL_SRC(x) (((x) & 0x1f) << 0) 784*8ffdff6aSGreg Kroah-Hartman #define NI_M_CLK_FOUT2_PLL_SRC_MASK NI_M_CLK_FOUT2_PLL_SRC(0x1f) 785*8ffdff6aSGreg Kroah-Hartman #define NI_M_MAX_RTSI_CHAN 7 786*8ffdff6aSGreg Kroah-Hartman #define NI_M_CLK_FOUT2_PLL_SRC_RTSI(x) (((x) == NI_M_MAX_RTSI_CHAN) \ 787*8ffdff6aSGreg Kroah-Hartman ? NI_M_CLK_FOUT2_PLL_SRC(0x1b) \ 788*8ffdff6aSGreg Kroah-Hartman : NI_M_CLK_FOUT2_PLL_SRC(0xb + (x))) 789*8ffdff6aSGreg Kroah-Hartman #define NI_M_CLK_FOUT2_PLL_SRC_STAR NI_M_CLK_FOUT2_PLL_SRC(0x14) 790*8ffdff6aSGreg Kroah-Hartman #define NI_M_CLK_FOUT2_PLL_SRC_PXI10 NI_M_CLK_FOUT2_PLL_SRC(0x1d) 791*8ffdff6aSGreg Kroah-Hartman #define NI_M_PLL_CTRL_REG 0x1c6 792*8ffdff6aSGreg Kroah-Hartman #define NI_M_PLL_CTRL_VCO_MODE(x) (((x) & 0x3) << 13) 793*8ffdff6aSGreg Kroah-Hartman #define NI_M_PLL_CTRL_VCO_MODE_200_325MHZ NI_M_PLL_CTRL_VCO_MODE(0) 794*8ffdff6aSGreg Kroah-Hartman #define NI_M_PLL_CTRL_VCO_MODE_175_225MHZ NI_M_PLL_CTRL_VCO_MODE(1) 795*8ffdff6aSGreg Kroah-Hartman #define NI_M_PLL_CTRL_VCO_MODE_100_225MHZ NI_M_PLL_CTRL_VCO_MODE(2) 796*8ffdff6aSGreg Kroah-Hartman #define NI_M_PLL_CTRL_VCO_MODE_75_150MHZ NI_M_PLL_CTRL_VCO_MODE(3) 797*8ffdff6aSGreg Kroah-Hartman #define NI_M_PLL_CTRL_ENA BIT(12) 798*8ffdff6aSGreg Kroah-Hartman #define NI_M_PLL_MAX_DIVISOR 0x10 799*8ffdff6aSGreg Kroah-Hartman #define NI_M_PLL_CTRL_DIVISOR(x) (((x) & 0xf) << 8) 800*8ffdff6aSGreg Kroah-Hartman #define NI_M_PLL_MAX_MULTIPLIER 0x100 801*8ffdff6aSGreg Kroah-Hartman #define NI_M_PLL_CTRL_MULTIPLIER(x) (((x) & 0xff) << 0) 802*8ffdff6aSGreg Kroah-Hartman #define NI_M_PLL_STATUS_REG 0x1c8 803*8ffdff6aSGreg Kroah-Hartman #define NI_M_PLL_STATUS_LOCKED BIT(0) 804*8ffdff6aSGreg Kroah-Hartman #define NI_M_PFI_OUT_SEL_REG(x) (0x1d0 + ((x) * 2)) 805*8ffdff6aSGreg Kroah-Hartman #define NI_M_PFI_CHAN(_c) (((_c) % 3) * 5) 806*8ffdff6aSGreg Kroah-Hartman #define NI_M_PFI_OUT_SEL(_c, _s) (((_s) & 0x1f) << NI_M_PFI_CHAN(_c)) 807*8ffdff6aSGreg Kroah-Hartman #define NI_M_PFI_OUT_SEL_MASK(_c) (0x1f << NI_M_PFI_CHAN(_c)) 808*8ffdff6aSGreg Kroah-Hartman #define NI_M_PFI_OUT_SEL_TO_SRC(_c, _b) (((_b) >> NI_M_PFI_CHAN(_c)) & 0x1f) 809*8ffdff6aSGreg Kroah-Hartman #define NI_M_PFI_DI_REG 0x1dc 810*8ffdff6aSGreg Kroah-Hartman #define NI_M_PFI_DO_REG 0x1de 811*8ffdff6aSGreg Kroah-Hartman #define NI_M_CFG_BYPASS_FIFO_REG 0x218 812*8ffdff6aSGreg Kroah-Hartman #define NI_M_CFG_BYPASS_FIFO BIT(31) 813*8ffdff6aSGreg Kroah-Hartman #define NI_M_CFG_BYPASS_AI_POLARITY BIT(22) 814*8ffdff6aSGreg Kroah-Hartman #define NI_M_CFG_BYPASS_AI_DITHER BIT(21) 815*8ffdff6aSGreg Kroah-Hartman #define NI_M_CFG_BYPASS_AI_GAIN(x) (((x) & 0x7) << 18) 816*8ffdff6aSGreg Kroah-Hartman #define NI_M_CFG_BYPASS_AO_CAL(x) (((x) & 0xf) << 15) 817*8ffdff6aSGreg Kroah-Hartman #define NI_M_CFG_BYPASS_AO_CAL_MASK NI_M_CFG_BYPASS_AO_CAL(0xf) 818*8ffdff6aSGreg Kroah-Hartman #define NI_M_CFG_BYPASS_AI_MODE_MUX(x) (((x) & 0x3) << 13) 819*8ffdff6aSGreg Kroah-Hartman #define NI_M_CFG_BYPASS_AI_MODE_MUX_MASK NI_M_CFG_BYPASS_AI_MODE_MUX(3) 820*8ffdff6aSGreg Kroah-Hartman #define NI_M_CFG_BYPASS_AI_CAL_NEG(x) (((x) & 0x7) << 10) 821*8ffdff6aSGreg Kroah-Hartman #define NI_M_CFG_BYPASS_AI_CAL_NEG_MASK NI_M_CFG_BYPASS_AI_CAL_NEG(7) 822*8ffdff6aSGreg Kroah-Hartman #define NI_M_CFG_BYPASS_AI_CAL_POS(x) (((x) & 0x7) << 7) 823*8ffdff6aSGreg Kroah-Hartman #define NI_M_CFG_BYPASS_AI_CAL_POS_MASK NI_M_CFG_BYPASS_AI_CAL_POS(7) 824*8ffdff6aSGreg Kroah-Hartman #define NI_M_CFG_BYPASS_AI_CAL_MASK (NI_M_CFG_BYPASS_AI_CAL_POS_MASK | \ 825*8ffdff6aSGreg Kroah-Hartman NI_M_CFG_BYPASS_AI_CAL_NEG_MASK | \ 826*8ffdff6aSGreg Kroah-Hartman NI_M_CFG_BYPASS_AI_MODE_MUX_MASK | \ 827*8ffdff6aSGreg Kroah-Hartman NI_M_CFG_BYPASS_AO_CAL_MASK) 828*8ffdff6aSGreg Kroah-Hartman #define NI_M_CFG_BYPASS_AI_BANK(x) (((x) & 0xf) << 3) 829*8ffdff6aSGreg Kroah-Hartman #define NI_M_CFG_BYPASS_AI_BANK_MASK NI_M_CFG_BYPASS_AI_BANK(0xf) 830*8ffdff6aSGreg Kroah-Hartman #define NI_M_CFG_BYPASS_AI_CHAN(x) (((x) & 0x7) << 0) 831*8ffdff6aSGreg Kroah-Hartman #define NI_M_CFG_BYPASS_AI_CHAN_MASK NI_M_CFG_BYPASS_AI_CHAN(7) 832*8ffdff6aSGreg Kroah-Hartman #define NI_M_SCXI_DIO_ENA_REG 0x21c 833*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDI_FIFO_DATA_REG 0x220 834*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDO_FIFO_DATA_REG 0x220 835*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDIO_STATUS_REG 0x224 836*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDIO_STATUS_CDI_OVERFLOW BIT(20) 837*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDIO_STATUS_CDI_OVERRUN BIT(19) 838*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDIO_STATUS_CDI_ERROR (NI_M_CDIO_STATUS_CDI_OVERFLOW | \ 839*8ffdff6aSGreg Kroah-Hartman NI_M_CDIO_STATUS_CDI_OVERRUN) 840*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDIO_STATUS_CDI_FIFO_REQ BIT(18) 841*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDIO_STATUS_CDI_FIFO_FULL BIT(17) 842*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDIO_STATUS_CDI_FIFO_EMPTY BIT(16) 843*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDIO_STATUS_CDO_UNDERFLOW BIT(4) 844*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDIO_STATUS_CDO_OVERRUN BIT(3) 845*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDIO_STATUS_CDO_ERROR (NI_M_CDIO_STATUS_CDO_UNDERFLOW | \ 846*8ffdff6aSGreg Kroah-Hartman NI_M_CDIO_STATUS_CDO_OVERRUN) 847*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDIO_STATUS_CDO_FIFO_REQ BIT(2) 848*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDIO_STATUS_CDO_FIFO_FULL BIT(1) 849*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDIO_STATUS_CDO_FIFO_EMPTY BIT(0) 850*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDIO_CMD_REG 0x224 851*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDI_CMD_SW_UPDATE BIT(20) 852*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDO_CMD_SW_UPDATE BIT(19) 853*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDO_CMD_F_E_INT_ENA_CLR BIT(17) 854*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDO_CMD_F_E_INT_ENA_SET BIT(16) 855*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDI_CMD_ERR_INT_CONFIRM BIT(15) 856*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDO_CMD_ERR_INT_CONFIRM BIT(14) 857*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDI_CMD_F_REQ_INT_ENA_CLR BIT(13) 858*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDI_CMD_F_REQ_INT_ENA_SET BIT(12) 859*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDO_CMD_F_REQ_INT_ENA_CLR BIT(11) 860*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDO_CMD_F_REQ_INT_ENA_SET BIT(10) 861*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDI_CMD_ERR_INT_ENA_CLR BIT(9) 862*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDI_CMD_ERR_INT_ENA_SET BIT(8) 863*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDO_CMD_ERR_INT_ENA_CLR BIT(7) 864*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDO_CMD_ERR_INT_ENA_SET BIT(6) 865*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDI_CMD_RESET BIT(5) 866*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDO_CMD_RESET BIT(4) 867*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDI_CMD_ARM BIT(3) 868*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDI_CMD_DISARM BIT(2) 869*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDO_CMD_ARM BIT(1) 870*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDO_CMD_DISARM BIT(0) 871*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDI_MODE_REG 0x228 872*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDI_MODE_DATA_LANE(x) (((x) & 0x3) << 12) 873*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDI_MODE_DATA_LANE_MASK NI_M_CDI_MODE_DATA_LANE(3) 874*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDI_MODE_DATA_LANE_0_15 NI_M_CDI_MODE_DATA_LANE(0) 875*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDI_MODE_DATA_LANE_16_31 NI_M_CDI_MODE_DATA_LANE(1) 876*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDI_MODE_DATA_LANE_0_7 NI_M_CDI_MODE_DATA_LANE(0) 877*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDI_MODE_DATA_LANE_8_15 NI_M_CDI_MODE_DATA_LANE(1) 878*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDI_MODE_DATA_LANE_16_23 NI_M_CDI_MODE_DATA_LANE(2) 879*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDI_MODE_DATA_LANE_24_31 NI_M_CDI_MODE_DATA_LANE(3) 880*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDI_MODE_FIFO_MODE BIT(11) 881*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDI_MODE_POLARITY BIT(10) 882*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDI_MODE_HALT_ON_ERROR BIT(9) 883*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDI_MODE_SAMPLE_SRC(x) (((x) & 0x3f) << 0) 884*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDI_MODE_SAMPLE_SRC_MASK NI_M_CDI_MODE_SAMPLE_SRC(0x3f) 885*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDO_MODE_REG 0x22c 886*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDO_MODE_DATA_LANE(x) (((x) & 0x3) << 12) 887*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDO_MODE_DATA_LANE_MASK NI_M_CDO_MODE_DATA_LANE(3) 888*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDO_MODE_DATA_LANE_0_15 NI_M_CDO_MODE_DATA_LANE(0) 889*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDO_MODE_DATA_LANE_16_31 NI_M_CDO_MODE_DATA_LANE(1) 890*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDO_MODE_DATA_LANE_0_7 NI_M_CDO_MODE_DATA_LANE(0) 891*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDO_MODE_DATA_LANE_8_15 NI_M_CDO_MODE_DATA_LANE(1) 892*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDO_MODE_DATA_LANE_16_23 NI_M_CDO_MODE_DATA_LANE(2) 893*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDO_MODE_DATA_LANE_24_31 NI_M_CDO_MODE_DATA_LANE(3) 894*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDO_MODE_FIFO_MODE BIT(11) 895*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDO_MODE_POLARITY BIT(10) 896*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDO_MODE_HALT_ON_ERROR BIT(9) 897*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDO_MODE_RETRANSMIT BIT(8) 898*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDO_MODE_SAMPLE_SRC(x) (((x) & 0x3f) << 0) 899*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDO_MODE_SAMPLE_SRC_MASK NI_M_CDO_MODE_SAMPLE_SRC(0x3f) 900*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDI_MASK_ENA_REG 0x230 901*8ffdff6aSGreg Kroah-Hartman #define NI_M_CDO_MASK_ENA_REG 0x234 902*8ffdff6aSGreg Kroah-Hartman #define NI_M_STATIC_AI_CTRL_REG(x) ((x) ? (0x260 + (x)) : 0x064) 903*8ffdff6aSGreg Kroah-Hartman #define NI_M_AO_REF_ATTENUATION_REG(x) (0x264 + (x)) 904*8ffdff6aSGreg Kroah-Hartman #define NI_M_AO_REF_ATTENUATION_X5 BIT(0) 905*8ffdff6aSGreg Kroah-Hartman 906*8ffdff6aSGreg Kroah-Hartman enum { 907*8ffdff6aSGreg Kroah-Hartman ai_gain_16 = 0, 908*8ffdff6aSGreg Kroah-Hartman ai_gain_8, 909*8ffdff6aSGreg Kroah-Hartman ai_gain_14, 910*8ffdff6aSGreg Kroah-Hartman ai_gain_4, 911*8ffdff6aSGreg Kroah-Hartman ai_gain_611x, 912*8ffdff6aSGreg Kroah-Hartman ai_gain_622x, 913*8ffdff6aSGreg Kroah-Hartman ai_gain_628x, 914*8ffdff6aSGreg Kroah-Hartman ai_gain_6143 915*8ffdff6aSGreg Kroah-Hartman }; 916*8ffdff6aSGreg Kroah-Hartman 917*8ffdff6aSGreg Kroah-Hartman enum caldac_enum { 918*8ffdff6aSGreg Kroah-Hartman caldac_none = 0, 919*8ffdff6aSGreg Kroah-Hartman mb88341, 920*8ffdff6aSGreg Kroah-Hartman dac8800, 921*8ffdff6aSGreg Kroah-Hartman dac8043, 922*8ffdff6aSGreg Kroah-Hartman ad8522, 923*8ffdff6aSGreg Kroah-Hartman ad8804, 924*8ffdff6aSGreg Kroah-Hartman ad8842, 925*8ffdff6aSGreg Kroah-Hartman ad8804_debug 926*8ffdff6aSGreg Kroah-Hartman }; 927*8ffdff6aSGreg Kroah-Hartman 928*8ffdff6aSGreg Kroah-Hartman enum ni_reg_type { 929*8ffdff6aSGreg Kroah-Hartman ni_reg_normal = 0x0, 930*8ffdff6aSGreg Kroah-Hartman ni_reg_611x = 0x1, 931*8ffdff6aSGreg Kroah-Hartman ni_reg_6711 = 0x2, 932*8ffdff6aSGreg Kroah-Hartman ni_reg_6713 = 0x4, 933*8ffdff6aSGreg Kroah-Hartman ni_reg_67xx_mask = 0x6, 934*8ffdff6aSGreg Kroah-Hartman ni_reg_6xxx_mask = 0x7, 935*8ffdff6aSGreg Kroah-Hartman ni_reg_622x = 0x8, 936*8ffdff6aSGreg Kroah-Hartman ni_reg_625x = 0x10, 937*8ffdff6aSGreg Kroah-Hartman ni_reg_628x = 0x18, 938*8ffdff6aSGreg Kroah-Hartman ni_reg_m_series_mask = 0x18, 939*8ffdff6aSGreg Kroah-Hartman ni_reg_6143 = 0x20 940*8ffdff6aSGreg Kroah-Hartman }; 941*8ffdff6aSGreg Kroah-Hartman 942*8ffdff6aSGreg Kroah-Hartman struct ni_board_struct { 943*8ffdff6aSGreg Kroah-Hartman const char *name; 944*8ffdff6aSGreg Kroah-Hartman const char *alt_route_name; 945*8ffdff6aSGreg Kroah-Hartman int device_id; 946*8ffdff6aSGreg Kroah-Hartman int isapnp_id; 947*8ffdff6aSGreg Kroah-Hartman 948*8ffdff6aSGreg Kroah-Hartman int n_adchan; 949*8ffdff6aSGreg Kroah-Hartman unsigned int ai_maxdata; 950*8ffdff6aSGreg Kroah-Hartman 951*8ffdff6aSGreg Kroah-Hartman int ai_fifo_depth; 952*8ffdff6aSGreg Kroah-Hartman unsigned int alwaysdither:1; 953*8ffdff6aSGreg Kroah-Hartman int gainlkup; 954*8ffdff6aSGreg Kroah-Hartman int ai_speed; 955*8ffdff6aSGreg Kroah-Hartman 956*8ffdff6aSGreg Kroah-Hartman int n_aochan; 957*8ffdff6aSGreg Kroah-Hartman unsigned int ao_maxdata; 958*8ffdff6aSGreg Kroah-Hartman int ao_fifo_depth; 959*8ffdff6aSGreg Kroah-Hartman const struct comedi_lrange *ao_range_table; 960*8ffdff6aSGreg Kroah-Hartman unsigned int ao_speed; 961*8ffdff6aSGreg Kroah-Hartman 962*8ffdff6aSGreg Kroah-Hartman int reg_type; 963*8ffdff6aSGreg Kroah-Hartman unsigned int has_8255:1; 964*8ffdff6aSGreg Kroah-Hartman unsigned int has_32dio_chan:1; 965*8ffdff6aSGreg Kroah-Hartman unsigned int dio_speed; /* not for e-series */ 966*8ffdff6aSGreg Kroah-Hartman 967*8ffdff6aSGreg Kroah-Hartman enum caldac_enum caldac[3]; 968*8ffdff6aSGreg Kroah-Hartman }; 969*8ffdff6aSGreg Kroah-Hartman 970*8ffdff6aSGreg Kroah-Hartman #define MAX_N_CALDACS 34 971*8ffdff6aSGreg Kroah-Hartman #define MAX_N_AO_CHAN 8 972*8ffdff6aSGreg Kroah-Hartman #define NUM_GPCT 2 973*8ffdff6aSGreg Kroah-Hartman 974*8ffdff6aSGreg Kroah-Hartman #define NUM_PFI_OUTPUT_SELECT_REGS 6 975*8ffdff6aSGreg Kroah-Hartman #define NUM_RTSI_SHARED_MUXS (NI_RTSI_BRD(-1) - NI_RTSI_BRD(0) + 1) 976*8ffdff6aSGreg Kroah-Hartman 977*8ffdff6aSGreg Kroah-Hartman #define M_SERIES_EEPROM_SIZE 1024 978*8ffdff6aSGreg Kroah-Hartman 979*8ffdff6aSGreg Kroah-Hartman struct ni_private { 980*8ffdff6aSGreg Kroah-Hartman unsigned short dio_output; 981*8ffdff6aSGreg Kroah-Hartman unsigned short dio_control; 982*8ffdff6aSGreg Kroah-Hartman int aimode; 983*8ffdff6aSGreg Kroah-Hartman unsigned int ai_calib_source; 984*8ffdff6aSGreg Kroah-Hartman unsigned int ai_calib_source_enabled; 985*8ffdff6aSGreg Kroah-Hartman /* protects access to windowed registers */ 986*8ffdff6aSGreg Kroah-Hartman spinlock_t window_lock; 987*8ffdff6aSGreg Kroah-Hartman /* protects interrupt/dma register access */ 988*8ffdff6aSGreg Kroah-Hartman spinlock_t soft_reg_copy_lock; 989*8ffdff6aSGreg Kroah-Hartman /* protects mite DMA channel request/release */ 990*8ffdff6aSGreg Kroah-Hartman spinlock_t mite_channel_lock; 991*8ffdff6aSGreg Kroah-Hartman 992*8ffdff6aSGreg Kroah-Hartman int changain_state; 993*8ffdff6aSGreg Kroah-Hartman unsigned int changain_spec; 994*8ffdff6aSGreg Kroah-Hartman 995*8ffdff6aSGreg Kroah-Hartman unsigned int caldac_maxdata_list[MAX_N_CALDACS]; 996*8ffdff6aSGreg Kroah-Hartman unsigned short caldacs[MAX_N_CALDACS]; 997*8ffdff6aSGreg Kroah-Hartman 998*8ffdff6aSGreg Kroah-Hartman unsigned short ai_cmd2; 999*8ffdff6aSGreg Kroah-Hartman 1000*8ffdff6aSGreg Kroah-Hartman unsigned short ao_conf[MAX_N_AO_CHAN]; 1001*8ffdff6aSGreg Kroah-Hartman unsigned short ao_mode1; 1002*8ffdff6aSGreg Kroah-Hartman unsigned short ao_mode2; 1003*8ffdff6aSGreg Kroah-Hartman unsigned short ao_mode3; 1004*8ffdff6aSGreg Kroah-Hartman unsigned short ao_cmd1; 1005*8ffdff6aSGreg Kroah-Hartman unsigned short ao_cmd2; 1006*8ffdff6aSGreg Kroah-Hartman 1007*8ffdff6aSGreg Kroah-Hartman struct ni_gpct_device *counter_dev; 1008*8ffdff6aSGreg Kroah-Hartman unsigned short an_trig_etc_reg; 1009*8ffdff6aSGreg Kroah-Hartman 1010*8ffdff6aSGreg Kroah-Hartman unsigned int ai_offset[512]; 1011*8ffdff6aSGreg Kroah-Hartman 1012*8ffdff6aSGreg Kroah-Hartman unsigned long serial_interval_ns; 1013*8ffdff6aSGreg Kroah-Hartman unsigned char serial_hw_mode; 1014*8ffdff6aSGreg Kroah-Hartman unsigned short clock_and_fout; 1015*8ffdff6aSGreg Kroah-Hartman unsigned short clock_and_fout2; 1016*8ffdff6aSGreg Kroah-Hartman 1017*8ffdff6aSGreg Kroah-Hartman unsigned short int_a_enable_reg; 1018*8ffdff6aSGreg Kroah-Hartman unsigned short int_b_enable_reg; 1019*8ffdff6aSGreg Kroah-Hartman unsigned short io_bidirection_pin_reg; 1020*8ffdff6aSGreg Kroah-Hartman unsigned short rtsi_trig_direction_reg; 1021*8ffdff6aSGreg Kroah-Hartman unsigned short rtsi_trig_a_output_reg; 1022*8ffdff6aSGreg Kroah-Hartman unsigned short rtsi_trig_b_output_reg; 1023*8ffdff6aSGreg Kroah-Hartman unsigned short pfi_output_select_reg[NUM_PFI_OUTPUT_SELECT_REGS]; 1024*8ffdff6aSGreg Kroah-Hartman unsigned short ai_ao_select_reg; 1025*8ffdff6aSGreg Kroah-Hartman unsigned short g0_g1_select_reg; 1026*8ffdff6aSGreg Kroah-Hartman unsigned short cdio_dma_select_reg; 1027*8ffdff6aSGreg Kroah-Hartman 1028*8ffdff6aSGreg Kroah-Hartman unsigned int clock_ns; 1029*8ffdff6aSGreg Kroah-Hartman unsigned int clock_source; 1030*8ffdff6aSGreg Kroah-Hartman 1031*8ffdff6aSGreg Kroah-Hartman unsigned short pwm_up_count; 1032*8ffdff6aSGreg Kroah-Hartman unsigned short pwm_down_count; 1033*8ffdff6aSGreg Kroah-Hartman 1034*8ffdff6aSGreg Kroah-Hartman unsigned short ai_fifo_buffer[0x2000]; 1035*8ffdff6aSGreg Kroah-Hartman u8 eeprom_buffer[M_SERIES_EEPROM_SIZE]; 1036*8ffdff6aSGreg Kroah-Hartman 1037*8ffdff6aSGreg Kroah-Hartman struct mite *mite; 1038*8ffdff6aSGreg Kroah-Hartman struct mite_channel *ai_mite_chan; 1039*8ffdff6aSGreg Kroah-Hartman struct mite_channel *ao_mite_chan; 1040*8ffdff6aSGreg Kroah-Hartman struct mite_channel *cdo_mite_chan; 1041*8ffdff6aSGreg Kroah-Hartman struct mite_ring *ai_mite_ring; 1042*8ffdff6aSGreg Kroah-Hartman struct mite_ring *ao_mite_ring; 1043*8ffdff6aSGreg Kroah-Hartman struct mite_ring *cdo_mite_ring; 1044*8ffdff6aSGreg Kroah-Hartman struct mite_ring *gpct_mite_ring[NUM_GPCT]; 1045*8ffdff6aSGreg Kroah-Hartman 1046*8ffdff6aSGreg Kroah-Hartman /* ni_pcimio board type flags (based on the boardinfo reg_type) */ 1047*8ffdff6aSGreg Kroah-Hartman unsigned int is_m_series:1; 1048*8ffdff6aSGreg Kroah-Hartman unsigned int is_6xxx:1; 1049*8ffdff6aSGreg Kroah-Hartman unsigned int is_611x:1; 1050*8ffdff6aSGreg Kroah-Hartman unsigned int is_6143:1; 1051*8ffdff6aSGreg Kroah-Hartman unsigned int is_622x:1; 1052*8ffdff6aSGreg Kroah-Hartman unsigned int is_625x:1; 1053*8ffdff6aSGreg Kroah-Hartman unsigned int is_628x:1; 1054*8ffdff6aSGreg Kroah-Hartman unsigned int is_67xx:1; 1055*8ffdff6aSGreg Kroah-Hartman unsigned int is_6711:1; 1056*8ffdff6aSGreg Kroah-Hartman unsigned int is_6713:1; 1057*8ffdff6aSGreg Kroah-Hartman 1058*8ffdff6aSGreg Kroah-Hartman /* 1059*8ffdff6aSGreg Kroah-Hartman * Boolean value of whether device needs to be armed. 1060*8ffdff6aSGreg Kroah-Hartman * 1061*8ffdff6aSGreg Kroah-Hartman * Currently, only NI AO devices are known to be needing arming, since 1062*8ffdff6aSGreg Kroah-Hartman * the DAC registers must be preloaded before triggering. 1063*8ffdff6aSGreg Kroah-Hartman * This variable should only be set true during a command operation 1064*8ffdff6aSGreg Kroah-Hartman * (e.g ni_ao_cmd) and should then be set false by the arming 1065*8ffdff6aSGreg Kroah-Hartman * function (e.g. ni_ao_arm). 1066*8ffdff6aSGreg Kroah-Hartman * 1067*8ffdff6aSGreg Kroah-Hartman * This variable helps to ensure that multiple DMA allocations are not 1068*8ffdff6aSGreg Kroah-Hartman * possible. 1069*8ffdff6aSGreg Kroah-Hartman */ 1070*8ffdff6aSGreg Kroah-Hartman unsigned int ao_needs_arming:1; 1071*8ffdff6aSGreg Kroah-Hartman 1072*8ffdff6aSGreg Kroah-Hartman /* device signal route tables */ 1073*8ffdff6aSGreg Kroah-Hartman struct ni_route_tables routing_tables; 1074*8ffdff6aSGreg Kroah-Hartman 1075*8ffdff6aSGreg Kroah-Hartman /* 1076*8ffdff6aSGreg Kroah-Hartman * Number of clients (RTSI lines) for current RTSI MUX source. 1077*8ffdff6aSGreg Kroah-Hartman * 1078*8ffdff6aSGreg Kroah-Hartman * This allows resource management of RTSI board/shared mux lines by 1079*8ffdff6aSGreg Kroah-Hartman * marking the RTSI line that is using a particular MUX. Currently, 1080*8ffdff6aSGreg Kroah-Hartman * these lines are only automatically allocated based on source of the 1081*8ffdff6aSGreg Kroah-Hartman * route requested. Furthermore, the only way that this auto-allocation 1082*8ffdff6aSGreg Kroah-Hartman * and configuration works is via the globally-named ni signal/terminal 1083*8ffdff6aSGreg Kroah-Hartman * names. 1084*8ffdff6aSGreg Kroah-Hartman */ 1085*8ffdff6aSGreg Kroah-Hartman u8 rtsi_shared_mux_usage[NUM_RTSI_SHARED_MUXS]; 1086*8ffdff6aSGreg Kroah-Hartman 1087*8ffdff6aSGreg Kroah-Hartman /* 1088*8ffdff6aSGreg Kroah-Hartman * softcopy register for rtsi shared mux/board lines. 1089*8ffdff6aSGreg Kroah-Hartman * For e-series, the bit layout of this register is 1090*8ffdff6aSGreg Kroah-Hartman * (docs: mhddk/nieseries/ChipObjects/tSTC.{h,ipp}, 1091*8ffdff6aSGreg Kroah-Hartman * DAQ-STC, Jan 1999, 340934B-01): 1092*8ffdff6aSGreg Kroah-Hartman * bits 0:2 -- NI_RTSI_BRD(0) source selection 1093*8ffdff6aSGreg Kroah-Hartman * bits 3:5 -- NI_RTSI_BRD(1) source selection 1094*8ffdff6aSGreg Kroah-Hartman * bits 6:8 -- NI_RTSI_BRD(2) source selection 1095*8ffdff6aSGreg Kroah-Hartman * bits 9:11 -- NI_RTSI_BRD(3) source selection 1096*8ffdff6aSGreg Kroah-Hartman * bit 12 -- NI_RTSI_BRD(0) direction, 0:input, 1:output 1097*8ffdff6aSGreg Kroah-Hartman * bit 13 -- NI_RTSI_BRD(1) direction, 0:input, 1:output 1098*8ffdff6aSGreg Kroah-Hartman * bit 14 -- NI_RTSI_BRD(2) direction, 0:input, 1:output 1099*8ffdff6aSGreg Kroah-Hartman * bit 15 -- NI_RTSI_BRD(3) direction, 0:input, 1:output 1100*8ffdff6aSGreg Kroah-Hartman * According to DAQ-STC: 1101*8ffdff6aSGreg Kroah-Hartman * RTSI Board Interface--Configured as an input, each bidirectional 1102*8ffdff6aSGreg Kroah-Hartman * RTSI_BRD pin can drive any of the seven RTSI_TRIGGER pins. 1103*8ffdff6aSGreg Kroah-Hartman * RTSI_BRD<0..1> can also be driven by AI STOP and RTSI_BRD<2..3> 1104*8ffdff6aSGreg Kroah-Hartman * can also be driven by the AI START and SCAN_IN_PROG signals. 1105*8ffdff6aSGreg Kroah-Hartman * These pins provide a mechanism for additional board-level signals 1106*8ffdff6aSGreg Kroah-Hartman * to be sent on or received from the RTSI bus. 1107*8ffdff6aSGreg Kroah-Hartman * Couple of comments: 1108*8ffdff6aSGreg Kroah-Hartman * - Neither the DAQ-STC nor the MHDDK is clear on what the direction 1109*8ffdff6aSGreg Kroah-Hartman * of the RTSI_BRD pins actually means. There does not appear to be 1110*8ffdff6aSGreg Kroah-Hartman * any clear indication on what "output" would mean, since the point 1111*8ffdff6aSGreg Kroah-Hartman * of the RTSI_BRD lines is to always drive one of the 1112*8ffdff6aSGreg Kroah-Hartman * RTSI_TRIGGER<0..6> lines. 1113*8ffdff6aSGreg Kroah-Hartman * - The DAQ-STC also indicates that the NI_RTSI_BRD lines can be 1114*8ffdff6aSGreg Kroah-Hartman * driven by any of the RTSI_TRIGGER<0..6> lines. 1115*8ffdff6aSGreg Kroah-Hartman * But, looking at valid device routes, as visually imported from 1116*8ffdff6aSGreg Kroah-Hartman * NI-MAX, there appears to be only one family (so far) that has the 1117*8ffdff6aSGreg Kroah-Hartman * ability to route a signal from one TRIGGER_LINE to another 1118*8ffdff6aSGreg Kroah-Hartman * TRIGGER_LINE: the 653x family of DIO devices. 1119*8ffdff6aSGreg Kroah-Hartman * 1120*8ffdff6aSGreg Kroah-Hartman * For m-series, the bit layout of this register is 1121*8ffdff6aSGreg Kroah-Hartman * (docs: mhddk/nimseries/ChipObjects/tMSeries.{h,ipp}): 1122*8ffdff6aSGreg Kroah-Hartman * bits 0:3 -- NI_RTSI_BRD(0) source selection 1123*8ffdff6aSGreg Kroah-Hartman * bits 4:7 -- NI_RTSI_BRD(1) source selection 1124*8ffdff6aSGreg Kroah-Hartman * bits 8:11 -- NI_RTSI_BRD(2) source selection 1125*8ffdff6aSGreg Kroah-Hartman * bits 12:15 -- NI_RTSI_BRD(3) source selection 1126*8ffdff6aSGreg Kroah-Hartman * Note: The m-series does not have any option to change direction of 1127*8ffdff6aSGreg Kroah-Hartman * NI_RTSI_BRD muxes. Furthermore, there are no register values that 1128*8ffdff6aSGreg Kroah-Hartman * indicate the ability to have TRIGGER_LINES driving the output of 1129*8ffdff6aSGreg Kroah-Hartman * the NI_RTSI_BRD muxes. 1130*8ffdff6aSGreg Kroah-Hartman */ 1131*8ffdff6aSGreg Kroah-Hartman u16 rtsi_shared_mux_reg; 1132*8ffdff6aSGreg Kroah-Hartman 1133*8ffdff6aSGreg Kroah-Hartman /* 1134*8ffdff6aSGreg Kroah-Hartman * Number of clients (RTSI lines) for current RGOUT0 path. 1135*8ffdff6aSGreg Kroah-Hartman * Stored in part of in RTSI_TRIG_DIR or RTSI_TRIGB registers 1136*8ffdff6aSGreg Kroah-Hartman */ 1137*8ffdff6aSGreg Kroah-Hartman u8 rgout0_usage; 1138*8ffdff6aSGreg Kroah-Hartman }; 1139*8ffdff6aSGreg Kroah-Hartman 1140*8ffdff6aSGreg Kroah-Hartman static const struct comedi_lrange range_ni_E_ao_ext; 1141*8ffdff6aSGreg Kroah-Hartman 1142*8ffdff6aSGreg Kroah-Hartman #endif /* _COMEDI_NI_STC_H */ 1143