1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 Freescale Semiconductor, Inc. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/cpu.h> 8 #include <linux/cpufreq.h> 9 #include <linux/err.h> 10 #include <linux/module.h> 11 #include <linux/nvmem-consumer.h> 12 #include <linux/of.h> 13 #include <linux/of_address.h> 14 #include <linux/pm_opp.h> 15 #include <linux/platform_device.h> 16 #include <linux/regulator/consumer.h> 17 18 #define PU_SOC_VOLTAGE_NORMAL 1250000 19 #define PU_SOC_VOLTAGE_HIGH 1275000 20 #define FREQ_1P2_GHZ 1200000000 21 22 static struct regulator *arm_reg; 23 static struct regulator *pu_reg; 24 static struct regulator *soc_reg; 25 26 enum IMX6_CPUFREQ_CLKS { 27 ARM, 28 PLL1_SYS, 29 STEP, 30 PLL1_SW, 31 PLL2_PFD2_396M, 32 /* MX6UL requires two more clks */ 33 PLL2_BUS, 34 SECONDARY_SEL, 35 }; 36 #define IMX6Q_CPUFREQ_CLK_NUM 5 37 #define IMX6UL_CPUFREQ_CLK_NUM 7 38 39 static int num_clks; 40 static struct clk_bulk_data clks[] = { 41 { .id = "arm" }, 42 { .id = "pll1_sys" }, 43 { .id = "step" }, 44 { .id = "pll1_sw" }, 45 { .id = "pll2_pfd2_396m" }, 46 { .id = "pll2_bus" }, 47 { .id = "secondary_sel" }, 48 }; 49 50 static struct device *cpu_dev; 51 static bool free_opp; 52 static struct cpufreq_frequency_table *freq_table; 53 static unsigned int max_freq; 54 static unsigned int transition_latency; 55 56 static u32 *imx6_soc_volt; 57 static u32 soc_opp_count; 58 59 static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index) 60 { 61 struct dev_pm_opp *opp; 62 unsigned long freq_hz, volt, volt_old; 63 unsigned int old_freq, new_freq; 64 bool pll1_sys_temp_enabled = false; 65 int ret; 66 67 new_freq = freq_table[index].frequency; 68 freq_hz = new_freq * 1000; 69 old_freq = clk_get_rate(clks[ARM].clk) / 1000; 70 71 opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz); 72 if (IS_ERR(opp)) { 73 dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz); 74 return PTR_ERR(opp); 75 } 76 77 volt = dev_pm_opp_get_voltage(opp); 78 dev_pm_opp_put(opp); 79 80 volt_old = regulator_get_voltage(arm_reg); 81 82 dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n", 83 old_freq / 1000, volt_old / 1000, 84 new_freq / 1000, volt / 1000); 85 86 /* scaling up? scale voltage before frequency */ 87 if (new_freq > old_freq) { 88 if (!IS_ERR(pu_reg)) { 89 ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0); 90 if (ret) { 91 dev_err(cpu_dev, "failed to scale vddpu up: %d\n", ret); 92 return ret; 93 } 94 } 95 ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0); 96 if (ret) { 97 dev_err(cpu_dev, "failed to scale vddsoc up: %d\n", ret); 98 return ret; 99 } 100 ret = regulator_set_voltage_tol(arm_reg, volt, 0); 101 if (ret) { 102 dev_err(cpu_dev, 103 "failed to scale vddarm up: %d\n", ret); 104 return ret; 105 } 106 } 107 108 /* 109 * The setpoints are selected per PLL/PDF frequencies, so we need to 110 * reprogram PLL for frequency scaling. The procedure of reprogramming 111 * PLL1 is as below. 112 * For i.MX6UL, it has a secondary clk mux, the cpu frequency change 113 * flow is slightly different from other i.MX6 OSC. 114 * The cpu frequeny change flow for i.MX6(except i.MX6UL) is as below: 115 * - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it 116 * - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it 117 * - Disable pll2_pfd2_396m_clk 118 */ 119 if (of_machine_is_compatible("fsl,imx6ul") || 120 of_machine_is_compatible("fsl,imx6ull")) { 121 /* 122 * When changing pll1_sw_clk's parent to pll1_sys_clk, 123 * CPU may run at higher than 528MHz, this will lead to 124 * the system unstable if the voltage is lower than the 125 * voltage of 528MHz, so lower the CPU frequency to one 126 * half before changing CPU frequency. 127 */ 128 clk_set_rate(clks[ARM].clk, (old_freq >> 1) * 1000); 129 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk); 130 if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk)) 131 clk_set_parent(clks[SECONDARY_SEL].clk, 132 clks[PLL2_BUS].clk); 133 else 134 clk_set_parent(clks[SECONDARY_SEL].clk, 135 clks[PLL2_PFD2_396M].clk); 136 clk_set_parent(clks[STEP].clk, clks[SECONDARY_SEL].clk); 137 clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk); 138 if (freq_hz > clk_get_rate(clks[PLL2_BUS].clk)) { 139 clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000); 140 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk); 141 } 142 } else { 143 clk_set_parent(clks[STEP].clk, clks[PLL2_PFD2_396M].clk); 144 clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk); 145 if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk)) { 146 clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000); 147 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk); 148 } else { 149 /* pll1_sys needs to be enabled for divider rate change to work. */ 150 pll1_sys_temp_enabled = true; 151 clk_prepare_enable(clks[PLL1_SYS].clk); 152 } 153 } 154 155 /* Ensure the arm clock divider is what we expect */ 156 ret = clk_set_rate(clks[ARM].clk, new_freq * 1000); 157 if (ret) { 158 int ret1; 159 160 dev_err(cpu_dev, "failed to set clock rate: %d\n", ret); 161 ret1 = regulator_set_voltage_tol(arm_reg, volt_old, 0); 162 if (ret1) 163 dev_warn(cpu_dev, 164 "failed to restore vddarm voltage: %d\n", ret1); 165 return ret; 166 } 167 168 /* PLL1 is only needed until after ARM-PODF is set. */ 169 if (pll1_sys_temp_enabled) 170 clk_disable_unprepare(clks[PLL1_SYS].clk); 171 172 /* scaling down? scale voltage after frequency */ 173 if (new_freq < old_freq) { 174 ret = regulator_set_voltage_tol(arm_reg, volt, 0); 175 if (ret) 176 dev_warn(cpu_dev, 177 "failed to scale vddarm down: %d\n", ret); 178 ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0); 179 if (ret) 180 dev_warn(cpu_dev, "failed to scale vddsoc down: %d\n", ret); 181 if (!IS_ERR(pu_reg)) { 182 ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0); 183 if (ret) 184 dev_warn(cpu_dev, "failed to scale vddpu down: %d\n", ret); 185 } 186 } 187 188 return 0; 189 } 190 191 static int imx6q_cpufreq_init(struct cpufreq_policy *policy) 192 { 193 policy->clk = clks[ARM].clk; 194 cpufreq_generic_init(policy, freq_table, transition_latency); 195 policy->suspend_freq = max_freq; 196 dev_pm_opp_of_register_em(policy->cpus); 197 198 return 0; 199 } 200 201 static struct cpufreq_driver imx6q_cpufreq_driver = { 202 .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK | 203 CPUFREQ_IS_COOLING_DEV, 204 .verify = cpufreq_generic_frequency_table_verify, 205 .target_index = imx6q_set_target, 206 .get = cpufreq_generic_get, 207 .init = imx6q_cpufreq_init, 208 .name = "imx6q-cpufreq", 209 .attr = cpufreq_generic_attr, 210 .suspend = cpufreq_generic_suspend, 211 }; 212 213 #define OCOTP_CFG3 0x440 214 #define OCOTP_CFG3_SPEED_SHIFT 16 215 #define OCOTP_CFG3_SPEED_1P2GHZ 0x3 216 #define OCOTP_CFG3_SPEED_996MHZ 0x2 217 #define OCOTP_CFG3_SPEED_852MHZ 0x1 218 219 static void imx6q_opp_check_speed_grading(struct device *dev) 220 { 221 struct device_node *np; 222 void __iomem *base; 223 u32 val; 224 225 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp"); 226 if (!np) 227 return; 228 229 base = of_iomap(np, 0); 230 if (!base) { 231 dev_err(dev, "failed to map ocotp\n"); 232 goto put_node; 233 } 234 235 /* 236 * SPEED_GRADING[1:0] defines the max speed of ARM: 237 * 2b'11: 1200000000Hz; 238 * 2b'10: 996000000Hz; 239 * 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz. 240 * 2b'00: 792000000Hz; 241 * We need to set the max speed of ARM according to fuse map. 242 */ 243 val = readl_relaxed(base + OCOTP_CFG3); 244 val >>= OCOTP_CFG3_SPEED_SHIFT; 245 val &= 0x3; 246 247 if (val < OCOTP_CFG3_SPEED_996MHZ) 248 if (dev_pm_opp_disable(dev, 996000000)) 249 dev_warn(dev, "failed to disable 996MHz OPP\n"); 250 251 if (of_machine_is_compatible("fsl,imx6q") || 252 of_machine_is_compatible("fsl,imx6qp")) { 253 if (val != OCOTP_CFG3_SPEED_852MHZ) 254 if (dev_pm_opp_disable(dev, 852000000)) 255 dev_warn(dev, "failed to disable 852MHz OPP\n"); 256 if (val != OCOTP_CFG3_SPEED_1P2GHZ) 257 if (dev_pm_opp_disable(dev, 1200000000)) 258 dev_warn(dev, "failed to disable 1.2GHz OPP\n"); 259 } 260 iounmap(base); 261 put_node: 262 of_node_put(np); 263 } 264 265 #define OCOTP_CFG3_6UL_SPEED_696MHZ 0x2 266 #define OCOTP_CFG3_6ULL_SPEED_792MHZ 0x2 267 #define OCOTP_CFG3_6ULL_SPEED_900MHZ 0x3 268 269 static int imx6ul_opp_check_speed_grading(struct device *dev) 270 { 271 u32 val; 272 int ret = 0; 273 274 if (of_find_property(dev->of_node, "nvmem-cells", NULL)) { 275 ret = nvmem_cell_read_u32(dev, "speed_grade", &val); 276 if (ret) 277 return ret; 278 } else { 279 struct device_node *np; 280 void __iomem *base; 281 282 np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-ocotp"); 283 if (!np) 284 np = of_find_compatible_node(NULL, NULL, 285 "fsl,imx6ull-ocotp"); 286 if (!np) 287 return -ENOENT; 288 289 base = of_iomap(np, 0); 290 of_node_put(np); 291 if (!base) { 292 dev_err(dev, "failed to map ocotp\n"); 293 return -EFAULT; 294 } 295 296 val = readl_relaxed(base + OCOTP_CFG3); 297 iounmap(base); 298 } 299 300 /* 301 * Speed GRADING[1:0] defines the max speed of ARM: 302 * 2b'00: Reserved; 303 * 2b'01: 528000000Hz; 304 * 2b'10: 696000000Hz on i.MX6UL, 792000000Hz on i.MX6ULL; 305 * 2b'11: 900000000Hz on i.MX6ULL only; 306 * We need to set the max speed of ARM according to fuse map. 307 */ 308 val >>= OCOTP_CFG3_SPEED_SHIFT; 309 val &= 0x3; 310 311 if (of_machine_is_compatible("fsl,imx6ul")) { 312 if (val != OCOTP_CFG3_6UL_SPEED_696MHZ) 313 if (dev_pm_opp_disable(dev, 696000000)) 314 dev_warn(dev, "failed to disable 696MHz OPP\n"); 315 } 316 317 if (of_machine_is_compatible("fsl,imx6ull")) { 318 if (val != OCOTP_CFG3_6ULL_SPEED_792MHZ) 319 if (dev_pm_opp_disable(dev, 792000000)) 320 dev_warn(dev, "failed to disable 792MHz OPP\n"); 321 322 if (val != OCOTP_CFG3_6ULL_SPEED_900MHZ) 323 if (dev_pm_opp_disable(dev, 900000000)) 324 dev_warn(dev, "failed to disable 900MHz OPP\n"); 325 } 326 327 return ret; 328 } 329 330 static int imx6q_cpufreq_probe(struct platform_device *pdev) 331 { 332 struct device_node *np; 333 struct dev_pm_opp *opp; 334 unsigned long min_volt, max_volt; 335 int num, ret; 336 const struct property *prop; 337 const __be32 *val; 338 u32 nr, i, j; 339 340 cpu_dev = get_cpu_device(0); 341 if (!cpu_dev) { 342 pr_err("failed to get cpu0 device\n"); 343 return -ENODEV; 344 } 345 346 np = of_node_get(cpu_dev->of_node); 347 if (!np) { 348 dev_err(cpu_dev, "failed to find cpu0 node\n"); 349 return -ENOENT; 350 } 351 352 if (of_machine_is_compatible("fsl,imx6ul") || 353 of_machine_is_compatible("fsl,imx6ull")) 354 num_clks = IMX6UL_CPUFREQ_CLK_NUM; 355 else 356 num_clks = IMX6Q_CPUFREQ_CLK_NUM; 357 358 ret = clk_bulk_get(cpu_dev, num_clks, clks); 359 if (ret) 360 goto put_node; 361 362 arm_reg = regulator_get(cpu_dev, "arm"); 363 pu_reg = regulator_get_optional(cpu_dev, "pu"); 364 soc_reg = regulator_get(cpu_dev, "soc"); 365 if (PTR_ERR(arm_reg) == -EPROBE_DEFER || 366 PTR_ERR(soc_reg) == -EPROBE_DEFER || 367 PTR_ERR(pu_reg) == -EPROBE_DEFER) { 368 ret = -EPROBE_DEFER; 369 dev_dbg(cpu_dev, "regulators not ready, defer\n"); 370 goto put_reg; 371 } 372 if (IS_ERR(arm_reg) || IS_ERR(soc_reg)) { 373 dev_err(cpu_dev, "failed to get regulators\n"); 374 ret = -ENOENT; 375 goto put_reg; 376 } 377 378 ret = dev_pm_opp_of_add_table(cpu_dev); 379 if (ret < 0) { 380 dev_err(cpu_dev, "failed to init OPP table: %d\n", ret); 381 goto put_reg; 382 } 383 384 if (of_machine_is_compatible("fsl,imx6ul") || 385 of_machine_is_compatible("fsl,imx6ull")) { 386 ret = imx6ul_opp_check_speed_grading(cpu_dev); 387 if (ret) { 388 if (ret == -EPROBE_DEFER) 389 goto put_node; 390 391 dev_err(cpu_dev, "failed to read ocotp: %d\n", 392 ret); 393 goto put_node; 394 } 395 } else { 396 imx6q_opp_check_speed_grading(cpu_dev); 397 } 398 399 /* Because we have added the OPPs here, we must free them */ 400 free_opp = true; 401 num = dev_pm_opp_get_opp_count(cpu_dev); 402 if (num < 0) { 403 ret = num; 404 dev_err(cpu_dev, "no OPP table is found: %d\n", ret); 405 goto out_free_opp; 406 } 407 408 ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table); 409 if (ret) { 410 dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret); 411 goto out_free_opp; 412 } 413 414 /* Make imx6_soc_volt array's size same as arm opp number */ 415 imx6_soc_volt = devm_kcalloc(cpu_dev, num, sizeof(*imx6_soc_volt), 416 GFP_KERNEL); 417 if (imx6_soc_volt == NULL) { 418 ret = -ENOMEM; 419 goto free_freq_table; 420 } 421 422 prop = of_find_property(np, "fsl,soc-operating-points", NULL); 423 if (!prop || !prop->value) 424 goto soc_opp_out; 425 426 /* 427 * Each OPP is a set of tuples consisting of frequency and 428 * voltage like <freq-kHz vol-uV>. 429 */ 430 nr = prop->length / sizeof(u32); 431 if (nr % 2 || (nr / 2) < num) 432 goto soc_opp_out; 433 434 for (j = 0; j < num; j++) { 435 val = prop->value; 436 for (i = 0; i < nr / 2; i++) { 437 unsigned long freq = be32_to_cpup(val++); 438 unsigned long volt = be32_to_cpup(val++); 439 if (freq_table[j].frequency == freq) { 440 imx6_soc_volt[soc_opp_count++] = volt; 441 break; 442 } 443 } 444 } 445 446 soc_opp_out: 447 /* use fixed soc opp volt if no valid soc opp info found in dtb */ 448 if (soc_opp_count != num) { 449 dev_warn(cpu_dev, "can NOT find valid fsl,soc-operating-points property in dtb, use default value!\n"); 450 for (j = 0; j < num; j++) 451 imx6_soc_volt[j] = PU_SOC_VOLTAGE_NORMAL; 452 if (freq_table[num - 1].frequency * 1000 == FREQ_1P2_GHZ) 453 imx6_soc_volt[num - 1] = PU_SOC_VOLTAGE_HIGH; 454 } 455 456 if (of_property_read_u32(np, "clock-latency", &transition_latency)) 457 transition_latency = CPUFREQ_ETERNAL; 458 459 /* 460 * Calculate the ramp time for max voltage change in the 461 * VDDSOC and VDDPU regulators. 462 */ 463 ret = regulator_set_voltage_time(soc_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]); 464 if (ret > 0) 465 transition_latency += ret * 1000; 466 if (!IS_ERR(pu_reg)) { 467 ret = regulator_set_voltage_time(pu_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]); 468 if (ret > 0) 469 transition_latency += ret * 1000; 470 } 471 472 /* 473 * OPP is maintained in order of increasing frequency, and 474 * freq_table initialised from OPP is therefore sorted in the 475 * same order. 476 */ 477 max_freq = freq_table[--num].frequency; 478 opp = dev_pm_opp_find_freq_exact(cpu_dev, 479 freq_table[0].frequency * 1000, true); 480 min_volt = dev_pm_opp_get_voltage(opp); 481 dev_pm_opp_put(opp); 482 opp = dev_pm_opp_find_freq_exact(cpu_dev, max_freq * 1000, true); 483 max_volt = dev_pm_opp_get_voltage(opp); 484 dev_pm_opp_put(opp); 485 486 ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt); 487 if (ret > 0) 488 transition_latency += ret * 1000; 489 490 ret = cpufreq_register_driver(&imx6q_cpufreq_driver); 491 if (ret) { 492 dev_err(cpu_dev, "failed register driver: %d\n", ret); 493 goto free_freq_table; 494 } 495 496 of_node_put(np); 497 return 0; 498 499 free_freq_table: 500 dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table); 501 out_free_opp: 502 if (free_opp) 503 dev_pm_opp_of_remove_table(cpu_dev); 504 put_reg: 505 if (!IS_ERR(arm_reg)) 506 regulator_put(arm_reg); 507 if (!IS_ERR(pu_reg)) 508 regulator_put(pu_reg); 509 if (!IS_ERR(soc_reg)) 510 regulator_put(soc_reg); 511 512 clk_bulk_put(num_clks, clks); 513 put_node: 514 of_node_put(np); 515 516 return ret; 517 } 518 519 static int imx6q_cpufreq_remove(struct platform_device *pdev) 520 { 521 cpufreq_unregister_driver(&imx6q_cpufreq_driver); 522 dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table); 523 if (free_opp) 524 dev_pm_opp_of_remove_table(cpu_dev); 525 regulator_put(arm_reg); 526 if (!IS_ERR(pu_reg)) 527 regulator_put(pu_reg); 528 regulator_put(soc_reg); 529 530 clk_bulk_put(num_clks, clks); 531 532 return 0; 533 } 534 535 static struct platform_driver imx6q_cpufreq_platdrv = { 536 .driver = { 537 .name = "imx6q-cpufreq", 538 }, 539 .probe = imx6q_cpufreq_probe, 540 .remove = imx6q_cpufreq_remove, 541 }; 542 module_platform_driver(imx6q_cpufreq_platdrv); 543 544 MODULE_ALIAS("platform:imx6q-cpufreq"); 545 MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>"); 546 MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver"); 547 MODULE_LICENSE("GPL"); 548