1 /* 2 * Copyright (C) 2013 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/cpu.h> 11 #include <linux/cpufreq.h> 12 #include <linux/cpu_cooling.h> 13 #include <linux/err.h> 14 #include <linux/module.h> 15 #include <linux/nvmem-consumer.h> 16 #include <linux/of.h> 17 #include <linux/of_address.h> 18 #include <linux/pm_opp.h> 19 #include <linux/platform_device.h> 20 #include <linux/regulator/consumer.h> 21 22 #define PU_SOC_VOLTAGE_NORMAL 1250000 23 #define PU_SOC_VOLTAGE_HIGH 1275000 24 #define FREQ_1P2_GHZ 1200000000 25 26 static struct regulator *arm_reg; 27 static struct regulator *pu_reg; 28 static struct regulator *soc_reg; 29 30 enum IMX6_CPUFREQ_CLKS { 31 ARM, 32 PLL1_SYS, 33 STEP, 34 PLL1_SW, 35 PLL2_PFD2_396M, 36 /* MX6UL requires two more clks */ 37 PLL2_BUS, 38 SECONDARY_SEL, 39 }; 40 #define IMX6Q_CPUFREQ_CLK_NUM 5 41 #define IMX6UL_CPUFREQ_CLK_NUM 7 42 43 static int num_clks; 44 static struct clk_bulk_data clks[] = { 45 { .id = "arm" }, 46 { .id = "pll1_sys" }, 47 { .id = "step" }, 48 { .id = "pll1_sw" }, 49 { .id = "pll2_pfd2_396m" }, 50 { .id = "pll2_bus" }, 51 { .id = "secondary_sel" }, 52 }; 53 54 static struct device *cpu_dev; 55 static struct thermal_cooling_device *cdev; 56 static bool free_opp; 57 static struct cpufreq_frequency_table *freq_table; 58 static unsigned int max_freq; 59 static unsigned int transition_latency; 60 61 static u32 *imx6_soc_volt; 62 static u32 soc_opp_count; 63 64 static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index) 65 { 66 struct dev_pm_opp *opp; 67 unsigned long freq_hz, volt, volt_old; 68 unsigned int old_freq, new_freq; 69 bool pll1_sys_temp_enabled = false; 70 int ret; 71 72 new_freq = freq_table[index].frequency; 73 freq_hz = new_freq * 1000; 74 old_freq = clk_get_rate(clks[ARM].clk) / 1000; 75 76 opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz); 77 if (IS_ERR(opp)) { 78 dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz); 79 return PTR_ERR(opp); 80 } 81 82 volt = dev_pm_opp_get_voltage(opp); 83 dev_pm_opp_put(opp); 84 85 volt_old = regulator_get_voltage(arm_reg); 86 87 dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n", 88 old_freq / 1000, volt_old / 1000, 89 new_freq / 1000, volt / 1000); 90 91 /* scaling up? scale voltage before frequency */ 92 if (new_freq > old_freq) { 93 if (!IS_ERR(pu_reg)) { 94 ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0); 95 if (ret) { 96 dev_err(cpu_dev, "failed to scale vddpu up: %d\n", ret); 97 return ret; 98 } 99 } 100 ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0); 101 if (ret) { 102 dev_err(cpu_dev, "failed to scale vddsoc up: %d\n", ret); 103 return ret; 104 } 105 ret = regulator_set_voltage_tol(arm_reg, volt, 0); 106 if (ret) { 107 dev_err(cpu_dev, 108 "failed to scale vddarm up: %d\n", ret); 109 return ret; 110 } 111 } 112 113 /* 114 * The setpoints are selected per PLL/PDF frequencies, so we need to 115 * reprogram PLL for frequency scaling. The procedure of reprogramming 116 * PLL1 is as below. 117 * For i.MX6UL, it has a secondary clk mux, the cpu frequency change 118 * flow is slightly different from other i.MX6 OSC. 119 * The cpu frequeny change flow for i.MX6(except i.MX6UL) is as below: 120 * - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it 121 * - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it 122 * - Disable pll2_pfd2_396m_clk 123 */ 124 if (of_machine_is_compatible("fsl,imx6ul") || 125 of_machine_is_compatible("fsl,imx6ull")) { 126 /* 127 * When changing pll1_sw_clk's parent to pll1_sys_clk, 128 * CPU may run at higher than 528MHz, this will lead to 129 * the system unstable if the voltage is lower than the 130 * voltage of 528MHz, so lower the CPU frequency to one 131 * half before changing CPU frequency. 132 */ 133 clk_set_rate(clks[ARM].clk, (old_freq >> 1) * 1000); 134 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk); 135 if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk)) 136 clk_set_parent(clks[SECONDARY_SEL].clk, 137 clks[PLL2_BUS].clk); 138 else 139 clk_set_parent(clks[SECONDARY_SEL].clk, 140 clks[PLL2_PFD2_396M].clk); 141 clk_set_parent(clks[STEP].clk, clks[SECONDARY_SEL].clk); 142 clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk); 143 if (freq_hz > clk_get_rate(clks[PLL2_BUS].clk)) { 144 clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000); 145 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk); 146 } 147 } else { 148 clk_set_parent(clks[STEP].clk, clks[PLL2_PFD2_396M].clk); 149 clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk); 150 if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk)) { 151 clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000); 152 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk); 153 } else { 154 /* pll1_sys needs to be enabled for divider rate change to work. */ 155 pll1_sys_temp_enabled = true; 156 clk_prepare_enable(clks[PLL1_SYS].clk); 157 } 158 } 159 160 /* Ensure the arm clock divider is what we expect */ 161 ret = clk_set_rate(clks[ARM].clk, new_freq * 1000); 162 if (ret) { 163 int ret1; 164 165 dev_err(cpu_dev, "failed to set clock rate: %d\n", ret); 166 ret1 = regulator_set_voltage_tol(arm_reg, volt_old, 0); 167 if (ret1) 168 dev_warn(cpu_dev, 169 "failed to restore vddarm voltage: %d\n", ret1); 170 return ret; 171 } 172 173 /* PLL1 is only needed until after ARM-PODF is set. */ 174 if (pll1_sys_temp_enabled) 175 clk_disable_unprepare(clks[PLL1_SYS].clk); 176 177 /* scaling down? scale voltage after frequency */ 178 if (new_freq < old_freq) { 179 ret = regulator_set_voltage_tol(arm_reg, volt, 0); 180 if (ret) 181 dev_warn(cpu_dev, 182 "failed to scale vddarm down: %d\n", ret); 183 ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0); 184 if (ret) 185 dev_warn(cpu_dev, "failed to scale vddsoc down: %d\n", ret); 186 if (!IS_ERR(pu_reg)) { 187 ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0); 188 if (ret) 189 dev_warn(cpu_dev, "failed to scale vddpu down: %d\n", ret); 190 } 191 } 192 193 return 0; 194 } 195 196 static void imx6q_cpufreq_ready(struct cpufreq_policy *policy) 197 { 198 cdev = of_cpufreq_cooling_register(policy); 199 200 if (!cdev) 201 dev_err(cpu_dev, 202 "running cpufreq without cooling device: %ld\n", 203 PTR_ERR(cdev)); 204 } 205 206 static int imx6q_cpufreq_init(struct cpufreq_policy *policy) 207 { 208 int ret; 209 210 policy->clk = clks[ARM].clk; 211 ret = cpufreq_generic_init(policy, freq_table, transition_latency); 212 policy->suspend_freq = max_freq; 213 214 return ret; 215 } 216 217 static int imx6q_cpufreq_exit(struct cpufreq_policy *policy) 218 { 219 cpufreq_cooling_unregister(cdev); 220 221 return 0; 222 } 223 224 static struct cpufreq_driver imx6q_cpufreq_driver = { 225 .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK, 226 .verify = cpufreq_generic_frequency_table_verify, 227 .target_index = imx6q_set_target, 228 .get = cpufreq_generic_get, 229 .init = imx6q_cpufreq_init, 230 .exit = imx6q_cpufreq_exit, 231 .name = "imx6q-cpufreq", 232 .ready = imx6q_cpufreq_ready, 233 .attr = cpufreq_generic_attr, 234 .suspend = cpufreq_generic_suspend, 235 }; 236 237 #define OCOTP_CFG3 0x440 238 #define OCOTP_CFG3_SPEED_SHIFT 16 239 #define OCOTP_CFG3_SPEED_1P2GHZ 0x3 240 #define OCOTP_CFG3_SPEED_996MHZ 0x2 241 #define OCOTP_CFG3_SPEED_852MHZ 0x1 242 243 static void imx6q_opp_check_speed_grading(struct device *dev) 244 { 245 struct device_node *np; 246 void __iomem *base; 247 u32 val; 248 249 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp"); 250 if (!np) 251 return; 252 253 base = of_iomap(np, 0); 254 if (!base) { 255 dev_err(dev, "failed to map ocotp\n"); 256 goto put_node; 257 } 258 259 /* 260 * SPEED_GRADING[1:0] defines the max speed of ARM: 261 * 2b'11: 1200000000Hz; 262 * 2b'10: 996000000Hz; 263 * 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz. 264 * 2b'00: 792000000Hz; 265 * We need to set the max speed of ARM according to fuse map. 266 */ 267 val = readl_relaxed(base + OCOTP_CFG3); 268 val >>= OCOTP_CFG3_SPEED_SHIFT; 269 val &= 0x3; 270 271 if (val < OCOTP_CFG3_SPEED_996MHZ) 272 if (dev_pm_opp_disable(dev, 996000000)) 273 dev_warn(dev, "failed to disable 996MHz OPP\n"); 274 275 if (of_machine_is_compatible("fsl,imx6q") || 276 of_machine_is_compatible("fsl,imx6qp")) { 277 if (val != OCOTP_CFG3_SPEED_852MHZ) 278 if (dev_pm_opp_disable(dev, 852000000)) 279 dev_warn(dev, "failed to disable 852MHz OPP\n"); 280 if (val != OCOTP_CFG3_SPEED_1P2GHZ) 281 if (dev_pm_opp_disable(dev, 1200000000)) 282 dev_warn(dev, "failed to disable 1.2GHz OPP\n"); 283 } 284 iounmap(base); 285 put_node: 286 of_node_put(np); 287 } 288 289 #define OCOTP_CFG3_6UL_SPEED_696MHZ 0x2 290 #define OCOTP_CFG3_6ULL_SPEED_792MHZ 0x2 291 #define OCOTP_CFG3_6ULL_SPEED_900MHZ 0x3 292 293 static int imx6ul_opp_check_speed_grading(struct device *dev) 294 { 295 u32 val; 296 int ret = 0; 297 298 if (of_find_property(dev->of_node, "nvmem-cells", NULL)) { 299 ret = nvmem_cell_read_u32(dev, "speed_grade", &val); 300 if (ret) 301 return ret; 302 } else { 303 struct device_node *np; 304 void __iomem *base; 305 306 np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-ocotp"); 307 if (!np) 308 return -ENOENT; 309 310 base = of_iomap(np, 0); 311 of_node_put(np); 312 if (!base) { 313 dev_err(dev, "failed to map ocotp\n"); 314 return -EFAULT; 315 } 316 317 val = readl_relaxed(base + OCOTP_CFG3); 318 iounmap(base); 319 } 320 321 /* 322 * Speed GRADING[1:0] defines the max speed of ARM: 323 * 2b'00: Reserved; 324 * 2b'01: 528000000Hz; 325 * 2b'10: 696000000Hz on i.MX6UL, 792000000Hz on i.MX6ULL; 326 * 2b'11: 900000000Hz on i.MX6ULL only; 327 * We need to set the max speed of ARM according to fuse map. 328 */ 329 val >>= OCOTP_CFG3_SPEED_SHIFT; 330 val &= 0x3; 331 332 if (of_machine_is_compatible("fsl,imx6ul")) { 333 if (val != OCOTP_CFG3_6UL_SPEED_696MHZ) 334 if (dev_pm_opp_disable(dev, 696000000)) 335 dev_warn(dev, "failed to disable 696MHz OPP\n"); 336 } 337 338 if (of_machine_is_compatible("fsl,imx6ull")) { 339 if (val != OCOTP_CFG3_6ULL_SPEED_792MHZ) 340 if (dev_pm_opp_disable(dev, 792000000)) 341 dev_warn(dev, "failed to disable 792MHz OPP\n"); 342 343 if (val != OCOTP_CFG3_6ULL_SPEED_900MHZ) 344 if (dev_pm_opp_disable(dev, 900000000)) 345 dev_warn(dev, "failed to disable 900MHz OPP\n"); 346 } 347 348 return ret; 349 } 350 351 static int imx6q_cpufreq_probe(struct platform_device *pdev) 352 { 353 struct device_node *np; 354 struct dev_pm_opp *opp; 355 unsigned long min_volt, max_volt; 356 int num, ret; 357 const struct property *prop; 358 const __be32 *val; 359 u32 nr, i, j; 360 361 cpu_dev = get_cpu_device(0); 362 if (!cpu_dev) { 363 pr_err("failed to get cpu0 device\n"); 364 return -ENODEV; 365 } 366 367 np = of_node_get(cpu_dev->of_node); 368 if (!np) { 369 dev_err(cpu_dev, "failed to find cpu0 node\n"); 370 return -ENOENT; 371 } 372 373 if (of_machine_is_compatible("fsl,imx6ul") || 374 of_machine_is_compatible("fsl,imx6ull")) 375 num_clks = IMX6UL_CPUFREQ_CLK_NUM; 376 else 377 num_clks = IMX6Q_CPUFREQ_CLK_NUM; 378 379 ret = clk_bulk_get(cpu_dev, num_clks, clks); 380 if (ret) 381 goto put_node; 382 383 arm_reg = regulator_get(cpu_dev, "arm"); 384 pu_reg = regulator_get_optional(cpu_dev, "pu"); 385 soc_reg = regulator_get(cpu_dev, "soc"); 386 if (PTR_ERR(arm_reg) == -EPROBE_DEFER || 387 PTR_ERR(soc_reg) == -EPROBE_DEFER || 388 PTR_ERR(pu_reg) == -EPROBE_DEFER) { 389 ret = -EPROBE_DEFER; 390 dev_dbg(cpu_dev, "regulators not ready, defer\n"); 391 goto put_reg; 392 } 393 if (IS_ERR(arm_reg) || IS_ERR(soc_reg)) { 394 dev_err(cpu_dev, "failed to get regulators\n"); 395 ret = -ENOENT; 396 goto put_reg; 397 } 398 399 ret = dev_pm_opp_of_add_table(cpu_dev); 400 if (ret < 0) { 401 dev_err(cpu_dev, "failed to init OPP table: %d\n", ret); 402 goto put_reg; 403 } 404 405 if (of_machine_is_compatible("fsl,imx6ul") || 406 of_machine_is_compatible("fsl,imx6ull")) { 407 ret = imx6ul_opp_check_speed_grading(cpu_dev); 408 if (ret == -EPROBE_DEFER) 409 return ret; 410 if (ret) { 411 dev_err(cpu_dev, "failed to read ocotp: %d\n", 412 ret); 413 return ret; 414 } 415 } else { 416 imx6q_opp_check_speed_grading(cpu_dev); 417 } 418 419 /* Because we have added the OPPs here, we must free them */ 420 free_opp = true; 421 num = dev_pm_opp_get_opp_count(cpu_dev); 422 if (num < 0) { 423 ret = num; 424 dev_err(cpu_dev, "no OPP table is found: %d\n", ret); 425 goto out_free_opp; 426 } 427 428 ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table); 429 if (ret) { 430 dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret); 431 goto out_free_opp; 432 } 433 434 /* Make imx6_soc_volt array's size same as arm opp number */ 435 imx6_soc_volt = devm_kcalloc(cpu_dev, num, sizeof(*imx6_soc_volt), 436 GFP_KERNEL); 437 if (imx6_soc_volt == NULL) { 438 ret = -ENOMEM; 439 goto free_freq_table; 440 } 441 442 prop = of_find_property(np, "fsl,soc-operating-points", NULL); 443 if (!prop || !prop->value) 444 goto soc_opp_out; 445 446 /* 447 * Each OPP is a set of tuples consisting of frequency and 448 * voltage like <freq-kHz vol-uV>. 449 */ 450 nr = prop->length / sizeof(u32); 451 if (nr % 2 || (nr / 2) < num) 452 goto soc_opp_out; 453 454 for (j = 0; j < num; j++) { 455 val = prop->value; 456 for (i = 0; i < nr / 2; i++) { 457 unsigned long freq = be32_to_cpup(val++); 458 unsigned long volt = be32_to_cpup(val++); 459 if (freq_table[j].frequency == freq) { 460 imx6_soc_volt[soc_opp_count++] = volt; 461 break; 462 } 463 } 464 } 465 466 soc_opp_out: 467 /* use fixed soc opp volt if no valid soc opp info found in dtb */ 468 if (soc_opp_count != num) { 469 dev_warn(cpu_dev, "can NOT find valid fsl,soc-operating-points property in dtb, use default value!\n"); 470 for (j = 0; j < num; j++) 471 imx6_soc_volt[j] = PU_SOC_VOLTAGE_NORMAL; 472 if (freq_table[num - 1].frequency * 1000 == FREQ_1P2_GHZ) 473 imx6_soc_volt[num - 1] = PU_SOC_VOLTAGE_HIGH; 474 } 475 476 if (of_property_read_u32(np, "clock-latency", &transition_latency)) 477 transition_latency = CPUFREQ_ETERNAL; 478 479 /* 480 * Calculate the ramp time for max voltage change in the 481 * VDDSOC and VDDPU regulators. 482 */ 483 ret = regulator_set_voltage_time(soc_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]); 484 if (ret > 0) 485 transition_latency += ret * 1000; 486 if (!IS_ERR(pu_reg)) { 487 ret = regulator_set_voltage_time(pu_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]); 488 if (ret > 0) 489 transition_latency += ret * 1000; 490 } 491 492 /* 493 * OPP is maintained in order of increasing frequency, and 494 * freq_table initialised from OPP is therefore sorted in the 495 * same order. 496 */ 497 max_freq = freq_table[--num].frequency; 498 opp = dev_pm_opp_find_freq_exact(cpu_dev, 499 freq_table[0].frequency * 1000, true); 500 min_volt = dev_pm_opp_get_voltage(opp); 501 dev_pm_opp_put(opp); 502 opp = dev_pm_opp_find_freq_exact(cpu_dev, max_freq * 1000, true); 503 max_volt = dev_pm_opp_get_voltage(opp); 504 dev_pm_opp_put(opp); 505 506 ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt); 507 if (ret > 0) 508 transition_latency += ret * 1000; 509 510 ret = cpufreq_register_driver(&imx6q_cpufreq_driver); 511 if (ret) { 512 dev_err(cpu_dev, "failed register driver: %d\n", ret); 513 goto free_freq_table; 514 } 515 516 of_node_put(np); 517 return 0; 518 519 free_freq_table: 520 dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table); 521 out_free_opp: 522 if (free_opp) 523 dev_pm_opp_of_remove_table(cpu_dev); 524 put_reg: 525 if (!IS_ERR(arm_reg)) 526 regulator_put(arm_reg); 527 if (!IS_ERR(pu_reg)) 528 regulator_put(pu_reg); 529 if (!IS_ERR(soc_reg)) 530 regulator_put(soc_reg); 531 532 clk_bulk_put(num_clks, clks); 533 put_node: 534 of_node_put(np); 535 536 return ret; 537 } 538 539 static int imx6q_cpufreq_remove(struct platform_device *pdev) 540 { 541 cpufreq_unregister_driver(&imx6q_cpufreq_driver); 542 dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table); 543 if (free_opp) 544 dev_pm_opp_of_remove_table(cpu_dev); 545 regulator_put(arm_reg); 546 if (!IS_ERR(pu_reg)) 547 regulator_put(pu_reg); 548 regulator_put(soc_reg); 549 550 clk_bulk_put(num_clks, clks); 551 552 return 0; 553 } 554 555 static struct platform_driver imx6q_cpufreq_platdrv = { 556 .driver = { 557 .name = "imx6q-cpufreq", 558 }, 559 .probe = imx6q_cpufreq_probe, 560 .remove = imx6q_cpufreq_remove, 561 }; 562 module_platform_driver(imx6q_cpufreq_platdrv); 563 564 MODULE_ALIAS("platform:imx6q-cpufreq"); 565 MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>"); 566 MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver"); 567 MODULE_LICENSE("GPL"); 568