1*3817d2b8SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2bb0a56ecSDave Jones /* 3bb0a56ecSDave Jones * (c) 2003-2006 Advanced Micro Devices, Inc. 4bb0a56ecSDave Jones */ 5bb0a56ecSDave Jones 6bb0a56ecSDave Jones struct powernow_k8_data { 7bb0a56ecSDave Jones unsigned int cpu; 8bb0a56ecSDave Jones 9bb0a56ecSDave Jones u32 numps; /* number of p-states */ 10bb0a56ecSDave Jones u32 batps; /* number of p-states supported on battery */ 11bb0a56ecSDave Jones 12bb0a56ecSDave Jones /* these values are constant when the PSB is used to determine 13bb0a56ecSDave Jones * vid/fid pairings, but are modified during the ->target() call 14bb0a56ecSDave Jones * when ACPI is used */ 15bb0a56ecSDave Jones u32 rvo; /* ramp voltage offset */ 16bb0a56ecSDave Jones u32 irt; /* isochronous relief time */ 17bb0a56ecSDave Jones u32 vidmvs; /* usable value calculated from mvs */ 18bb0a56ecSDave Jones u32 vstable; /* voltage stabilization time, units 20 us */ 19bb0a56ecSDave Jones u32 plllock; /* pll lock time, units 1 us */ 20bb0a56ecSDave Jones u32 exttype; /* extended interface = 1 */ 21bb0a56ecSDave Jones 22bb0a56ecSDave Jones /* keep track of the current fid / vid or pstate */ 23bb0a56ecSDave Jones u32 currvid; 24bb0a56ecSDave Jones u32 currfid; 25bb0a56ecSDave Jones 26bb0a56ecSDave Jones /* the powernow_table includes all frequency and vid/fid pairings: 27bb0a56ecSDave Jones * fid are the lower 8 bits of the index, vid are the upper 8 bits. 28bb0a56ecSDave Jones * frequency is in kHz */ 29bb0a56ecSDave Jones struct cpufreq_frequency_table *powernow_table; 30bb0a56ecSDave Jones 31bb0a56ecSDave Jones /* the acpi table needs to be kept. it's only available if ACPI was 32bb0a56ecSDave Jones * used to determine valid frequency/vid/fid states */ 33bb0a56ecSDave Jones struct acpi_processor_performance acpi_data; 34bb0a56ecSDave Jones 35bb0a56ecSDave Jones /* we need to keep track of associated cores, but let cpufreq 36bb0a56ecSDave Jones * handle hotplug events - so just point at cpufreq pol->cpus 37bb0a56ecSDave Jones * structure */ 38bb0a56ecSDave Jones struct cpumask *available_cores; 39bb0a56ecSDave Jones }; 40bb0a56ecSDave Jones 41bb0a56ecSDave Jones /* processor's cpuid instruction support */ 42bb0a56ecSDave Jones #define CPUID_PROCESSOR_SIGNATURE 1 /* function 1 */ 43bb0a56ecSDave Jones #define CPUID_XFAM 0x0ff00000 /* extended family */ 44bb0a56ecSDave Jones #define CPUID_XFAM_K8 0 45bb0a56ecSDave Jones #define CPUID_XMOD 0x000f0000 /* extended model */ 46bb0a56ecSDave Jones #define CPUID_XMOD_REV_MASK 0x000c0000 47bb0a56ecSDave Jones #define CPUID_XFAM_10H 0x00100000 /* family 0x10 */ 48bb0a56ecSDave Jones #define CPUID_USE_XFAM_XMOD 0x00000f00 49bb0a56ecSDave Jones #define CPUID_GET_MAX_CAPABILITIES 0x80000000 50bb0a56ecSDave Jones #define CPUID_FREQ_VOLT_CAPABILITIES 0x80000007 51bb0a56ecSDave Jones #define P_STATE_TRANSITION_CAPABLE 6 52bb0a56ecSDave Jones 53bb0a56ecSDave Jones /* Model Specific Registers for p-state transitions. MSRs are 64-bit. For */ 54bb0a56ecSDave Jones /* writes (wrmsr - opcode 0f 30), the register number is placed in ecx, and */ 55bb0a56ecSDave Jones /* the value to write is placed in edx:eax. For reads (rdmsr - opcode 0f 32), */ 56bb0a56ecSDave Jones /* the register number is placed in ecx, and the data is returned in edx:eax. */ 57bb0a56ecSDave Jones 58bb0a56ecSDave Jones #define MSR_FIDVID_CTL 0xc0010041 59bb0a56ecSDave Jones #define MSR_FIDVID_STATUS 0xc0010042 60bb0a56ecSDave Jones 61bb0a56ecSDave Jones /* Field definitions within the FID VID Low Control MSR : */ 62bb0a56ecSDave Jones #define MSR_C_LO_INIT_FID_VID 0x00010000 63bb0a56ecSDave Jones #define MSR_C_LO_NEW_VID 0x00003f00 64bb0a56ecSDave Jones #define MSR_C_LO_NEW_FID 0x0000003f 65bb0a56ecSDave Jones #define MSR_C_LO_VID_SHIFT 8 66bb0a56ecSDave Jones 67bb0a56ecSDave Jones /* Field definitions within the FID VID High Control MSR : */ 68bb0a56ecSDave Jones #define MSR_C_HI_STP_GNT_TO 0x000fffff 69bb0a56ecSDave Jones 70bb0a56ecSDave Jones /* Field definitions within the FID VID Low Status MSR : */ 71bb0a56ecSDave Jones #define MSR_S_LO_CHANGE_PENDING 0x80000000 /* cleared when completed */ 72bb0a56ecSDave Jones #define MSR_S_LO_MAX_RAMP_VID 0x3f000000 73bb0a56ecSDave Jones #define MSR_S_LO_MAX_FID 0x003f0000 74bb0a56ecSDave Jones #define MSR_S_LO_START_FID 0x00003f00 75bb0a56ecSDave Jones #define MSR_S_LO_CURRENT_FID 0x0000003f 76bb0a56ecSDave Jones 77bb0a56ecSDave Jones /* Field definitions within the FID VID High Status MSR : */ 78bb0a56ecSDave Jones #define MSR_S_HI_MIN_WORKING_VID 0x3f000000 79bb0a56ecSDave Jones #define MSR_S_HI_MAX_WORKING_VID 0x003f0000 80bb0a56ecSDave Jones #define MSR_S_HI_START_VID 0x00003f00 81bb0a56ecSDave Jones #define MSR_S_HI_CURRENT_VID 0x0000003f 82bb0a56ecSDave Jones #define MSR_C_HI_STP_GNT_BENIGN 0x00000001 83bb0a56ecSDave Jones 84bb0a56ecSDave Jones /* 85bb0a56ecSDave Jones * There are restrictions frequencies have to follow: 86bb0a56ecSDave Jones * - only 1 entry in the low fid table ( <=1.4GHz ) 87bb0a56ecSDave Jones * - lowest entry in the high fid table must be >= 2 * the entry in the 88bb0a56ecSDave Jones * low fid table 89bb0a56ecSDave Jones * - lowest entry in the high fid table must be a <= 200MHz + 2 * the entry 90bb0a56ecSDave Jones * in the low fid table 91bb0a56ecSDave Jones * - the parts can only step at <= 200 MHz intervals, odd fid values are 92bb0a56ecSDave Jones * supported in revision G and later revisions. 93bb0a56ecSDave Jones * - lowest frequency must be >= interprocessor hypertransport link speed 94bb0a56ecSDave Jones * (only applies to MP systems obviously) 95bb0a56ecSDave Jones */ 96bb0a56ecSDave Jones 97bb0a56ecSDave Jones /* fids (frequency identifiers) are arranged in 2 tables - lo and hi */ 98bb0a56ecSDave Jones #define LO_FID_TABLE_TOP 7 /* fid values marking the boundary */ 99bb0a56ecSDave Jones #define HI_FID_TABLE_BOTTOM 8 /* between the low and high tables */ 100bb0a56ecSDave Jones 101bb0a56ecSDave Jones #define LO_VCOFREQ_TABLE_TOP 1400 /* corresponding vco frequency values */ 102bb0a56ecSDave Jones #define HI_VCOFREQ_TABLE_BOTTOM 1600 103bb0a56ecSDave Jones 104bb0a56ecSDave Jones #define MIN_FREQ_RESOLUTION 200 /* fids jump by 2 matching freq jumps by 200 */ 105bb0a56ecSDave Jones 106bb0a56ecSDave Jones #define MAX_FID 0x2a /* Spec only gives FID values as far as 5 GHz */ 107bb0a56ecSDave Jones #define LEAST_VID 0x3e /* Lowest (numerically highest) useful vid value */ 108bb0a56ecSDave Jones 109bb0a56ecSDave Jones #define MIN_FREQ 800 /* Min and max freqs, per spec */ 110bb0a56ecSDave Jones #define MAX_FREQ 5000 111bb0a56ecSDave Jones 112bb0a56ecSDave Jones #define INVALID_FID_MASK 0xffffffc0 /* not a valid fid if these bits are set */ 113bb0a56ecSDave Jones #define INVALID_VID_MASK 0xffffffc0 /* not a valid vid if these bits are set */ 114bb0a56ecSDave Jones 115bb0a56ecSDave Jones #define VID_OFF 0x3f 116bb0a56ecSDave Jones 117bb0a56ecSDave Jones #define STOP_GRANT_5NS 1 /* min poss memory access latency for voltage change */ 118bb0a56ecSDave Jones 119bb0a56ecSDave Jones #define PLL_LOCK_CONVERSION (1000/5) /* ms to ns, then divide by clock period */ 120bb0a56ecSDave Jones 121bb0a56ecSDave Jones #define MAXIMUM_VID_STEPS 1 /* Current cpus only allow a single step of 25mV */ 122bb0a56ecSDave Jones #define VST_UNITS_20US 20 /* Voltage Stabilization Time is in units of 20us */ 123bb0a56ecSDave Jones 124bb0a56ecSDave Jones /* 125bb0a56ecSDave Jones * Most values of interest are encoded in a single field of the _PSS 126bb0a56ecSDave Jones * entries: the "control" value. 127bb0a56ecSDave Jones */ 128bb0a56ecSDave Jones 129bb0a56ecSDave Jones #define IRT_SHIFT 30 130bb0a56ecSDave Jones #define RVO_SHIFT 28 131bb0a56ecSDave Jones #define EXT_TYPE_SHIFT 27 132bb0a56ecSDave Jones #define PLL_L_SHIFT 20 133bb0a56ecSDave Jones #define MVS_SHIFT 18 134bb0a56ecSDave Jones #define VST_SHIFT 11 135bb0a56ecSDave Jones #define VID_SHIFT 6 136bb0a56ecSDave Jones #define IRT_MASK 3 137bb0a56ecSDave Jones #define RVO_MASK 3 138bb0a56ecSDave Jones #define EXT_TYPE_MASK 1 139bb0a56ecSDave Jones #define PLL_L_MASK 0x7f 140bb0a56ecSDave Jones #define MVS_MASK 3 141bb0a56ecSDave Jones #define VST_MASK 0x7f 142bb0a56ecSDave Jones #define VID_MASK 0x1f 143bb0a56ecSDave Jones #define FID_MASK 0x1f 144bb0a56ecSDave Jones #define EXT_VID_MASK 0x3f 145bb0a56ecSDave Jones #define EXT_FID_MASK 0x3f 146bb0a56ecSDave Jones 147bb0a56ecSDave Jones 148bb0a56ecSDave Jones /* 149bb0a56ecSDave Jones * Version 1.4 of the PSB table. This table is constructed by BIOS and is 150bb0a56ecSDave Jones * to tell the OS's power management driver which VIDs and FIDs are 151bb0a56ecSDave Jones * supported by this particular processor. 152bb0a56ecSDave Jones * If the data in the PSB / PST is wrong, then this driver will program the 153bb0a56ecSDave Jones * wrong values into hardware, which is very likely to lead to a crash. 154bb0a56ecSDave Jones */ 155bb0a56ecSDave Jones 156bb0a56ecSDave Jones #define PSB_ID_STRING "AMDK7PNOW!" 157bb0a56ecSDave Jones #define PSB_ID_STRING_LEN 10 158bb0a56ecSDave Jones 159bb0a56ecSDave Jones #define PSB_VERSION_1_4 0x14 160bb0a56ecSDave Jones 161bb0a56ecSDave Jones struct psb_s { 162bb0a56ecSDave Jones u8 signature[10]; 163bb0a56ecSDave Jones u8 tableversion; 164bb0a56ecSDave Jones u8 flags1; 165bb0a56ecSDave Jones u16 vstable; 166bb0a56ecSDave Jones u8 flags2; 167bb0a56ecSDave Jones u8 num_tables; 168bb0a56ecSDave Jones u32 cpuid; 169bb0a56ecSDave Jones u8 plllocktime; 170bb0a56ecSDave Jones u8 maxfid; 171bb0a56ecSDave Jones u8 maxvid; 172bb0a56ecSDave Jones u8 numps; 173bb0a56ecSDave Jones }; 174bb0a56ecSDave Jones 175bb0a56ecSDave Jones /* Pairs of fid/vid values are appended to the version 1.4 PSB table. */ 176bb0a56ecSDave Jones struct pst_s { 177bb0a56ecSDave Jones u8 fid; 178bb0a56ecSDave Jones u8 vid; 179bb0a56ecSDave Jones }; 180bb0a56ecSDave Jones 181bb0a56ecSDave Jones static int core_voltage_pre_transition(struct powernow_k8_data *data, 182bb0a56ecSDave Jones u32 reqvid, u32 regfid); 183bb0a56ecSDave Jones static int core_voltage_post_transition(struct powernow_k8_data *data, u32 reqvid); 184bb0a56ecSDave Jones static int core_frequency_transition(struct powernow_k8_data *data, u32 reqfid); 185bb0a56ecSDave Jones 186bb0a56ecSDave Jones static void powernow_k8_acpi_pst_values(struct powernow_k8_data *data, unsigned int index); 187bb0a56ecSDave Jones 188bb0a56ecSDave Jones static int fill_powernow_table_fidvid(struct powernow_k8_data *data, struct cpufreq_frequency_table *powernow_table); 189