1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 #ifndef __ASPEED_HACE_H__ 3 #define __ASPEED_HACE_H__ 4 5 #include <linux/interrupt.h> 6 #include <linux/delay.h> 7 #include <linux/err.h> 8 #include <linux/fips.h> 9 #include <linux/dma-mapping.h> 10 #include <crypto/aes.h> 11 #include <crypto/des.h> 12 #include <crypto/scatterwalk.h> 13 #include <crypto/internal/aead.h> 14 #include <crypto/internal/akcipher.h> 15 #include <crypto/internal/des.h> 16 #include <crypto/internal/hash.h> 17 #include <crypto/internal/kpp.h> 18 #include <crypto/internal/skcipher.h> 19 #include <crypto/algapi.h> 20 #include <crypto/engine.h> 21 #include <crypto/hmac.h> 22 #include <crypto/sha1.h> 23 #include <crypto/sha2.h> 24 25 /***************************** 26 * * 27 * HACE register definitions * 28 * * 29 * ***************************/ 30 #define ASPEED_HACE_SRC 0x00 /* Crypto Data Source Base Address Register */ 31 #define ASPEED_HACE_DEST 0x04 /* Crypto Data Destination Base Address Register */ 32 #define ASPEED_HACE_CONTEXT 0x08 /* Crypto Context Buffer Base Address Register */ 33 #define ASPEED_HACE_DATA_LEN 0x0C /* Crypto Data Length Register */ 34 #define ASPEED_HACE_CMD 0x10 /* Crypto Engine Command Register */ 35 36 /* G5 */ 37 #define ASPEED_HACE_TAG 0x18 /* HACE Tag Register */ 38 /* G6 */ 39 #define ASPEED_HACE_GCM_ADD_LEN 0x14 /* Crypto AES-GCM Additional Data Length Register */ 40 #define ASPEED_HACE_GCM_TAG_BASE_ADDR 0x18 /* Crypto AES-GCM Tag Write Buff Base Address Reg */ 41 42 #define ASPEED_HACE_STS 0x1C /* HACE Status Register */ 43 44 #define ASPEED_HACE_HASH_SRC 0x20 /* Hash Data Source Base Address Register */ 45 #define ASPEED_HACE_HASH_DIGEST_BUFF 0x24 /* Hash Digest Write Buffer Base Address Register */ 46 #define ASPEED_HACE_HASH_KEY_BUFF 0x28 /* Hash HMAC Key Buffer Base Address Register */ 47 #define ASPEED_HACE_HASH_DATA_LEN 0x2C /* Hash Data Length Register */ 48 #define ASPEED_HACE_HASH_CMD 0x30 /* Hash Engine Command Register */ 49 50 /* crypto cmd */ 51 #define HACE_CMD_SINGLE_DES 0 52 #define HACE_CMD_TRIPLE_DES BIT(17) 53 #define HACE_CMD_AES_SELECT 0 54 #define HACE_CMD_DES_SELECT BIT(16) 55 #define HACE_CMD_ISR_EN BIT(12) 56 #define HACE_CMD_CONTEXT_SAVE_ENABLE (0) 57 #define HACE_CMD_CONTEXT_SAVE_DISABLE BIT(9) 58 #define HACE_CMD_AES (0) 59 #define HACE_CMD_DES (0) 60 #define HACE_CMD_RC4 BIT(8) 61 #define HACE_CMD_DECRYPT (0) 62 #define HACE_CMD_ENCRYPT BIT(7) 63 64 #define HACE_CMD_ECB (0x0 << 4) 65 #define HACE_CMD_CBC (0x1 << 4) 66 #define HACE_CMD_CFB (0x2 << 4) 67 #define HACE_CMD_OFB (0x3 << 4) 68 #define HACE_CMD_CTR (0x4 << 4) 69 #define HACE_CMD_OP_MODE_MASK (0x7 << 4) 70 71 #define HACE_CMD_AES128 (0x0 << 2) 72 #define HACE_CMD_AES192 (0x1 << 2) 73 #define HACE_CMD_AES256 (0x2 << 2) 74 #define HACE_CMD_OP_CASCADE (0x3) 75 #define HACE_CMD_OP_INDEPENDENT (0x1) 76 77 /* G5 */ 78 #define HACE_CMD_RI_WO_DATA_ENABLE (0) 79 #define HACE_CMD_RI_WO_DATA_DISABLE BIT(11) 80 #define HACE_CMD_CONTEXT_LOAD_ENABLE (0) 81 #define HACE_CMD_CONTEXT_LOAD_DISABLE BIT(10) 82 /* G6 */ 83 #define HACE_CMD_AES_KEY_FROM_OTP BIT(24) 84 #define HACE_CMD_GHASH_TAG_XOR_EN BIT(23) 85 #define HACE_CMD_GHASH_PAD_LEN_INV BIT(22) 86 #define HACE_CMD_GCM_TAG_ADDR_SEL BIT(21) 87 #define HACE_CMD_MBUS_REQ_SYNC_EN BIT(20) 88 #define HACE_CMD_DES_SG_CTRL BIT(19) 89 #define HACE_CMD_SRC_SG_CTRL BIT(18) 90 #define HACE_CMD_CTR_IV_AES_96 (0x1 << 14) 91 #define HACE_CMD_CTR_IV_DES_32 (0x1 << 14) 92 #define HACE_CMD_CTR_IV_AES_64 (0x2 << 14) 93 #define HACE_CMD_CTR_IV_AES_32 (0x3 << 14) 94 #define HACE_CMD_AES_KEY_HW_EXP BIT(13) 95 #define HACE_CMD_GCM (0x5 << 4) 96 97 /* interrupt status reg */ 98 #define HACE_CRYPTO_ISR BIT(12) 99 #define HACE_HASH_ISR BIT(9) 100 #define HACE_HASH_BUSY BIT(0) 101 102 /* hash cmd reg */ 103 #define HASH_CMD_MBUS_REQ_SYNC_EN BIT(20) 104 #define HASH_CMD_HASH_SRC_SG_CTRL BIT(18) 105 #define HASH_CMD_SHA512_224 (0x3 << 10) 106 #define HASH_CMD_SHA512_256 (0x2 << 10) 107 #define HASH_CMD_SHA384 (0x1 << 10) 108 #define HASH_CMD_SHA512 (0) 109 #define HASH_CMD_INT_ENABLE BIT(9) 110 #define HASH_CMD_HMAC (0x1 << 7) 111 #define HASH_CMD_ACC_MODE (0x2 << 7) 112 #define HASH_CMD_HMAC_KEY (0x3 << 7) 113 #define HASH_CMD_SHA1 (0x2 << 4) 114 #define HASH_CMD_SHA224 (0x4 << 4) 115 #define HASH_CMD_SHA256 (0x5 << 4) 116 #define HASH_CMD_SHA512_SER (0x6 << 4) 117 #define HASH_CMD_SHA_SWAP (0x2 << 2) 118 119 #define HASH_SG_LAST_LIST BIT(31) 120 121 #define CRYPTO_FLAGS_BUSY BIT(1) 122 123 #define SHA_OP_UPDATE 1 124 #define SHA_OP_FINAL 2 125 126 #define SHA_FLAGS_SHA1 BIT(0) 127 #define SHA_FLAGS_SHA224 BIT(1) 128 #define SHA_FLAGS_SHA256 BIT(2) 129 #define SHA_FLAGS_SHA384 BIT(3) 130 #define SHA_FLAGS_SHA512 BIT(4) 131 #define SHA_FLAGS_SHA512_224 BIT(5) 132 #define SHA_FLAGS_SHA512_256 BIT(6) 133 #define SHA_FLAGS_HMAC BIT(8) 134 #define SHA_FLAGS_FINUP BIT(9) 135 #define SHA_FLAGS_MASK (0xff) 136 137 #define ASPEED_CRYPTO_SRC_DMA_BUF_LEN 0xa000 138 #define ASPEED_CRYPTO_DST_DMA_BUF_LEN 0xa000 139 #define ASPEED_CRYPTO_GCM_TAG_OFFSET 0x9ff0 140 #define ASPEED_HASH_SRC_DMA_BUF_LEN 0xa000 141 #define ASPEED_HASH_QUEUE_LENGTH 50 142 143 #define HACE_CMD_IV_REQUIRE (HACE_CMD_CBC | HACE_CMD_CFB | \ 144 HACE_CMD_OFB | HACE_CMD_CTR) 145 146 struct aspeed_hace_dev; 147 148 typedef int (*aspeed_hace_fn_t)(struct aspeed_hace_dev *); 149 150 struct aspeed_sg_list { 151 __le32 len; 152 __le32 phy_addr; 153 }; 154 155 struct aspeed_engine_hash { 156 struct tasklet_struct done_task; 157 unsigned long flags; 158 struct ahash_request *req; 159 160 /* input buffer */ 161 void *ahash_src_addr; 162 dma_addr_t ahash_src_dma_addr; 163 164 dma_addr_t src_dma; 165 dma_addr_t digest_dma; 166 167 size_t src_length; 168 169 /* callback func */ 170 aspeed_hace_fn_t resume; 171 aspeed_hace_fn_t dma_prepare; 172 }; 173 174 struct aspeed_sha_hmac_ctx { 175 struct crypto_shash *shash; 176 u8 ipad[SHA512_BLOCK_SIZE]; 177 u8 opad[SHA512_BLOCK_SIZE]; 178 }; 179 180 struct aspeed_sham_ctx { 181 struct crypto_engine_ctx enginectx; 182 183 struct aspeed_hace_dev *hace_dev; 184 unsigned long flags; /* hmac flag */ 185 186 struct aspeed_sha_hmac_ctx base[]; 187 }; 188 189 struct aspeed_sham_reqctx { 190 unsigned long flags; /* final update flag should no use*/ 191 unsigned long op; /* final or update */ 192 u32 cmd; /* trigger cmd */ 193 194 /* walk state */ 195 struct scatterlist *src_sg; 196 int src_nents; 197 unsigned int offset; /* offset in current sg */ 198 unsigned int total; /* per update length */ 199 200 size_t digsize; 201 size_t block_size; 202 size_t ivsize; 203 const __be32 *sha_iv; 204 205 /* remain data buffer */ 206 u8 buffer[SHA512_BLOCK_SIZE * 2]; 207 dma_addr_t buffer_dma_addr; 208 size_t bufcnt; /* buffer counter */ 209 210 /* output buffer */ 211 u8 digest[SHA512_DIGEST_SIZE] __aligned(64); 212 dma_addr_t digest_dma_addr; 213 u64 digcnt[2]; 214 }; 215 216 struct aspeed_engine_crypto { 217 struct tasklet_struct done_task; 218 unsigned long flags; 219 struct skcipher_request *req; 220 221 /* context buffer */ 222 void *cipher_ctx; 223 dma_addr_t cipher_ctx_dma; 224 225 /* input buffer, could be single/scatter-gather lists */ 226 void *cipher_addr; 227 dma_addr_t cipher_dma_addr; 228 229 /* output buffer, only used in scatter-gather lists */ 230 void *dst_sg_addr; 231 dma_addr_t dst_sg_dma_addr; 232 233 /* callback func */ 234 aspeed_hace_fn_t resume; 235 }; 236 237 struct aspeed_cipher_ctx { 238 struct crypto_engine_ctx enginectx; 239 240 struct aspeed_hace_dev *hace_dev; 241 int key_len; 242 u8 key[AES_MAX_KEYLENGTH]; 243 244 /* callback func */ 245 aspeed_hace_fn_t start; 246 247 struct crypto_skcipher *fallback_tfm; 248 }; 249 250 struct aspeed_cipher_reqctx { 251 int enc_cmd; 252 int src_nents; 253 int dst_nents; 254 255 struct skcipher_request fallback_req; /* keep at the end */ 256 }; 257 258 struct aspeed_hace_dev { 259 void __iomem *regs; 260 struct device *dev; 261 int irq; 262 struct clk *clk; 263 unsigned long version; 264 265 struct crypto_engine *crypt_engine_hash; 266 struct crypto_engine *crypt_engine_crypto; 267 268 struct aspeed_engine_hash hash_engine; 269 struct aspeed_engine_crypto crypto_engine; 270 }; 271 272 struct aspeed_hace_alg { 273 struct aspeed_hace_dev *hace_dev; 274 275 const char *alg_base; 276 277 union { 278 struct skcipher_alg skcipher; 279 struct ahash_alg ahash; 280 } alg; 281 }; 282 283 enum aspeed_version { 284 AST2500_VERSION = 5, 285 AST2600_VERSION 286 }; 287 288 #define ast_hace_write(hace, val, offset) \ 289 writel((val), (hace)->regs + (offset)) 290 #define ast_hace_read(hace, offset) \ 291 readl((hace)->regs + (offset)) 292 293 void aspeed_register_hace_hash_algs(struct aspeed_hace_dev *hace_dev); 294 void aspeed_unregister_hace_hash_algs(struct aspeed_hace_dev *hace_dev); 295 void aspeed_register_hace_crypto_algs(struct aspeed_hace_dev *hace_dev); 296 void aspeed_unregister_hace_crypto_algs(struct aspeed_hace_dev *hace_dev); 297 298 #endif 299