14c3f9727SGilad Ben-Yossef /* SPDX-License-Identifier: GPL-2.0 */ 24c3f9727SGilad Ben-Yossef /* Copyright (C) 2012-2018 ARM Limited or its affiliates. */ 34c3f9727SGilad Ben-Yossef 44c3f9727SGilad Ben-Yossef #ifndef __CC_HW_QUEUE_DEFS_H__ 54c3f9727SGilad Ben-Yossef #define __CC_HW_QUEUE_DEFS_H__ 64c3f9727SGilad Ben-Yossef 74c3f9727SGilad Ben-Yossef #include <linux/types.h> 84c3f9727SGilad Ben-Yossef 94c3f9727SGilad Ben-Yossef #include "cc_kernel_regs.h" 104c3f9727SGilad Ben-Yossef #include <linux/bitfield.h> 114c3f9727SGilad Ben-Yossef 124c3f9727SGilad Ben-Yossef /****************************************************************************** 134c3f9727SGilad Ben-Yossef * DEFINITIONS 144c3f9727SGilad Ben-Yossef ******************************************************************************/ 154c3f9727SGilad Ben-Yossef 164c3f9727SGilad Ben-Yossef #define HW_DESC_SIZE_WORDS 6 174c3f9727SGilad Ben-Yossef /* Define max. available slots in HW queue */ 184c3f9727SGilad Ben-Yossef #define HW_QUEUE_SLOTS_MAX 15 194c3f9727SGilad Ben-Yossef 204c3f9727SGilad Ben-Yossef #define CC_REG_LOW(word, name) \ 214c3f9727SGilad Ben-Yossef (CC_DSCRPTR_QUEUE_WORD ## word ## _ ## name ## _BIT_SHIFT) 224c3f9727SGilad Ben-Yossef 234c3f9727SGilad Ben-Yossef #define CC_REG_HIGH(word, name) \ 244c3f9727SGilad Ben-Yossef (CC_REG_LOW(word, name) + \ 254c3f9727SGilad Ben-Yossef CC_DSCRPTR_QUEUE_WORD ## word ## _ ## name ## _BIT_SIZE - 1) 264c3f9727SGilad Ben-Yossef 274c3f9727SGilad Ben-Yossef #define CC_GENMASK(word, name) \ 284c3f9727SGilad Ben-Yossef GENMASK(CC_REG_HIGH(word, name), CC_REG_LOW(word, name)) 294c3f9727SGilad Ben-Yossef 304c3f9727SGilad Ben-Yossef #define WORD0_VALUE CC_GENMASK(0, VALUE) 314c3f9727SGilad Ben-Yossef #define WORD1_DIN_CONST_VALUE CC_GENMASK(1, DIN_CONST_VALUE) 324c3f9727SGilad Ben-Yossef #define WORD1_DIN_DMA_MODE CC_GENMASK(1, DIN_DMA_MODE) 334c3f9727SGilad Ben-Yossef #define WORD1_DIN_SIZE CC_GENMASK(1, DIN_SIZE) 344c3f9727SGilad Ben-Yossef #define WORD1_NOT_LAST CC_GENMASK(1, NOT_LAST) 354c3f9727SGilad Ben-Yossef #define WORD1_NS_BIT CC_GENMASK(1, NS_BIT) 364c3f9727SGilad Ben-Yossef #define WORD2_VALUE CC_GENMASK(2, VALUE) 374c3f9727SGilad Ben-Yossef #define WORD3_DOUT_DMA_MODE CC_GENMASK(3, DOUT_DMA_MODE) 384c3f9727SGilad Ben-Yossef #define WORD3_DOUT_LAST_IND CC_GENMASK(3, DOUT_LAST_IND) 394c3f9727SGilad Ben-Yossef #define WORD3_DOUT_SIZE CC_GENMASK(3, DOUT_SIZE) 404c3f9727SGilad Ben-Yossef #define WORD3_HASH_XOR_BIT CC_GENMASK(3, HASH_XOR_BIT) 414c3f9727SGilad Ben-Yossef #define WORD3_NS_BIT CC_GENMASK(3, NS_BIT) 424c3f9727SGilad Ben-Yossef #define WORD3_QUEUE_LAST_IND CC_GENMASK(3, QUEUE_LAST_IND) 434c3f9727SGilad Ben-Yossef #define WORD4_ACK_NEEDED CC_GENMASK(4, ACK_NEEDED) 444c3f9727SGilad Ben-Yossef #define WORD4_AES_SEL_N_HASH CC_GENMASK(4, AES_SEL_N_HASH) 454c3f9727SGilad Ben-Yossef #define WORD4_BYTES_SWAP CC_GENMASK(4, BYTES_SWAP) 464c3f9727SGilad Ben-Yossef #define WORD4_CIPHER_CONF0 CC_GENMASK(4, CIPHER_CONF0) 474c3f9727SGilad Ben-Yossef #define WORD4_CIPHER_CONF1 CC_GENMASK(4, CIPHER_CONF1) 484c3f9727SGilad Ben-Yossef #define WORD4_CIPHER_CONF2 CC_GENMASK(4, CIPHER_CONF2) 494c3f9727SGilad Ben-Yossef #define WORD4_CIPHER_DO CC_GENMASK(4, CIPHER_DO) 504c3f9727SGilad Ben-Yossef #define WORD4_CIPHER_MODE CC_GENMASK(4, CIPHER_MODE) 514c3f9727SGilad Ben-Yossef #define WORD4_CMAC_SIZE0 CC_GENMASK(4, CMAC_SIZE0) 524c3f9727SGilad Ben-Yossef #define WORD4_DATA_FLOW_MODE CC_GENMASK(4, DATA_FLOW_MODE) 534c3f9727SGilad Ben-Yossef #define WORD4_KEY_SIZE CC_GENMASK(4, KEY_SIZE) 544c3f9727SGilad Ben-Yossef #define WORD4_SETUP_OPERATION CC_GENMASK(4, SETUP_OPERATION) 554c3f9727SGilad Ben-Yossef #define WORD5_DIN_ADDR_HIGH CC_GENMASK(5, DIN_ADDR_HIGH) 564c3f9727SGilad Ben-Yossef #define WORD5_DOUT_ADDR_HIGH CC_GENMASK(5, DOUT_ADDR_HIGH) 574c3f9727SGilad Ben-Yossef 584c3f9727SGilad Ben-Yossef /****************************************************************************** 594c3f9727SGilad Ben-Yossef * TYPE DEFINITIONS 604c3f9727SGilad Ben-Yossef ******************************************************************************/ 614c3f9727SGilad Ben-Yossef 624c3f9727SGilad Ben-Yossef struct cc_hw_desc { 634c3f9727SGilad Ben-Yossef union { 644c3f9727SGilad Ben-Yossef u32 word[HW_DESC_SIZE_WORDS]; 654c3f9727SGilad Ben-Yossef u16 hword[HW_DESC_SIZE_WORDS * 2]; 664c3f9727SGilad Ben-Yossef }; 674c3f9727SGilad Ben-Yossef }; 684c3f9727SGilad Ben-Yossef 694c3f9727SGilad Ben-Yossef enum cc_axi_sec { 704c3f9727SGilad Ben-Yossef AXI_SECURE = 0, 714c3f9727SGilad Ben-Yossef AXI_NOT_SECURE = 1 724c3f9727SGilad Ben-Yossef }; 734c3f9727SGilad Ben-Yossef 744c3f9727SGilad Ben-Yossef enum cc_desc_direction { 754c3f9727SGilad Ben-Yossef DESC_DIRECTION_ILLEGAL = -1, 764c3f9727SGilad Ben-Yossef DESC_DIRECTION_ENCRYPT_ENCRYPT = 0, 774c3f9727SGilad Ben-Yossef DESC_DIRECTION_DECRYPT_DECRYPT = 1, 784c3f9727SGilad Ben-Yossef DESC_DIRECTION_DECRYPT_ENCRYPT = 3, 794c3f9727SGilad Ben-Yossef DESC_DIRECTION_END = S32_MAX, 804c3f9727SGilad Ben-Yossef }; 814c3f9727SGilad Ben-Yossef 824c3f9727SGilad Ben-Yossef enum cc_dma_mode { 834c3f9727SGilad Ben-Yossef DMA_MODE_NULL = -1, 844c3f9727SGilad Ben-Yossef NO_DMA = 0, 854c3f9727SGilad Ben-Yossef DMA_SRAM = 1, 864c3f9727SGilad Ben-Yossef DMA_DLLI = 2, 874c3f9727SGilad Ben-Yossef DMA_MLLI = 3, 884c3f9727SGilad Ben-Yossef DMA_MODE_END = S32_MAX, 894c3f9727SGilad Ben-Yossef }; 904c3f9727SGilad Ben-Yossef 914c3f9727SGilad Ben-Yossef enum cc_flow_mode { 924c3f9727SGilad Ben-Yossef FLOW_MODE_NULL = -1, 934c3f9727SGilad Ben-Yossef /* data flows */ 944c3f9727SGilad Ben-Yossef BYPASS = 0, 954c3f9727SGilad Ben-Yossef DIN_AES_DOUT = 1, 964c3f9727SGilad Ben-Yossef AES_to_HASH = 2, 974c3f9727SGilad Ben-Yossef AES_and_HASH = 3, 984c3f9727SGilad Ben-Yossef DIN_DES_DOUT = 4, 994c3f9727SGilad Ben-Yossef DES_to_HASH = 5, 1004c3f9727SGilad Ben-Yossef DES_and_HASH = 6, 1014c3f9727SGilad Ben-Yossef DIN_HASH = 7, 1024c3f9727SGilad Ben-Yossef DIN_HASH_and_BYPASS = 8, 1034c3f9727SGilad Ben-Yossef AESMAC_and_BYPASS = 9, 1044c3f9727SGilad Ben-Yossef AES_to_HASH_and_DOUT = 10, 1054c3f9727SGilad Ben-Yossef DIN_RC4_DOUT = 11, 1064c3f9727SGilad Ben-Yossef DES_to_HASH_and_DOUT = 12, 1074c3f9727SGilad Ben-Yossef AES_to_AES_to_HASH_and_DOUT = 13, 1084c3f9727SGilad Ben-Yossef AES_to_AES_to_HASH = 14, 1094c3f9727SGilad Ben-Yossef AES_to_HASH_and_AES = 15, 1109b8d51f8SGilad Ben-Yossef DIN_SM4_DOUT = 16, 1114c3f9727SGilad Ben-Yossef DIN_AES_AESMAC = 17, 1124c3f9727SGilad Ben-Yossef HASH_to_DOUT = 18, 1134c3f9727SGilad Ben-Yossef /* setup flows */ 1144c3f9727SGilad Ben-Yossef S_DIN_to_AES = 32, 1154c3f9727SGilad Ben-Yossef S_DIN_to_AES2 = 33, 1164c3f9727SGilad Ben-Yossef S_DIN_to_DES = 34, 1174c3f9727SGilad Ben-Yossef S_DIN_to_RC4 = 35, 1189b8d51f8SGilad Ben-Yossef S_DIN_to_SM4 = 36, 1194c3f9727SGilad Ben-Yossef S_DIN_to_HASH = 37, 1204c3f9727SGilad Ben-Yossef S_AES_to_DOUT = 38, 1214c3f9727SGilad Ben-Yossef S_AES2_to_DOUT = 39, 1229b8d51f8SGilad Ben-Yossef S_SM4_to_DOUT = 40, 1234c3f9727SGilad Ben-Yossef S_RC4_to_DOUT = 41, 1244c3f9727SGilad Ben-Yossef S_DES_to_DOUT = 42, 1254c3f9727SGilad Ben-Yossef S_HASH_to_DOUT = 43, 1264c3f9727SGilad Ben-Yossef SET_FLOW_ID = 44, 1274c3f9727SGilad Ben-Yossef FLOW_MODE_END = S32_MAX, 1284c3f9727SGilad Ben-Yossef }; 1294c3f9727SGilad Ben-Yossef 1304c3f9727SGilad Ben-Yossef enum cc_setup_op { 1314c3f9727SGilad Ben-Yossef SETUP_LOAD_NOP = 0, 1324c3f9727SGilad Ben-Yossef SETUP_LOAD_STATE0 = 1, 1334c3f9727SGilad Ben-Yossef SETUP_LOAD_STATE1 = 2, 1344c3f9727SGilad Ben-Yossef SETUP_LOAD_STATE2 = 3, 1354c3f9727SGilad Ben-Yossef SETUP_LOAD_KEY0 = 4, 1364c3f9727SGilad Ben-Yossef SETUP_LOAD_XEX_KEY = 5, 1374c3f9727SGilad Ben-Yossef SETUP_WRITE_STATE0 = 8, 1384c3f9727SGilad Ben-Yossef SETUP_WRITE_STATE1 = 9, 1394c3f9727SGilad Ben-Yossef SETUP_WRITE_STATE2 = 10, 1404c3f9727SGilad Ben-Yossef SETUP_WRITE_STATE3 = 11, 1414c3f9727SGilad Ben-Yossef SETUP_OP_END = S32_MAX, 1424c3f9727SGilad Ben-Yossef }; 1434c3f9727SGilad Ben-Yossef 144f444ec10SGilad Ben-Yossef enum cc_hash_conf_pad { 145f444ec10SGilad Ben-Yossef HASH_PADDING_DISABLED = 0, 146f444ec10SGilad Ben-Yossef HASH_PADDING_ENABLED = 1, 147f444ec10SGilad Ben-Yossef HASH_DIGEST_RESULT_LITTLE_ENDIAN = 2, 148f444ec10SGilad Ben-Yossef HASH_CONFIG1_PADDING_RESERVE32 = S32_MAX, 149f444ec10SGilad Ben-Yossef }; 150f444ec10SGilad Ben-Yossef 1514c3f9727SGilad Ben-Yossef enum cc_aes_mac_selector { 1524c3f9727SGilad Ben-Yossef AES_SK = 1, 1534c3f9727SGilad Ben-Yossef AES_CMAC_INIT = 2, 1544c3f9727SGilad Ben-Yossef AES_CMAC_SIZE0 = 3, 1554c3f9727SGilad Ben-Yossef AES_MAC_END = S32_MAX, 1564c3f9727SGilad Ben-Yossef }; 1574c3f9727SGilad Ben-Yossef 1584c3f9727SGilad Ben-Yossef #define HW_KEY_MASK_CIPHER_DO 0x3 1594c3f9727SGilad Ben-Yossef #define HW_KEY_SHIFT_CIPHER_CFG2 2 1604c3f9727SGilad Ben-Yossef 1614c3f9727SGilad Ben-Yossef /* HwCryptoKey[1:0] is mapped to cipher_do[1:0] */ 1624c3f9727SGilad Ben-Yossef /* HwCryptoKey[2:3] is mapped to cipher_config2[1:0] */ 1634c3f9727SGilad Ben-Yossef enum cc_hw_crypto_key { 1644c3f9727SGilad Ben-Yossef USER_KEY = 0, /* 0x0000 */ 1654c3f9727SGilad Ben-Yossef ROOT_KEY = 1, /* 0x0001 */ 1664c3f9727SGilad Ben-Yossef PROVISIONING_KEY = 2, /* 0x0010 */ /* ==KCP */ 1674c3f9727SGilad Ben-Yossef SESSION_KEY = 3, /* 0x0011 */ 1684c3f9727SGilad Ben-Yossef RESERVED_KEY = 4, /* NA */ 1694c3f9727SGilad Ben-Yossef PLATFORM_KEY = 5, /* 0x0101 */ 1704c3f9727SGilad Ben-Yossef CUSTOMER_KEY = 6, /* 0x0110 */ 1714c3f9727SGilad Ben-Yossef KFDE0_KEY = 7, /* 0x0111 */ 1724c3f9727SGilad Ben-Yossef KFDE1_KEY = 9, /* 0x1001 */ 1734c3f9727SGilad Ben-Yossef KFDE2_KEY = 10, /* 0x1010 */ 1744c3f9727SGilad Ben-Yossef KFDE3_KEY = 11, /* 0x1011 */ 1754c3f9727SGilad Ben-Yossef END_OF_KEYS = S32_MAX, 1764c3f9727SGilad Ben-Yossef }; 1774c3f9727SGilad Ben-Yossef 1784c3f9727SGilad Ben-Yossef enum cc_hw_aes_key_size { 1794c3f9727SGilad Ben-Yossef AES_128_KEY = 0, 1804c3f9727SGilad Ben-Yossef AES_192_KEY = 1, 1814c3f9727SGilad Ben-Yossef AES_256_KEY = 2, 1824c3f9727SGilad Ben-Yossef END_OF_AES_KEYS = S32_MAX, 1834c3f9727SGilad Ben-Yossef }; 1844c3f9727SGilad Ben-Yossef 1854c3f9727SGilad Ben-Yossef enum cc_hash_cipher_pad { 1864c3f9727SGilad Ben-Yossef DO_NOT_PAD = 0, 1874c3f9727SGilad Ben-Yossef DO_PAD = 1, 1884c3f9727SGilad Ben-Yossef HASH_CIPHER_DO_PADDING_RESERVE32 = S32_MAX, 1894c3f9727SGilad Ben-Yossef }; 1904c3f9727SGilad Ben-Yossef 1914c3f9727SGilad Ben-Yossef /*****************************/ 1924c3f9727SGilad Ben-Yossef /* Descriptor packing macros */ 1934c3f9727SGilad Ben-Yossef /*****************************/ 1944c3f9727SGilad Ben-Yossef 1954c3f9727SGilad Ben-Yossef /* 1964c3f9727SGilad Ben-Yossef * Init a HW descriptor struct 1974c3f9727SGilad Ben-Yossef * @pdesc: pointer HW descriptor struct 1984c3f9727SGilad Ben-Yossef */ 1994c3f9727SGilad Ben-Yossef static inline void hw_desc_init(struct cc_hw_desc *pdesc) 2004c3f9727SGilad Ben-Yossef { 2014c3f9727SGilad Ben-Yossef memset(pdesc, 0, sizeof(struct cc_hw_desc)); 2024c3f9727SGilad Ben-Yossef } 2034c3f9727SGilad Ben-Yossef 2044c3f9727SGilad Ben-Yossef /* 2054c3f9727SGilad Ben-Yossef * Indicates the end of current HW descriptors flow and release the HW engines. 2064c3f9727SGilad Ben-Yossef * 2074c3f9727SGilad Ben-Yossef * @pdesc: pointer HW descriptor struct 2084c3f9727SGilad Ben-Yossef */ 20927b3b22dSGilad Ben-Yossef static inline void set_queue_last_ind_bit(struct cc_hw_desc *pdesc) 2104c3f9727SGilad Ben-Yossef { 2114c3f9727SGilad Ben-Yossef pdesc->word[3] |= FIELD_PREP(WORD3_QUEUE_LAST_IND, 1); 2124c3f9727SGilad Ben-Yossef } 2134c3f9727SGilad Ben-Yossef 2144c3f9727SGilad Ben-Yossef /* 2154c3f9727SGilad Ben-Yossef * Set the DIN field of a HW descriptors 2164c3f9727SGilad Ben-Yossef * 2174c3f9727SGilad Ben-Yossef * @pdesc: pointer HW descriptor struct 2184c3f9727SGilad Ben-Yossef * @dma_mode: dmaMode The DMA mode: NO_DMA, SRAM, DLLI, MLLI, CONSTANT 2194c3f9727SGilad Ben-Yossef * @addr: dinAdr DIN address 2204c3f9727SGilad Ben-Yossef * @size: Data size in bytes 2214c3f9727SGilad Ben-Yossef * @axi_sec: AXI secure bit 2224c3f9727SGilad Ben-Yossef */ 2234c3f9727SGilad Ben-Yossef static inline void set_din_type(struct cc_hw_desc *pdesc, 2244c3f9727SGilad Ben-Yossef enum cc_dma_mode dma_mode, dma_addr_t addr, 2254c3f9727SGilad Ben-Yossef u32 size, enum cc_axi_sec axi_sec) 2264c3f9727SGilad Ben-Yossef { 2274c3f9727SGilad Ben-Yossef pdesc->word[0] = (u32)addr; 2284c3f9727SGilad Ben-Yossef #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 2294c3f9727SGilad Ben-Yossef pdesc->word[5] |= FIELD_PREP(WORD5_DIN_ADDR_HIGH, ((u16)(addr >> 32))); 2304c3f9727SGilad Ben-Yossef #endif 2314c3f9727SGilad Ben-Yossef pdesc->word[1] |= FIELD_PREP(WORD1_DIN_DMA_MODE, dma_mode) | 2324c3f9727SGilad Ben-Yossef FIELD_PREP(WORD1_DIN_SIZE, size) | 2334c3f9727SGilad Ben-Yossef FIELD_PREP(WORD1_NS_BIT, axi_sec); 2344c3f9727SGilad Ben-Yossef } 2354c3f9727SGilad Ben-Yossef 2364c3f9727SGilad Ben-Yossef /* 2374c3f9727SGilad Ben-Yossef * Set the DIN field of a HW descriptors to NO DMA mode. 2384c3f9727SGilad Ben-Yossef * Used for NOP descriptor, register patches and other special modes. 2394c3f9727SGilad Ben-Yossef * 2404c3f9727SGilad Ben-Yossef * @pdesc: pointer HW descriptor struct 2414c3f9727SGilad Ben-Yossef * @addr: DIN address 2424c3f9727SGilad Ben-Yossef * @size: Data size in bytes 2434c3f9727SGilad Ben-Yossef */ 2444c3f9727SGilad Ben-Yossef static inline void set_din_no_dma(struct cc_hw_desc *pdesc, u32 addr, u32 size) 2454c3f9727SGilad Ben-Yossef { 2464c3f9727SGilad Ben-Yossef pdesc->word[0] = addr; 2474c3f9727SGilad Ben-Yossef pdesc->word[1] |= FIELD_PREP(WORD1_DIN_SIZE, size); 2484c3f9727SGilad Ben-Yossef } 2494c3f9727SGilad Ben-Yossef 2504c3f9727SGilad Ben-Yossef /* 2514c3f9727SGilad Ben-Yossef * Set the DIN field of a HW descriptors to SRAM mode. 2524c3f9727SGilad Ben-Yossef * Note: No need to check SRAM alignment since host requests do not use SRAM and 2534c3f9727SGilad Ben-Yossef * adaptor will enforce alignment check. 2544c3f9727SGilad Ben-Yossef * 2554c3f9727SGilad Ben-Yossef * @pdesc: pointer HW descriptor struct 2564c3f9727SGilad Ben-Yossef * @addr: DIN address 2574c3f9727SGilad Ben-Yossef * @size Data size in bytes 2584c3f9727SGilad Ben-Yossef */ 2594c3f9727SGilad Ben-Yossef static inline void set_din_sram(struct cc_hw_desc *pdesc, dma_addr_t addr, 2604c3f9727SGilad Ben-Yossef u32 size) 2614c3f9727SGilad Ben-Yossef { 2624c3f9727SGilad Ben-Yossef pdesc->word[0] = (u32)addr; 2634c3f9727SGilad Ben-Yossef pdesc->word[1] |= FIELD_PREP(WORD1_DIN_SIZE, size) | 2644c3f9727SGilad Ben-Yossef FIELD_PREP(WORD1_DIN_DMA_MODE, DMA_SRAM); 2654c3f9727SGilad Ben-Yossef } 2664c3f9727SGilad Ben-Yossef 2674c3f9727SGilad Ben-Yossef /* 2684c3f9727SGilad Ben-Yossef * Set the DIN field of a HW descriptors to CONST mode 2694c3f9727SGilad Ben-Yossef * 2704c3f9727SGilad Ben-Yossef * @pdesc: pointer HW descriptor struct 2714c3f9727SGilad Ben-Yossef * @val: DIN const value 2724c3f9727SGilad Ben-Yossef * @size: Data size in bytes 2734c3f9727SGilad Ben-Yossef */ 2744c3f9727SGilad Ben-Yossef static inline void set_din_const(struct cc_hw_desc *pdesc, u32 val, u32 size) 2754c3f9727SGilad Ben-Yossef { 2764c3f9727SGilad Ben-Yossef pdesc->word[0] = val; 2774c3f9727SGilad Ben-Yossef pdesc->word[1] |= FIELD_PREP(WORD1_DIN_CONST_VALUE, 1) | 2784c3f9727SGilad Ben-Yossef FIELD_PREP(WORD1_DIN_DMA_MODE, DMA_SRAM) | 2794c3f9727SGilad Ben-Yossef FIELD_PREP(WORD1_DIN_SIZE, size); 2804c3f9727SGilad Ben-Yossef } 2814c3f9727SGilad Ben-Yossef 2824c3f9727SGilad Ben-Yossef /* 2834c3f9727SGilad Ben-Yossef * Set the DIN not last input data indicator 2844c3f9727SGilad Ben-Yossef * 2854c3f9727SGilad Ben-Yossef * @pdesc: pointer HW descriptor struct 2864c3f9727SGilad Ben-Yossef */ 2874c3f9727SGilad Ben-Yossef static inline void set_din_not_last_indication(struct cc_hw_desc *pdesc) 2884c3f9727SGilad Ben-Yossef { 2894c3f9727SGilad Ben-Yossef pdesc->word[1] |= FIELD_PREP(WORD1_NOT_LAST, 1); 2904c3f9727SGilad Ben-Yossef } 2914c3f9727SGilad Ben-Yossef 2924c3f9727SGilad Ben-Yossef /* 2934c3f9727SGilad Ben-Yossef * Set the DOUT field of a HW descriptors 2944c3f9727SGilad Ben-Yossef * 2954c3f9727SGilad Ben-Yossef * @pdesc: pointer HW descriptor struct 2964c3f9727SGilad Ben-Yossef * @dma_mode: The DMA mode: NO_DMA, SRAM, DLLI, MLLI, CONSTANT 2974c3f9727SGilad Ben-Yossef * @addr: DOUT address 2984c3f9727SGilad Ben-Yossef * @size: Data size in bytes 2994c3f9727SGilad Ben-Yossef * @axi_sec: AXI secure bit 3004c3f9727SGilad Ben-Yossef */ 3014c3f9727SGilad Ben-Yossef static inline void set_dout_type(struct cc_hw_desc *pdesc, 3024c3f9727SGilad Ben-Yossef enum cc_dma_mode dma_mode, dma_addr_t addr, 3034c3f9727SGilad Ben-Yossef u32 size, enum cc_axi_sec axi_sec) 3044c3f9727SGilad Ben-Yossef { 3054c3f9727SGilad Ben-Yossef pdesc->word[2] = (u32)addr; 3064c3f9727SGilad Ben-Yossef #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 3074c3f9727SGilad Ben-Yossef pdesc->word[5] |= FIELD_PREP(WORD5_DOUT_ADDR_HIGH, ((u16)(addr >> 32))); 3084c3f9727SGilad Ben-Yossef #endif 3094c3f9727SGilad Ben-Yossef pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_DMA_MODE, dma_mode) | 3104c3f9727SGilad Ben-Yossef FIELD_PREP(WORD3_DOUT_SIZE, size) | 3114c3f9727SGilad Ben-Yossef FIELD_PREP(WORD3_NS_BIT, axi_sec); 3124c3f9727SGilad Ben-Yossef } 3134c3f9727SGilad Ben-Yossef 3144c3f9727SGilad Ben-Yossef /* 3154c3f9727SGilad Ben-Yossef * Set the DOUT field of a HW descriptors to DLLI type 3164c3f9727SGilad Ben-Yossef * The LAST INDICATION is provided by the user 3174c3f9727SGilad Ben-Yossef * 3184c3f9727SGilad Ben-Yossef * @pdesc pointer HW descriptor struct 3194c3f9727SGilad Ben-Yossef * @addr: DOUT address 3204c3f9727SGilad Ben-Yossef * @size: Data size in bytes 3214c3f9727SGilad Ben-Yossef * @last_ind: The last indication bit 3224c3f9727SGilad Ben-Yossef * @axi_sec: AXI secure bit 3234c3f9727SGilad Ben-Yossef */ 3244c3f9727SGilad Ben-Yossef static inline void set_dout_dlli(struct cc_hw_desc *pdesc, dma_addr_t addr, 3254c3f9727SGilad Ben-Yossef u32 size, enum cc_axi_sec axi_sec, 3264c3f9727SGilad Ben-Yossef u32 last_ind) 3274c3f9727SGilad Ben-Yossef { 3284c3f9727SGilad Ben-Yossef set_dout_type(pdesc, DMA_DLLI, addr, size, axi_sec); 3294c3f9727SGilad Ben-Yossef pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_LAST_IND, last_ind); 3304c3f9727SGilad Ben-Yossef } 3314c3f9727SGilad Ben-Yossef 3324c3f9727SGilad Ben-Yossef /* 3334c3f9727SGilad Ben-Yossef * Set the DOUT field of a HW descriptors to DLLI type 3344c3f9727SGilad Ben-Yossef * The LAST INDICATION is provided by the user 3354c3f9727SGilad Ben-Yossef * 3364c3f9727SGilad Ben-Yossef * @pdesc: pointer HW descriptor struct 3374c3f9727SGilad Ben-Yossef * @addr: DOUT address 3384c3f9727SGilad Ben-Yossef * @size: Data size in bytes 3394c3f9727SGilad Ben-Yossef * @last_ind: The last indication bit 3404c3f9727SGilad Ben-Yossef * @axi_sec: AXI secure bit 3414c3f9727SGilad Ben-Yossef */ 3424c3f9727SGilad Ben-Yossef static inline void set_dout_mlli(struct cc_hw_desc *pdesc, dma_addr_t addr, 3434c3f9727SGilad Ben-Yossef u32 size, enum cc_axi_sec axi_sec, 3444c3f9727SGilad Ben-Yossef bool last_ind) 3454c3f9727SGilad Ben-Yossef { 3464c3f9727SGilad Ben-Yossef set_dout_type(pdesc, DMA_MLLI, addr, size, axi_sec); 3474c3f9727SGilad Ben-Yossef pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_LAST_IND, last_ind); 3484c3f9727SGilad Ben-Yossef } 3494c3f9727SGilad Ben-Yossef 3504c3f9727SGilad Ben-Yossef /* 3514c3f9727SGilad Ben-Yossef * Set the DOUT field of a HW descriptors to NO DMA mode. 3524c3f9727SGilad Ben-Yossef * Used for NOP descriptor, register patches and other special modes. 3534c3f9727SGilad Ben-Yossef * 3544c3f9727SGilad Ben-Yossef * @pdesc: pointer HW descriptor struct 3554c3f9727SGilad Ben-Yossef * @addr: DOUT address 3564c3f9727SGilad Ben-Yossef * @size: Data size in bytes 3574c3f9727SGilad Ben-Yossef * @write_enable: Enables a write operation to a register 3584c3f9727SGilad Ben-Yossef */ 3594c3f9727SGilad Ben-Yossef static inline void set_dout_no_dma(struct cc_hw_desc *pdesc, u32 addr, 3604c3f9727SGilad Ben-Yossef u32 size, bool write_enable) 3614c3f9727SGilad Ben-Yossef { 3624c3f9727SGilad Ben-Yossef pdesc->word[2] = addr; 3634c3f9727SGilad Ben-Yossef pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_SIZE, size) | 3644c3f9727SGilad Ben-Yossef FIELD_PREP(WORD3_DOUT_LAST_IND, write_enable); 3654c3f9727SGilad Ben-Yossef } 3664c3f9727SGilad Ben-Yossef 3674c3f9727SGilad Ben-Yossef /* 3684c3f9727SGilad Ben-Yossef * Set the word for the XOR operation. 3694c3f9727SGilad Ben-Yossef * 3704c3f9727SGilad Ben-Yossef * @pdesc: pointer HW descriptor struct 3714c3f9727SGilad Ben-Yossef * @val: xor data value 3724c3f9727SGilad Ben-Yossef */ 3734c3f9727SGilad Ben-Yossef static inline void set_xor_val(struct cc_hw_desc *pdesc, u32 val) 3744c3f9727SGilad Ben-Yossef { 3754c3f9727SGilad Ben-Yossef pdesc->word[2] = val; 3764c3f9727SGilad Ben-Yossef } 3774c3f9727SGilad Ben-Yossef 3784c3f9727SGilad Ben-Yossef /* 3794c3f9727SGilad Ben-Yossef * Sets the XOR indicator bit in the descriptor 3804c3f9727SGilad Ben-Yossef * 3814c3f9727SGilad Ben-Yossef * @pdesc: pointer HW descriptor struct 3824c3f9727SGilad Ben-Yossef */ 3834c3f9727SGilad Ben-Yossef static inline void set_xor_active(struct cc_hw_desc *pdesc) 3844c3f9727SGilad Ben-Yossef { 3854c3f9727SGilad Ben-Yossef pdesc->word[3] |= FIELD_PREP(WORD3_HASH_XOR_BIT, 1); 3864c3f9727SGilad Ben-Yossef } 3874c3f9727SGilad Ben-Yossef 3884c3f9727SGilad Ben-Yossef /* 3894c3f9727SGilad Ben-Yossef * Select the AES engine instead of HASH engine when setting up combined mode 3904c3f9727SGilad Ben-Yossef * with AES XCBC MAC 3914c3f9727SGilad Ben-Yossef * 3924c3f9727SGilad Ben-Yossef * @pdesc: pointer HW descriptor struct 3934c3f9727SGilad Ben-Yossef */ 3944c3f9727SGilad Ben-Yossef static inline void set_aes_not_hash_mode(struct cc_hw_desc *pdesc) 3954c3f9727SGilad Ben-Yossef { 3964c3f9727SGilad Ben-Yossef pdesc->word[4] |= FIELD_PREP(WORD4_AES_SEL_N_HASH, 1); 3974c3f9727SGilad Ben-Yossef } 3984c3f9727SGilad Ben-Yossef 3994c3f9727SGilad Ben-Yossef /* 4004c3f9727SGilad Ben-Yossef * Set the DOUT field of a HW descriptors to SRAM mode 4014c3f9727SGilad Ben-Yossef * Note: No need to check SRAM alignment since host requests do not use SRAM and 4024c3f9727SGilad Ben-Yossef * adaptor will enforce alignment check. 4034c3f9727SGilad Ben-Yossef * 4044c3f9727SGilad Ben-Yossef * @pdesc: pointer HW descriptor struct 4054c3f9727SGilad Ben-Yossef * @addr: DOUT address 4064c3f9727SGilad Ben-Yossef * @size: Data size in bytes 4074c3f9727SGilad Ben-Yossef */ 4084c3f9727SGilad Ben-Yossef static inline void set_dout_sram(struct cc_hw_desc *pdesc, u32 addr, u32 size) 4094c3f9727SGilad Ben-Yossef { 4104c3f9727SGilad Ben-Yossef pdesc->word[2] = addr; 4114c3f9727SGilad Ben-Yossef pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_DMA_MODE, DMA_SRAM) | 4124c3f9727SGilad Ben-Yossef FIELD_PREP(WORD3_DOUT_SIZE, size); 4134c3f9727SGilad Ben-Yossef } 4144c3f9727SGilad Ben-Yossef 4154c3f9727SGilad Ben-Yossef /* 4164c3f9727SGilad Ben-Yossef * Sets the data unit size for XEX mode in data_out_addr[15:0] 4174c3f9727SGilad Ben-Yossef * 4184c3f9727SGilad Ben-Yossef * @pdesc: pDesc pointer HW descriptor struct 4194c3f9727SGilad Ben-Yossef * @size: data unit size for XEX mode 4204c3f9727SGilad Ben-Yossef */ 4214c3f9727SGilad Ben-Yossef static inline void set_xex_data_unit_size(struct cc_hw_desc *pdesc, u32 size) 4224c3f9727SGilad Ben-Yossef { 4234c3f9727SGilad Ben-Yossef pdesc->word[2] = size; 4244c3f9727SGilad Ben-Yossef } 4254c3f9727SGilad Ben-Yossef 4264c3f9727SGilad Ben-Yossef /* 4274c3f9727SGilad Ben-Yossef * Set the number of rounds for Multi2 in data_out_addr[15:0] 4284c3f9727SGilad Ben-Yossef * 4294c3f9727SGilad Ben-Yossef * @pdesc: pointer HW descriptor struct 4304c3f9727SGilad Ben-Yossef * @num: number of rounds for Multi2 4314c3f9727SGilad Ben-Yossef */ 4324c3f9727SGilad Ben-Yossef static inline void set_multi2_num_rounds(struct cc_hw_desc *pdesc, u32 num) 4334c3f9727SGilad Ben-Yossef { 4344c3f9727SGilad Ben-Yossef pdesc->word[2] = num; 4354c3f9727SGilad Ben-Yossef } 4364c3f9727SGilad Ben-Yossef 4374c3f9727SGilad Ben-Yossef /* 4384c3f9727SGilad Ben-Yossef * Set the flow mode. 4394c3f9727SGilad Ben-Yossef * 4404c3f9727SGilad Ben-Yossef * @pdesc: pointer HW descriptor struct 4414c3f9727SGilad Ben-Yossef * @mode: Any one of the modes defined in [CC7x-DESC] 4424c3f9727SGilad Ben-Yossef */ 4434c3f9727SGilad Ben-Yossef static inline void set_flow_mode(struct cc_hw_desc *pdesc, 4444c3f9727SGilad Ben-Yossef enum cc_flow_mode mode) 4454c3f9727SGilad Ben-Yossef { 4464c3f9727SGilad Ben-Yossef pdesc->word[4] |= FIELD_PREP(WORD4_DATA_FLOW_MODE, mode); 4474c3f9727SGilad Ben-Yossef } 4484c3f9727SGilad Ben-Yossef 4494c3f9727SGilad Ben-Yossef /* 4504c3f9727SGilad Ben-Yossef * Set the cipher mode. 4514c3f9727SGilad Ben-Yossef * 4524c3f9727SGilad Ben-Yossef * @pdesc: pointer HW descriptor struct 4534c3f9727SGilad Ben-Yossef * @mode: Any one of the modes defined in [CC7x-DESC] 4544c3f9727SGilad Ben-Yossef */ 45518e732b8SNathan Chancellor static inline void set_cipher_mode(struct cc_hw_desc *pdesc, int mode) 4564c3f9727SGilad Ben-Yossef { 4574c3f9727SGilad Ben-Yossef pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_MODE, mode); 4584c3f9727SGilad Ben-Yossef } 4594c3f9727SGilad Ben-Yossef 4604c3f9727SGilad Ben-Yossef /* 461*18a1dc1fSYael Chemla * Set the cipher mode for hash algorithms. 462*18a1dc1fSYael Chemla * 463*18a1dc1fSYael Chemla * @pdesc: pointer HW descriptor struct 464*18a1dc1fSYael Chemla * @cipher_mode: Any one of the modes defined in [CC7x-DESC] 465*18a1dc1fSYael Chemla * @hash_mode: specifies which hash is being handled 466*18a1dc1fSYael Chemla */ 467*18a1dc1fSYael Chemla static inline void set_hash_cipher_mode(struct cc_hw_desc *pdesc, 468*18a1dc1fSYael Chemla enum drv_cipher_mode cipher_mode, 469*18a1dc1fSYael Chemla enum drv_hash_mode hash_mode) 470*18a1dc1fSYael Chemla { 471*18a1dc1fSYael Chemla set_cipher_mode(pdesc, cipher_mode); 472*18a1dc1fSYael Chemla } 473*18a1dc1fSYael Chemla 474*18a1dc1fSYael Chemla /* 4754c3f9727SGilad Ben-Yossef * Set the cipher configuration fields. 4764c3f9727SGilad Ben-Yossef * 4774c3f9727SGilad Ben-Yossef * @pdesc: pointer HW descriptor struct 4784c3f9727SGilad Ben-Yossef * @mode: Any one of the modes defined in [CC7x-DESC] 4794c3f9727SGilad Ben-Yossef */ 48018e732b8SNathan Chancellor static inline void set_cipher_config0(struct cc_hw_desc *pdesc, int mode) 4814c3f9727SGilad Ben-Yossef { 4824c3f9727SGilad Ben-Yossef pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_CONF0, mode); 4834c3f9727SGilad Ben-Yossef } 4844c3f9727SGilad Ben-Yossef 4854c3f9727SGilad Ben-Yossef /* 4864c3f9727SGilad Ben-Yossef * Set the cipher configuration fields. 4874c3f9727SGilad Ben-Yossef * 4884c3f9727SGilad Ben-Yossef * @pdesc: pointer HW descriptor struct 4894c3f9727SGilad Ben-Yossef * @config: Any one of the modes defined in [CC7x-DESC] 4904c3f9727SGilad Ben-Yossef */ 4914c3f9727SGilad Ben-Yossef static inline void set_cipher_config1(struct cc_hw_desc *pdesc, 4924c3f9727SGilad Ben-Yossef enum cc_hash_conf_pad config) 4934c3f9727SGilad Ben-Yossef { 4944c3f9727SGilad Ben-Yossef pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_CONF1, config); 4954c3f9727SGilad Ben-Yossef } 4964c3f9727SGilad Ben-Yossef 4974c3f9727SGilad Ben-Yossef /* 4984c3f9727SGilad Ben-Yossef * Set HW key configuration fields. 4994c3f9727SGilad Ben-Yossef * 5004c3f9727SGilad Ben-Yossef * @pdesc: pointer HW descriptor struct 5014c3f9727SGilad Ben-Yossef * @hw_key: The HW key slot asdefined in enum cc_hw_crypto_key 5024c3f9727SGilad Ben-Yossef */ 5034c3f9727SGilad Ben-Yossef static inline void set_hw_crypto_key(struct cc_hw_desc *pdesc, 5044c3f9727SGilad Ben-Yossef enum cc_hw_crypto_key hw_key) 5054c3f9727SGilad Ben-Yossef { 5064c3f9727SGilad Ben-Yossef pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_DO, 5074c3f9727SGilad Ben-Yossef (hw_key & HW_KEY_MASK_CIPHER_DO)) | 5084c3f9727SGilad Ben-Yossef FIELD_PREP(WORD4_CIPHER_CONF2, 5094c3f9727SGilad Ben-Yossef (hw_key >> HW_KEY_SHIFT_CIPHER_CFG2)); 5104c3f9727SGilad Ben-Yossef } 5114c3f9727SGilad Ben-Yossef 5124c3f9727SGilad Ben-Yossef /* 5134c3f9727SGilad Ben-Yossef * Set byte order of all setup-finalize descriptors. 5144c3f9727SGilad Ben-Yossef * 5154c3f9727SGilad Ben-Yossef * @pdesc: pointer HW descriptor struct 5164c3f9727SGilad Ben-Yossef * @config: Any one of the modes defined in [CC7x-DESC] 5174c3f9727SGilad Ben-Yossef */ 5184c3f9727SGilad Ben-Yossef static inline void set_bytes_swap(struct cc_hw_desc *pdesc, bool config) 5194c3f9727SGilad Ben-Yossef { 5204c3f9727SGilad Ben-Yossef pdesc->word[4] |= FIELD_PREP(WORD4_BYTES_SWAP, config); 5214c3f9727SGilad Ben-Yossef } 5224c3f9727SGilad Ben-Yossef 5234c3f9727SGilad Ben-Yossef /* 5244c3f9727SGilad Ben-Yossef * Set CMAC_SIZE0 mode. 5254c3f9727SGilad Ben-Yossef * 5264c3f9727SGilad Ben-Yossef * @pdesc: pointer HW descriptor struct 5274c3f9727SGilad Ben-Yossef */ 5284c3f9727SGilad Ben-Yossef static inline void set_cmac_size0_mode(struct cc_hw_desc *pdesc) 5294c3f9727SGilad Ben-Yossef { 5304c3f9727SGilad Ben-Yossef pdesc->word[4] |= FIELD_PREP(WORD4_CMAC_SIZE0, 1); 5314c3f9727SGilad Ben-Yossef } 5324c3f9727SGilad Ben-Yossef 5334c3f9727SGilad Ben-Yossef /* 5344c3f9727SGilad Ben-Yossef * Set key size descriptor field. 5354c3f9727SGilad Ben-Yossef * 5364c3f9727SGilad Ben-Yossef * @pdesc: pointer HW descriptor struct 5374c3f9727SGilad Ben-Yossef * @size: key size in bytes (NOT size code) 5384c3f9727SGilad Ben-Yossef */ 5394c3f9727SGilad Ben-Yossef static inline void set_key_size(struct cc_hw_desc *pdesc, u32 size) 5404c3f9727SGilad Ben-Yossef { 5414c3f9727SGilad Ben-Yossef pdesc->word[4] |= FIELD_PREP(WORD4_KEY_SIZE, size); 5424c3f9727SGilad Ben-Yossef } 5434c3f9727SGilad Ben-Yossef 5444c3f9727SGilad Ben-Yossef /* 5454c3f9727SGilad Ben-Yossef * Set AES key size. 5464c3f9727SGilad Ben-Yossef * 5474c3f9727SGilad Ben-Yossef * @pdesc: pointer HW descriptor struct 5484c3f9727SGilad Ben-Yossef * @size: key size in bytes (NOT size code) 5494c3f9727SGilad Ben-Yossef */ 5504c3f9727SGilad Ben-Yossef static inline void set_key_size_aes(struct cc_hw_desc *pdesc, u32 size) 5514c3f9727SGilad Ben-Yossef { 5524c3f9727SGilad Ben-Yossef set_key_size(pdesc, ((size >> 3) - 2)); 5534c3f9727SGilad Ben-Yossef } 5544c3f9727SGilad Ben-Yossef 5554c3f9727SGilad Ben-Yossef /* 5564c3f9727SGilad Ben-Yossef * Set DES key size. 5574c3f9727SGilad Ben-Yossef * 5584c3f9727SGilad Ben-Yossef * @pdesc: pointer HW descriptor struct 5594c3f9727SGilad Ben-Yossef * @size: key size in bytes (NOT size code) 5604c3f9727SGilad Ben-Yossef */ 5614c3f9727SGilad Ben-Yossef static inline void set_key_size_des(struct cc_hw_desc *pdesc, u32 size) 5624c3f9727SGilad Ben-Yossef { 5634c3f9727SGilad Ben-Yossef set_key_size(pdesc, ((size >> 3) - 1)); 5644c3f9727SGilad Ben-Yossef } 5654c3f9727SGilad Ben-Yossef 5664c3f9727SGilad Ben-Yossef /* 5674c3f9727SGilad Ben-Yossef * Set the descriptor setup mode 5684c3f9727SGilad Ben-Yossef * 5694c3f9727SGilad Ben-Yossef * @pdesc: pointer HW descriptor struct 5704c3f9727SGilad Ben-Yossef * @mode: Any one of the setup modes defined in [CC7x-DESC] 5714c3f9727SGilad Ben-Yossef */ 5724c3f9727SGilad Ben-Yossef static inline void set_setup_mode(struct cc_hw_desc *pdesc, 5734c3f9727SGilad Ben-Yossef enum cc_setup_op mode) 5744c3f9727SGilad Ben-Yossef { 5754c3f9727SGilad Ben-Yossef pdesc->word[4] |= FIELD_PREP(WORD4_SETUP_OPERATION, mode); 5764c3f9727SGilad Ben-Yossef } 5774c3f9727SGilad Ben-Yossef 5784c3f9727SGilad Ben-Yossef /* 5794c3f9727SGilad Ben-Yossef * Set the descriptor cipher DO 5804c3f9727SGilad Ben-Yossef * 5814c3f9727SGilad Ben-Yossef * @pdesc: pointer HW descriptor struct 5824c3f9727SGilad Ben-Yossef * @config: Any one of the cipher do defined in [CC7x-DESC] 5834c3f9727SGilad Ben-Yossef */ 5844c3f9727SGilad Ben-Yossef static inline void set_cipher_do(struct cc_hw_desc *pdesc, 5854c3f9727SGilad Ben-Yossef enum cc_hash_cipher_pad config) 5864c3f9727SGilad Ben-Yossef { 5874c3f9727SGilad Ben-Yossef pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_DO, 5884c3f9727SGilad Ben-Yossef (config & HW_KEY_MASK_CIPHER_DO)); 5894c3f9727SGilad Ben-Yossef } 5904c3f9727SGilad Ben-Yossef 5914c3f9727SGilad Ben-Yossef #endif /*__CC_HW_QUEUE_DEFS_H__*/ 592