1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2019 HiSilicon Limited. */ 3 4 #include <linux/acpi.h> 5 #include <linux/bitops.h> 6 #include <linux/debugfs.h> 7 #include <linux/init.h> 8 #include <linux/io.h> 9 #include <linux/iommu.h> 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/pci.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/seq_file.h> 15 #include <linux/topology.h> 16 #include <linux/uacce.h> 17 18 #include "sec.h" 19 20 #define SEC_VF_NUM 63 21 #define SEC_QUEUE_NUM_V1 4096 22 #define PCI_DEVICE_ID_HUAWEI_SEC_PF 0xa255 23 24 #define SEC_BD_ERR_CHK_EN0 0xEFFFFFFF 25 #define SEC_BD_ERR_CHK_EN1 0x7ffff7fd 26 #define SEC_BD_ERR_CHK_EN3 0xffffbfff 27 28 #define SEC_SQE_SIZE 128 29 #define SEC_PF_DEF_Q_NUM 256 30 #define SEC_PF_DEF_Q_BASE 0 31 #define SEC_CTX_Q_NUM_DEF 2 32 #define SEC_CTX_Q_NUM_MAX 32 33 34 #define SEC_CTRL_CNT_CLR_CE 0x301120 35 #define SEC_CTRL_CNT_CLR_CE_BIT BIT(0) 36 #define SEC_CORE_INT_SOURCE 0x301010 37 #define SEC_CORE_INT_MASK 0x301000 38 #define SEC_CORE_INT_STATUS 0x301008 39 #define SEC_CORE_SRAM_ECC_ERR_INFO 0x301C14 40 #define SEC_ECC_NUM 16 41 #define SEC_ECC_MASH 0xFF 42 #define SEC_CORE_INT_DISABLE 0x0 43 44 #define SEC_RAS_CE_REG 0x301050 45 #define SEC_RAS_FE_REG 0x301054 46 #define SEC_RAS_NFE_REG 0x301058 47 #define SEC_RAS_FE_ENB_MSK 0x0 48 #define SEC_OOO_SHUTDOWN_SEL 0x301014 49 #define SEC_RAS_DISABLE 0x0 50 #define SEC_MEM_START_INIT_REG 0x301100 51 #define SEC_MEM_INIT_DONE_REG 0x301104 52 53 /* clock gating */ 54 #define SEC_CONTROL_REG 0x301200 55 #define SEC_DYNAMIC_GATE_REG 0x30121c 56 #define SEC_CORE_AUTO_GATE 0x30212c 57 #define SEC_DYNAMIC_GATE_EN 0x7fff 58 #define SEC_CORE_AUTO_GATE_EN GENMASK(3, 0) 59 #define SEC_CLK_GATE_ENABLE BIT(3) 60 #define SEC_CLK_GATE_DISABLE (~BIT(3)) 61 62 #define SEC_TRNG_EN_SHIFT 8 63 #define SEC_AXI_SHUTDOWN_ENABLE BIT(12) 64 #define SEC_AXI_SHUTDOWN_DISABLE 0xFFFFEFFF 65 66 #define SEC_INTERFACE_USER_CTRL0_REG 0x301220 67 #define SEC_INTERFACE_USER_CTRL1_REG 0x301224 68 #define SEC_SAA_EN_REG 0x301270 69 #define SEC_BD_ERR_CHK_EN_REG0 0x301380 70 #define SEC_BD_ERR_CHK_EN_REG1 0x301384 71 #define SEC_BD_ERR_CHK_EN_REG3 0x30138c 72 73 #define SEC_USER0_SMMU_NORMAL (BIT(23) | BIT(15)) 74 #define SEC_USER1_SMMU_NORMAL (BIT(31) | BIT(23) | BIT(15) | BIT(7)) 75 #define SEC_USER1_ENABLE_CONTEXT_SSV BIT(24) 76 #define SEC_USER1_ENABLE_DATA_SSV BIT(16) 77 #define SEC_USER1_WB_CONTEXT_SSV BIT(8) 78 #define SEC_USER1_WB_DATA_SSV BIT(0) 79 #define SEC_USER1_SVA_SET (SEC_USER1_ENABLE_CONTEXT_SSV | \ 80 SEC_USER1_ENABLE_DATA_SSV | \ 81 SEC_USER1_WB_CONTEXT_SSV | \ 82 SEC_USER1_WB_DATA_SSV) 83 #define SEC_USER1_SMMU_SVA (SEC_USER1_SMMU_NORMAL | SEC_USER1_SVA_SET) 84 #define SEC_USER1_SMMU_MASK (~SEC_USER1_SVA_SET) 85 #define SEC_INTERFACE_USER_CTRL0_REG_V3 0x302220 86 #define SEC_INTERFACE_USER_CTRL1_REG_V3 0x302224 87 #define SEC_USER1_SMMU_NORMAL_V3 (BIT(23) | BIT(17) | BIT(11) | BIT(5)) 88 #define SEC_USER1_SMMU_MASK_V3 0xFF79E79E 89 #define SEC_CORE_INT_STATUS_M_ECC BIT(2) 90 91 #define SEC_PREFETCH_CFG 0x301130 92 #define SEC_SVA_TRANS 0x301EC4 93 #define SEC_PREFETCH_ENABLE (~(BIT(0) | BIT(1) | BIT(11))) 94 #define SEC_PREFETCH_DISABLE BIT(1) 95 #define SEC_SVA_DISABLE_READY (BIT(7) | BIT(11)) 96 97 #define SEC_DELAY_10_US 10 98 #define SEC_POLL_TIMEOUT_US 1000 99 #define SEC_DBGFS_VAL_MAX_LEN 20 100 #define SEC_SINGLE_PORT_MAX_TRANS 0x2060 101 102 #define SEC_SQE_MASK_OFFSET 64 103 #define SEC_SQE_MASK_LEN 48 104 #define SEC_SHAPER_TYPE_RATE 400 105 106 #define SEC_DFX_BASE 0x301000 107 #define SEC_DFX_CORE 0x302100 108 #define SEC_DFX_COMMON1 0x301600 109 #define SEC_DFX_COMMON2 0x301C00 110 #define SEC_DFX_BASE_LEN 0x9D 111 #define SEC_DFX_CORE_LEN 0x32B 112 #define SEC_DFX_COMMON1_LEN 0x45 113 #define SEC_DFX_COMMON2_LEN 0xBA 114 115 #define SEC_ALG_BITMAP_SHIFT 32 116 117 #define SEC_CIPHER_BITMAP (GENMASK_ULL(5, 0) | GENMASK_ULL(16, 12) | \ 118 GENMASK(24, 21)) 119 #define SEC_DIGEST_BITMAP (GENMASK_ULL(11, 8) | GENMASK_ULL(20, 19) | \ 120 GENMASK_ULL(42, 25)) 121 #define SEC_AEAD_BITMAP (GENMASK_ULL(7, 6) | GENMASK_ULL(18, 17) | \ 122 GENMASK_ULL(45, 43)) 123 124 struct sec_hw_error { 125 u32 int_msk; 126 const char *msg; 127 }; 128 129 struct sec_dfx_item { 130 const char *name; 131 u32 offset; 132 }; 133 134 static const char sec_name[] = "hisi_sec2"; 135 static struct dentry *sec_debugfs_root; 136 137 static struct hisi_qm_list sec_devices = { 138 .register_to_crypto = sec_register_to_crypto, 139 .unregister_from_crypto = sec_unregister_from_crypto, 140 }; 141 142 static const struct hisi_qm_cap_info sec_basic_info[] = { 143 {SEC_QM_NFE_MASK_CAP, 0x3124, 0, GENMASK(31, 0), 0x0, 0x1C77, 0x7C77}, 144 {SEC_QM_RESET_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0xC77, 0x6C77}, 145 {SEC_QM_OOO_SHUTDOWN_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0x4, 0x6C77}, 146 {SEC_QM_CE_MASK_CAP, 0x312C, 0, GENMASK(31, 0), 0x0, 0x8, 0x8}, 147 {SEC_NFE_MASK_CAP, 0x3130, 0, GENMASK(31, 0), 0x0, 0x177, 0x60177}, 148 {SEC_RESET_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x177, 0x177}, 149 {SEC_OOO_SHUTDOWN_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x4, 0x177}, 150 {SEC_CE_MASK_CAP, 0x3138, 0, GENMASK(31, 0), 0x0, 0x88, 0xC088}, 151 {SEC_CLUSTER_NUM_CAP, 0x313c, 20, GENMASK(3, 0), 0x1, 0x1, 0x1}, 152 {SEC_CORE_TYPE_NUM_CAP, 0x313c, 16, GENMASK(3, 0), 0x1, 0x1, 0x1}, 153 {SEC_CORE_NUM_CAP, 0x313c, 8, GENMASK(7, 0), 0x4, 0x4, 0x4}, 154 {SEC_CORES_PER_CLUSTER_NUM_CAP, 0x313c, 0, GENMASK(7, 0), 0x4, 0x4, 0x4}, 155 {SEC_CORE_ENABLE_BITMAP, 0x3140, 32, GENMASK(31, 0), 0x17F, 0x17F, 0xF}, 156 {SEC_DRV_ALG_BITMAP_LOW, 0x3144, 0, GENMASK(31, 0), 0x18050CB, 0x18050CB, 0x18670CF}, 157 {SEC_DRV_ALG_BITMAP_HIGH, 0x3148, 0, GENMASK(31, 0), 0x395C, 0x395C, 0x395C}, 158 {SEC_DEV_ALG_BITMAP_LOW, 0x314c, 0, GENMASK(31, 0), 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}, 159 {SEC_DEV_ALG_BITMAP_HIGH, 0x3150, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF}, 160 {SEC_CORE1_ALG_BITMAP_LOW, 0x3154, 0, GENMASK(31, 0), 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}, 161 {SEC_CORE1_ALG_BITMAP_HIGH, 0x3158, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF}, 162 {SEC_CORE2_ALG_BITMAP_LOW, 0x315c, 0, GENMASK(31, 0), 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}, 163 {SEC_CORE2_ALG_BITMAP_HIGH, 0x3160, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF}, 164 {SEC_CORE3_ALG_BITMAP_LOW, 0x3164, 0, GENMASK(31, 0), 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}, 165 {SEC_CORE3_ALG_BITMAP_HIGH, 0x3168, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF}, 166 {SEC_CORE4_ALG_BITMAP_LOW, 0x316c, 0, GENMASK(31, 0), 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}, 167 {SEC_CORE4_ALG_BITMAP_HIGH, 0x3170, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF}, 168 }; 169 170 static const u32 sec_pre_store_caps[] = { 171 SEC_DRV_ALG_BITMAP_LOW, 172 SEC_DRV_ALG_BITMAP_HIGH, 173 SEC_DEV_ALG_BITMAP_LOW, 174 SEC_DEV_ALG_BITMAP_HIGH, 175 }; 176 177 static const struct qm_dev_alg sec_dev_algs[] = { { 178 .alg_msk = SEC_CIPHER_BITMAP, 179 .alg = "cipher\n", 180 }, { 181 .alg_msk = SEC_DIGEST_BITMAP, 182 .alg = "digest\n", 183 }, { 184 .alg_msk = SEC_AEAD_BITMAP, 185 .alg = "aead\n", 186 }, 187 }; 188 189 static const struct sec_hw_error sec_hw_errors[] = { 190 { 191 .int_msk = BIT(0), 192 .msg = "sec_axi_rresp_err_rint" 193 }, 194 { 195 .int_msk = BIT(1), 196 .msg = "sec_axi_bresp_err_rint" 197 }, 198 { 199 .int_msk = BIT(2), 200 .msg = "sec_ecc_2bit_err_rint" 201 }, 202 { 203 .int_msk = BIT(3), 204 .msg = "sec_ecc_1bit_err_rint" 205 }, 206 { 207 .int_msk = BIT(4), 208 .msg = "sec_req_trng_timeout_rint" 209 }, 210 { 211 .int_msk = BIT(5), 212 .msg = "sec_fsm_hbeat_rint" 213 }, 214 { 215 .int_msk = BIT(6), 216 .msg = "sec_channel_req_rng_timeout_rint" 217 }, 218 { 219 .int_msk = BIT(7), 220 .msg = "sec_bd_err_rint" 221 }, 222 { 223 .int_msk = BIT(8), 224 .msg = "sec_chain_buff_err_rint" 225 }, 226 { 227 .int_msk = BIT(14), 228 .msg = "sec_no_secure_access" 229 }, 230 { 231 .int_msk = BIT(15), 232 .msg = "sec_wrapping_key_auth_err" 233 }, 234 { 235 .int_msk = BIT(16), 236 .msg = "sec_km_key_crc_fail" 237 }, 238 { 239 .int_msk = BIT(17), 240 .msg = "sec_axi_poison_err" 241 }, 242 { 243 .int_msk = BIT(18), 244 .msg = "sec_sva_err" 245 }, 246 {} 247 }; 248 249 static const char * const sec_dbg_file_name[] = { 250 [SEC_CLEAR_ENABLE] = "clear_enable", 251 }; 252 253 static struct sec_dfx_item sec_dfx_labels[] = { 254 {"send_cnt", offsetof(struct sec_dfx, send_cnt)}, 255 {"recv_cnt", offsetof(struct sec_dfx, recv_cnt)}, 256 {"send_busy_cnt", offsetof(struct sec_dfx, send_busy_cnt)}, 257 {"recv_busy_cnt", offsetof(struct sec_dfx, recv_busy_cnt)}, 258 {"err_bd_cnt", offsetof(struct sec_dfx, err_bd_cnt)}, 259 {"invalid_req_cnt", offsetof(struct sec_dfx, invalid_req_cnt)}, 260 {"done_flag_cnt", offsetof(struct sec_dfx, done_flag_cnt)}, 261 }; 262 263 static const struct debugfs_reg32 sec_dfx_regs[] = { 264 {"SEC_PF_ABNORMAL_INT_SOURCE ", 0x301010}, 265 {"SEC_SAA_EN ", 0x301270}, 266 {"SEC_BD_LATENCY_MIN ", 0x301600}, 267 {"SEC_BD_LATENCY_MAX ", 0x301608}, 268 {"SEC_BD_LATENCY_AVG ", 0x30160C}, 269 {"SEC_BD_NUM_IN_SAA0 ", 0x301670}, 270 {"SEC_BD_NUM_IN_SAA1 ", 0x301674}, 271 {"SEC_BD_NUM_IN_SEC ", 0x301680}, 272 {"SEC_ECC_1BIT_CNT ", 0x301C00}, 273 {"SEC_ECC_1BIT_INFO ", 0x301C04}, 274 {"SEC_ECC_2BIT_CNT ", 0x301C10}, 275 {"SEC_ECC_2BIT_INFO ", 0x301C14}, 276 {"SEC_BD_SAA0 ", 0x301C20}, 277 {"SEC_BD_SAA1 ", 0x301C24}, 278 {"SEC_BD_SAA2 ", 0x301C28}, 279 {"SEC_BD_SAA3 ", 0x301C2C}, 280 {"SEC_BD_SAA4 ", 0x301C30}, 281 {"SEC_BD_SAA5 ", 0x301C34}, 282 {"SEC_BD_SAA6 ", 0x301C38}, 283 {"SEC_BD_SAA7 ", 0x301C3C}, 284 {"SEC_BD_SAA8 ", 0x301C40}, 285 }; 286 287 /* define the SEC's dfx regs region and region length */ 288 static struct dfx_diff_registers sec_diff_regs[] = { 289 { 290 .reg_offset = SEC_DFX_BASE, 291 .reg_len = SEC_DFX_BASE_LEN, 292 }, { 293 .reg_offset = SEC_DFX_COMMON1, 294 .reg_len = SEC_DFX_COMMON1_LEN, 295 }, { 296 .reg_offset = SEC_DFX_COMMON2, 297 .reg_len = SEC_DFX_COMMON2_LEN, 298 }, { 299 .reg_offset = SEC_DFX_CORE, 300 .reg_len = SEC_DFX_CORE_LEN, 301 }, 302 }; 303 304 static int sec_diff_regs_show(struct seq_file *s, void *unused) 305 { 306 struct hisi_qm *qm = s->private; 307 308 hisi_qm_acc_diff_regs_dump(qm, s, qm->debug.acc_diff_regs, 309 ARRAY_SIZE(sec_diff_regs)); 310 311 return 0; 312 } 313 DEFINE_SHOW_ATTRIBUTE(sec_diff_regs); 314 315 static bool pf_q_num_flag; 316 static int sec_pf_q_num_set(const char *val, const struct kernel_param *kp) 317 { 318 pf_q_num_flag = true; 319 320 return q_num_set(val, kp, PCI_DEVICE_ID_HUAWEI_SEC_PF); 321 } 322 323 static const struct kernel_param_ops sec_pf_q_num_ops = { 324 .set = sec_pf_q_num_set, 325 .get = param_get_int, 326 }; 327 328 static u32 pf_q_num = SEC_PF_DEF_Q_NUM; 329 module_param_cb(pf_q_num, &sec_pf_q_num_ops, &pf_q_num, 0444); 330 MODULE_PARM_DESC(pf_q_num, "Number of queues in PF(v1 2-4096, v2 2-1024)"); 331 332 static int sec_ctx_q_num_set(const char *val, const struct kernel_param *kp) 333 { 334 u32 ctx_q_num; 335 int ret; 336 337 if (!val) 338 return -EINVAL; 339 340 ret = kstrtou32(val, 10, &ctx_q_num); 341 if (ret) 342 return -EINVAL; 343 344 if (!ctx_q_num || ctx_q_num > SEC_CTX_Q_NUM_MAX || ctx_q_num & 0x1) { 345 pr_err("ctx queue num[%u] is invalid!\n", ctx_q_num); 346 return -EINVAL; 347 } 348 349 return param_set_int(val, kp); 350 } 351 352 static const struct kernel_param_ops sec_ctx_q_num_ops = { 353 .set = sec_ctx_q_num_set, 354 .get = param_get_int, 355 }; 356 static u32 ctx_q_num = SEC_CTX_Q_NUM_DEF; 357 module_param_cb(ctx_q_num, &sec_ctx_q_num_ops, &ctx_q_num, 0444); 358 MODULE_PARM_DESC(ctx_q_num, "Queue num in ctx (2 default, 2, 4, ..., 32)"); 359 360 static const struct kernel_param_ops vfs_num_ops = { 361 .set = vfs_num_set, 362 .get = param_get_int, 363 }; 364 365 static u32 vfs_num; 366 module_param_cb(vfs_num, &vfs_num_ops, &vfs_num, 0444); 367 MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63), 0(default)"); 368 369 void sec_destroy_qps(struct hisi_qp **qps, int qp_num) 370 { 371 hisi_qm_free_qps(qps, qp_num); 372 kfree(qps); 373 } 374 375 struct hisi_qp **sec_create_qps(void) 376 { 377 int node = cpu_to_node(smp_processor_id()); 378 u32 ctx_num = ctx_q_num; 379 struct hisi_qp **qps; 380 int ret; 381 382 qps = kcalloc(ctx_num, sizeof(struct hisi_qp *), GFP_KERNEL); 383 if (!qps) 384 return NULL; 385 386 ret = hisi_qm_alloc_qps_node(&sec_devices, ctx_num, 0, node, qps); 387 if (!ret) 388 return qps; 389 390 kfree(qps); 391 return NULL; 392 } 393 394 u64 sec_get_alg_bitmap(struct hisi_qm *qm, u32 high, u32 low) 395 { 396 u32 cap_val_h, cap_val_l; 397 398 cap_val_h = qm->cap_tables.dev_cap_table[high].cap_val; 399 cap_val_l = qm->cap_tables.dev_cap_table[low].cap_val; 400 401 return ((u64)cap_val_h << SEC_ALG_BITMAP_SHIFT) | (u64)cap_val_l; 402 } 403 404 static const struct kernel_param_ops sec_uacce_mode_ops = { 405 .set = uacce_mode_set, 406 .get = param_get_int, 407 }; 408 409 /* 410 * uacce_mode = 0 means sec only register to crypto, 411 * uacce_mode = 1 means sec both register to crypto and uacce. 412 */ 413 static u32 uacce_mode = UACCE_MODE_NOUACCE; 414 module_param_cb(uacce_mode, &sec_uacce_mode_ops, &uacce_mode, 0444); 415 MODULE_PARM_DESC(uacce_mode, UACCE_MODE_DESC); 416 417 static const struct pci_device_id sec_dev_ids[] = { 418 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_SEC_PF) }, 419 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_SEC_VF) }, 420 { 0, } 421 }; 422 MODULE_DEVICE_TABLE(pci, sec_dev_ids); 423 424 static void sec_set_endian(struct hisi_qm *qm) 425 { 426 u32 reg; 427 428 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG); 429 reg &= ~(BIT(1) | BIT(0)); 430 if (!IS_ENABLED(CONFIG_64BIT)) 431 reg |= BIT(1); 432 433 if (!IS_ENABLED(CONFIG_CPU_LITTLE_ENDIAN)) 434 reg |= BIT(0); 435 436 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG); 437 } 438 439 static void sec_engine_sva_config(struct hisi_qm *qm) 440 { 441 u32 reg; 442 443 if (qm->ver > QM_HW_V2) { 444 reg = readl_relaxed(qm->io_base + 445 SEC_INTERFACE_USER_CTRL0_REG_V3); 446 reg |= SEC_USER0_SMMU_NORMAL; 447 writel_relaxed(reg, qm->io_base + 448 SEC_INTERFACE_USER_CTRL0_REG_V3); 449 450 reg = readl_relaxed(qm->io_base + 451 SEC_INTERFACE_USER_CTRL1_REG_V3); 452 reg &= SEC_USER1_SMMU_MASK_V3; 453 reg |= SEC_USER1_SMMU_NORMAL_V3; 454 writel_relaxed(reg, qm->io_base + 455 SEC_INTERFACE_USER_CTRL1_REG_V3); 456 } else { 457 reg = readl_relaxed(qm->io_base + 458 SEC_INTERFACE_USER_CTRL0_REG); 459 reg |= SEC_USER0_SMMU_NORMAL; 460 writel_relaxed(reg, qm->io_base + 461 SEC_INTERFACE_USER_CTRL0_REG); 462 reg = readl_relaxed(qm->io_base + 463 SEC_INTERFACE_USER_CTRL1_REG); 464 reg &= SEC_USER1_SMMU_MASK; 465 if (qm->use_sva) 466 reg |= SEC_USER1_SMMU_SVA; 467 else 468 reg |= SEC_USER1_SMMU_NORMAL; 469 writel_relaxed(reg, qm->io_base + 470 SEC_INTERFACE_USER_CTRL1_REG); 471 } 472 } 473 474 static void sec_open_sva_prefetch(struct hisi_qm *qm) 475 { 476 u32 val; 477 int ret; 478 479 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps)) 480 return; 481 482 /* Enable prefetch */ 483 val = readl_relaxed(qm->io_base + SEC_PREFETCH_CFG); 484 val &= SEC_PREFETCH_ENABLE; 485 writel(val, qm->io_base + SEC_PREFETCH_CFG); 486 487 ret = readl_relaxed_poll_timeout(qm->io_base + SEC_PREFETCH_CFG, 488 val, !(val & SEC_PREFETCH_DISABLE), 489 SEC_DELAY_10_US, SEC_POLL_TIMEOUT_US); 490 if (ret) 491 pci_err(qm->pdev, "failed to open sva prefetch\n"); 492 } 493 494 static void sec_close_sva_prefetch(struct hisi_qm *qm) 495 { 496 u32 val; 497 int ret; 498 499 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps)) 500 return; 501 502 val = readl_relaxed(qm->io_base + SEC_PREFETCH_CFG); 503 val |= SEC_PREFETCH_DISABLE; 504 writel(val, qm->io_base + SEC_PREFETCH_CFG); 505 506 ret = readl_relaxed_poll_timeout(qm->io_base + SEC_SVA_TRANS, 507 val, !(val & SEC_SVA_DISABLE_READY), 508 SEC_DELAY_10_US, SEC_POLL_TIMEOUT_US); 509 if (ret) 510 pci_err(qm->pdev, "failed to close sva prefetch\n"); 511 } 512 513 static void sec_enable_clock_gate(struct hisi_qm *qm) 514 { 515 u32 val; 516 517 if (qm->ver < QM_HW_V3) 518 return; 519 520 val = readl_relaxed(qm->io_base + SEC_CONTROL_REG); 521 val |= SEC_CLK_GATE_ENABLE; 522 writel_relaxed(val, qm->io_base + SEC_CONTROL_REG); 523 524 val = readl(qm->io_base + SEC_DYNAMIC_GATE_REG); 525 val |= SEC_DYNAMIC_GATE_EN; 526 writel(val, qm->io_base + SEC_DYNAMIC_GATE_REG); 527 528 val = readl(qm->io_base + SEC_CORE_AUTO_GATE); 529 val |= SEC_CORE_AUTO_GATE_EN; 530 writel(val, qm->io_base + SEC_CORE_AUTO_GATE); 531 } 532 533 static void sec_disable_clock_gate(struct hisi_qm *qm) 534 { 535 u32 val; 536 537 /* Kunpeng920 needs to close clock gating */ 538 val = readl_relaxed(qm->io_base + SEC_CONTROL_REG); 539 val &= SEC_CLK_GATE_DISABLE; 540 writel_relaxed(val, qm->io_base + SEC_CONTROL_REG); 541 } 542 543 static int sec_engine_init(struct hisi_qm *qm) 544 { 545 int ret; 546 u32 reg; 547 548 /* disable clock gate control before mem init */ 549 sec_disable_clock_gate(qm); 550 551 writel_relaxed(0x1, qm->io_base + SEC_MEM_START_INIT_REG); 552 553 ret = readl_relaxed_poll_timeout(qm->io_base + SEC_MEM_INIT_DONE_REG, 554 reg, reg & 0x1, SEC_DELAY_10_US, 555 SEC_POLL_TIMEOUT_US); 556 if (ret) { 557 pci_err(qm->pdev, "fail to init sec mem\n"); 558 return ret; 559 } 560 561 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG); 562 reg |= (0x1 << SEC_TRNG_EN_SHIFT); 563 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG); 564 565 sec_engine_sva_config(qm); 566 567 writel(SEC_SINGLE_PORT_MAX_TRANS, 568 qm->io_base + AM_CFG_SINGLE_PORT_MAX_TRANS); 569 570 reg = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_CORE_ENABLE_BITMAP, qm->cap_ver); 571 writel(reg, qm->io_base + SEC_SAA_EN_REG); 572 573 if (qm->ver < QM_HW_V3) { 574 /* HW V2 enable sm4 extra mode, as ctr/ecb */ 575 writel_relaxed(SEC_BD_ERR_CHK_EN0, 576 qm->io_base + SEC_BD_ERR_CHK_EN_REG0); 577 578 /* HW V2 enable sm4 xts mode multiple iv */ 579 writel_relaxed(SEC_BD_ERR_CHK_EN1, 580 qm->io_base + SEC_BD_ERR_CHK_EN_REG1); 581 writel_relaxed(SEC_BD_ERR_CHK_EN3, 582 qm->io_base + SEC_BD_ERR_CHK_EN_REG3); 583 } 584 585 /* config endian */ 586 sec_set_endian(qm); 587 588 sec_enable_clock_gate(qm); 589 590 return 0; 591 } 592 593 static int sec_set_user_domain_and_cache(struct hisi_qm *qm) 594 { 595 /* qm user domain */ 596 writel(AXUSER_BASE, qm->io_base + QM_ARUSER_M_CFG_1); 597 writel(ARUSER_M_CFG_ENABLE, qm->io_base + QM_ARUSER_M_CFG_ENABLE); 598 writel(AXUSER_BASE, qm->io_base + QM_AWUSER_M_CFG_1); 599 writel(AWUSER_M_CFG_ENABLE, qm->io_base + QM_AWUSER_M_CFG_ENABLE); 600 writel(WUSER_M_CFG_ENABLE, qm->io_base + QM_WUSER_M_CFG_ENABLE); 601 602 /* qm cache */ 603 writel(AXI_M_CFG, qm->io_base + QM_AXI_M_CFG); 604 writel(AXI_M_CFG_ENABLE, qm->io_base + QM_AXI_M_CFG_ENABLE); 605 606 /* disable FLR triggered by BME(bus master enable) */ 607 writel(PEH_AXUSER_CFG, qm->io_base + QM_PEH_AXUSER_CFG); 608 writel(PEH_AXUSER_CFG_ENABLE, qm->io_base + QM_PEH_AXUSER_CFG_ENABLE); 609 610 /* enable sqc,cqc writeback */ 611 writel(SQC_CACHE_ENABLE | CQC_CACHE_ENABLE | SQC_CACHE_WB_ENABLE | 612 CQC_CACHE_WB_ENABLE | FIELD_PREP(SQC_CACHE_WB_THRD, 1) | 613 FIELD_PREP(CQC_CACHE_WB_THRD, 1), qm->io_base + QM_CACHE_CTL); 614 615 return sec_engine_init(qm); 616 } 617 618 /* sec_debug_regs_clear() - clear the sec debug regs */ 619 static void sec_debug_regs_clear(struct hisi_qm *qm) 620 { 621 int i; 622 623 /* clear sec dfx regs */ 624 writel(0x1, qm->io_base + SEC_CTRL_CNT_CLR_CE); 625 for (i = 0; i < ARRAY_SIZE(sec_dfx_regs); i++) 626 readl(qm->io_base + sec_dfx_regs[i].offset); 627 628 /* clear rdclr_en */ 629 writel(0x0, qm->io_base + SEC_CTRL_CNT_CLR_CE); 630 631 hisi_qm_debug_regs_clear(qm); 632 } 633 634 static void sec_master_ooo_ctrl(struct hisi_qm *qm, bool enable) 635 { 636 u32 val1, val2; 637 638 val1 = readl(qm->io_base + SEC_CONTROL_REG); 639 if (enable) { 640 val1 |= SEC_AXI_SHUTDOWN_ENABLE; 641 val2 = hisi_qm_get_hw_info(qm, sec_basic_info, 642 SEC_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 643 } else { 644 val1 &= SEC_AXI_SHUTDOWN_DISABLE; 645 val2 = 0x0; 646 } 647 648 if (qm->ver > QM_HW_V2) 649 writel(val2, qm->io_base + SEC_OOO_SHUTDOWN_SEL); 650 651 writel(val1, qm->io_base + SEC_CONTROL_REG); 652 } 653 654 static void sec_hw_error_enable(struct hisi_qm *qm) 655 { 656 u32 ce, nfe; 657 658 if (qm->ver == QM_HW_V1) { 659 writel(SEC_CORE_INT_DISABLE, qm->io_base + SEC_CORE_INT_MASK); 660 pci_info(qm->pdev, "V1 not support hw error handle\n"); 661 return; 662 } 663 664 ce = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_CE_MASK_CAP, qm->cap_ver); 665 nfe = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_NFE_MASK_CAP, qm->cap_ver); 666 667 /* clear SEC hw error source if having */ 668 writel(ce | nfe | SEC_RAS_FE_ENB_MSK, qm->io_base + SEC_CORE_INT_SOURCE); 669 670 /* enable RAS int */ 671 writel(ce, qm->io_base + SEC_RAS_CE_REG); 672 writel(SEC_RAS_FE_ENB_MSK, qm->io_base + SEC_RAS_FE_REG); 673 writel(nfe, qm->io_base + SEC_RAS_NFE_REG); 674 675 /* enable SEC block master OOO when nfe occurs on Kunpeng930 */ 676 sec_master_ooo_ctrl(qm, true); 677 678 /* enable SEC hw error interrupts */ 679 writel(ce | nfe | SEC_RAS_FE_ENB_MSK, qm->io_base + SEC_CORE_INT_MASK); 680 } 681 682 static void sec_hw_error_disable(struct hisi_qm *qm) 683 { 684 /* disable SEC hw error interrupts */ 685 writel(SEC_CORE_INT_DISABLE, qm->io_base + SEC_CORE_INT_MASK); 686 687 /* disable SEC block master OOO when nfe occurs on Kunpeng930 */ 688 sec_master_ooo_ctrl(qm, false); 689 690 /* disable RAS int */ 691 writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_CE_REG); 692 writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_FE_REG); 693 writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_NFE_REG); 694 } 695 696 static u32 sec_clear_enable_read(struct hisi_qm *qm) 697 { 698 return readl(qm->io_base + SEC_CTRL_CNT_CLR_CE) & 699 SEC_CTRL_CNT_CLR_CE_BIT; 700 } 701 702 static int sec_clear_enable_write(struct hisi_qm *qm, u32 val) 703 { 704 u32 tmp; 705 706 if (val != 1 && val) 707 return -EINVAL; 708 709 tmp = (readl(qm->io_base + SEC_CTRL_CNT_CLR_CE) & 710 ~SEC_CTRL_CNT_CLR_CE_BIT) | val; 711 writel(tmp, qm->io_base + SEC_CTRL_CNT_CLR_CE); 712 713 return 0; 714 } 715 716 static ssize_t sec_debug_read(struct file *filp, char __user *buf, 717 size_t count, loff_t *pos) 718 { 719 struct sec_debug_file *file = filp->private_data; 720 char tbuf[SEC_DBGFS_VAL_MAX_LEN]; 721 struct hisi_qm *qm = file->qm; 722 u32 val; 723 int ret; 724 725 ret = hisi_qm_get_dfx_access(qm); 726 if (ret) 727 return ret; 728 729 spin_lock_irq(&file->lock); 730 731 switch (file->index) { 732 case SEC_CLEAR_ENABLE: 733 val = sec_clear_enable_read(qm); 734 break; 735 default: 736 goto err_input; 737 } 738 739 spin_unlock_irq(&file->lock); 740 741 hisi_qm_put_dfx_access(qm); 742 ret = snprintf(tbuf, SEC_DBGFS_VAL_MAX_LEN, "%u\n", val); 743 return simple_read_from_buffer(buf, count, pos, tbuf, ret); 744 745 err_input: 746 spin_unlock_irq(&file->lock); 747 hisi_qm_put_dfx_access(qm); 748 return -EINVAL; 749 } 750 751 static ssize_t sec_debug_write(struct file *filp, const char __user *buf, 752 size_t count, loff_t *pos) 753 { 754 struct sec_debug_file *file = filp->private_data; 755 char tbuf[SEC_DBGFS_VAL_MAX_LEN]; 756 struct hisi_qm *qm = file->qm; 757 unsigned long val; 758 int len, ret; 759 760 if (*pos != 0) 761 return 0; 762 763 if (count >= SEC_DBGFS_VAL_MAX_LEN) 764 return -ENOSPC; 765 766 len = simple_write_to_buffer(tbuf, SEC_DBGFS_VAL_MAX_LEN - 1, 767 pos, buf, count); 768 if (len < 0) 769 return len; 770 771 tbuf[len] = '\0'; 772 if (kstrtoul(tbuf, 0, &val)) 773 return -EFAULT; 774 775 ret = hisi_qm_get_dfx_access(qm); 776 if (ret) 777 return ret; 778 779 spin_lock_irq(&file->lock); 780 781 switch (file->index) { 782 case SEC_CLEAR_ENABLE: 783 ret = sec_clear_enable_write(qm, val); 784 if (ret) 785 goto err_input; 786 break; 787 default: 788 ret = -EINVAL; 789 goto err_input; 790 } 791 792 ret = count; 793 794 err_input: 795 spin_unlock_irq(&file->lock); 796 hisi_qm_put_dfx_access(qm); 797 return ret; 798 } 799 800 static const struct file_operations sec_dbg_fops = { 801 .owner = THIS_MODULE, 802 .open = simple_open, 803 .read = sec_debug_read, 804 .write = sec_debug_write, 805 }; 806 807 static int sec_debugfs_atomic64_get(void *data, u64 *val) 808 { 809 *val = atomic64_read((atomic64_t *)data); 810 811 return 0; 812 } 813 814 static int sec_debugfs_atomic64_set(void *data, u64 val) 815 { 816 if (val) 817 return -EINVAL; 818 819 atomic64_set((atomic64_t *)data, 0); 820 821 return 0; 822 } 823 824 DEFINE_DEBUGFS_ATTRIBUTE(sec_atomic64_ops, sec_debugfs_atomic64_get, 825 sec_debugfs_atomic64_set, "%lld\n"); 826 827 static int sec_regs_show(struct seq_file *s, void *unused) 828 { 829 hisi_qm_regs_dump(s, s->private); 830 831 return 0; 832 } 833 834 DEFINE_SHOW_ATTRIBUTE(sec_regs); 835 836 static int sec_core_debug_init(struct hisi_qm *qm) 837 { 838 struct dfx_diff_registers *sec_regs = qm->debug.acc_diff_regs; 839 struct sec_dev *sec = container_of(qm, struct sec_dev, qm); 840 struct device *dev = &qm->pdev->dev; 841 struct sec_dfx *dfx = &sec->debug.dfx; 842 struct debugfs_regset32 *regset; 843 struct dentry *tmp_d; 844 int i; 845 846 tmp_d = debugfs_create_dir("sec_dfx", qm->debug.debug_root); 847 848 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); 849 if (!regset) 850 return -ENOMEM; 851 852 regset->regs = sec_dfx_regs; 853 regset->nregs = ARRAY_SIZE(sec_dfx_regs); 854 regset->base = qm->io_base; 855 regset->dev = dev; 856 857 if (qm->pdev->device == PCI_DEVICE_ID_HUAWEI_SEC_PF) 858 debugfs_create_file("regs", 0444, tmp_d, regset, &sec_regs_fops); 859 if (qm->fun_type == QM_HW_PF && sec_regs) 860 debugfs_create_file("diff_regs", 0444, tmp_d, 861 qm, &sec_diff_regs_fops); 862 863 for (i = 0; i < ARRAY_SIZE(sec_dfx_labels); i++) { 864 atomic64_t *data = (atomic64_t *)((uintptr_t)dfx + 865 sec_dfx_labels[i].offset); 866 debugfs_create_file(sec_dfx_labels[i].name, 0644, 867 tmp_d, data, &sec_atomic64_ops); 868 } 869 870 return 0; 871 } 872 873 static int sec_debug_init(struct hisi_qm *qm) 874 { 875 struct sec_dev *sec = container_of(qm, struct sec_dev, qm); 876 int i; 877 878 if (qm->pdev->device == PCI_DEVICE_ID_HUAWEI_SEC_PF) { 879 for (i = SEC_CLEAR_ENABLE; i < SEC_DEBUG_FILE_NUM; i++) { 880 spin_lock_init(&sec->debug.files[i].lock); 881 sec->debug.files[i].index = i; 882 sec->debug.files[i].qm = qm; 883 884 debugfs_create_file(sec_dbg_file_name[i], 0600, 885 qm->debug.debug_root, 886 sec->debug.files + i, 887 &sec_dbg_fops); 888 } 889 } 890 891 return sec_core_debug_init(qm); 892 } 893 894 static int sec_debugfs_init(struct hisi_qm *qm) 895 { 896 struct device *dev = &qm->pdev->dev; 897 int ret; 898 899 qm->debug.debug_root = debugfs_create_dir(dev_name(dev), 900 sec_debugfs_root); 901 qm->debug.sqe_mask_offset = SEC_SQE_MASK_OFFSET; 902 qm->debug.sqe_mask_len = SEC_SQE_MASK_LEN; 903 904 ret = hisi_qm_regs_debugfs_init(qm, sec_diff_regs, ARRAY_SIZE(sec_diff_regs)); 905 if (ret) { 906 dev_warn(dev, "Failed to init SEC diff regs!\n"); 907 goto debugfs_remove; 908 } 909 910 hisi_qm_debug_init(qm); 911 912 ret = sec_debug_init(qm); 913 if (ret) 914 goto failed_to_create; 915 916 return 0; 917 918 failed_to_create: 919 hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(sec_diff_regs)); 920 debugfs_remove: 921 debugfs_remove_recursive(sec_debugfs_root); 922 return ret; 923 } 924 925 static void sec_debugfs_exit(struct hisi_qm *qm) 926 { 927 hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(sec_diff_regs)); 928 929 debugfs_remove_recursive(qm->debug.debug_root); 930 } 931 932 static int sec_show_last_regs_init(struct hisi_qm *qm) 933 { 934 struct qm_debug *debug = &qm->debug; 935 int i; 936 937 debug->last_words = kcalloc(ARRAY_SIZE(sec_dfx_regs), 938 sizeof(unsigned int), GFP_KERNEL); 939 if (!debug->last_words) 940 return -ENOMEM; 941 942 for (i = 0; i < ARRAY_SIZE(sec_dfx_regs); i++) 943 debug->last_words[i] = readl_relaxed(qm->io_base + 944 sec_dfx_regs[i].offset); 945 946 return 0; 947 } 948 949 static void sec_show_last_regs_uninit(struct hisi_qm *qm) 950 { 951 struct qm_debug *debug = &qm->debug; 952 953 if (qm->fun_type == QM_HW_VF || !debug->last_words) 954 return; 955 956 kfree(debug->last_words); 957 debug->last_words = NULL; 958 } 959 960 static void sec_show_last_dfx_regs(struct hisi_qm *qm) 961 { 962 struct qm_debug *debug = &qm->debug; 963 struct pci_dev *pdev = qm->pdev; 964 u32 val; 965 int i; 966 967 if (qm->fun_type == QM_HW_VF || !debug->last_words) 968 return; 969 970 /* dumps last word of the debugging registers during controller reset */ 971 for (i = 0; i < ARRAY_SIZE(sec_dfx_regs); i++) { 972 val = readl_relaxed(qm->io_base + sec_dfx_regs[i].offset); 973 if (val != debug->last_words[i]) 974 pci_info(pdev, "%s \t= 0x%08x => 0x%08x\n", 975 sec_dfx_regs[i].name, debug->last_words[i], val); 976 } 977 } 978 979 static void sec_log_hw_error(struct hisi_qm *qm, u32 err_sts) 980 { 981 const struct sec_hw_error *errs = sec_hw_errors; 982 struct device *dev = &qm->pdev->dev; 983 u32 err_val; 984 985 while (errs->msg) { 986 if (errs->int_msk & err_sts) { 987 dev_err(dev, "%s [error status=0x%x] found\n", 988 errs->msg, errs->int_msk); 989 990 if (SEC_CORE_INT_STATUS_M_ECC & errs->int_msk) { 991 err_val = readl(qm->io_base + 992 SEC_CORE_SRAM_ECC_ERR_INFO); 993 dev_err(dev, "multi ecc sram num=0x%x\n", 994 ((err_val) >> SEC_ECC_NUM) & 995 SEC_ECC_MASH); 996 } 997 } 998 errs++; 999 } 1000 } 1001 1002 static u32 sec_get_hw_err_status(struct hisi_qm *qm) 1003 { 1004 return readl(qm->io_base + SEC_CORE_INT_STATUS); 1005 } 1006 1007 static void sec_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts) 1008 { 1009 u32 nfe; 1010 1011 writel(err_sts, qm->io_base + SEC_CORE_INT_SOURCE); 1012 nfe = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_NFE_MASK_CAP, qm->cap_ver); 1013 writel(nfe, qm->io_base + SEC_RAS_NFE_REG); 1014 } 1015 1016 static void sec_open_axi_master_ooo(struct hisi_qm *qm) 1017 { 1018 u32 val; 1019 1020 val = readl(qm->io_base + SEC_CONTROL_REG); 1021 writel(val & SEC_AXI_SHUTDOWN_DISABLE, qm->io_base + SEC_CONTROL_REG); 1022 writel(val | SEC_AXI_SHUTDOWN_ENABLE, qm->io_base + SEC_CONTROL_REG); 1023 } 1024 1025 static void sec_err_info_init(struct hisi_qm *qm) 1026 { 1027 struct hisi_qm_err_info *err_info = &qm->err_info; 1028 1029 err_info->fe = SEC_RAS_FE_ENB_MSK; 1030 err_info->ce = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_QM_CE_MASK_CAP, qm->cap_ver); 1031 err_info->nfe = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_QM_NFE_MASK_CAP, qm->cap_ver); 1032 err_info->ecc_2bits_mask = SEC_CORE_INT_STATUS_M_ECC; 1033 err_info->qm_shutdown_mask = hisi_qm_get_hw_info(qm, sec_basic_info, 1034 SEC_QM_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 1035 err_info->dev_shutdown_mask = hisi_qm_get_hw_info(qm, sec_basic_info, 1036 SEC_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 1037 err_info->qm_reset_mask = hisi_qm_get_hw_info(qm, sec_basic_info, 1038 SEC_QM_RESET_MASK_CAP, qm->cap_ver); 1039 err_info->dev_reset_mask = hisi_qm_get_hw_info(qm, sec_basic_info, 1040 SEC_RESET_MASK_CAP, qm->cap_ver); 1041 err_info->msi_wr_port = BIT(0); 1042 err_info->acpi_rst = "SRST"; 1043 } 1044 1045 static const struct hisi_qm_err_ini sec_err_ini = { 1046 .hw_init = sec_set_user_domain_and_cache, 1047 .hw_err_enable = sec_hw_error_enable, 1048 .hw_err_disable = sec_hw_error_disable, 1049 .get_dev_hw_err_status = sec_get_hw_err_status, 1050 .clear_dev_hw_err_status = sec_clear_hw_err_status, 1051 .log_dev_hw_err = sec_log_hw_error, 1052 .open_axi_master_ooo = sec_open_axi_master_ooo, 1053 .open_sva_prefetch = sec_open_sva_prefetch, 1054 .close_sva_prefetch = sec_close_sva_prefetch, 1055 .show_last_dfx_regs = sec_show_last_dfx_regs, 1056 .err_info_init = sec_err_info_init, 1057 }; 1058 1059 static int sec_pf_probe_init(struct sec_dev *sec) 1060 { 1061 struct hisi_qm *qm = &sec->qm; 1062 int ret; 1063 1064 qm->err_ini = &sec_err_ini; 1065 qm->err_ini->err_info_init(qm); 1066 1067 ret = sec_set_user_domain_and_cache(qm); 1068 if (ret) 1069 return ret; 1070 1071 sec_open_sva_prefetch(qm); 1072 hisi_qm_dev_err_init(qm); 1073 sec_debug_regs_clear(qm); 1074 ret = sec_show_last_regs_init(qm); 1075 if (ret) 1076 pci_err(qm->pdev, "Failed to init last word regs!\n"); 1077 1078 return ret; 1079 } 1080 1081 static int sec_pre_store_cap_reg(struct hisi_qm *qm) 1082 { 1083 struct hisi_qm_cap_record *sec_cap; 1084 struct pci_dev *pdev = qm->pdev; 1085 size_t i, size; 1086 1087 size = ARRAY_SIZE(sec_pre_store_caps); 1088 sec_cap = devm_kzalloc(&pdev->dev, sizeof(*sec_cap) * size, GFP_KERNEL); 1089 if (!sec_cap) 1090 return -ENOMEM; 1091 1092 for (i = 0; i < size; i++) { 1093 sec_cap[i].type = sec_pre_store_caps[i]; 1094 sec_cap[i].cap_val = hisi_qm_get_hw_info(qm, sec_basic_info, 1095 sec_pre_store_caps[i], qm->cap_ver); 1096 } 1097 1098 qm->cap_tables.dev_cap_table = sec_cap; 1099 1100 return 0; 1101 } 1102 1103 static int sec_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) 1104 { 1105 u64 alg_msk; 1106 int ret; 1107 1108 qm->pdev = pdev; 1109 qm->ver = pdev->revision; 1110 qm->mode = uacce_mode; 1111 qm->sqe_size = SEC_SQE_SIZE; 1112 qm->dev_name = sec_name; 1113 1114 qm->fun_type = (pdev->device == PCI_DEVICE_ID_HUAWEI_SEC_PF) ? 1115 QM_HW_PF : QM_HW_VF; 1116 if (qm->fun_type == QM_HW_PF) { 1117 qm->qp_base = SEC_PF_DEF_Q_BASE; 1118 qm->qp_num = pf_q_num; 1119 qm->debug.curr_qm_qp_num = pf_q_num; 1120 qm->qm_list = &sec_devices; 1121 if (pf_q_num_flag) 1122 set_bit(QM_MODULE_PARAM, &qm->misc_ctl); 1123 } else if (qm->fun_type == QM_HW_VF && qm->ver == QM_HW_V1) { 1124 /* 1125 * have no way to get qm configure in VM in v1 hardware, 1126 * so currently force PF to uses SEC_PF_DEF_Q_NUM, and force 1127 * to trigger only one VF in v1 hardware. 1128 * v2 hardware has no such problem. 1129 */ 1130 qm->qp_base = SEC_PF_DEF_Q_NUM; 1131 qm->qp_num = SEC_QUEUE_NUM_V1 - SEC_PF_DEF_Q_NUM; 1132 } 1133 1134 ret = hisi_qm_init(qm); 1135 if (ret) { 1136 pci_err(qm->pdev, "Failed to init sec qm configures!\n"); 1137 return ret; 1138 } 1139 1140 /* Fetch and save the value of capability registers */ 1141 ret = sec_pre_store_cap_reg(qm); 1142 if (ret) { 1143 pci_err(qm->pdev, "Failed to pre-store capability registers!\n"); 1144 hisi_qm_uninit(qm); 1145 return ret; 1146 } 1147 1148 alg_msk = sec_get_alg_bitmap(qm, SEC_DEV_ALG_BITMAP_HIGH_IDX, SEC_DEV_ALG_BITMAP_LOW_IDX); 1149 ret = hisi_qm_set_algs(qm, alg_msk, sec_dev_algs, ARRAY_SIZE(sec_dev_algs)); 1150 if (ret) { 1151 pci_err(qm->pdev, "Failed to set sec algs!\n"); 1152 hisi_qm_uninit(qm); 1153 } 1154 1155 return ret; 1156 } 1157 1158 static void sec_qm_uninit(struct hisi_qm *qm) 1159 { 1160 hisi_qm_uninit(qm); 1161 } 1162 1163 static int sec_probe_init(struct sec_dev *sec) 1164 { 1165 u32 type_rate = SEC_SHAPER_TYPE_RATE; 1166 struct hisi_qm *qm = &sec->qm; 1167 int ret; 1168 1169 if (qm->fun_type == QM_HW_PF) { 1170 ret = sec_pf_probe_init(sec); 1171 if (ret) 1172 return ret; 1173 /* enable shaper type 0 */ 1174 if (qm->ver >= QM_HW_V3) { 1175 type_rate |= QM_SHAPER_ENABLE; 1176 qm->type_rate = type_rate; 1177 } 1178 } 1179 1180 return 0; 1181 } 1182 1183 static void sec_probe_uninit(struct hisi_qm *qm) 1184 { 1185 hisi_qm_dev_err_uninit(qm); 1186 } 1187 1188 static void sec_iommu_used_check(struct sec_dev *sec) 1189 { 1190 struct iommu_domain *domain; 1191 struct device *dev = &sec->qm.pdev->dev; 1192 1193 domain = iommu_get_domain_for_dev(dev); 1194 1195 /* Check if iommu is used */ 1196 sec->iommu_used = false; 1197 if (domain) { 1198 if (domain->type & __IOMMU_DOMAIN_PAGING) 1199 sec->iommu_used = true; 1200 dev_info(dev, "SMMU Opened, the iommu type = %u\n", 1201 domain->type); 1202 } 1203 } 1204 1205 static int sec_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1206 { 1207 struct sec_dev *sec; 1208 struct hisi_qm *qm; 1209 int ret; 1210 1211 sec = devm_kzalloc(&pdev->dev, sizeof(*sec), GFP_KERNEL); 1212 if (!sec) 1213 return -ENOMEM; 1214 1215 qm = &sec->qm; 1216 ret = sec_qm_init(qm, pdev); 1217 if (ret) { 1218 pci_err(pdev, "Failed to init SEC QM (%d)!\n", ret); 1219 return ret; 1220 } 1221 1222 sec->ctx_q_num = ctx_q_num; 1223 sec_iommu_used_check(sec); 1224 1225 ret = sec_probe_init(sec); 1226 if (ret) { 1227 pci_err(pdev, "Failed to probe!\n"); 1228 goto err_qm_uninit; 1229 } 1230 1231 ret = hisi_qm_start(qm); 1232 if (ret) { 1233 pci_err(pdev, "Failed to start sec qm!\n"); 1234 goto err_probe_uninit; 1235 } 1236 1237 ret = sec_debugfs_init(qm); 1238 if (ret) 1239 pci_warn(pdev, "Failed to init debugfs!\n"); 1240 1241 hisi_qm_add_list(qm, &sec_devices); 1242 ret = hisi_qm_alg_register(qm, &sec_devices, ctx_q_num); 1243 if (ret < 0) { 1244 pr_err("Failed to register driver to crypto.\n"); 1245 goto err_qm_del_list; 1246 } 1247 1248 if (qm->uacce) { 1249 ret = uacce_register(qm->uacce); 1250 if (ret) { 1251 pci_err(pdev, "failed to register uacce (%d)!\n", ret); 1252 goto err_alg_unregister; 1253 } 1254 } 1255 1256 if (qm->fun_type == QM_HW_PF && vfs_num) { 1257 ret = hisi_qm_sriov_enable(pdev, vfs_num); 1258 if (ret < 0) 1259 goto err_alg_unregister; 1260 } 1261 1262 hisi_qm_pm_init(qm); 1263 1264 return 0; 1265 1266 err_alg_unregister: 1267 hisi_qm_alg_unregister(qm, &sec_devices, ctx_q_num); 1268 err_qm_del_list: 1269 hisi_qm_del_list(qm, &sec_devices); 1270 sec_debugfs_exit(qm); 1271 hisi_qm_stop(qm, QM_NORMAL); 1272 err_probe_uninit: 1273 sec_show_last_regs_uninit(qm); 1274 sec_probe_uninit(qm); 1275 err_qm_uninit: 1276 sec_qm_uninit(qm); 1277 return ret; 1278 } 1279 1280 static void sec_remove(struct pci_dev *pdev) 1281 { 1282 struct hisi_qm *qm = pci_get_drvdata(pdev); 1283 1284 hisi_qm_pm_uninit(qm); 1285 hisi_qm_wait_task_finish(qm, &sec_devices); 1286 hisi_qm_alg_unregister(qm, &sec_devices, ctx_q_num); 1287 hisi_qm_del_list(qm, &sec_devices); 1288 1289 if (qm->fun_type == QM_HW_PF && qm->vfs_num) 1290 hisi_qm_sriov_disable(pdev, true); 1291 1292 sec_debugfs_exit(qm); 1293 1294 (void)hisi_qm_stop(qm, QM_NORMAL); 1295 1296 if (qm->fun_type == QM_HW_PF) 1297 sec_debug_regs_clear(qm); 1298 sec_show_last_regs_uninit(qm); 1299 1300 sec_probe_uninit(qm); 1301 1302 sec_qm_uninit(qm); 1303 } 1304 1305 static const struct dev_pm_ops sec_pm_ops = { 1306 SET_RUNTIME_PM_OPS(hisi_qm_suspend, hisi_qm_resume, NULL) 1307 }; 1308 1309 static const struct pci_error_handlers sec_err_handler = { 1310 .error_detected = hisi_qm_dev_err_detected, 1311 .slot_reset = hisi_qm_dev_slot_reset, 1312 .reset_prepare = hisi_qm_reset_prepare, 1313 .reset_done = hisi_qm_reset_done, 1314 }; 1315 1316 static struct pci_driver sec_pci_driver = { 1317 .name = "hisi_sec2", 1318 .id_table = sec_dev_ids, 1319 .probe = sec_probe, 1320 .remove = sec_remove, 1321 .err_handler = &sec_err_handler, 1322 .sriov_configure = hisi_qm_sriov_configure, 1323 .shutdown = hisi_qm_dev_shutdown, 1324 .driver.pm = &sec_pm_ops, 1325 }; 1326 1327 struct pci_driver *hisi_sec_get_pf_driver(void) 1328 { 1329 return &sec_pci_driver; 1330 } 1331 EXPORT_SYMBOL_GPL(hisi_sec_get_pf_driver); 1332 1333 static void sec_register_debugfs(void) 1334 { 1335 if (!debugfs_initialized()) 1336 return; 1337 1338 sec_debugfs_root = debugfs_create_dir("hisi_sec2", NULL); 1339 } 1340 1341 static void sec_unregister_debugfs(void) 1342 { 1343 debugfs_remove_recursive(sec_debugfs_root); 1344 } 1345 1346 static int __init sec_init(void) 1347 { 1348 int ret; 1349 1350 hisi_qm_init_list(&sec_devices); 1351 sec_register_debugfs(); 1352 1353 ret = pci_register_driver(&sec_pci_driver); 1354 if (ret < 0) { 1355 sec_unregister_debugfs(); 1356 pr_err("Failed to register pci driver.\n"); 1357 return ret; 1358 } 1359 1360 return 0; 1361 } 1362 1363 static void __exit sec_exit(void) 1364 { 1365 pci_unregister_driver(&sec_pci_driver); 1366 sec_unregister_debugfs(); 1367 } 1368 1369 module_init(sec_init); 1370 module_exit(sec_exit); 1371 1372 MODULE_LICENSE("GPL v2"); 1373 MODULE_AUTHOR("Zaibo Xu <xuzaibo@huawei.com>"); 1374 MODULE_AUTHOR("Longfang Liu <liulongfang@huawei.com>"); 1375 MODULE_AUTHOR("Kai Ye <yekai13@huawei.com>"); 1376 MODULE_AUTHOR("Wei Zhang <zhangwei375@huawei.com>"); 1377 MODULE_DESCRIPTION("Driver for HiSilicon SEC accelerator"); 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