1655ff1a1SSrujanaChalla // SPDX-License-Identifier: GPL-2.0-only
2655ff1a1SSrujanaChalla /*
3655ff1a1SSrujanaChalla * Support for Marvell's Cryptographic Engine and Security Accelerator (CESA)
4655ff1a1SSrujanaChalla * that can be found on the following platform: Orion, Kirkwood, Armada. This
5655ff1a1SSrujanaChalla * driver supports the TDMA engine on platforms on which it is available.
6655ff1a1SSrujanaChalla *
7655ff1a1SSrujanaChalla * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
8655ff1a1SSrujanaChalla * Author: Arnaud Ebalard <arno@natisbad.org>
9655ff1a1SSrujanaChalla *
10655ff1a1SSrujanaChalla * This work is based on an initial version written by
11655ff1a1SSrujanaChalla * Sebastian Andrzej Siewior < sebastian at breakpoint dot cc >
12655ff1a1SSrujanaChalla */
13655ff1a1SSrujanaChalla
14655ff1a1SSrujanaChalla #include <linux/delay.h>
15655ff1a1SSrujanaChalla #include <linux/dma-mapping.h>
16655ff1a1SSrujanaChalla #include <linux/genalloc.h>
17655ff1a1SSrujanaChalla #include <linux/interrupt.h>
18655ff1a1SSrujanaChalla #include <linux/io.h>
19655ff1a1SSrujanaChalla #include <linux/kthread.h>
20655ff1a1SSrujanaChalla #include <linux/mbus.h>
21655ff1a1SSrujanaChalla #include <linux/platform_device.h>
22655ff1a1SSrujanaChalla #include <linux/scatterlist.h>
23655ff1a1SSrujanaChalla #include <linux/slab.h>
24655ff1a1SSrujanaChalla #include <linux/module.h>
25655ff1a1SSrujanaChalla #include <linux/clk.h>
26655ff1a1SSrujanaChalla #include <linux/of.h>
27655ff1a1SSrujanaChalla #include <linux/of_platform.h>
28655ff1a1SSrujanaChalla #include <linux/of_irq.h>
29655ff1a1SSrujanaChalla
30655ff1a1SSrujanaChalla #include "cesa.h"
31655ff1a1SSrujanaChalla
32655ff1a1SSrujanaChalla /* Limit of the crypto queue before reaching the backlog */
33655ff1a1SSrujanaChalla #define CESA_CRYPTO_DEFAULT_MAX_QLEN 128
34655ff1a1SSrujanaChalla
35655ff1a1SSrujanaChalla struct mv_cesa_dev *cesa_dev;
36655ff1a1SSrujanaChalla
37655ff1a1SSrujanaChalla struct crypto_async_request *
mv_cesa_dequeue_req_locked(struct mv_cesa_engine * engine,struct crypto_async_request ** backlog)38655ff1a1SSrujanaChalla mv_cesa_dequeue_req_locked(struct mv_cesa_engine *engine,
39655ff1a1SSrujanaChalla struct crypto_async_request **backlog)
40655ff1a1SSrujanaChalla {
41655ff1a1SSrujanaChalla struct crypto_async_request *req;
42655ff1a1SSrujanaChalla
43655ff1a1SSrujanaChalla *backlog = crypto_get_backlog(&engine->queue);
44655ff1a1SSrujanaChalla req = crypto_dequeue_request(&engine->queue);
45655ff1a1SSrujanaChalla
46655ff1a1SSrujanaChalla if (!req)
47655ff1a1SSrujanaChalla return NULL;
48655ff1a1SSrujanaChalla
49655ff1a1SSrujanaChalla return req;
50655ff1a1SSrujanaChalla }
51655ff1a1SSrujanaChalla
mv_cesa_rearm_engine(struct mv_cesa_engine * engine)52655ff1a1SSrujanaChalla static void mv_cesa_rearm_engine(struct mv_cesa_engine *engine)
53655ff1a1SSrujanaChalla {
54655ff1a1SSrujanaChalla struct crypto_async_request *req = NULL, *backlog = NULL;
55655ff1a1SSrujanaChalla struct mv_cesa_ctx *ctx;
56655ff1a1SSrujanaChalla
57655ff1a1SSrujanaChalla
58655ff1a1SSrujanaChalla spin_lock_bh(&engine->lock);
59655ff1a1SSrujanaChalla if (!engine->req) {
60655ff1a1SSrujanaChalla req = mv_cesa_dequeue_req_locked(engine, &backlog);
61655ff1a1SSrujanaChalla engine->req = req;
62655ff1a1SSrujanaChalla }
63655ff1a1SSrujanaChalla spin_unlock_bh(&engine->lock);
64655ff1a1SSrujanaChalla
65655ff1a1SSrujanaChalla if (!req)
66655ff1a1SSrujanaChalla return;
67655ff1a1SSrujanaChalla
68655ff1a1SSrujanaChalla if (backlog)
6925e3159cSHerbert Xu crypto_request_complete(backlog, -EINPROGRESS);
70655ff1a1SSrujanaChalla
71655ff1a1SSrujanaChalla ctx = crypto_tfm_ctx(req->tfm);
72655ff1a1SSrujanaChalla ctx->ops->step(req);
73655ff1a1SSrujanaChalla }
74655ff1a1SSrujanaChalla
mv_cesa_std_process(struct mv_cesa_engine * engine,u32 status)75655ff1a1SSrujanaChalla static int mv_cesa_std_process(struct mv_cesa_engine *engine, u32 status)
76655ff1a1SSrujanaChalla {
77655ff1a1SSrujanaChalla struct crypto_async_request *req;
78655ff1a1SSrujanaChalla struct mv_cesa_ctx *ctx;
79655ff1a1SSrujanaChalla int res;
80655ff1a1SSrujanaChalla
81655ff1a1SSrujanaChalla req = engine->req;
82655ff1a1SSrujanaChalla ctx = crypto_tfm_ctx(req->tfm);
83655ff1a1SSrujanaChalla res = ctx->ops->process(req, status);
84655ff1a1SSrujanaChalla
85655ff1a1SSrujanaChalla if (res == 0) {
86655ff1a1SSrujanaChalla ctx->ops->complete(req);
87655ff1a1SSrujanaChalla mv_cesa_engine_enqueue_complete_request(engine, req);
88655ff1a1SSrujanaChalla } else if (res == -EINPROGRESS) {
89655ff1a1SSrujanaChalla ctx->ops->step(req);
90655ff1a1SSrujanaChalla }
91655ff1a1SSrujanaChalla
92655ff1a1SSrujanaChalla return res;
93655ff1a1SSrujanaChalla }
94655ff1a1SSrujanaChalla
mv_cesa_int_process(struct mv_cesa_engine * engine,u32 status)95655ff1a1SSrujanaChalla static int mv_cesa_int_process(struct mv_cesa_engine *engine, u32 status)
96655ff1a1SSrujanaChalla {
97655ff1a1SSrujanaChalla if (engine->chain.first && engine->chain.last)
98655ff1a1SSrujanaChalla return mv_cesa_tdma_process(engine, status);
99655ff1a1SSrujanaChalla
100655ff1a1SSrujanaChalla return mv_cesa_std_process(engine, status);
101655ff1a1SSrujanaChalla }
102655ff1a1SSrujanaChalla
103655ff1a1SSrujanaChalla static inline void
mv_cesa_complete_req(struct mv_cesa_ctx * ctx,struct crypto_async_request * req,int res)104655ff1a1SSrujanaChalla mv_cesa_complete_req(struct mv_cesa_ctx *ctx, struct crypto_async_request *req,
105655ff1a1SSrujanaChalla int res)
106655ff1a1SSrujanaChalla {
107655ff1a1SSrujanaChalla ctx->ops->cleanup(req);
108655ff1a1SSrujanaChalla local_bh_disable();
10925e3159cSHerbert Xu crypto_request_complete(req, res);
110655ff1a1SSrujanaChalla local_bh_enable();
111655ff1a1SSrujanaChalla }
112655ff1a1SSrujanaChalla
mv_cesa_int(int irq,void * priv)113655ff1a1SSrujanaChalla static irqreturn_t mv_cesa_int(int irq, void *priv)
114655ff1a1SSrujanaChalla {
115655ff1a1SSrujanaChalla struct mv_cesa_engine *engine = priv;
116655ff1a1SSrujanaChalla struct crypto_async_request *req;
117655ff1a1SSrujanaChalla struct mv_cesa_ctx *ctx;
118655ff1a1SSrujanaChalla u32 status, mask;
119655ff1a1SSrujanaChalla irqreturn_t ret = IRQ_NONE;
120655ff1a1SSrujanaChalla
121655ff1a1SSrujanaChalla while (true) {
122655ff1a1SSrujanaChalla int res;
123655ff1a1SSrujanaChalla
124655ff1a1SSrujanaChalla mask = mv_cesa_get_int_mask(engine);
125655ff1a1SSrujanaChalla status = readl(engine->regs + CESA_SA_INT_STATUS);
126655ff1a1SSrujanaChalla
127655ff1a1SSrujanaChalla if (!(status & mask))
128655ff1a1SSrujanaChalla break;
129655ff1a1SSrujanaChalla
130655ff1a1SSrujanaChalla /*
131655ff1a1SSrujanaChalla * TODO: avoid clearing the FPGA_INT_STATUS if this not
132655ff1a1SSrujanaChalla * relevant on some platforms.
133655ff1a1SSrujanaChalla */
134655ff1a1SSrujanaChalla writel(~status, engine->regs + CESA_SA_FPGA_INT_STATUS);
135655ff1a1SSrujanaChalla writel(~status, engine->regs + CESA_SA_INT_STATUS);
136655ff1a1SSrujanaChalla
137655ff1a1SSrujanaChalla /* Process fetched requests */
138655ff1a1SSrujanaChalla res = mv_cesa_int_process(engine, status & mask);
139655ff1a1SSrujanaChalla ret = IRQ_HANDLED;
140655ff1a1SSrujanaChalla
141655ff1a1SSrujanaChalla spin_lock_bh(&engine->lock);
142655ff1a1SSrujanaChalla req = engine->req;
143655ff1a1SSrujanaChalla if (res != -EINPROGRESS)
144655ff1a1SSrujanaChalla engine->req = NULL;
145655ff1a1SSrujanaChalla spin_unlock_bh(&engine->lock);
146655ff1a1SSrujanaChalla
147655ff1a1SSrujanaChalla ctx = crypto_tfm_ctx(req->tfm);
148655ff1a1SSrujanaChalla
149655ff1a1SSrujanaChalla if (res && res != -EINPROGRESS)
150655ff1a1SSrujanaChalla mv_cesa_complete_req(ctx, req, res);
151655ff1a1SSrujanaChalla
152655ff1a1SSrujanaChalla /* Launch the next pending request */
153655ff1a1SSrujanaChalla mv_cesa_rearm_engine(engine);
154655ff1a1SSrujanaChalla
155655ff1a1SSrujanaChalla /* Iterate over the complete queue */
156655ff1a1SSrujanaChalla while (true) {
157655ff1a1SSrujanaChalla req = mv_cesa_engine_dequeue_complete_request(engine);
158655ff1a1SSrujanaChalla if (!req)
159655ff1a1SSrujanaChalla break;
160655ff1a1SSrujanaChalla
161655ff1a1SSrujanaChalla ctx = crypto_tfm_ctx(req->tfm);
162655ff1a1SSrujanaChalla mv_cesa_complete_req(ctx, req, 0);
163655ff1a1SSrujanaChalla }
164655ff1a1SSrujanaChalla }
165655ff1a1SSrujanaChalla
166655ff1a1SSrujanaChalla return ret;
167655ff1a1SSrujanaChalla }
168655ff1a1SSrujanaChalla
mv_cesa_queue_req(struct crypto_async_request * req,struct mv_cesa_req * creq)169655ff1a1SSrujanaChalla int mv_cesa_queue_req(struct crypto_async_request *req,
170655ff1a1SSrujanaChalla struct mv_cesa_req *creq)
171655ff1a1SSrujanaChalla {
172655ff1a1SSrujanaChalla int ret;
173655ff1a1SSrujanaChalla struct mv_cesa_engine *engine = creq->engine;
174655ff1a1SSrujanaChalla
175655ff1a1SSrujanaChalla spin_lock_bh(&engine->lock);
176655ff1a1SSrujanaChalla ret = crypto_enqueue_request(&engine->queue, req);
177655ff1a1SSrujanaChalla if ((mv_cesa_req_get_type(creq) == CESA_DMA_REQ) &&
178655ff1a1SSrujanaChalla (ret == -EINPROGRESS || ret == -EBUSY))
179655ff1a1SSrujanaChalla mv_cesa_tdma_chain(engine, creq);
180655ff1a1SSrujanaChalla spin_unlock_bh(&engine->lock);
181655ff1a1SSrujanaChalla
182655ff1a1SSrujanaChalla if (ret != -EINPROGRESS)
183655ff1a1SSrujanaChalla return ret;
184655ff1a1SSrujanaChalla
185655ff1a1SSrujanaChalla mv_cesa_rearm_engine(engine);
186655ff1a1SSrujanaChalla
187655ff1a1SSrujanaChalla return -EINPROGRESS;
188655ff1a1SSrujanaChalla }
189655ff1a1SSrujanaChalla
mv_cesa_add_algs(struct mv_cesa_dev * cesa)190655ff1a1SSrujanaChalla static int mv_cesa_add_algs(struct mv_cesa_dev *cesa)
191655ff1a1SSrujanaChalla {
192655ff1a1SSrujanaChalla int ret;
193655ff1a1SSrujanaChalla int i, j;
194655ff1a1SSrujanaChalla
195655ff1a1SSrujanaChalla for (i = 0; i < cesa->caps->ncipher_algs; i++) {
196655ff1a1SSrujanaChalla ret = crypto_register_skcipher(cesa->caps->cipher_algs[i]);
197655ff1a1SSrujanaChalla if (ret)
198655ff1a1SSrujanaChalla goto err_unregister_crypto;
199655ff1a1SSrujanaChalla }
200655ff1a1SSrujanaChalla
201655ff1a1SSrujanaChalla for (i = 0; i < cesa->caps->nahash_algs; i++) {
202655ff1a1SSrujanaChalla ret = crypto_register_ahash(cesa->caps->ahash_algs[i]);
203655ff1a1SSrujanaChalla if (ret)
204655ff1a1SSrujanaChalla goto err_unregister_ahash;
205655ff1a1SSrujanaChalla }
206655ff1a1SSrujanaChalla
207655ff1a1SSrujanaChalla return 0;
208655ff1a1SSrujanaChalla
209655ff1a1SSrujanaChalla err_unregister_ahash:
210655ff1a1SSrujanaChalla for (j = 0; j < i; j++)
211655ff1a1SSrujanaChalla crypto_unregister_ahash(cesa->caps->ahash_algs[j]);
212655ff1a1SSrujanaChalla i = cesa->caps->ncipher_algs;
213655ff1a1SSrujanaChalla
214655ff1a1SSrujanaChalla err_unregister_crypto:
215655ff1a1SSrujanaChalla for (j = 0; j < i; j++)
216655ff1a1SSrujanaChalla crypto_unregister_skcipher(cesa->caps->cipher_algs[j]);
217655ff1a1SSrujanaChalla
218655ff1a1SSrujanaChalla return ret;
219655ff1a1SSrujanaChalla }
220655ff1a1SSrujanaChalla
mv_cesa_remove_algs(struct mv_cesa_dev * cesa)221655ff1a1SSrujanaChalla static void mv_cesa_remove_algs(struct mv_cesa_dev *cesa)
222655ff1a1SSrujanaChalla {
223655ff1a1SSrujanaChalla int i;
224655ff1a1SSrujanaChalla
225655ff1a1SSrujanaChalla for (i = 0; i < cesa->caps->nahash_algs; i++)
226655ff1a1SSrujanaChalla crypto_unregister_ahash(cesa->caps->ahash_algs[i]);
227655ff1a1SSrujanaChalla
228655ff1a1SSrujanaChalla for (i = 0; i < cesa->caps->ncipher_algs; i++)
229655ff1a1SSrujanaChalla crypto_unregister_skcipher(cesa->caps->cipher_algs[i]);
230655ff1a1SSrujanaChalla }
231655ff1a1SSrujanaChalla
232655ff1a1SSrujanaChalla static struct skcipher_alg *orion_cipher_algs[] = {
233655ff1a1SSrujanaChalla &mv_cesa_ecb_des_alg,
234655ff1a1SSrujanaChalla &mv_cesa_cbc_des_alg,
235655ff1a1SSrujanaChalla &mv_cesa_ecb_des3_ede_alg,
236655ff1a1SSrujanaChalla &mv_cesa_cbc_des3_ede_alg,
237655ff1a1SSrujanaChalla &mv_cesa_ecb_aes_alg,
238655ff1a1SSrujanaChalla &mv_cesa_cbc_aes_alg,
239655ff1a1SSrujanaChalla };
240655ff1a1SSrujanaChalla
241655ff1a1SSrujanaChalla static struct ahash_alg *orion_ahash_algs[] = {
242655ff1a1SSrujanaChalla &mv_md5_alg,
243655ff1a1SSrujanaChalla &mv_sha1_alg,
244655ff1a1SSrujanaChalla &mv_ahmac_md5_alg,
245655ff1a1SSrujanaChalla &mv_ahmac_sha1_alg,
246655ff1a1SSrujanaChalla };
247655ff1a1SSrujanaChalla
248655ff1a1SSrujanaChalla static struct skcipher_alg *armada_370_cipher_algs[] = {
249655ff1a1SSrujanaChalla &mv_cesa_ecb_des_alg,
250655ff1a1SSrujanaChalla &mv_cesa_cbc_des_alg,
251655ff1a1SSrujanaChalla &mv_cesa_ecb_des3_ede_alg,
252655ff1a1SSrujanaChalla &mv_cesa_cbc_des3_ede_alg,
253655ff1a1SSrujanaChalla &mv_cesa_ecb_aes_alg,
254655ff1a1SSrujanaChalla &mv_cesa_cbc_aes_alg,
255655ff1a1SSrujanaChalla };
256655ff1a1SSrujanaChalla
257655ff1a1SSrujanaChalla static struct ahash_alg *armada_370_ahash_algs[] = {
258655ff1a1SSrujanaChalla &mv_md5_alg,
259655ff1a1SSrujanaChalla &mv_sha1_alg,
260655ff1a1SSrujanaChalla &mv_sha256_alg,
261655ff1a1SSrujanaChalla &mv_ahmac_md5_alg,
262655ff1a1SSrujanaChalla &mv_ahmac_sha1_alg,
263655ff1a1SSrujanaChalla &mv_ahmac_sha256_alg,
264655ff1a1SSrujanaChalla };
265655ff1a1SSrujanaChalla
266655ff1a1SSrujanaChalla static const struct mv_cesa_caps orion_caps = {
267655ff1a1SSrujanaChalla .nengines = 1,
268655ff1a1SSrujanaChalla .cipher_algs = orion_cipher_algs,
269655ff1a1SSrujanaChalla .ncipher_algs = ARRAY_SIZE(orion_cipher_algs),
270655ff1a1SSrujanaChalla .ahash_algs = orion_ahash_algs,
271655ff1a1SSrujanaChalla .nahash_algs = ARRAY_SIZE(orion_ahash_algs),
272655ff1a1SSrujanaChalla .has_tdma = false,
273655ff1a1SSrujanaChalla };
274655ff1a1SSrujanaChalla
275655ff1a1SSrujanaChalla static const struct mv_cesa_caps kirkwood_caps = {
276655ff1a1SSrujanaChalla .nengines = 1,
277655ff1a1SSrujanaChalla .cipher_algs = orion_cipher_algs,
278655ff1a1SSrujanaChalla .ncipher_algs = ARRAY_SIZE(orion_cipher_algs),
279655ff1a1SSrujanaChalla .ahash_algs = orion_ahash_algs,
280655ff1a1SSrujanaChalla .nahash_algs = ARRAY_SIZE(orion_ahash_algs),
281655ff1a1SSrujanaChalla .has_tdma = true,
282655ff1a1SSrujanaChalla };
283655ff1a1SSrujanaChalla
284655ff1a1SSrujanaChalla static const struct mv_cesa_caps armada_370_caps = {
285655ff1a1SSrujanaChalla .nengines = 1,
286655ff1a1SSrujanaChalla .cipher_algs = armada_370_cipher_algs,
287655ff1a1SSrujanaChalla .ncipher_algs = ARRAY_SIZE(armada_370_cipher_algs),
288655ff1a1SSrujanaChalla .ahash_algs = armada_370_ahash_algs,
289655ff1a1SSrujanaChalla .nahash_algs = ARRAY_SIZE(armada_370_ahash_algs),
290655ff1a1SSrujanaChalla .has_tdma = true,
291655ff1a1SSrujanaChalla };
292655ff1a1SSrujanaChalla
293655ff1a1SSrujanaChalla static const struct mv_cesa_caps armada_xp_caps = {
294655ff1a1SSrujanaChalla .nengines = 2,
295655ff1a1SSrujanaChalla .cipher_algs = armada_370_cipher_algs,
296655ff1a1SSrujanaChalla .ncipher_algs = ARRAY_SIZE(armada_370_cipher_algs),
297655ff1a1SSrujanaChalla .ahash_algs = armada_370_ahash_algs,
298655ff1a1SSrujanaChalla .nahash_algs = ARRAY_SIZE(armada_370_ahash_algs),
299655ff1a1SSrujanaChalla .has_tdma = true,
300655ff1a1SSrujanaChalla };
301655ff1a1SSrujanaChalla
302655ff1a1SSrujanaChalla static const struct of_device_id mv_cesa_of_match_table[] = {
303655ff1a1SSrujanaChalla { .compatible = "marvell,orion-crypto", .data = &orion_caps },
304655ff1a1SSrujanaChalla { .compatible = "marvell,kirkwood-crypto", .data = &kirkwood_caps },
305655ff1a1SSrujanaChalla { .compatible = "marvell,dove-crypto", .data = &kirkwood_caps },
306655ff1a1SSrujanaChalla { .compatible = "marvell,armada-370-crypto", .data = &armada_370_caps },
307655ff1a1SSrujanaChalla { .compatible = "marvell,armada-xp-crypto", .data = &armada_xp_caps },
308655ff1a1SSrujanaChalla { .compatible = "marvell,armada-375-crypto", .data = &armada_xp_caps },
309655ff1a1SSrujanaChalla { .compatible = "marvell,armada-38x-crypto", .data = &armada_xp_caps },
310655ff1a1SSrujanaChalla {}
311655ff1a1SSrujanaChalla };
312655ff1a1SSrujanaChalla MODULE_DEVICE_TABLE(of, mv_cesa_of_match_table);
313655ff1a1SSrujanaChalla
314655ff1a1SSrujanaChalla static void
mv_cesa_conf_mbus_windows(struct mv_cesa_engine * engine,const struct mbus_dram_target_info * dram)315655ff1a1SSrujanaChalla mv_cesa_conf_mbus_windows(struct mv_cesa_engine *engine,
316655ff1a1SSrujanaChalla const struct mbus_dram_target_info *dram)
317655ff1a1SSrujanaChalla {
318655ff1a1SSrujanaChalla void __iomem *iobase = engine->regs;
319655ff1a1SSrujanaChalla int i;
320655ff1a1SSrujanaChalla
321655ff1a1SSrujanaChalla for (i = 0; i < 4; i++) {
322655ff1a1SSrujanaChalla writel(0, iobase + CESA_TDMA_WINDOW_CTRL(i));
323655ff1a1SSrujanaChalla writel(0, iobase + CESA_TDMA_WINDOW_BASE(i));
324655ff1a1SSrujanaChalla }
325655ff1a1SSrujanaChalla
326655ff1a1SSrujanaChalla for (i = 0; i < dram->num_cs; i++) {
327655ff1a1SSrujanaChalla const struct mbus_dram_window *cs = dram->cs + i;
328655ff1a1SSrujanaChalla
329655ff1a1SSrujanaChalla writel(((cs->size - 1) & 0xffff0000) |
330655ff1a1SSrujanaChalla (cs->mbus_attr << 8) |
331655ff1a1SSrujanaChalla (dram->mbus_dram_target_id << 4) | 1,
332655ff1a1SSrujanaChalla iobase + CESA_TDMA_WINDOW_CTRL(i));
333655ff1a1SSrujanaChalla writel(cs->base, iobase + CESA_TDMA_WINDOW_BASE(i));
334655ff1a1SSrujanaChalla }
335655ff1a1SSrujanaChalla }
336655ff1a1SSrujanaChalla
mv_cesa_dev_dma_init(struct mv_cesa_dev * cesa)337655ff1a1SSrujanaChalla static int mv_cesa_dev_dma_init(struct mv_cesa_dev *cesa)
338655ff1a1SSrujanaChalla {
339655ff1a1SSrujanaChalla struct device *dev = cesa->dev;
340655ff1a1SSrujanaChalla struct mv_cesa_dev_dma *dma;
341655ff1a1SSrujanaChalla
342655ff1a1SSrujanaChalla if (!cesa->caps->has_tdma)
343655ff1a1SSrujanaChalla return 0;
344655ff1a1SSrujanaChalla
345655ff1a1SSrujanaChalla dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
346655ff1a1SSrujanaChalla if (!dma)
347655ff1a1SSrujanaChalla return -ENOMEM;
348655ff1a1SSrujanaChalla
349655ff1a1SSrujanaChalla dma->tdma_desc_pool = dmam_pool_create("tdma_desc", dev,
350655ff1a1SSrujanaChalla sizeof(struct mv_cesa_tdma_desc),
351655ff1a1SSrujanaChalla 16, 0);
352655ff1a1SSrujanaChalla if (!dma->tdma_desc_pool)
353655ff1a1SSrujanaChalla return -ENOMEM;
354655ff1a1SSrujanaChalla
355655ff1a1SSrujanaChalla dma->op_pool = dmam_pool_create("cesa_op", dev,
356655ff1a1SSrujanaChalla sizeof(struct mv_cesa_op_ctx), 16, 0);
357655ff1a1SSrujanaChalla if (!dma->op_pool)
358655ff1a1SSrujanaChalla return -ENOMEM;
359655ff1a1SSrujanaChalla
360655ff1a1SSrujanaChalla dma->cache_pool = dmam_pool_create("cesa_cache", dev,
361655ff1a1SSrujanaChalla CESA_MAX_HASH_BLOCK_SIZE, 1, 0);
362655ff1a1SSrujanaChalla if (!dma->cache_pool)
363655ff1a1SSrujanaChalla return -ENOMEM;
364655ff1a1SSrujanaChalla
365655ff1a1SSrujanaChalla dma->padding_pool = dmam_pool_create("cesa_padding", dev, 72, 1, 0);
366655ff1a1SSrujanaChalla if (!dma->padding_pool)
367655ff1a1SSrujanaChalla return -ENOMEM;
368655ff1a1SSrujanaChalla
369655ff1a1SSrujanaChalla cesa->dma = dma;
370655ff1a1SSrujanaChalla
371655ff1a1SSrujanaChalla return 0;
372655ff1a1SSrujanaChalla }
373655ff1a1SSrujanaChalla
mv_cesa_get_sram(struct platform_device * pdev,int idx)374655ff1a1SSrujanaChalla static int mv_cesa_get_sram(struct platform_device *pdev, int idx)
375655ff1a1SSrujanaChalla {
376655ff1a1SSrujanaChalla struct mv_cesa_dev *cesa = platform_get_drvdata(pdev);
377655ff1a1SSrujanaChalla struct mv_cesa_engine *engine = &cesa->engines[idx];
378655ff1a1SSrujanaChalla const char *res_name = "sram";
379655ff1a1SSrujanaChalla struct resource *res;
380655ff1a1SSrujanaChalla
381655ff1a1SSrujanaChalla engine->pool = of_gen_pool_get(cesa->dev->of_node,
382655ff1a1SSrujanaChalla "marvell,crypto-srams", idx);
383655ff1a1SSrujanaChalla if (engine->pool) {
384c114cf7fSHerbert Xu engine->sram_pool = gen_pool_dma_alloc(engine->pool,
385655ff1a1SSrujanaChalla cesa->sram_size,
386655ff1a1SSrujanaChalla &engine->sram_dma);
387c114cf7fSHerbert Xu if (engine->sram_pool)
388655ff1a1SSrujanaChalla return 0;
389655ff1a1SSrujanaChalla
390655ff1a1SSrujanaChalla engine->pool = NULL;
391655ff1a1SSrujanaChalla return -ENOMEM;
392655ff1a1SSrujanaChalla }
393655ff1a1SSrujanaChalla
394655ff1a1SSrujanaChalla if (cesa->caps->nengines > 1) {
395655ff1a1SSrujanaChalla if (!idx)
396655ff1a1SSrujanaChalla res_name = "sram0";
397655ff1a1SSrujanaChalla else
398655ff1a1SSrujanaChalla res_name = "sram1";
399655ff1a1SSrujanaChalla }
400655ff1a1SSrujanaChalla
401655ff1a1SSrujanaChalla res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
402655ff1a1SSrujanaChalla res_name);
403655ff1a1SSrujanaChalla if (!res || resource_size(res) < cesa->sram_size)
404655ff1a1SSrujanaChalla return -EINVAL;
405655ff1a1SSrujanaChalla
406655ff1a1SSrujanaChalla engine->sram = devm_ioremap_resource(cesa->dev, res);
407655ff1a1SSrujanaChalla if (IS_ERR(engine->sram))
408655ff1a1SSrujanaChalla return PTR_ERR(engine->sram);
409655ff1a1SSrujanaChalla
410655ff1a1SSrujanaChalla engine->sram_dma = dma_map_resource(cesa->dev, res->start,
411655ff1a1SSrujanaChalla cesa->sram_size,
412655ff1a1SSrujanaChalla DMA_BIDIRECTIONAL, 0);
413655ff1a1SSrujanaChalla if (dma_mapping_error(cesa->dev, engine->sram_dma))
414655ff1a1SSrujanaChalla return -ENOMEM;
415655ff1a1SSrujanaChalla
416655ff1a1SSrujanaChalla return 0;
417655ff1a1SSrujanaChalla }
418655ff1a1SSrujanaChalla
mv_cesa_put_sram(struct platform_device * pdev,int idx)419655ff1a1SSrujanaChalla static void mv_cesa_put_sram(struct platform_device *pdev, int idx)
420655ff1a1SSrujanaChalla {
421655ff1a1SSrujanaChalla struct mv_cesa_dev *cesa = platform_get_drvdata(pdev);
422655ff1a1SSrujanaChalla struct mv_cesa_engine *engine = &cesa->engines[idx];
423655ff1a1SSrujanaChalla
424655ff1a1SSrujanaChalla if (engine->pool)
425c114cf7fSHerbert Xu gen_pool_free(engine->pool, (unsigned long)engine->sram_pool,
426655ff1a1SSrujanaChalla cesa->sram_size);
427655ff1a1SSrujanaChalla else
428655ff1a1SSrujanaChalla dma_unmap_resource(cesa->dev, engine->sram_dma,
429655ff1a1SSrujanaChalla cesa->sram_size, DMA_BIDIRECTIONAL, 0);
430655ff1a1SSrujanaChalla }
431655ff1a1SSrujanaChalla
mv_cesa_probe(struct platform_device * pdev)432655ff1a1SSrujanaChalla static int mv_cesa_probe(struct platform_device *pdev)
433655ff1a1SSrujanaChalla {
434655ff1a1SSrujanaChalla const struct mv_cesa_caps *caps = &orion_caps;
435655ff1a1SSrujanaChalla const struct mbus_dram_target_info *dram;
436655ff1a1SSrujanaChalla const struct of_device_id *match;
437655ff1a1SSrujanaChalla struct device *dev = &pdev->dev;
438655ff1a1SSrujanaChalla struct mv_cesa_dev *cesa;
439655ff1a1SSrujanaChalla struct mv_cesa_engine *engines;
44028ee8b09SSven Auhagen int irq, ret, i, cpu;
441655ff1a1SSrujanaChalla u32 sram_size;
442655ff1a1SSrujanaChalla
443655ff1a1SSrujanaChalla if (cesa_dev) {
444655ff1a1SSrujanaChalla dev_err(&pdev->dev, "Only one CESA device authorized\n");
445655ff1a1SSrujanaChalla return -EEXIST;
446655ff1a1SSrujanaChalla }
447655ff1a1SSrujanaChalla
448655ff1a1SSrujanaChalla if (dev->of_node) {
449655ff1a1SSrujanaChalla match = of_match_node(mv_cesa_of_match_table, dev->of_node);
450655ff1a1SSrujanaChalla if (!match || !match->data)
451655ff1a1SSrujanaChalla return -ENOTSUPP;
452655ff1a1SSrujanaChalla
453655ff1a1SSrujanaChalla caps = match->data;
454655ff1a1SSrujanaChalla }
455655ff1a1SSrujanaChalla
456655ff1a1SSrujanaChalla cesa = devm_kzalloc(dev, sizeof(*cesa), GFP_KERNEL);
457655ff1a1SSrujanaChalla if (!cesa)
458655ff1a1SSrujanaChalla return -ENOMEM;
459655ff1a1SSrujanaChalla
460655ff1a1SSrujanaChalla cesa->caps = caps;
461655ff1a1SSrujanaChalla cesa->dev = dev;
462655ff1a1SSrujanaChalla
463655ff1a1SSrujanaChalla sram_size = CESA_SA_DEFAULT_SRAM_SIZE;
464655ff1a1SSrujanaChalla of_property_read_u32(cesa->dev->of_node, "marvell,crypto-sram-size",
465655ff1a1SSrujanaChalla &sram_size);
466655ff1a1SSrujanaChalla if (sram_size < CESA_SA_MIN_SRAM_SIZE)
467655ff1a1SSrujanaChalla sram_size = CESA_SA_MIN_SRAM_SIZE;
468655ff1a1SSrujanaChalla
469655ff1a1SSrujanaChalla cesa->sram_size = sram_size;
470655ff1a1SSrujanaChalla cesa->engines = devm_kcalloc(dev, caps->nengines, sizeof(*engines),
471655ff1a1SSrujanaChalla GFP_KERNEL);
472655ff1a1SSrujanaChalla if (!cesa->engines)
473655ff1a1SSrujanaChalla return -ENOMEM;
474655ff1a1SSrujanaChalla
475655ff1a1SSrujanaChalla spin_lock_init(&cesa->lock);
476655ff1a1SSrujanaChalla
4773cea6b36SZhang Qilong cesa->regs = devm_platform_ioremap_resource_byname(pdev, "regs");
478655ff1a1SSrujanaChalla if (IS_ERR(cesa->regs))
479655ff1a1SSrujanaChalla return PTR_ERR(cesa->regs);
480655ff1a1SSrujanaChalla
481655ff1a1SSrujanaChalla ret = mv_cesa_dev_dma_init(cesa);
482655ff1a1SSrujanaChalla if (ret)
483655ff1a1SSrujanaChalla return ret;
484655ff1a1SSrujanaChalla
485655ff1a1SSrujanaChalla dram = mv_mbus_dram_info_nooverlap();
486655ff1a1SSrujanaChalla
487655ff1a1SSrujanaChalla platform_set_drvdata(pdev, cesa);
488655ff1a1SSrujanaChalla
489655ff1a1SSrujanaChalla for (i = 0; i < caps->nengines; i++) {
490655ff1a1SSrujanaChalla struct mv_cesa_engine *engine = &cesa->engines[i];
491*0501d0d1SHerbert Xu char res_name[16];
492655ff1a1SSrujanaChalla
493655ff1a1SSrujanaChalla engine->id = i;
494655ff1a1SSrujanaChalla spin_lock_init(&engine->lock);
495655ff1a1SSrujanaChalla
496655ff1a1SSrujanaChalla ret = mv_cesa_get_sram(pdev, i);
497655ff1a1SSrujanaChalla if (ret)
498655ff1a1SSrujanaChalla goto err_cleanup;
499655ff1a1SSrujanaChalla
500655ff1a1SSrujanaChalla irq = platform_get_irq(pdev, i);
501655ff1a1SSrujanaChalla if (irq < 0) {
502655ff1a1SSrujanaChalla ret = irq;
503655ff1a1SSrujanaChalla goto err_cleanup;
504655ff1a1SSrujanaChalla }
505655ff1a1SSrujanaChalla
50628ee8b09SSven Auhagen engine->irq = irq;
50728ee8b09SSven Auhagen
508655ff1a1SSrujanaChalla /*
509655ff1a1SSrujanaChalla * Not all platforms can gate the CESA clocks: do not complain
510655ff1a1SSrujanaChalla * if the clock does not exist.
511655ff1a1SSrujanaChalla */
512*0501d0d1SHerbert Xu snprintf(res_name, sizeof(res_name), "cesa%u", i);
513655ff1a1SSrujanaChalla engine->clk = devm_clk_get(dev, res_name);
514655ff1a1SSrujanaChalla if (IS_ERR(engine->clk)) {
515655ff1a1SSrujanaChalla engine->clk = devm_clk_get(dev, NULL);
516655ff1a1SSrujanaChalla if (IS_ERR(engine->clk))
517655ff1a1SSrujanaChalla engine->clk = NULL;
518655ff1a1SSrujanaChalla }
519655ff1a1SSrujanaChalla
520*0501d0d1SHerbert Xu snprintf(res_name, sizeof(res_name), "cesaz%u", i);
521655ff1a1SSrujanaChalla engine->zclk = devm_clk_get(dev, res_name);
522655ff1a1SSrujanaChalla if (IS_ERR(engine->zclk))
523655ff1a1SSrujanaChalla engine->zclk = NULL;
524655ff1a1SSrujanaChalla
525655ff1a1SSrujanaChalla ret = clk_prepare_enable(engine->clk);
526655ff1a1SSrujanaChalla if (ret)
527655ff1a1SSrujanaChalla goto err_cleanup;
528655ff1a1SSrujanaChalla
529655ff1a1SSrujanaChalla ret = clk_prepare_enable(engine->zclk);
530655ff1a1SSrujanaChalla if (ret)
531655ff1a1SSrujanaChalla goto err_cleanup;
532655ff1a1SSrujanaChalla
533655ff1a1SSrujanaChalla engine->regs = cesa->regs + CESA_ENGINE_OFF(i);
534655ff1a1SSrujanaChalla
535655ff1a1SSrujanaChalla if (dram && cesa->caps->has_tdma)
536655ff1a1SSrujanaChalla mv_cesa_conf_mbus_windows(engine, dram);
537655ff1a1SSrujanaChalla
538655ff1a1SSrujanaChalla writel(0, engine->regs + CESA_SA_INT_STATUS);
539655ff1a1SSrujanaChalla writel(CESA_SA_CFG_STOP_DIG_ERR,
540655ff1a1SSrujanaChalla engine->regs + CESA_SA_CFG);
541655ff1a1SSrujanaChalla writel(engine->sram_dma & CESA_SA_SRAM_MSK,
542655ff1a1SSrujanaChalla engine->regs + CESA_SA_DESC_P0);
543655ff1a1SSrujanaChalla
544655ff1a1SSrujanaChalla ret = devm_request_threaded_irq(dev, irq, NULL, mv_cesa_int,
545655ff1a1SSrujanaChalla IRQF_ONESHOT,
546655ff1a1SSrujanaChalla dev_name(&pdev->dev),
547655ff1a1SSrujanaChalla engine);
548655ff1a1SSrujanaChalla if (ret)
549655ff1a1SSrujanaChalla goto err_cleanup;
550655ff1a1SSrujanaChalla
55128ee8b09SSven Auhagen /* Set affinity */
55228ee8b09SSven Auhagen cpu = cpumask_local_spread(engine->id, NUMA_NO_NODE);
55328ee8b09SSven Auhagen irq_set_affinity_hint(irq, get_cpu_mask(cpu));
55428ee8b09SSven Auhagen
555655ff1a1SSrujanaChalla crypto_init_queue(&engine->queue, CESA_CRYPTO_DEFAULT_MAX_QLEN);
556655ff1a1SSrujanaChalla atomic_set(&engine->load, 0);
557655ff1a1SSrujanaChalla INIT_LIST_HEAD(&engine->complete_queue);
558655ff1a1SSrujanaChalla }
559655ff1a1SSrujanaChalla
560655ff1a1SSrujanaChalla cesa_dev = cesa;
561655ff1a1SSrujanaChalla
562655ff1a1SSrujanaChalla ret = mv_cesa_add_algs(cesa);
563655ff1a1SSrujanaChalla if (ret) {
564655ff1a1SSrujanaChalla cesa_dev = NULL;
565655ff1a1SSrujanaChalla goto err_cleanup;
566655ff1a1SSrujanaChalla }
567655ff1a1SSrujanaChalla
568655ff1a1SSrujanaChalla dev_info(dev, "CESA device successfully registered\n");
569655ff1a1SSrujanaChalla
570655ff1a1SSrujanaChalla return 0;
571655ff1a1SSrujanaChalla
572655ff1a1SSrujanaChalla err_cleanup:
573655ff1a1SSrujanaChalla for (i = 0; i < caps->nengines; i++) {
574655ff1a1SSrujanaChalla clk_disable_unprepare(cesa->engines[i].zclk);
575655ff1a1SSrujanaChalla clk_disable_unprepare(cesa->engines[i].clk);
576655ff1a1SSrujanaChalla mv_cesa_put_sram(pdev, i);
57728ee8b09SSven Auhagen if (cesa->engines[i].irq > 0)
57828ee8b09SSven Auhagen irq_set_affinity_hint(cesa->engines[i].irq, NULL);
579655ff1a1SSrujanaChalla }
580655ff1a1SSrujanaChalla
581655ff1a1SSrujanaChalla return ret;
582655ff1a1SSrujanaChalla }
583655ff1a1SSrujanaChalla
mv_cesa_remove(struct platform_device * pdev)584e79de44eSUwe Kleine-König static void mv_cesa_remove(struct platform_device *pdev)
585655ff1a1SSrujanaChalla {
586655ff1a1SSrujanaChalla struct mv_cesa_dev *cesa = platform_get_drvdata(pdev);
587655ff1a1SSrujanaChalla int i;
588655ff1a1SSrujanaChalla
589655ff1a1SSrujanaChalla mv_cesa_remove_algs(cesa);
590655ff1a1SSrujanaChalla
591655ff1a1SSrujanaChalla for (i = 0; i < cesa->caps->nengines; i++) {
592655ff1a1SSrujanaChalla clk_disable_unprepare(cesa->engines[i].zclk);
593655ff1a1SSrujanaChalla clk_disable_unprepare(cesa->engines[i].clk);
594655ff1a1SSrujanaChalla mv_cesa_put_sram(pdev, i);
59528ee8b09SSven Auhagen irq_set_affinity_hint(cesa->engines[i].irq, NULL);
596655ff1a1SSrujanaChalla }
597655ff1a1SSrujanaChalla }
598655ff1a1SSrujanaChalla
599655ff1a1SSrujanaChalla static const struct platform_device_id mv_cesa_plat_id_table[] = {
600655ff1a1SSrujanaChalla { .name = "mv_crypto" },
601655ff1a1SSrujanaChalla { /* sentinel */ },
602655ff1a1SSrujanaChalla };
603655ff1a1SSrujanaChalla MODULE_DEVICE_TABLE(platform, mv_cesa_plat_id_table);
604655ff1a1SSrujanaChalla
605655ff1a1SSrujanaChalla static struct platform_driver marvell_cesa = {
606655ff1a1SSrujanaChalla .probe = mv_cesa_probe,
607e79de44eSUwe Kleine-König .remove_new = mv_cesa_remove,
608655ff1a1SSrujanaChalla .id_table = mv_cesa_plat_id_table,
609655ff1a1SSrujanaChalla .driver = {
610655ff1a1SSrujanaChalla .name = "marvell-cesa",
611655ff1a1SSrujanaChalla .of_match_table = mv_cesa_of_match_table,
612655ff1a1SSrujanaChalla },
613655ff1a1SSrujanaChalla };
614655ff1a1SSrujanaChalla module_platform_driver(marvell_cesa);
615655ff1a1SSrujanaChalla
616655ff1a1SSrujanaChalla MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");
617655ff1a1SSrujanaChalla MODULE_AUTHOR("Arnaud Ebalard <arno@natisbad.org>");
618655ff1a1SSrujanaChalla MODULE_DESCRIPTION("Support for Marvell's cryptographic engine");
619655ff1a1SSrujanaChalla MODULE_LICENSE("GPL v2");
620