1 // SPDX-License-Identifier: GPL-2.0 2 // (C) 2017-2018 Synopsys, Inc. (www.synopsys.com) 3 4 /* 5 * Synopsys DesignWare AXI DMA Controller driver. 6 * 7 * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> 8 */ 9 10 #include <linux/bitops.h> 11 #include <linux/delay.h> 12 #include <linux/device.h> 13 #include <linux/dmaengine.h> 14 #include <linux/dmapool.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/err.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/iopoll.h> 20 #include <linux/io-64-nonatomic-lo-hi.h> 21 #include <linux/kernel.h> 22 #include <linux/module.h> 23 #include <linux/of.h> 24 #include <linux/of_dma.h> 25 #include <linux/platform_device.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/property.h> 28 #include <linux/slab.h> 29 #include <linux/types.h> 30 31 #include "dw-axi-dmac.h" 32 #include "../dmaengine.h" 33 #include "../virt-dma.h" 34 35 /* 36 * The set of bus widths supported by the DMA controller. DW AXI DMAC supports 37 * master data bus width up to 512 bits (for both AXI master interfaces), but 38 * it depends on IP block configuration. 39 */ 40 #define AXI_DMA_BUSWIDTHS \ 41 (DMA_SLAVE_BUSWIDTH_1_BYTE | \ 42 DMA_SLAVE_BUSWIDTH_2_BYTES | \ 43 DMA_SLAVE_BUSWIDTH_4_BYTES | \ 44 DMA_SLAVE_BUSWIDTH_8_BYTES | \ 45 DMA_SLAVE_BUSWIDTH_16_BYTES | \ 46 DMA_SLAVE_BUSWIDTH_32_BYTES | \ 47 DMA_SLAVE_BUSWIDTH_64_BYTES) 48 49 static inline void 50 axi_dma_iowrite32(struct axi_dma_chip *chip, u32 reg, u32 val) 51 { 52 iowrite32(val, chip->regs + reg); 53 } 54 55 static inline u32 axi_dma_ioread32(struct axi_dma_chip *chip, u32 reg) 56 { 57 return ioread32(chip->regs + reg); 58 } 59 60 static inline void 61 axi_chan_iowrite32(struct axi_dma_chan *chan, u32 reg, u32 val) 62 { 63 iowrite32(val, chan->chan_regs + reg); 64 } 65 66 static inline u32 axi_chan_ioread32(struct axi_dma_chan *chan, u32 reg) 67 { 68 return ioread32(chan->chan_regs + reg); 69 } 70 71 static inline void 72 axi_chan_iowrite64(struct axi_dma_chan *chan, u32 reg, u64 val) 73 { 74 /* 75 * We split one 64 bit write for two 32 bit write as some HW doesn't 76 * support 64 bit access. 77 */ 78 iowrite32(lower_32_bits(val), chan->chan_regs + reg); 79 iowrite32(upper_32_bits(val), chan->chan_regs + reg + 4); 80 } 81 82 static inline void axi_chan_config_write(struct axi_dma_chan *chan, 83 struct axi_dma_chan_config *config) 84 { 85 u32 cfg_lo, cfg_hi; 86 87 cfg_lo = (config->dst_multblk_type << CH_CFG_L_DST_MULTBLK_TYPE_POS | 88 config->src_multblk_type << CH_CFG_L_SRC_MULTBLK_TYPE_POS); 89 if (chan->chip->dw->hdata->reg_map_8_channels) { 90 cfg_hi = config->tt_fc << CH_CFG_H_TT_FC_POS | 91 config->hs_sel_src << CH_CFG_H_HS_SEL_SRC_POS | 92 config->hs_sel_dst << CH_CFG_H_HS_SEL_DST_POS | 93 config->src_per << CH_CFG_H_SRC_PER_POS | 94 config->dst_per << CH_CFG_H_DST_PER_POS | 95 config->prior << CH_CFG_H_PRIORITY_POS; 96 } else { 97 cfg_lo |= config->src_per << CH_CFG2_L_SRC_PER_POS | 98 config->dst_per << CH_CFG2_L_DST_PER_POS; 99 cfg_hi = config->tt_fc << CH_CFG2_H_TT_FC_POS | 100 config->hs_sel_src << CH_CFG2_H_HS_SEL_SRC_POS | 101 config->hs_sel_dst << CH_CFG2_H_HS_SEL_DST_POS | 102 config->prior << CH_CFG2_H_PRIORITY_POS; 103 } 104 axi_chan_iowrite32(chan, CH_CFG_L, cfg_lo); 105 axi_chan_iowrite32(chan, CH_CFG_H, cfg_hi); 106 } 107 108 static inline void axi_dma_disable(struct axi_dma_chip *chip) 109 { 110 u32 val; 111 112 val = axi_dma_ioread32(chip, DMAC_CFG); 113 val &= ~DMAC_EN_MASK; 114 axi_dma_iowrite32(chip, DMAC_CFG, val); 115 } 116 117 static inline void axi_dma_enable(struct axi_dma_chip *chip) 118 { 119 u32 val; 120 121 val = axi_dma_ioread32(chip, DMAC_CFG); 122 val |= DMAC_EN_MASK; 123 axi_dma_iowrite32(chip, DMAC_CFG, val); 124 } 125 126 static inline void axi_dma_irq_disable(struct axi_dma_chip *chip) 127 { 128 u32 val; 129 130 val = axi_dma_ioread32(chip, DMAC_CFG); 131 val &= ~INT_EN_MASK; 132 axi_dma_iowrite32(chip, DMAC_CFG, val); 133 } 134 135 static inline void axi_dma_irq_enable(struct axi_dma_chip *chip) 136 { 137 u32 val; 138 139 val = axi_dma_ioread32(chip, DMAC_CFG); 140 val |= INT_EN_MASK; 141 axi_dma_iowrite32(chip, DMAC_CFG, val); 142 } 143 144 static inline void axi_chan_irq_disable(struct axi_dma_chan *chan, u32 irq_mask) 145 { 146 u32 val; 147 148 if (likely(irq_mask == DWAXIDMAC_IRQ_ALL)) { 149 axi_chan_iowrite32(chan, CH_INTSTATUS_ENA, DWAXIDMAC_IRQ_NONE); 150 } else { 151 val = axi_chan_ioread32(chan, CH_INTSTATUS_ENA); 152 val &= ~irq_mask; 153 axi_chan_iowrite32(chan, CH_INTSTATUS_ENA, val); 154 } 155 } 156 157 static inline void axi_chan_irq_set(struct axi_dma_chan *chan, u32 irq_mask) 158 { 159 axi_chan_iowrite32(chan, CH_INTSTATUS_ENA, irq_mask); 160 } 161 162 static inline void axi_chan_irq_sig_set(struct axi_dma_chan *chan, u32 irq_mask) 163 { 164 axi_chan_iowrite32(chan, CH_INTSIGNAL_ENA, irq_mask); 165 } 166 167 static inline void axi_chan_irq_clear(struct axi_dma_chan *chan, u32 irq_mask) 168 { 169 axi_chan_iowrite32(chan, CH_INTCLEAR, irq_mask); 170 } 171 172 static inline u32 axi_chan_irq_read(struct axi_dma_chan *chan) 173 { 174 return axi_chan_ioread32(chan, CH_INTSTATUS); 175 } 176 177 static inline void axi_chan_disable(struct axi_dma_chan *chan) 178 { 179 u32 val; 180 181 val = axi_dma_ioread32(chan->chip, DMAC_CHEN); 182 val &= ~(BIT(chan->id) << DMAC_CHAN_EN_SHIFT); 183 if (chan->chip->dw->hdata->reg_map_8_channels) 184 val |= BIT(chan->id) << DMAC_CHAN_EN_WE_SHIFT; 185 else 186 val |= BIT(chan->id) << DMAC_CHAN_EN2_WE_SHIFT; 187 axi_dma_iowrite32(chan->chip, DMAC_CHEN, val); 188 } 189 190 static inline void axi_chan_enable(struct axi_dma_chan *chan) 191 { 192 u32 val; 193 194 val = axi_dma_ioread32(chan->chip, DMAC_CHEN); 195 if (chan->chip->dw->hdata->reg_map_8_channels) 196 val |= BIT(chan->id) << DMAC_CHAN_EN_SHIFT | 197 BIT(chan->id) << DMAC_CHAN_EN_WE_SHIFT; 198 else 199 val |= BIT(chan->id) << DMAC_CHAN_EN_SHIFT | 200 BIT(chan->id) << DMAC_CHAN_EN2_WE_SHIFT; 201 axi_dma_iowrite32(chan->chip, DMAC_CHEN, val); 202 } 203 204 static inline bool axi_chan_is_hw_enable(struct axi_dma_chan *chan) 205 { 206 u32 val; 207 208 val = axi_dma_ioread32(chan->chip, DMAC_CHEN); 209 210 return !!(val & (BIT(chan->id) << DMAC_CHAN_EN_SHIFT)); 211 } 212 213 static void axi_dma_hw_init(struct axi_dma_chip *chip) 214 { 215 int ret; 216 u32 i; 217 218 for (i = 0; i < chip->dw->hdata->nr_channels; i++) { 219 axi_chan_irq_disable(&chip->dw->chan[i], DWAXIDMAC_IRQ_ALL); 220 axi_chan_disable(&chip->dw->chan[i]); 221 } 222 ret = dma_set_mask_and_coherent(chip->dev, DMA_BIT_MASK(64)); 223 if (ret) 224 dev_warn(chip->dev, "Unable to set coherent mask\n"); 225 } 226 227 static u32 axi_chan_get_xfer_width(struct axi_dma_chan *chan, dma_addr_t src, 228 dma_addr_t dst, size_t len) 229 { 230 u32 max_width = chan->chip->dw->hdata->m_data_width; 231 232 return __ffs(src | dst | len | BIT(max_width)); 233 } 234 235 static inline const char *axi_chan_name(struct axi_dma_chan *chan) 236 { 237 return dma_chan_name(&chan->vc.chan); 238 } 239 240 static struct axi_dma_desc *axi_desc_alloc(u32 num) 241 { 242 struct axi_dma_desc *desc; 243 244 desc = kzalloc(sizeof(*desc), GFP_NOWAIT); 245 if (!desc) 246 return NULL; 247 248 desc->hw_desc = kcalloc(num, sizeof(*desc->hw_desc), GFP_NOWAIT); 249 if (!desc->hw_desc) { 250 kfree(desc); 251 return NULL; 252 } 253 254 return desc; 255 } 256 257 static struct axi_dma_lli *axi_desc_get(struct axi_dma_chan *chan, 258 dma_addr_t *addr) 259 { 260 struct axi_dma_lli *lli; 261 dma_addr_t phys; 262 263 lli = dma_pool_zalloc(chan->desc_pool, GFP_NOWAIT, &phys); 264 if (unlikely(!lli)) { 265 dev_err(chan2dev(chan), "%s: not enough descriptors available\n", 266 axi_chan_name(chan)); 267 return NULL; 268 } 269 270 atomic_inc(&chan->descs_allocated); 271 *addr = phys; 272 273 return lli; 274 } 275 276 static void axi_desc_put(struct axi_dma_desc *desc) 277 { 278 struct axi_dma_chan *chan = desc->chan; 279 int count = atomic_read(&chan->descs_allocated); 280 struct axi_dma_hw_desc *hw_desc; 281 int descs_put; 282 283 for (descs_put = 0; descs_put < count; descs_put++) { 284 hw_desc = &desc->hw_desc[descs_put]; 285 dma_pool_free(chan->desc_pool, hw_desc->lli, hw_desc->llp); 286 } 287 288 kfree(desc->hw_desc); 289 kfree(desc); 290 atomic_sub(descs_put, &chan->descs_allocated); 291 dev_vdbg(chan2dev(chan), "%s: %d descs put, %d still allocated\n", 292 axi_chan_name(chan), descs_put, 293 atomic_read(&chan->descs_allocated)); 294 } 295 296 static void vchan_desc_put(struct virt_dma_desc *vdesc) 297 { 298 axi_desc_put(vd_to_axi_desc(vdesc)); 299 } 300 301 static enum dma_status 302 dma_chan_tx_status(struct dma_chan *dchan, dma_cookie_t cookie, 303 struct dma_tx_state *txstate) 304 { 305 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); 306 struct virt_dma_desc *vdesc; 307 enum dma_status status; 308 u32 completed_length; 309 unsigned long flags; 310 u32 completed_blocks; 311 size_t bytes = 0; 312 u32 length; 313 u32 len; 314 315 status = dma_cookie_status(dchan, cookie, txstate); 316 if (status == DMA_COMPLETE || !txstate) 317 return status; 318 319 spin_lock_irqsave(&chan->vc.lock, flags); 320 321 vdesc = vchan_find_desc(&chan->vc, cookie); 322 if (vdesc) { 323 length = vd_to_axi_desc(vdesc)->length; 324 completed_blocks = vd_to_axi_desc(vdesc)->completed_blocks; 325 len = vd_to_axi_desc(vdesc)->hw_desc[0].len; 326 completed_length = completed_blocks * len; 327 bytes = length - completed_length; 328 } 329 330 spin_unlock_irqrestore(&chan->vc.lock, flags); 331 dma_set_residue(txstate, bytes); 332 333 return status; 334 } 335 336 static void write_desc_llp(struct axi_dma_hw_desc *desc, dma_addr_t adr) 337 { 338 desc->lli->llp = cpu_to_le64(adr); 339 } 340 341 static void write_chan_llp(struct axi_dma_chan *chan, dma_addr_t adr) 342 { 343 axi_chan_iowrite64(chan, CH_LLP, adr); 344 } 345 346 static void dw_axi_dma_set_byte_halfword(struct axi_dma_chan *chan, bool set) 347 { 348 u32 offset = DMAC_APB_BYTE_WR_CH_EN; 349 u32 reg_width, val; 350 351 if (!chan->chip->apb_regs) { 352 dev_dbg(chan->chip->dev, "apb_regs not initialized\n"); 353 return; 354 } 355 356 reg_width = __ffs(chan->config.dst_addr_width); 357 if (reg_width == DWAXIDMAC_TRANS_WIDTH_16) 358 offset = DMAC_APB_HALFWORD_WR_CH_EN; 359 360 val = ioread32(chan->chip->apb_regs + offset); 361 362 if (set) 363 val |= BIT(chan->id); 364 else 365 val &= ~BIT(chan->id); 366 367 iowrite32(val, chan->chip->apb_regs + offset); 368 } 369 /* Called in chan locked context */ 370 static void axi_chan_block_xfer_start(struct axi_dma_chan *chan, 371 struct axi_dma_desc *first) 372 { 373 u32 priority = chan->chip->dw->hdata->priority[chan->id]; 374 struct axi_dma_chan_config config = {}; 375 u32 irq_mask; 376 u8 lms = 0; /* Select AXI0 master for LLI fetching */ 377 378 if (unlikely(axi_chan_is_hw_enable(chan))) { 379 dev_err(chan2dev(chan), "%s is non-idle!\n", 380 axi_chan_name(chan)); 381 382 return; 383 } 384 385 axi_dma_enable(chan->chip); 386 387 config.dst_multblk_type = DWAXIDMAC_MBLK_TYPE_LL; 388 config.src_multblk_type = DWAXIDMAC_MBLK_TYPE_LL; 389 config.tt_fc = DWAXIDMAC_TT_FC_MEM_TO_MEM_DMAC; 390 config.prior = priority; 391 config.hs_sel_dst = DWAXIDMAC_HS_SEL_HW; 392 config.hs_sel_src = DWAXIDMAC_HS_SEL_HW; 393 switch (chan->direction) { 394 case DMA_MEM_TO_DEV: 395 dw_axi_dma_set_byte_halfword(chan, true); 396 config.tt_fc = chan->config.device_fc ? 397 DWAXIDMAC_TT_FC_MEM_TO_PER_DST : 398 DWAXIDMAC_TT_FC_MEM_TO_PER_DMAC; 399 if (chan->chip->apb_regs) 400 config.dst_per = chan->id; 401 else 402 config.dst_per = chan->hw_handshake_num; 403 break; 404 case DMA_DEV_TO_MEM: 405 config.tt_fc = chan->config.device_fc ? 406 DWAXIDMAC_TT_FC_PER_TO_MEM_SRC : 407 DWAXIDMAC_TT_FC_PER_TO_MEM_DMAC; 408 if (chan->chip->apb_regs) 409 config.src_per = chan->id; 410 else 411 config.src_per = chan->hw_handshake_num; 412 break; 413 default: 414 break; 415 } 416 axi_chan_config_write(chan, &config); 417 418 write_chan_llp(chan, first->hw_desc[0].llp | lms); 419 420 irq_mask = DWAXIDMAC_IRQ_DMA_TRF | DWAXIDMAC_IRQ_ALL_ERR; 421 axi_chan_irq_sig_set(chan, irq_mask); 422 423 /* Generate 'suspend' status but don't generate interrupt */ 424 irq_mask |= DWAXIDMAC_IRQ_SUSPENDED; 425 axi_chan_irq_set(chan, irq_mask); 426 427 axi_chan_enable(chan); 428 } 429 430 static void axi_chan_start_first_queued(struct axi_dma_chan *chan) 431 { 432 struct axi_dma_desc *desc; 433 struct virt_dma_desc *vd; 434 435 vd = vchan_next_desc(&chan->vc); 436 if (!vd) 437 return; 438 439 desc = vd_to_axi_desc(vd); 440 dev_vdbg(chan2dev(chan), "%s: started %u\n", axi_chan_name(chan), 441 vd->tx.cookie); 442 axi_chan_block_xfer_start(chan, desc); 443 } 444 445 static void dma_chan_issue_pending(struct dma_chan *dchan) 446 { 447 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); 448 unsigned long flags; 449 450 spin_lock_irqsave(&chan->vc.lock, flags); 451 if (vchan_issue_pending(&chan->vc)) 452 axi_chan_start_first_queued(chan); 453 spin_unlock_irqrestore(&chan->vc.lock, flags); 454 } 455 456 static void dw_axi_dma_synchronize(struct dma_chan *dchan) 457 { 458 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); 459 460 vchan_synchronize(&chan->vc); 461 } 462 463 static int dma_chan_alloc_chan_resources(struct dma_chan *dchan) 464 { 465 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); 466 467 /* ASSERT: channel is idle */ 468 if (axi_chan_is_hw_enable(chan)) { 469 dev_err(chan2dev(chan), "%s is non-idle!\n", 470 axi_chan_name(chan)); 471 return -EBUSY; 472 } 473 474 /* LLI address must be aligned to a 64-byte boundary */ 475 chan->desc_pool = dma_pool_create(dev_name(chan2dev(chan)), 476 chan->chip->dev, 477 sizeof(struct axi_dma_lli), 478 64, 0); 479 if (!chan->desc_pool) { 480 dev_err(chan2dev(chan), "No memory for descriptors\n"); 481 return -ENOMEM; 482 } 483 dev_vdbg(dchan2dev(dchan), "%s: allocating\n", axi_chan_name(chan)); 484 485 pm_runtime_get(chan->chip->dev); 486 487 return 0; 488 } 489 490 static void dma_chan_free_chan_resources(struct dma_chan *dchan) 491 { 492 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); 493 494 /* ASSERT: channel is idle */ 495 if (axi_chan_is_hw_enable(chan)) 496 dev_err(dchan2dev(dchan), "%s is non-idle!\n", 497 axi_chan_name(chan)); 498 499 axi_chan_disable(chan); 500 axi_chan_irq_disable(chan, DWAXIDMAC_IRQ_ALL); 501 502 vchan_free_chan_resources(&chan->vc); 503 504 dma_pool_destroy(chan->desc_pool); 505 chan->desc_pool = NULL; 506 dev_vdbg(dchan2dev(dchan), 507 "%s: free resources, descriptor still allocated: %u\n", 508 axi_chan_name(chan), atomic_read(&chan->descs_allocated)); 509 510 pm_runtime_put(chan->chip->dev); 511 } 512 513 static void dw_axi_dma_set_hw_channel(struct axi_dma_chan *chan, bool set) 514 { 515 struct axi_dma_chip *chip = chan->chip; 516 unsigned long reg_value, val; 517 518 if (!chip->apb_regs) { 519 dev_err(chip->dev, "apb_regs not initialized\n"); 520 return; 521 } 522 523 /* 524 * An unused DMA channel has a default value of 0x3F. 525 * Lock the DMA channel by assign a handshake number to the channel. 526 * Unlock the DMA channel by assign 0x3F to the channel. 527 */ 528 if (set) 529 val = chan->hw_handshake_num; 530 else 531 val = UNUSED_CHANNEL; 532 533 reg_value = lo_hi_readq(chip->apb_regs + DMAC_APB_HW_HS_SEL_0); 534 535 /* Channel is already allocated, set handshake as per channel ID */ 536 /* 64 bit write should handle for 8 channels */ 537 538 reg_value &= ~(DMA_APB_HS_SEL_MASK << 539 (chan->id * DMA_APB_HS_SEL_BIT_SIZE)); 540 reg_value |= (val << (chan->id * DMA_APB_HS_SEL_BIT_SIZE)); 541 lo_hi_writeq(reg_value, chip->apb_regs + DMAC_APB_HW_HS_SEL_0); 542 543 return; 544 } 545 546 /* 547 * If DW_axi_dmac sees CHx_CTL.ShadowReg_Or_LLI_Last bit of the fetched LLI 548 * as 1, it understands that the current block is the final block in the 549 * transfer and completes the DMA transfer operation at the end of current 550 * block transfer. 551 */ 552 static void set_desc_last(struct axi_dma_hw_desc *desc) 553 { 554 u32 val; 555 556 val = le32_to_cpu(desc->lli->ctl_hi); 557 val |= CH_CTL_H_LLI_LAST; 558 desc->lli->ctl_hi = cpu_to_le32(val); 559 } 560 561 static void write_desc_sar(struct axi_dma_hw_desc *desc, dma_addr_t adr) 562 { 563 desc->lli->sar = cpu_to_le64(adr); 564 } 565 566 static void write_desc_dar(struct axi_dma_hw_desc *desc, dma_addr_t adr) 567 { 568 desc->lli->dar = cpu_to_le64(adr); 569 } 570 571 static void set_desc_src_master(struct axi_dma_hw_desc *desc) 572 { 573 u32 val; 574 575 /* Select AXI0 for source master */ 576 val = le32_to_cpu(desc->lli->ctl_lo); 577 val &= ~CH_CTL_L_SRC_MAST; 578 desc->lli->ctl_lo = cpu_to_le32(val); 579 } 580 581 static void set_desc_dest_master(struct axi_dma_hw_desc *hw_desc, 582 struct axi_dma_desc *desc) 583 { 584 u32 val; 585 586 /* Select AXI1 for source master if available */ 587 val = le32_to_cpu(hw_desc->lli->ctl_lo); 588 if (desc->chan->chip->dw->hdata->nr_masters > 1) 589 val |= CH_CTL_L_DST_MAST; 590 else 591 val &= ~CH_CTL_L_DST_MAST; 592 593 hw_desc->lli->ctl_lo = cpu_to_le32(val); 594 } 595 596 static int dw_axi_dma_set_hw_desc(struct axi_dma_chan *chan, 597 struct axi_dma_hw_desc *hw_desc, 598 dma_addr_t mem_addr, size_t len) 599 { 600 unsigned int data_width = BIT(chan->chip->dw->hdata->m_data_width); 601 unsigned int reg_width; 602 unsigned int mem_width; 603 dma_addr_t device_addr; 604 size_t axi_block_ts; 605 size_t block_ts; 606 u32 ctllo, ctlhi; 607 u32 burst_len; 608 609 axi_block_ts = chan->chip->dw->hdata->block_size[chan->id]; 610 611 mem_width = __ffs(data_width | mem_addr | len); 612 if (mem_width > DWAXIDMAC_TRANS_WIDTH_32) 613 mem_width = DWAXIDMAC_TRANS_WIDTH_32; 614 615 if (!IS_ALIGNED(mem_addr, 4)) { 616 dev_err(chan->chip->dev, "invalid buffer alignment\n"); 617 return -EINVAL; 618 } 619 620 switch (chan->direction) { 621 case DMA_MEM_TO_DEV: 622 reg_width = __ffs(chan->config.dst_addr_width); 623 device_addr = chan->config.dst_addr; 624 ctllo = reg_width << CH_CTL_L_DST_WIDTH_POS | 625 mem_width << CH_CTL_L_SRC_WIDTH_POS | 626 DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_DST_INC_POS | 627 DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_SRC_INC_POS; 628 block_ts = len >> mem_width; 629 break; 630 case DMA_DEV_TO_MEM: 631 reg_width = __ffs(chan->config.src_addr_width); 632 device_addr = chan->config.src_addr; 633 ctllo = reg_width << CH_CTL_L_SRC_WIDTH_POS | 634 mem_width << CH_CTL_L_DST_WIDTH_POS | 635 DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_DST_INC_POS | 636 DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_SRC_INC_POS; 637 block_ts = len >> reg_width; 638 break; 639 default: 640 return -EINVAL; 641 } 642 643 if (block_ts > axi_block_ts) 644 return -EINVAL; 645 646 hw_desc->lli = axi_desc_get(chan, &hw_desc->llp); 647 if (unlikely(!hw_desc->lli)) 648 return -ENOMEM; 649 650 ctlhi = CH_CTL_H_LLI_VALID; 651 652 if (chan->chip->dw->hdata->restrict_axi_burst_len) { 653 burst_len = chan->chip->dw->hdata->axi_rw_burst_len; 654 ctlhi |= CH_CTL_H_ARLEN_EN | CH_CTL_H_AWLEN_EN | 655 burst_len << CH_CTL_H_ARLEN_POS | 656 burst_len << CH_CTL_H_AWLEN_POS; 657 } 658 659 hw_desc->lli->ctl_hi = cpu_to_le32(ctlhi); 660 661 if (chan->direction == DMA_MEM_TO_DEV) { 662 write_desc_sar(hw_desc, mem_addr); 663 write_desc_dar(hw_desc, device_addr); 664 } else { 665 write_desc_sar(hw_desc, device_addr); 666 write_desc_dar(hw_desc, mem_addr); 667 } 668 669 hw_desc->lli->block_ts_lo = cpu_to_le32(block_ts - 1); 670 671 ctllo |= DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_DST_MSIZE_POS | 672 DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_SRC_MSIZE_POS; 673 hw_desc->lli->ctl_lo = cpu_to_le32(ctllo); 674 675 set_desc_src_master(hw_desc); 676 677 hw_desc->len = len; 678 return 0; 679 } 680 681 static size_t calculate_block_len(struct axi_dma_chan *chan, 682 dma_addr_t dma_addr, size_t buf_len, 683 enum dma_transfer_direction direction) 684 { 685 u32 data_width, reg_width, mem_width; 686 size_t axi_block_ts, block_len; 687 688 axi_block_ts = chan->chip->dw->hdata->block_size[chan->id]; 689 690 switch (direction) { 691 case DMA_MEM_TO_DEV: 692 data_width = BIT(chan->chip->dw->hdata->m_data_width); 693 mem_width = __ffs(data_width | dma_addr | buf_len); 694 if (mem_width > DWAXIDMAC_TRANS_WIDTH_32) 695 mem_width = DWAXIDMAC_TRANS_WIDTH_32; 696 697 block_len = axi_block_ts << mem_width; 698 break; 699 case DMA_DEV_TO_MEM: 700 reg_width = __ffs(chan->config.src_addr_width); 701 block_len = axi_block_ts << reg_width; 702 break; 703 default: 704 block_len = 0; 705 } 706 707 return block_len; 708 } 709 710 static struct dma_async_tx_descriptor * 711 dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan, dma_addr_t dma_addr, 712 size_t buf_len, size_t period_len, 713 enum dma_transfer_direction direction, 714 unsigned long flags) 715 { 716 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); 717 struct axi_dma_hw_desc *hw_desc = NULL; 718 struct axi_dma_desc *desc = NULL; 719 dma_addr_t src_addr = dma_addr; 720 u32 num_periods, num_segments; 721 size_t axi_block_len; 722 u32 total_segments; 723 u32 segment_len; 724 unsigned int i; 725 int status; 726 u64 llp = 0; 727 u8 lms = 0; /* Select AXI0 master for LLI fetching */ 728 729 num_periods = buf_len / period_len; 730 731 axi_block_len = calculate_block_len(chan, dma_addr, buf_len, direction); 732 if (axi_block_len == 0) 733 return NULL; 734 735 num_segments = DIV_ROUND_UP(period_len, axi_block_len); 736 segment_len = DIV_ROUND_UP(period_len, num_segments); 737 738 total_segments = num_periods * num_segments; 739 740 desc = axi_desc_alloc(total_segments); 741 if (unlikely(!desc)) 742 goto err_desc_get; 743 744 chan->direction = direction; 745 desc->chan = chan; 746 chan->cyclic = true; 747 desc->length = 0; 748 desc->period_len = period_len; 749 750 for (i = 0; i < total_segments; i++) { 751 hw_desc = &desc->hw_desc[i]; 752 753 status = dw_axi_dma_set_hw_desc(chan, hw_desc, src_addr, 754 segment_len); 755 if (status < 0) 756 goto err_desc_get; 757 758 desc->length += hw_desc->len; 759 /* Set end-of-link to the linked descriptor, so that cyclic 760 * callback function can be triggered during interrupt. 761 */ 762 set_desc_last(hw_desc); 763 764 src_addr += segment_len; 765 } 766 767 llp = desc->hw_desc[0].llp; 768 769 /* Managed transfer list */ 770 do { 771 hw_desc = &desc->hw_desc[--total_segments]; 772 write_desc_llp(hw_desc, llp | lms); 773 llp = hw_desc->llp; 774 } while (total_segments); 775 776 dw_axi_dma_set_hw_channel(chan, true); 777 778 return vchan_tx_prep(&chan->vc, &desc->vd, flags); 779 780 err_desc_get: 781 if (desc) 782 axi_desc_put(desc); 783 784 return NULL; 785 } 786 787 static struct dma_async_tx_descriptor * 788 dw_axi_dma_chan_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl, 789 unsigned int sg_len, 790 enum dma_transfer_direction direction, 791 unsigned long flags, void *context) 792 { 793 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); 794 struct axi_dma_hw_desc *hw_desc = NULL; 795 struct axi_dma_desc *desc = NULL; 796 u32 num_segments, segment_len; 797 unsigned int loop = 0; 798 struct scatterlist *sg; 799 size_t axi_block_len; 800 u32 len, num_sgs = 0; 801 unsigned int i; 802 dma_addr_t mem; 803 int status; 804 u64 llp = 0; 805 u8 lms = 0; /* Select AXI0 master for LLI fetching */ 806 807 if (unlikely(!is_slave_direction(direction) || !sg_len)) 808 return NULL; 809 810 mem = sg_dma_address(sgl); 811 len = sg_dma_len(sgl); 812 813 axi_block_len = calculate_block_len(chan, mem, len, direction); 814 if (axi_block_len == 0) 815 return NULL; 816 817 for_each_sg(sgl, sg, sg_len, i) 818 num_sgs += DIV_ROUND_UP(sg_dma_len(sg), axi_block_len); 819 820 desc = axi_desc_alloc(num_sgs); 821 if (unlikely(!desc)) 822 goto err_desc_get; 823 824 desc->chan = chan; 825 desc->length = 0; 826 chan->direction = direction; 827 828 for_each_sg(sgl, sg, sg_len, i) { 829 mem = sg_dma_address(sg); 830 len = sg_dma_len(sg); 831 num_segments = DIV_ROUND_UP(sg_dma_len(sg), axi_block_len); 832 segment_len = DIV_ROUND_UP(sg_dma_len(sg), num_segments); 833 834 do { 835 hw_desc = &desc->hw_desc[loop++]; 836 status = dw_axi_dma_set_hw_desc(chan, hw_desc, mem, segment_len); 837 if (status < 0) 838 goto err_desc_get; 839 840 desc->length += hw_desc->len; 841 len -= segment_len; 842 mem += segment_len; 843 } while (len >= segment_len); 844 } 845 846 /* Set end-of-link to the last link descriptor of list */ 847 set_desc_last(&desc->hw_desc[num_sgs - 1]); 848 849 /* Managed transfer list */ 850 do { 851 hw_desc = &desc->hw_desc[--num_sgs]; 852 write_desc_llp(hw_desc, llp | lms); 853 llp = hw_desc->llp; 854 } while (num_sgs); 855 856 dw_axi_dma_set_hw_channel(chan, true); 857 858 return vchan_tx_prep(&chan->vc, &desc->vd, flags); 859 860 err_desc_get: 861 if (desc) 862 axi_desc_put(desc); 863 864 return NULL; 865 } 866 867 static struct dma_async_tx_descriptor * 868 dma_chan_prep_dma_memcpy(struct dma_chan *dchan, dma_addr_t dst_adr, 869 dma_addr_t src_adr, size_t len, unsigned long flags) 870 { 871 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); 872 size_t block_ts, max_block_ts, xfer_len; 873 struct axi_dma_hw_desc *hw_desc = NULL; 874 struct axi_dma_desc *desc = NULL; 875 u32 xfer_width, reg, num; 876 u64 llp = 0; 877 u8 lms = 0; /* Select AXI0 master for LLI fetching */ 878 879 dev_dbg(chan2dev(chan), "%s: memcpy: src: %pad dst: %pad length: %zd flags: %#lx", 880 axi_chan_name(chan), &src_adr, &dst_adr, len, flags); 881 882 max_block_ts = chan->chip->dw->hdata->block_size[chan->id]; 883 xfer_width = axi_chan_get_xfer_width(chan, src_adr, dst_adr, len); 884 num = DIV_ROUND_UP(len, max_block_ts << xfer_width); 885 desc = axi_desc_alloc(num); 886 if (unlikely(!desc)) 887 goto err_desc_get; 888 889 desc->chan = chan; 890 num = 0; 891 desc->length = 0; 892 while (len) { 893 xfer_len = len; 894 895 hw_desc = &desc->hw_desc[num]; 896 /* 897 * Take care for the alignment. 898 * Actually source and destination widths can be different, but 899 * make them same to be simpler. 900 */ 901 xfer_width = axi_chan_get_xfer_width(chan, src_adr, dst_adr, xfer_len); 902 903 /* 904 * block_ts indicates the total number of data of width 905 * to be transferred in a DMA block transfer. 906 * BLOCK_TS register should be set to block_ts - 1 907 */ 908 block_ts = xfer_len >> xfer_width; 909 if (block_ts > max_block_ts) { 910 block_ts = max_block_ts; 911 xfer_len = max_block_ts << xfer_width; 912 } 913 914 hw_desc->lli = axi_desc_get(chan, &hw_desc->llp); 915 if (unlikely(!hw_desc->lli)) 916 goto err_desc_get; 917 918 write_desc_sar(hw_desc, src_adr); 919 write_desc_dar(hw_desc, dst_adr); 920 hw_desc->lli->block_ts_lo = cpu_to_le32(block_ts - 1); 921 922 reg = CH_CTL_H_LLI_VALID; 923 if (chan->chip->dw->hdata->restrict_axi_burst_len) { 924 u32 burst_len = chan->chip->dw->hdata->axi_rw_burst_len; 925 926 reg |= (CH_CTL_H_ARLEN_EN | 927 burst_len << CH_CTL_H_ARLEN_POS | 928 CH_CTL_H_AWLEN_EN | 929 burst_len << CH_CTL_H_AWLEN_POS); 930 } 931 hw_desc->lli->ctl_hi = cpu_to_le32(reg); 932 933 reg = (DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_DST_MSIZE_POS | 934 DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_SRC_MSIZE_POS | 935 xfer_width << CH_CTL_L_DST_WIDTH_POS | 936 xfer_width << CH_CTL_L_SRC_WIDTH_POS | 937 DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_DST_INC_POS | 938 DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_SRC_INC_POS); 939 hw_desc->lli->ctl_lo = cpu_to_le32(reg); 940 941 set_desc_src_master(hw_desc); 942 set_desc_dest_master(hw_desc, desc); 943 944 hw_desc->len = xfer_len; 945 desc->length += hw_desc->len; 946 /* update the length and addresses for the next loop cycle */ 947 len -= xfer_len; 948 dst_adr += xfer_len; 949 src_adr += xfer_len; 950 num++; 951 } 952 953 /* Set end-of-link to the last link descriptor of list */ 954 set_desc_last(&desc->hw_desc[num - 1]); 955 /* Managed transfer list */ 956 do { 957 hw_desc = &desc->hw_desc[--num]; 958 write_desc_llp(hw_desc, llp | lms); 959 llp = hw_desc->llp; 960 } while (num); 961 962 return vchan_tx_prep(&chan->vc, &desc->vd, flags); 963 964 err_desc_get: 965 if (desc) 966 axi_desc_put(desc); 967 return NULL; 968 } 969 970 static int dw_axi_dma_chan_slave_config(struct dma_chan *dchan, 971 struct dma_slave_config *config) 972 { 973 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); 974 975 memcpy(&chan->config, config, sizeof(*config)); 976 977 return 0; 978 } 979 980 static void axi_chan_dump_lli(struct axi_dma_chan *chan, 981 struct axi_dma_hw_desc *desc) 982 { 983 if (!desc->lli) { 984 dev_err(dchan2dev(&chan->vc.chan), "NULL LLI\n"); 985 return; 986 } 987 988 dev_err(dchan2dev(&chan->vc.chan), 989 "SAR: 0x%llx DAR: 0x%llx LLP: 0x%llx BTS 0x%x CTL: 0x%x:%08x", 990 le64_to_cpu(desc->lli->sar), 991 le64_to_cpu(desc->lli->dar), 992 le64_to_cpu(desc->lli->llp), 993 le32_to_cpu(desc->lli->block_ts_lo), 994 le32_to_cpu(desc->lli->ctl_hi), 995 le32_to_cpu(desc->lli->ctl_lo)); 996 } 997 998 static void axi_chan_list_dump_lli(struct axi_dma_chan *chan, 999 struct axi_dma_desc *desc_head) 1000 { 1001 int count = atomic_read(&chan->descs_allocated); 1002 int i; 1003 1004 for (i = 0; i < count; i++) 1005 axi_chan_dump_lli(chan, &desc_head->hw_desc[i]); 1006 } 1007 1008 static noinline void axi_chan_handle_err(struct axi_dma_chan *chan, u32 status) 1009 { 1010 struct virt_dma_desc *vd; 1011 unsigned long flags; 1012 1013 spin_lock_irqsave(&chan->vc.lock, flags); 1014 1015 axi_chan_disable(chan); 1016 1017 /* The bad descriptor currently is in the head of vc list */ 1018 vd = vchan_next_desc(&chan->vc); 1019 if (!vd) { 1020 dev_err(chan2dev(chan), "BUG: %s, IRQ with no descriptors\n", 1021 axi_chan_name(chan)); 1022 goto out; 1023 } 1024 /* Remove the completed descriptor from issued list */ 1025 list_del(&vd->node); 1026 1027 /* WARN about bad descriptor */ 1028 dev_err(chan2dev(chan), 1029 "Bad descriptor submitted for %s, cookie: %d, irq: 0x%08x\n", 1030 axi_chan_name(chan), vd->tx.cookie, status); 1031 axi_chan_list_dump_lli(chan, vd_to_axi_desc(vd)); 1032 1033 vchan_cookie_complete(vd); 1034 1035 /* Try to restart the controller */ 1036 axi_chan_start_first_queued(chan); 1037 1038 out: 1039 spin_unlock_irqrestore(&chan->vc.lock, flags); 1040 } 1041 1042 static void axi_chan_block_xfer_complete(struct axi_dma_chan *chan) 1043 { 1044 int count = atomic_read(&chan->descs_allocated); 1045 struct axi_dma_hw_desc *hw_desc; 1046 struct axi_dma_desc *desc; 1047 struct virt_dma_desc *vd; 1048 unsigned long flags; 1049 u64 llp; 1050 int i; 1051 1052 spin_lock_irqsave(&chan->vc.lock, flags); 1053 if (unlikely(axi_chan_is_hw_enable(chan))) { 1054 dev_err(chan2dev(chan), "BUG: %s caught DWAXIDMAC_IRQ_DMA_TRF, but channel not idle!\n", 1055 axi_chan_name(chan)); 1056 axi_chan_disable(chan); 1057 } 1058 1059 /* The completed descriptor currently is in the head of vc list */ 1060 vd = vchan_next_desc(&chan->vc); 1061 if (!vd) { 1062 dev_err(chan2dev(chan), "BUG: %s, IRQ with no descriptors\n", 1063 axi_chan_name(chan)); 1064 goto out; 1065 } 1066 1067 if (chan->cyclic) { 1068 desc = vd_to_axi_desc(vd); 1069 if (desc) { 1070 llp = lo_hi_readq(chan->chan_regs + CH_LLP); 1071 for (i = 0; i < count; i++) { 1072 hw_desc = &desc->hw_desc[i]; 1073 if (hw_desc->llp == llp) { 1074 axi_chan_irq_clear(chan, hw_desc->lli->status_lo); 1075 hw_desc->lli->ctl_hi |= CH_CTL_H_LLI_VALID; 1076 desc->completed_blocks = i; 1077 1078 if (((hw_desc->len * (i + 1)) % desc->period_len) == 0) 1079 vchan_cyclic_callback(vd); 1080 break; 1081 } 1082 } 1083 1084 axi_chan_enable(chan); 1085 } 1086 } else { 1087 /* Remove the completed descriptor from issued list before completing */ 1088 list_del(&vd->node); 1089 vchan_cookie_complete(vd); 1090 1091 /* Submit queued descriptors after processing the completed ones */ 1092 axi_chan_start_first_queued(chan); 1093 } 1094 1095 out: 1096 spin_unlock_irqrestore(&chan->vc.lock, flags); 1097 } 1098 1099 static irqreturn_t dw_axi_dma_interrupt(int irq, void *dev_id) 1100 { 1101 struct axi_dma_chip *chip = dev_id; 1102 struct dw_axi_dma *dw = chip->dw; 1103 struct axi_dma_chan *chan; 1104 1105 u32 status, i; 1106 1107 /* Disable DMAC interrupts. We'll enable them after processing channels */ 1108 axi_dma_irq_disable(chip); 1109 1110 /* Poll, clear and process every channel interrupt status */ 1111 for (i = 0; i < dw->hdata->nr_channels; i++) { 1112 chan = &dw->chan[i]; 1113 status = axi_chan_irq_read(chan); 1114 axi_chan_irq_clear(chan, status); 1115 1116 dev_vdbg(chip->dev, "%s %u IRQ status: 0x%08x\n", 1117 axi_chan_name(chan), i, status); 1118 1119 if (status & DWAXIDMAC_IRQ_ALL_ERR) 1120 axi_chan_handle_err(chan, status); 1121 else if (status & DWAXIDMAC_IRQ_DMA_TRF) 1122 axi_chan_block_xfer_complete(chan); 1123 } 1124 1125 /* Re-enable interrupts */ 1126 axi_dma_irq_enable(chip); 1127 1128 return IRQ_HANDLED; 1129 } 1130 1131 static int dma_chan_terminate_all(struct dma_chan *dchan) 1132 { 1133 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); 1134 u32 chan_active = BIT(chan->id) << DMAC_CHAN_EN_SHIFT; 1135 unsigned long flags; 1136 u32 val; 1137 int ret; 1138 LIST_HEAD(head); 1139 1140 axi_chan_disable(chan); 1141 1142 ret = readl_poll_timeout_atomic(chan->chip->regs + DMAC_CHEN, val, 1143 !(val & chan_active), 1000, 10000); 1144 if (ret == -ETIMEDOUT) 1145 dev_warn(dchan2dev(dchan), 1146 "%s failed to stop\n", axi_chan_name(chan)); 1147 1148 if (chan->direction != DMA_MEM_TO_MEM) 1149 dw_axi_dma_set_hw_channel(chan, false); 1150 if (chan->direction == DMA_MEM_TO_DEV) 1151 dw_axi_dma_set_byte_halfword(chan, false); 1152 1153 spin_lock_irqsave(&chan->vc.lock, flags); 1154 1155 vchan_get_all_descriptors(&chan->vc, &head); 1156 1157 chan->cyclic = false; 1158 spin_unlock_irqrestore(&chan->vc.lock, flags); 1159 1160 vchan_dma_desc_free_list(&chan->vc, &head); 1161 1162 dev_vdbg(dchan2dev(dchan), "terminated: %s\n", axi_chan_name(chan)); 1163 1164 return 0; 1165 } 1166 1167 static int dma_chan_pause(struct dma_chan *dchan) 1168 { 1169 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); 1170 unsigned long flags; 1171 unsigned int timeout = 20; /* timeout iterations */ 1172 u32 val; 1173 1174 spin_lock_irqsave(&chan->vc.lock, flags); 1175 1176 if (chan->chip->dw->hdata->reg_map_8_channels) { 1177 val = axi_dma_ioread32(chan->chip, DMAC_CHEN); 1178 val |= BIT(chan->id) << DMAC_CHAN_SUSP_SHIFT | 1179 BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT; 1180 axi_dma_iowrite32(chan->chip, DMAC_CHEN, val); 1181 } else { 1182 val = axi_dma_ioread32(chan->chip, DMAC_CHSUSPREG); 1183 val |= BIT(chan->id) << DMAC_CHAN_SUSP2_SHIFT | 1184 BIT(chan->id) << DMAC_CHAN_SUSP2_WE_SHIFT; 1185 axi_dma_iowrite32(chan->chip, DMAC_CHSUSPREG, val); 1186 } 1187 1188 do { 1189 if (axi_chan_irq_read(chan) & DWAXIDMAC_IRQ_SUSPENDED) 1190 break; 1191 1192 udelay(2); 1193 } while (--timeout); 1194 1195 axi_chan_irq_clear(chan, DWAXIDMAC_IRQ_SUSPENDED); 1196 1197 chan->is_paused = true; 1198 1199 spin_unlock_irqrestore(&chan->vc.lock, flags); 1200 1201 return timeout ? 0 : -EAGAIN; 1202 } 1203 1204 /* Called in chan locked context */ 1205 static inline void axi_chan_resume(struct axi_dma_chan *chan) 1206 { 1207 u32 val; 1208 1209 if (chan->chip->dw->hdata->reg_map_8_channels) { 1210 val = axi_dma_ioread32(chan->chip, DMAC_CHEN); 1211 val &= ~(BIT(chan->id) << DMAC_CHAN_SUSP_SHIFT); 1212 val |= (BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT); 1213 axi_dma_iowrite32(chan->chip, DMAC_CHEN, val); 1214 } else { 1215 val = axi_dma_ioread32(chan->chip, DMAC_CHSUSPREG); 1216 val &= ~(BIT(chan->id) << DMAC_CHAN_SUSP2_SHIFT); 1217 val |= (BIT(chan->id) << DMAC_CHAN_SUSP2_WE_SHIFT); 1218 axi_dma_iowrite32(chan->chip, DMAC_CHSUSPREG, val); 1219 } 1220 1221 chan->is_paused = false; 1222 } 1223 1224 static int dma_chan_resume(struct dma_chan *dchan) 1225 { 1226 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); 1227 unsigned long flags; 1228 1229 spin_lock_irqsave(&chan->vc.lock, flags); 1230 1231 if (chan->is_paused) 1232 axi_chan_resume(chan); 1233 1234 spin_unlock_irqrestore(&chan->vc.lock, flags); 1235 1236 return 0; 1237 } 1238 1239 static int axi_dma_suspend(struct axi_dma_chip *chip) 1240 { 1241 axi_dma_irq_disable(chip); 1242 axi_dma_disable(chip); 1243 1244 clk_disable_unprepare(chip->core_clk); 1245 clk_disable_unprepare(chip->cfgr_clk); 1246 1247 return 0; 1248 } 1249 1250 static int axi_dma_resume(struct axi_dma_chip *chip) 1251 { 1252 int ret; 1253 1254 ret = clk_prepare_enable(chip->cfgr_clk); 1255 if (ret < 0) 1256 return ret; 1257 1258 ret = clk_prepare_enable(chip->core_clk); 1259 if (ret < 0) 1260 return ret; 1261 1262 axi_dma_enable(chip); 1263 axi_dma_irq_enable(chip); 1264 1265 return 0; 1266 } 1267 1268 static int __maybe_unused axi_dma_runtime_suspend(struct device *dev) 1269 { 1270 struct axi_dma_chip *chip = dev_get_drvdata(dev); 1271 1272 return axi_dma_suspend(chip); 1273 } 1274 1275 static int __maybe_unused axi_dma_runtime_resume(struct device *dev) 1276 { 1277 struct axi_dma_chip *chip = dev_get_drvdata(dev); 1278 1279 return axi_dma_resume(chip); 1280 } 1281 1282 static struct dma_chan *dw_axi_dma_of_xlate(struct of_phandle_args *dma_spec, 1283 struct of_dma *ofdma) 1284 { 1285 struct dw_axi_dma *dw = ofdma->of_dma_data; 1286 struct axi_dma_chan *chan; 1287 struct dma_chan *dchan; 1288 1289 dchan = dma_get_any_slave_channel(&dw->dma); 1290 if (!dchan) 1291 return NULL; 1292 1293 chan = dchan_to_axi_dma_chan(dchan); 1294 chan->hw_handshake_num = dma_spec->args[0]; 1295 return dchan; 1296 } 1297 1298 static int parse_device_properties(struct axi_dma_chip *chip) 1299 { 1300 struct device *dev = chip->dev; 1301 u32 tmp, carr[DMAC_MAX_CHANNELS]; 1302 int ret; 1303 1304 ret = device_property_read_u32(dev, "dma-channels", &tmp); 1305 if (ret) 1306 return ret; 1307 if (tmp == 0 || tmp > DMAC_MAX_CHANNELS) 1308 return -EINVAL; 1309 1310 chip->dw->hdata->nr_channels = tmp; 1311 if (tmp <= DMA_REG_MAP_CH_REF) 1312 chip->dw->hdata->reg_map_8_channels = true; 1313 1314 ret = device_property_read_u32(dev, "snps,dma-masters", &tmp); 1315 if (ret) 1316 return ret; 1317 if (tmp == 0 || tmp > DMAC_MAX_MASTERS) 1318 return -EINVAL; 1319 1320 chip->dw->hdata->nr_masters = tmp; 1321 1322 ret = device_property_read_u32(dev, "snps,data-width", &tmp); 1323 if (ret) 1324 return ret; 1325 if (tmp > DWAXIDMAC_TRANS_WIDTH_MAX) 1326 return -EINVAL; 1327 1328 chip->dw->hdata->m_data_width = tmp; 1329 1330 ret = device_property_read_u32_array(dev, "snps,block-size", carr, 1331 chip->dw->hdata->nr_channels); 1332 if (ret) 1333 return ret; 1334 for (tmp = 0; tmp < chip->dw->hdata->nr_channels; tmp++) { 1335 if (carr[tmp] == 0 || carr[tmp] > DMAC_MAX_BLK_SIZE) 1336 return -EINVAL; 1337 1338 chip->dw->hdata->block_size[tmp] = carr[tmp]; 1339 } 1340 1341 ret = device_property_read_u32_array(dev, "snps,priority", carr, 1342 chip->dw->hdata->nr_channels); 1343 if (ret) 1344 return ret; 1345 /* Priority value must be programmed within [0:nr_channels-1] range */ 1346 for (tmp = 0; tmp < chip->dw->hdata->nr_channels; tmp++) { 1347 if (carr[tmp] >= chip->dw->hdata->nr_channels) 1348 return -EINVAL; 1349 1350 chip->dw->hdata->priority[tmp] = carr[tmp]; 1351 } 1352 1353 /* axi-max-burst-len is optional property */ 1354 ret = device_property_read_u32(dev, "snps,axi-max-burst-len", &tmp); 1355 if (!ret) { 1356 if (tmp > DWAXIDMAC_ARWLEN_MAX + 1) 1357 return -EINVAL; 1358 if (tmp < DWAXIDMAC_ARWLEN_MIN + 1) 1359 return -EINVAL; 1360 1361 chip->dw->hdata->restrict_axi_burst_len = true; 1362 chip->dw->hdata->axi_rw_burst_len = tmp; 1363 } 1364 1365 return 0; 1366 } 1367 1368 static int dw_probe(struct platform_device *pdev) 1369 { 1370 struct device_node *node = pdev->dev.of_node; 1371 struct axi_dma_chip *chip; 1372 struct dw_axi_dma *dw; 1373 struct dw_axi_dma_hcfg *hdata; 1374 u32 i; 1375 int ret; 1376 1377 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 1378 if (!chip) 1379 return -ENOMEM; 1380 1381 dw = devm_kzalloc(&pdev->dev, sizeof(*dw), GFP_KERNEL); 1382 if (!dw) 1383 return -ENOMEM; 1384 1385 hdata = devm_kzalloc(&pdev->dev, sizeof(*hdata), GFP_KERNEL); 1386 if (!hdata) 1387 return -ENOMEM; 1388 1389 chip->dw = dw; 1390 chip->dev = &pdev->dev; 1391 chip->dw->hdata = hdata; 1392 1393 chip->irq = platform_get_irq(pdev, 0); 1394 if (chip->irq < 0) 1395 return chip->irq; 1396 1397 chip->regs = devm_platform_ioremap_resource(pdev, 0); 1398 if (IS_ERR(chip->regs)) 1399 return PTR_ERR(chip->regs); 1400 1401 if (of_device_is_compatible(node, "intel,kmb-axi-dma")) { 1402 chip->apb_regs = devm_platform_ioremap_resource(pdev, 1); 1403 if (IS_ERR(chip->apb_regs)) 1404 return PTR_ERR(chip->apb_regs); 1405 } 1406 1407 chip->core_clk = devm_clk_get(chip->dev, "core-clk"); 1408 if (IS_ERR(chip->core_clk)) 1409 return PTR_ERR(chip->core_clk); 1410 1411 chip->cfgr_clk = devm_clk_get(chip->dev, "cfgr-clk"); 1412 if (IS_ERR(chip->cfgr_clk)) 1413 return PTR_ERR(chip->cfgr_clk); 1414 1415 ret = parse_device_properties(chip); 1416 if (ret) 1417 return ret; 1418 1419 dw->chan = devm_kcalloc(chip->dev, hdata->nr_channels, 1420 sizeof(*dw->chan), GFP_KERNEL); 1421 if (!dw->chan) 1422 return -ENOMEM; 1423 1424 ret = devm_request_irq(chip->dev, chip->irq, dw_axi_dma_interrupt, 1425 IRQF_SHARED, KBUILD_MODNAME, chip); 1426 if (ret) 1427 return ret; 1428 1429 INIT_LIST_HEAD(&dw->dma.channels); 1430 for (i = 0; i < hdata->nr_channels; i++) { 1431 struct axi_dma_chan *chan = &dw->chan[i]; 1432 1433 chan->chip = chip; 1434 chan->id = i; 1435 chan->chan_regs = chip->regs + COMMON_REG_LEN + i * CHAN_REG_LEN; 1436 atomic_set(&chan->descs_allocated, 0); 1437 1438 chan->vc.desc_free = vchan_desc_put; 1439 vchan_init(&chan->vc, &dw->dma); 1440 } 1441 1442 /* Set capabilities */ 1443 dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask); 1444 dma_cap_set(DMA_SLAVE, dw->dma.cap_mask); 1445 dma_cap_set(DMA_CYCLIC, dw->dma.cap_mask); 1446 1447 /* DMA capabilities */ 1448 dw->dma.chancnt = hdata->nr_channels; 1449 dw->dma.max_burst = hdata->axi_rw_burst_len; 1450 dw->dma.src_addr_widths = AXI_DMA_BUSWIDTHS; 1451 dw->dma.dst_addr_widths = AXI_DMA_BUSWIDTHS; 1452 dw->dma.directions = BIT(DMA_MEM_TO_MEM); 1453 dw->dma.directions |= BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM); 1454 dw->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; 1455 1456 dw->dma.dev = chip->dev; 1457 dw->dma.device_tx_status = dma_chan_tx_status; 1458 dw->dma.device_issue_pending = dma_chan_issue_pending; 1459 dw->dma.device_terminate_all = dma_chan_terminate_all; 1460 dw->dma.device_pause = dma_chan_pause; 1461 dw->dma.device_resume = dma_chan_resume; 1462 1463 dw->dma.device_alloc_chan_resources = dma_chan_alloc_chan_resources; 1464 dw->dma.device_free_chan_resources = dma_chan_free_chan_resources; 1465 1466 dw->dma.device_prep_dma_memcpy = dma_chan_prep_dma_memcpy; 1467 dw->dma.device_synchronize = dw_axi_dma_synchronize; 1468 dw->dma.device_config = dw_axi_dma_chan_slave_config; 1469 dw->dma.device_prep_slave_sg = dw_axi_dma_chan_prep_slave_sg; 1470 dw->dma.device_prep_dma_cyclic = dw_axi_dma_chan_prep_cyclic; 1471 1472 /* 1473 * Synopsis DesignWare AxiDMA datasheet mentioned Maximum 1474 * supported blocks is 1024. Device register width is 4 bytes. 1475 * Therefore, set constraint to 1024 * 4. 1476 */ 1477 dw->dma.dev->dma_parms = &dw->dma_parms; 1478 dma_set_max_seg_size(&pdev->dev, MAX_BLOCK_SIZE); 1479 platform_set_drvdata(pdev, chip); 1480 1481 pm_runtime_enable(chip->dev); 1482 1483 /* 1484 * We can't just call pm_runtime_get here instead of 1485 * pm_runtime_get_noresume + axi_dma_resume because we need 1486 * driver to work also without Runtime PM. 1487 */ 1488 pm_runtime_get_noresume(chip->dev); 1489 ret = axi_dma_resume(chip); 1490 if (ret < 0) 1491 goto err_pm_disable; 1492 1493 axi_dma_hw_init(chip); 1494 1495 pm_runtime_put(chip->dev); 1496 1497 ret = dmaenginem_async_device_register(&dw->dma); 1498 if (ret) 1499 goto err_pm_disable; 1500 1501 /* Register with OF helpers for DMA lookups */ 1502 ret = of_dma_controller_register(pdev->dev.of_node, 1503 dw_axi_dma_of_xlate, dw); 1504 if (ret < 0) 1505 dev_warn(&pdev->dev, 1506 "Failed to register OF DMA controller, fallback to MEM_TO_MEM mode\n"); 1507 1508 dev_info(chip->dev, "DesignWare AXI DMA Controller, %d channels\n", 1509 dw->hdata->nr_channels); 1510 1511 return 0; 1512 1513 err_pm_disable: 1514 pm_runtime_disable(chip->dev); 1515 1516 return ret; 1517 } 1518 1519 static int dw_remove(struct platform_device *pdev) 1520 { 1521 struct axi_dma_chip *chip = platform_get_drvdata(pdev); 1522 struct dw_axi_dma *dw = chip->dw; 1523 struct axi_dma_chan *chan, *_chan; 1524 u32 i; 1525 1526 /* Enable clk before accessing to registers */ 1527 clk_prepare_enable(chip->cfgr_clk); 1528 clk_prepare_enable(chip->core_clk); 1529 axi_dma_irq_disable(chip); 1530 for (i = 0; i < dw->hdata->nr_channels; i++) { 1531 axi_chan_disable(&chip->dw->chan[i]); 1532 axi_chan_irq_disable(&chip->dw->chan[i], DWAXIDMAC_IRQ_ALL); 1533 } 1534 axi_dma_disable(chip); 1535 1536 pm_runtime_disable(chip->dev); 1537 axi_dma_suspend(chip); 1538 1539 devm_free_irq(chip->dev, chip->irq, chip); 1540 1541 of_dma_controller_free(chip->dev->of_node); 1542 1543 list_for_each_entry_safe(chan, _chan, &dw->dma.channels, 1544 vc.chan.device_node) { 1545 list_del(&chan->vc.chan.device_node); 1546 tasklet_kill(&chan->vc.task); 1547 } 1548 1549 return 0; 1550 } 1551 1552 static const struct dev_pm_ops dw_axi_dma_pm_ops = { 1553 SET_RUNTIME_PM_OPS(axi_dma_runtime_suspend, axi_dma_runtime_resume, NULL) 1554 }; 1555 1556 static const struct of_device_id dw_dma_of_id_table[] = { 1557 { .compatible = "snps,axi-dma-1.01a" }, 1558 { .compatible = "intel,kmb-axi-dma" }, 1559 {} 1560 }; 1561 MODULE_DEVICE_TABLE(of, dw_dma_of_id_table); 1562 1563 static struct platform_driver dw_driver = { 1564 .probe = dw_probe, 1565 .remove = dw_remove, 1566 .driver = { 1567 .name = KBUILD_MODNAME, 1568 .of_match_table = dw_dma_of_id_table, 1569 .pm = &dw_axi_dma_pm_ops, 1570 }, 1571 }; 1572 module_platform_driver(dw_driver); 1573 1574 MODULE_LICENSE("GPL v2"); 1575 MODULE_DESCRIPTION("Synopsys DesignWare AXI DMA Controller platform driver"); 1576 MODULE_AUTHOR("Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>"); 1577