1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2013-2014 Freescale Semiconductor, Inc. 4 * Copyright 2018 Angelo Dureghello <angelo@sysam.it> 5 */ 6 #ifndef _FSL_EDMA_COMMON_H_ 7 #define _FSL_EDMA_COMMON_H_ 8 9 #include <linux/dma-direction.h> 10 #include "virt-dma.h" 11 12 #define EDMA_CR_EDBG BIT(1) 13 #define EDMA_CR_ERCA BIT(2) 14 #define EDMA_CR_ERGA BIT(3) 15 #define EDMA_CR_HOE BIT(4) 16 #define EDMA_CR_HALT BIT(5) 17 #define EDMA_CR_CLM BIT(6) 18 #define EDMA_CR_EMLM BIT(7) 19 #define EDMA_CR_ECX BIT(16) 20 #define EDMA_CR_CX BIT(17) 21 22 #define EDMA_SEEI_SEEI(x) ((x) & GENMASK(4, 0)) 23 #define EDMA_CEEI_CEEI(x) ((x) & GENMASK(4, 0)) 24 #define EDMA_CINT_CINT(x) ((x) & GENMASK(4, 0)) 25 #define EDMA_CERR_CERR(x) ((x) & GENMASK(4, 0)) 26 27 #define EDMA_TCD_ATTR_DSIZE(x) (((x) & GENMASK(2, 0))) 28 #define EDMA_TCD_ATTR_DMOD(x) (((x) & GENMASK(4, 0)) << 3) 29 #define EDMA_TCD_ATTR_SSIZE(x) (((x) & GENMASK(2, 0)) << 8) 30 #define EDMA_TCD_ATTR_SMOD(x) (((x) & GENMASK(4, 0)) << 11) 31 #define EDMA_TCD_ATTR_DSIZE_8BIT 0 32 #define EDMA_TCD_ATTR_DSIZE_16BIT BIT(0) 33 #define EDMA_TCD_ATTR_DSIZE_32BIT BIT(1) 34 #define EDMA_TCD_ATTR_DSIZE_64BIT (BIT(0) | BIT(1)) 35 #define EDMA_TCD_ATTR_DSIZE_32BYTE (BIT(3) | BIT(0)) 36 #define EDMA_TCD_ATTR_SSIZE_8BIT 0 37 #define EDMA_TCD_ATTR_SSIZE_16BIT (EDMA_TCD_ATTR_DSIZE_16BIT << 8) 38 #define EDMA_TCD_ATTR_SSIZE_32BIT (EDMA_TCD_ATTR_DSIZE_32BIT << 8) 39 #define EDMA_TCD_ATTR_SSIZE_64BIT (EDMA_TCD_ATTR_DSIZE_64BIT << 8) 40 #define EDMA_TCD_ATTR_SSIZE_32BYTE (EDMA_TCD_ATTR_DSIZE_32BYTE << 8) 41 42 #define EDMA_TCD_CITER_CITER(x) ((x) & GENMASK(14, 0)) 43 #define EDMA_TCD_BITER_BITER(x) ((x) & GENMASK(14, 0)) 44 45 #define EDMA_TCD_CSR_START BIT(0) 46 #define EDMA_TCD_CSR_INT_MAJOR BIT(1) 47 #define EDMA_TCD_CSR_INT_HALF BIT(2) 48 #define EDMA_TCD_CSR_D_REQ BIT(3) 49 #define EDMA_TCD_CSR_E_SG BIT(4) 50 #define EDMA_TCD_CSR_E_LINK BIT(5) 51 #define EDMA_TCD_CSR_ACTIVE BIT(6) 52 #define EDMA_TCD_CSR_DONE BIT(7) 53 54 #define EDMAMUX_CHCFG_DIS 0x0 55 #define EDMAMUX_CHCFG_ENBL 0x80 56 #define EDMAMUX_CHCFG_SOURCE(n) ((n) & 0x3F) 57 58 #define DMAMUX_NR 2 59 60 #define FSL_EDMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ 61 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ 62 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \ 63 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)) 64 enum fsl_edma_pm_state { 65 RUNNING = 0, 66 SUSPENDED, 67 }; 68 69 struct fsl_edma_hw_tcd { 70 __le32 saddr; 71 __le16 soff; 72 __le16 attr; 73 __le32 nbytes; 74 __le32 slast; 75 __le32 daddr; 76 __le16 doff; 77 __le16 citer; 78 __le32 dlast_sga; 79 __le16 csr; 80 __le16 biter; 81 }; 82 83 /* 84 * These are iomem pointers, for both v32 and v64. 85 */ 86 struct edma_regs { 87 void __iomem *cr; 88 void __iomem *es; 89 void __iomem *erqh; 90 void __iomem *erql; /* aka erq on v32 */ 91 void __iomem *eeih; 92 void __iomem *eeil; /* aka eei on v32 */ 93 void __iomem *seei; 94 void __iomem *ceei; 95 void __iomem *serq; 96 void __iomem *cerq; 97 void __iomem *cint; 98 void __iomem *cerr; 99 void __iomem *ssrt; 100 void __iomem *cdne; 101 void __iomem *inth; 102 void __iomem *intl; 103 void __iomem *errh; 104 void __iomem *errl; 105 struct fsl_edma_hw_tcd __iomem *tcd; 106 }; 107 108 struct fsl_edma_sw_tcd { 109 dma_addr_t ptcd; 110 struct fsl_edma_hw_tcd *vtcd; 111 }; 112 113 struct fsl_edma_chan { 114 struct virt_dma_chan vchan; 115 enum dma_status status; 116 enum fsl_edma_pm_state pm_state; 117 bool idle; 118 u32 slave_id; 119 struct fsl_edma_engine *edma; 120 struct fsl_edma_desc *edesc; 121 struct dma_slave_config cfg; 122 u32 attr; 123 struct dma_pool *tcd_pool; 124 dma_addr_t dma_dev_addr; 125 u32 dma_dev_size; 126 enum dma_data_direction dma_dir; 127 }; 128 129 struct fsl_edma_desc { 130 struct virt_dma_desc vdesc; 131 struct fsl_edma_chan *echan; 132 bool iscyclic; 133 enum dma_transfer_direction dirn; 134 unsigned int n_tcds; 135 struct fsl_edma_sw_tcd tcd[]; 136 }; 137 138 enum edma_version { 139 v1, /* 32ch, Vybrid, mpc57x, etc */ 140 v2, /* 64ch Coldfire */ 141 }; 142 143 struct fsl_edma_engine { 144 struct dma_device dma_dev; 145 void __iomem *membase; 146 void __iomem *muxbase[DMAMUX_NR]; 147 struct clk *muxclk[DMAMUX_NR]; 148 struct mutex fsl_edma_mutex; 149 u32 n_chans; 150 int txirq; 151 int errirq; 152 bool big_endian; 153 enum edma_version version; 154 struct edma_regs regs; 155 struct fsl_edma_chan chans[]; 156 }; 157 158 /* 159 * R/W functions for big- or little-endian registers: 160 * The eDMA controller's endian is independent of the CPU core's endian. 161 * For the big-endian IP module, the offset for 8-bit or 16-bit registers 162 * should also be swapped opposite to that in little-endian IP. 163 */ 164 static inline u32 edma_readl(struct fsl_edma_engine *edma, void __iomem *addr) 165 { 166 if (edma->big_endian) 167 return ioread32be(addr); 168 else 169 return ioread32(addr); 170 } 171 172 static inline void edma_writeb(struct fsl_edma_engine *edma, 173 u8 val, void __iomem *addr) 174 { 175 /* swap the reg offset for these in big-endian mode */ 176 if (edma->big_endian) 177 iowrite8(val, (void __iomem *)((unsigned long)addr ^ 0x3)); 178 else 179 iowrite8(val, addr); 180 } 181 182 static inline void edma_writew(struct fsl_edma_engine *edma, 183 u16 val, void __iomem *addr) 184 { 185 /* swap the reg offset for these in big-endian mode */ 186 if (edma->big_endian) 187 iowrite16be(val, (void __iomem *)((unsigned long)addr ^ 0x2)); 188 else 189 iowrite16(val, addr); 190 } 191 192 static inline void edma_writel(struct fsl_edma_engine *edma, 193 u32 val, void __iomem *addr) 194 { 195 if (edma->big_endian) 196 iowrite32be(val, addr); 197 else 198 iowrite32(val, addr); 199 } 200 201 static inline struct fsl_edma_chan *to_fsl_edma_chan(struct dma_chan *chan) 202 { 203 return container_of(chan, struct fsl_edma_chan, vchan.chan); 204 } 205 206 static inline struct fsl_edma_desc *to_fsl_edma_desc(struct virt_dma_desc *vd) 207 { 208 return container_of(vd, struct fsl_edma_desc, vdesc); 209 } 210 211 void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan); 212 void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan, 213 unsigned int slot, bool enable); 214 void fsl_edma_free_desc(struct virt_dma_desc *vdesc); 215 int fsl_edma_terminate_all(struct dma_chan *chan); 216 int fsl_edma_pause(struct dma_chan *chan); 217 int fsl_edma_resume(struct dma_chan *chan); 218 int fsl_edma_slave_config(struct dma_chan *chan, 219 struct dma_slave_config *cfg); 220 enum dma_status fsl_edma_tx_status(struct dma_chan *chan, 221 dma_cookie_t cookie, struct dma_tx_state *txstate); 222 struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic( 223 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, 224 size_t period_len, enum dma_transfer_direction direction, 225 unsigned long flags); 226 struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg( 227 struct dma_chan *chan, struct scatterlist *sgl, 228 unsigned int sg_len, enum dma_transfer_direction direction, 229 unsigned long flags, void *context); 230 void fsl_edma_xfer_desc(struct fsl_edma_chan *fsl_chan); 231 void fsl_edma_issue_pending(struct dma_chan *chan); 232 int fsl_edma_alloc_chan_resources(struct dma_chan *chan); 233 void fsl_edma_free_chan_resources(struct dma_chan *chan); 234 void fsl_edma_cleanup_vchan(struct dma_device *dmadev); 235 void fsl_edma_setup_regs(struct fsl_edma_engine *edma); 236 237 #endif /* _FSL_EDMA_COMMON_H_ */ 238