1 /* 2 * Intel 5400 class Memory Controllers kernel module (Seaburg) 3 * 4 * This file may be distributed under the terms of the 5 * GNU General Public License. 6 * 7 * Copyright (c) 2008 by: 8 * Ben Woodard <woodard@redhat.com> 9 * Mauro Carvalho Chehab <mchehab@redhat.com> 10 * 11 * Red Hat Inc. http://www.redhat.com 12 * 13 * Forked and adapted from the i5000_edac driver which was 14 * written by Douglas Thompson Linux Networx <norsk5@xmission.com> 15 * 16 * This module is based on the following document: 17 * 18 * Intel 5400 Chipset Memory Controller Hub (MCH) - Datasheet 19 * http://developer.intel.com/design/chipsets/datashts/313070.htm 20 * 21 * This Memory Controller manages DDR2 FB-DIMMs. It has 2 branches, each with 22 * 2 channels operating in lockstep no-mirror mode. Each channel can have up to 23 * 4 dimm's, each with up to 8GB. 24 * 25 */ 26 27 #include <linux/module.h> 28 #include <linux/init.h> 29 #include <linux/pci.h> 30 #include <linux/pci_ids.h> 31 #include <linux/slab.h> 32 #include <linux/edac.h> 33 #include <linux/mmzone.h> 34 35 #include "edac_core.h" 36 37 /* 38 * Alter this version for the I5400 module when modifications are made 39 */ 40 #define I5400_REVISION " Ver: 1.0.0" 41 42 #define EDAC_MOD_STR "i5400_edac" 43 44 #define i5400_printk(level, fmt, arg...) \ 45 edac_printk(level, "i5400", fmt, ##arg) 46 47 #define i5400_mc_printk(mci, level, fmt, arg...) \ 48 edac_mc_chipset_printk(mci, level, "i5400", fmt, ##arg) 49 50 /* Limits for i5400 */ 51 #define MAX_BRANCHES 2 52 #define CHANNELS_PER_BRANCH 2 53 #define DIMMS_PER_CHANNEL 4 54 #define MAX_CHANNELS (MAX_BRANCHES * CHANNELS_PER_BRANCH) 55 56 /* Device 16, 57 * Function 0: System Address 58 * Function 1: Memory Branch Map, Control, Errors Register 59 * Function 2: FSB Error Registers 60 * 61 * All 3 functions of Device 16 (0,1,2) share the SAME DID and 62 * uses PCI_DEVICE_ID_INTEL_5400_ERR for device 16 (0,1,2), 63 * PCI_DEVICE_ID_INTEL_5400_FBD0 and PCI_DEVICE_ID_INTEL_5400_FBD1 64 * for device 21 (0,1). 65 */ 66 67 /* OFFSETS for Function 0 */ 68 #define AMBASE 0x48 /* AMB Mem Mapped Reg Region Base */ 69 #define MAXCH 0x56 /* Max Channel Number */ 70 #define MAXDIMMPERCH 0x57 /* Max DIMM PER Channel Number */ 71 72 /* OFFSETS for Function 1 */ 73 #define TOLM 0x6C 74 #define REDMEMB 0x7C 75 #define REC_ECC_LOCATOR_ODD(x) ((x) & 0x3fe00) /* bits [17:9] indicate ODD, [8:0] indicate EVEN */ 76 #define MIR0 0x80 77 #define MIR1 0x84 78 #define AMIR0 0x8c 79 #define AMIR1 0x90 80 81 /* Fatal error registers */ 82 #define FERR_FAT_FBD 0x98 /* also called as FERR_FAT_FB_DIMM at datasheet */ 83 #define FERR_FAT_FBDCHAN (3<<28) /* channel index where the highest-order error occurred */ 84 85 #define NERR_FAT_FBD 0x9c 86 #define FERR_NF_FBD 0xa0 /* also called as FERR_NFAT_FB_DIMM at datasheet */ 87 88 /* Non-fatal error register */ 89 #define NERR_NF_FBD 0xa4 90 91 /* Enable error mask */ 92 #define EMASK_FBD 0xa8 93 94 #define ERR0_FBD 0xac 95 #define ERR1_FBD 0xb0 96 #define ERR2_FBD 0xb4 97 #define MCERR_FBD 0xb8 98 99 /* No OFFSETS for Device 16 Function 2 */ 100 101 /* 102 * Device 21, 103 * Function 0: Memory Map Branch 0 104 * 105 * Device 22, 106 * Function 0: Memory Map Branch 1 107 */ 108 109 /* OFFSETS for Function 0 */ 110 #define AMBPRESENT_0 0x64 111 #define AMBPRESENT_1 0x66 112 #define MTR0 0x80 113 #define MTR1 0x82 114 #define MTR2 0x84 115 #define MTR3 0x86 116 117 /* OFFSETS for Function 1 */ 118 #define NRECFGLOG 0x74 119 #define RECFGLOG 0x78 120 #define NRECMEMA 0xbe 121 #define NRECMEMB 0xc0 122 #define NRECFB_DIMMA 0xc4 123 #define NRECFB_DIMMB 0xc8 124 #define NRECFB_DIMMC 0xcc 125 #define NRECFB_DIMMD 0xd0 126 #define NRECFB_DIMME 0xd4 127 #define NRECFB_DIMMF 0xd8 128 #define REDMEMA 0xdC 129 #define RECMEMA 0xf0 130 #define RECMEMB 0xf4 131 #define RECFB_DIMMA 0xf8 132 #define RECFB_DIMMB 0xec 133 #define RECFB_DIMMC 0xf0 134 #define RECFB_DIMMD 0xf4 135 #define RECFB_DIMME 0xf8 136 #define RECFB_DIMMF 0xfC 137 138 /* 139 * Error indicator bits and masks 140 * Error masks are according with Table 5-17 of i5400 datasheet 141 */ 142 143 enum error_mask { 144 EMASK_M1 = 1<<0, /* Memory Write error on non-redundant retry */ 145 EMASK_M2 = 1<<1, /* Memory or FB-DIMM configuration CRC read error */ 146 EMASK_M3 = 1<<2, /* Reserved */ 147 EMASK_M4 = 1<<3, /* Uncorrectable Data ECC on Replay */ 148 EMASK_M5 = 1<<4, /* Aliased Uncorrectable Non-Mirrored Demand Data ECC */ 149 EMASK_M6 = 1<<5, /* Unsupported on i5400 */ 150 EMASK_M7 = 1<<6, /* Aliased Uncorrectable Resilver- or Spare-Copy Data ECC */ 151 EMASK_M8 = 1<<7, /* Aliased Uncorrectable Patrol Data ECC */ 152 EMASK_M9 = 1<<8, /* Non-Aliased Uncorrectable Non-Mirrored Demand Data ECC */ 153 EMASK_M10 = 1<<9, /* Unsupported on i5400 */ 154 EMASK_M11 = 1<<10, /* Non-Aliased Uncorrectable Resilver- or Spare-Copy Data ECC */ 155 EMASK_M12 = 1<<11, /* Non-Aliased Uncorrectable Patrol Data ECC */ 156 EMASK_M13 = 1<<12, /* Memory Write error on first attempt */ 157 EMASK_M14 = 1<<13, /* FB-DIMM Configuration Write error on first attempt */ 158 EMASK_M15 = 1<<14, /* Memory or FB-DIMM configuration CRC read error */ 159 EMASK_M16 = 1<<15, /* Channel Failed-Over Occurred */ 160 EMASK_M17 = 1<<16, /* Correctable Non-Mirrored Demand Data ECC */ 161 EMASK_M18 = 1<<17, /* Unsupported on i5400 */ 162 EMASK_M19 = 1<<18, /* Correctable Resilver- or Spare-Copy Data ECC */ 163 EMASK_M20 = 1<<19, /* Correctable Patrol Data ECC */ 164 EMASK_M21 = 1<<20, /* FB-DIMM Northbound parity error on FB-DIMM Sync Status */ 165 EMASK_M22 = 1<<21, /* SPD protocol Error */ 166 EMASK_M23 = 1<<22, /* Non-Redundant Fast Reset Timeout */ 167 EMASK_M24 = 1<<23, /* Refresh error */ 168 EMASK_M25 = 1<<24, /* Memory Write error on redundant retry */ 169 EMASK_M26 = 1<<25, /* Redundant Fast Reset Timeout */ 170 EMASK_M27 = 1<<26, /* Correctable Counter Threshold Exceeded */ 171 EMASK_M28 = 1<<27, /* DIMM-Spare Copy Completed */ 172 EMASK_M29 = 1<<28, /* DIMM-Isolation Completed */ 173 }; 174 175 /* 176 * Names to translate bit error into something useful 177 */ 178 static const char *error_name[] = { 179 [0] = "Memory Write error on non-redundant retry", 180 [1] = "Memory or FB-DIMM configuration CRC read error", 181 /* Reserved */ 182 [3] = "Uncorrectable Data ECC on Replay", 183 [4] = "Aliased Uncorrectable Non-Mirrored Demand Data ECC", 184 /* M6 Unsupported on i5400 */ 185 [6] = "Aliased Uncorrectable Resilver- or Spare-Copy Data ECC", 186 [7] = "Aliased Uncorrectable Patrol Data ECC", 187 [8] = "Non-Aliased Uncorrectable Non-Mirrored Demand Data ECC", 188 /* M10 Unsupported on i5400 */ 189 [10] = "Non-Aliased Uncorrectable Resilver- or Spare-Copy Data ECC", 190 [11] = "Non-Aliased Uncorrectable Patrol Data ECC", 191 [12] = "Memory Write error on first attempt", 192 [13] = "FB-DIMM Configuration Write error on first attempt", 193 [14] = "Memory or FB-DIMM configuration CRC read error", 194 [15] = "Channel Failed-Over Occurred", 195 [16] = "Correctable Non-Mirrored Demand Data ECC", 196 /* M18 Unsupported on i5400 */ 197 [18] = "Correctable Resilver- or Spare-Copy Data ECC", 198 [19] = "Correctable Patrol Data ECC", 199 [20] = "FB-DIMM Northbound parity error on FB-DIMM Sync Status", 200 [21] = "SPD protocol Error", 201 [22] = "Non-Redundant Fast Reset Timeout", 202 [23] = "Refresh error", 203 [24] = "Memory Write error on redundant retry", 204 [25] = "Redundant Fast Reset Timeout", 205 [26] = "Correctable Counter Threshold Exceeded", 206 [27] = "DIMM-Spare Copy Completed", 207 [28] = "DIMM-Isolation Completed", 208 }; 209 210 /* Fatal errors */ 211 #define ERROR_FAT_MASK (EMASK_M1 | \ 212 EMASK_M2 | \ 213 EMASK_M23) 214 215 /* Correctable errors */ 216 #define ERROR_NF_CORRECTABLE (EMASK_M27 | \ 217 EMASK_M20 | \ 218 EMASK_M19 | \ 219 EMASK_M18 | \ 220 EMASK_M17 | \ 221 EMASK_M16) 222 #define ERROR_NF_DIMM_SPARE (EMASK_M29 | \ 223 EMASK_M28) 224 #define ERROR_NF_SPD_PROTOCOL (EMASK_M22) 225 #define ERROR_NF_NORTH_CRC (EMASK_M21) 226 227 /* Recoverable errors */ 228 #define ERROR_NF_RECOVERABLE (EMASK_M26 | \ 229 EMASK_M25 | \ 230 EMASK_M24 | \ 231 EMASK_M15 | \ 232 EMASK_M14 | \ 233 EMASK_M13 | \ 234 EMASK_M12 | \ 235 EMASK_M11 | \ 236 EMASK_M9 | \ 237 EMASK_M8 | \ 238 EMASK_M7 | \ 239 EMASK_M5) 240 241 /* uncorrectable errors */ 242 #define ERROR_NF_UNCORRECTABLE (EMASK_M4) 243 244 /* mask to all non-fatal errors */ 245 #define ERROR_NF_MASK (ERROR_NF_CORRECTABLE | \ 246 ERROR_NF_UNCORRECTABLE | \ 247 ERROR_NF_RECOVERABLE | \ 248 ERROR_NF_DIMM_SPARE | \ 249 ERROR_NF_SPD_PROTOCOL | \ 250 ERROR_NF_NORTH_CRC) 251 252 /* 253 * Define error masks for the several registers 254 */ 255 256 /* Enable all fatal and non fatal errors */ 257 #define ENABLE_EMASK_ALL (ERROR_FAT_MASK | ERROR_NF_MASK) 258 259 /* mask for fatal error registers */ 260 #define FERR_FAT_MASK ERROR_FAT_MASK 261 262 /* masks for non-fatal error register */ 263 static inline int to_nf_mask(unsigned int mask) 264 { 265 return (mask & EMASK_M29) | (mask >> 3); 266 }; 267 268 static inline int from_nf_ferr(unsigned int mask) 269 { 270 return (mask & EMASK_M29) | /* Bit 28 */ 271 (mask & ((1 << 28) - 1) << 3); /* Bits 0 to 27 */ 272 }; 273 274 #define FERR_NF_MASK to_nf_mask(ERROR_NF_MASK) 275 #define FERR_NF_CORRECTABLE to_nf_mask(ERROR_NF_CORRECTABLE) 276 #define FERR_NF_DIMM_SPARE to_nf_mask(ERROR_NF_DIMM_SPARE) 277 #define FERR_NF_SPD_PROTOCOL to_nf_mask(ERROR_NF_SPD_PROTOCOL) 278 #define FERR_NF_NORTH_CRC to_nf_mask(ERROR_NF_NORTH_CRC) 279 #define FERR_NF_RECOVERABLE to_nf_mask(ERROR_NF_RECOVERABLE) 280 #define FERR_NF_UNCORRECTABLE to_nf_mask(ERROR_NF_UNCORRECTABLE) 281 282 /* Defines to extract the vaious fields from the 283 * MTRx - Memory Technology Registers 284 */ 285 #define MTR_DIMMS_PRESENT(mtr) ((mtr) & (1 << 10)) 286 #define MTR_DIMMS_ETHROTTLE(mtr) ((mtr) & (1 << 9)) 287 #define MTR_DRAM_WIDTH(mtr) (((mtr) & (1 << 8)) ? 8 : 4) 288 #define MTR_DRAM_BANKS(mtr) (((mtr) & (1 << 6)) ? 8 : 4) 289 #define MTR_DRAM_BANKS_ADDR_BITS(mtr) ((MTR_DRAM_BANKS(mtr) == 8) ? 3 : 2) 290 #define MTR_DIMM_RANK(mtr) (((mtr) >> 5) & 0x1) 291 #define MTR_DIMM_RANK_ADDR_BITS(mtr) (MTR_DIMM_RANK(mtr) ? 2 : 1) 292 #define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3) 293 #define MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13) 294 #define MTR_DIMM_COLS(mtr) ((mtr) & 0x3) 295 #define MTR_DIMM_COLS_ADDR_BITS(mtr) (MTR_DIMM_COLS(mtr) + 10) 296 297 /* This applies to FERR_NF_FB-DIMM as well as FERR_FAT_FB-DIMM */ 298 static inline int extract_fbdchan_indx(u32 x) 299 { 300 return (x>>28) & 0x3; 301 } 302 303 #ifdef CONFIG_EDAC_DEBUG 304 /* MTR NUMROW */ 305 static const char *numrow_toString[] = { 306 "8,192 - 13 rows", 307 "16,384 - 14 rows", 308 "32,768 - 15 rows", 309 "65,536 - 16 rows" 310 }; 311 312 /* MTR NUMCOL */ 313 static const char *numcol_toString[] = { 314 "1,024 - 10 columns", 315 "2,048 - 11 columns", 316 "4,096 - 12 columns", 317 "reserved" 318 }; 319 #endif 320 321 /* Device name and register DID (Device ID) */ 322 struct i5400_dev_info { 323 const char *ctl_name; /* name for this device */ 324 u16 fsb_mapping_errors; /* DID for the branchmap,control */ 325 }; 326 327 /* Table of devices attributes supported by this driver */ 328 static const struct i5400_dev_info i5400_devs[] = { 329 { 330 .ctl_name = "I5400", 331 .fsb_mapping_errors = PCI_DEVICE_ID_INTEL_5400_ERR, 332 }, 333 }; 334 335 struct i5400_dimm_info { 336 int megabytes; /* size, 0 means not present */ 337 }; 338 339 /* driver private data structure */ 340 struct i5400_pvt { 341 struct pci_dev *system_address; /* 16.0 */ 342 struct pci_dev *branchmap_werrors; /* 16.1 */ 343 struct pci_dev *fsb_error_regs; /* 16.2 */ 344 struct pci_dev *branch_0; /* 21.0 */ 345 struct pci_dev *branch_1; /* 22.0 */ 346 347 u16 tolm; /* top of low memory */ 348 u64 ambase; /* AMB BAR */ 349 350 u16 mir0, mir1; 351 352 u16 b0_mtr[DIMMS_PER_CHANNEL]; /* Memory Technlogy Reg */ 353 u16 b0_ambpresent0; /* Branch 0, Channel 0 */ 354 u16 b0_ambpresent1; /* Brnach 0, Channel 1 */ 355 356 u16 b1_mtr[DIMMS_PER_CHANNEL]; /* Memory Technlogy Reg */ 357 u16 b1_ambpresent0; /* Branch 1, Channel 8 */ 358 u16 b1_ambpresent1; /* Branch 1, Channel 1 */ 359 360 /* DIMM information matrix, allocating architecture maximums */ 361 struct i5400_dimm_info dimm_info[DIMMS_PER_CHANNEL][MAX_CHANNELS]; 362 363 /* Actual values for this controller */ 364 int maxch; /* Max channels */ 365 int maxdimmperch; /* Max DIMMs per channel */ 366 }; 367 368 /* I5400 MCH error information retrieved from Hardware */ 369 struct i5400_error_info { 370 /* These registers are always read from the MC */ 371 u32 ferr_fat_fbd; /* First Errors Fatal */ 372 u32 nerr_fat_fbd; /* Next Errors Fatal */ 373 u32 ferr_nf_fbd; /* First Errors Non-Fatal */ 374 u32 nerr_nf_fbd; /* Next Errors Non-Fatal */ 375 376 /* These registers are input ONLY if there was a Recoverable Error */ 377 u32 redmemb; /* Recoverable Mem Data Error log B */ 378 u16 recmema; /* Recoverable Mem Error log A */ 379 u32 recmemb; /* Recoverable Mem Error log B */ 380 381 /* These registers are input ONLY if there was a Non-Rec Error */ 382 u16 nrecmema; /* Non-Recoverable Mem log A */ 383 u16 nrecmemb; /* Non-Recoverable Mem log B */ 384 385 }; 386 387 /* note that nrec_rdwr changed from NRECMEMA to NRECMEMB between the 5000 and 388 5400 better to use an inline function than a macro in this case */ 389 static inline int nrec_bank(struct i5400_error_info *info) 390 { 391 return ((info->nrecmema) >> 12) & 0x7; 392 } 393 static inline int nrec_rank(struct i5400_error_info *info) 394 { 395 return ((info->nrecmema) >> 8) & 0xf; 396 } 397 static inline int nrec_buf_id(struct i5400_error_info *info) 398 { 399 return ((info->nrecmema)) & 0xff; 400 } 401 static inline int nrec_rdwr(struct i5400_error_info *info) 402 { 403 return (info->nrecmemb) >> 31; 404 } 405 /* This applies to both NREC and REC string so it can be used with nrec_rdwr 406 and rec_rdwr */ 407 static inline const char *rdwr_str(int rdwr) 408 { 409 return rdwr ? "Write" : "Read"; 410 } 411 static inline int nrec_cas(struct i5400_error_info *info) 412 { 413 return ((info->nrecmemb) >> 16) & 0x1fff; 414 } 415 static inline int nrec_ras(struct i5400_error_info *info) 416 { 417 return (info->nrecmemb) & 0xffff; 418 } 419 static inline int rec_bank(struct i5400_error_info *info) 420 { 421 return ((info->recmema) >> 12) & 0x7; 422 } 423 static inline int rec_rank(struct i5400_error_info *info) 424 { 425 return ((info->recmema) >> 8) & 0xf; 426 } 427 static inline int rec_rdwr(struct i5400_error_info *info) 428 { 429 return (info->recmemb) >> 31; 430 } 431 static inline int rec_cas(struct i5400_error_info *info) 432 { 433 return ((info->recmemb) >> 16) & 0x1fff; 434 } 435 static inline int rec_ras(struct i5400_error_info *info) 436 { 437 return (info->recmemb) & 0xffff; 438 } 439 440 static struct edac_pci_ctl_info *i5400_pci; 441 442 /* 443 * i5400_get_error_info Retrieve the hardware error information from 444 * the hardware and cache it in the 'info' 445 * structure 446 */ 447 static void i5400_get_error_info(struct mem_ctl_info *mci, 448 struct i5400_error_info *info) 449 { 450 struct i5400_pvt *pvt; 451 u32 value; 452 453 pvt = mci->pvt_info; 454 455 /* read in the 1st FATAL error register */ 456 pci_read_config_dword(pvt->branchmap_werrors, FERR_FAT_FBD, &value); 457 458 /* Mask only the bits that the doc says are valid 459 */ 460 value &= (FERR_FAT_FBDCHAN | FERR_FAT_MASK); 461 462 /* If there is an error, then read in the 463 NEXT FATAL error register and the Memory Error Log Register A 464 */ 465 if (value & FERR_FAT_MASK) { 466 info->ferr_fat_fbd = value; 467 468 /* harvest the various error data we need */ 469 pci_read_config_dword(pvt->branchmap_werrors, 470 NERR_FAT_FBD, &info->nerr_fat_fbd); 471 pci_read_config_word(pvt->branchmap_werrors, 472 NRECMEMA, &info->nrecmema); 473 pci_read_config_word(pvt->branchmap_werrors, 474 NRECMEMB, &info->nrecmemb); 475 476 /* Clear the error bits, by writing them back */ 477 pci_write_config_dword(pvt->branchmap_werrors, 478 FERR_FAT_FBD, value); 479 } else { 480 info->ferr_fat_fbd = 0; 481 info->nerr_fat_fbd = 0; 482 info->nrecmema = 0; 483 info->nrecmemb = 0; 484 } 485 486 /* read in the 1st NON-FATAL error register */ 487 pci_read_config_dword(pvt->branchmap_werrors, FERR_NF_FBD, &value); 488 489 /* If there is an error, then read in the 1st NON-FATAL error 490 * register as well */ 491 if (value & FERR_NF_MASK) { 492 info->ferr_nf_fbd = value; 493 494 /* harvest the various error data we need */ 495 pci_read_config_dword(pvt->branchmap_werrors, 496 NERR_NF_FBD, &info->nerr_nf_fbd); 497 pci_read_config_word(pvt->branchmap_werrors, 498 RECMEMA, &info->recmema); 499 pci_read_config_dword(pvt->branchmap_werrors, 500 RECMEMB, &info->recmemb); 501 pci_read_config_dword(pvt->branchmap_werrors, 502 REDMEMB, &info->redmemb); 503 504 /* Clear the error bits, by writing them back */ 505 pci_write_config_dword(pvt->branchmap_werrors, 506 FERR_NF_FBD, value); 507 } else { 508 info->ferr_nf_fbd = 0; 509 info->nerr_nf_fbd = 0; 510 info->recmema = 0; 511 info->recmemb = 0; 512 info->redmemb = 0; 513 } 514 } 515 516 /* 517 * i5400_proccess_non_recoverable_info(struct mem_ctl_info *mci, 518 * struct i5400_error_info *info, 519 * int handle_errors); 520 * 521 * handle the Intel FATAL and unrecoverable errors, if any 522 */ 523 static void i5400_proccess_non_recoverable_info(struct mem_ctl_info *mci, 524 struct i5400_error_info *info, 525 unsigned long allErrors) 526 { 527 char msg[EDAC_MC_LABEL_LEN + 1 + 90 + 80]; 528 int branch; 529 int channel; 530 int bank; 531 int buf_id; 532 int rank; 533 int rdwr; 534 int ras, cas; 535 int errnum; 536 char *type = NULL; 537 enum hw_event_mc_err_type tp_event = HW_EVENT_ERR_UNCORRECTED; 538 539 if (!allErrors) 540 return; /* if no error, return now */ 541 542 if (allErrors & ERROR_FAT_MASK) { 543 type = "FATAL"; 544 tp_event = HW_EVENT_ERR_FATAL; 545 } else if (allErrors & FERR_NF_UNCORRECTABLE) 546 type = "NON-FATAL uncorrected"; 547 else 548 type = "NON-FATAL recoverable"; 549 550 /* ONLY ONE of the possible error bits will be set, as per the docs */ 551 552 branch = extract_fbdchan_indx(info->ferr_fat_fbd); 553 channel = branch; 554 555 /* Use the NON-Recoverable macros to extract data */ 556 bank = nrec_bank(info); 557 rank = nrec_rank(info); 558 buf_id = nrec_buf_id(info); 559 rdwr = nrec_rdwr(info); 560 ras = nrec_ras(info); 561 cas = nrec_cas(info); 562 563 debugf0("\t\tDIMM= %d Channels= %d,%d (Branch= %d " 564 "DRAM Bank= %d Buffer ID = %d rdwr= %s ras= %d cas= %d)\n", 565 rank, channel, channel + 1, branch >> 1, bank, 566 buf_id, rdwr_str(rdwr), ras, cas); 567 568 /* Only 1 bit will be on */ 569 errnum = find_first_bit(&allErrors, ARRAY_SIZE(error_name)); 570 571 /* Form out message */ 572 snprintf(msg, sizeof(msg), 573 "Bank=%d Buffer ID = %d RAS=%d CAS=%d Err=0x%lx (%s)", 574 bank, buf_id, ras, cas, allErrors, error_name[errnum]); 575 576 edac_mc_handle_error(tp_event, mci, 0, 0, 0, 577 branch >> 1, -1, rank, 578 rdwr ? "Write error" : "Read error", 579 msg, NULL); 580 } 581 582 /* 583 * i5400_process_fatal_error_info(struct mem_ctl_info *mci, 584 * struct i5400_error_info *info, 585 * int handle_errors); 586 * 587 * handle the Intel NON-FATAL errors, if any 588 */ 589 static void i5400_process_nonfatal_error_info(struct mem_ctl_info *mci, 590 struct i5400_error_info *info) 591 { 592 char msg[EDAC_MC_LABEL_LEN + 1 + 90 + 80]; 593 unsigned long allErrors; 594 int branch; 595 int channel; 596 int bank; 597 int rank; 598 int rdwr; 599 int ras, cas; 600 int errnum; 601 602 /* mask off the Error bits that are possible */ 603 allErrors = from_nf_ferr(info->ferr_nf_fbd & FERR_NF_MASK); 604 if (!allErrors) 605 return; /* if no error, return now */ 606 607 /* ONLY ONE of the possible error bits will be set, as per the docs */ 608 609 if (allErrors & (ERROR_NF_UNCORRECTABLE | ERROR_NF_RECOVERABLE)) { 610 i5400_proccess_non_recoverable_info(mci, info, allErrors); 611 return; 612 } 613 614 /* Correctable errors */ 615 if (allErrors & ERROR_NF_CORRECTABLE) { 616 debugf0("\tCorrected bits= 0x%lx\n", allErrors); 617 618 branch = extract_fbdchan_indx(info->ferr_nf_fbd); 619 620 channel = 0; 621 if (REC_ECC_LOCATOR_ODD(info->redmemb)) 622 channel = 1; 623 624 /* Convert channel to be based from zero, instead of 625 * from branch base of 0 */ 626 channel += branch; 627 628 bank = rec_bank(info); 629 rank = rec_rank(info); 630 rdwr = rec_rdwr(info); 631 ras = rec_ras(info); 632 cas = rec_cas(info); 633 634 /* Only 1 bit will be on */ 635 errnum = find_first_bit(&allErrors, ARRAY_SIZE(error_name)); 636 637 debugf0("\t\tDIMM= %d Channel= %d (Branch %d " 638 "DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n", 639 rank, channel, branch >> 1, bank, 640 rdwr_str(rdwr), ras, cas); 641 642 /* Form out message */ 643 snprintf(msg, sizeof(msg), 644 "Corrected error (Branch=%d DRAM-Bank=%d RDWR=%s " 645 "RAS=%d CAS=%d, CE Err=0x%lx (%s))", 646 branch >> 1, bank, rdwr_str(rdwr), ras, cas, 647 allErrors, error_name[errnum]); 648 649 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 0, 0, 0, 650 branch >> 1, channel % 2, rank, 651 rdwr ? "Write error" : "Read error", 652 msg, NULL); 653 654 return; 655 } 656 657 /* Miscellaneous errors */ 658 errnum = find_first_bit(&allErrors, ARRAY_SIZE(error_name)); 659 660 branch = extract_fbdchan_indx(info->ferr_nf_fbd); 661 662 i5400_mc_printk(mci, KERN_EMERG, 663 "Non-Fatal misc error (Branch=%d Err=%#lx (%s))", 664 branch >> 1, allErrors, error_name[errnum]); 665 } 666 667 /* 668 * i5400_process_error_info Process the error info that is 669 * in the 'info' structure, previously retrieved from hardware 670 */ 671 static void i5400_process_error_info(struct mem_ctl_info *mci, 672 struct i5400_error_info *info) 673 { u32 allErrors; 674 675 /* First handle any fatal errors that occurred */ 676 allErrors = (info->ferr_fat_fbd & FERR_FAT_MASK); 677 i5400_proccess_non_recoverable_info(mci, info, allErrors); 678 679 /* now handle any non-fatal errors that occurred */ 680 i5400_process_nonfatal_error_info(mci, info); 681 } 682 683 /* 684 * i5400_clear_error Retrieve any error from the hardware 685 * but do NOT process that error. 686 * Used for 'clearing' out of previous errors 687 * Called by the Core module. 688 */ 689 static void i5400_clear_error(struct mem_ctl_info *mci) 690 { 691 struct i5400_error_info info; 692 693 i5400_get_error_info(mci, &info); 694 } 695 696 /* 697 * i5400_check_error Retrieve and process errors reported by the 698 * hardware. Called by the Core module. 699 */ 700 static void i5400_check_error(struct mem_ctl_info *mci) 701 { 702 struct i5400_error_info info; 703 debugf4("MC%d: %s: %s()\n", mci->mc_idx, __FILE__, __func__); 704 i5400_get_error_info(mci, &info); 705 i5400_process_error_info(mci, &info); 706 } 707 708 /* 709 * i5400_put_devices 'put' all the devices that we have 710 * reserved via 'get' 711 */ 712 static void i5400_put_devices(struct mem_ctl_info *mci) 713 { 714 struct i5400_pvt *pvt; 715 716 pvt = mci->pvt_info; 717 718 /* Decrement usage count for devices */ 719 pci_dev_put(pvt->branch_1); 720 pci_dev_put(pvt->branch_0); 721 pci_dev_put(pvt->fsb_error_regs); 722 pci_dev_put(pvt->branchmap_werrors); 723 } 724 725 /* 726 * i5400_get_devices Find and perform 'get' operation on the MCH's 727 * device/functions we want to reference for this driver 728 * 729 * Need to 'get' device 16 func 1 and func 2 730 */ 731 static int i5400_get_devices(struct mem_ctl_info *mci, int dev_idx) 732 { 733 struct i5400_pvt *pvt; 734 struct pci_dev *pdev; 735 736 pvt = mci->pvt_info; 737 pvt->branchmap_werrors = NULL; 738 pvt->fsb_error_regs = NULL; 739 pvt->branch_0 = NULL; 740 pvt->branch_1 = NULL; 741 742 /* Attempt to 'get' the MCH register we want */ 743 pdev = NULL; 744 while (1) { 745 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 746 PCI_DEVICE_ID_INTEL_5400_ERR, pdev); 747 if (!pdev) { 748 /* End of list, leave */ 749 i5400_printk(KERN_ERR, 750 "'system address,Process Bus' " 751 "device not found:" 752 "vendor 0x%x device 0x%x ERR func 1 " 753 "(broken BIOS?)\n", 754 PCI_VENDOR_ID_INTEL, 755 PCI_DEVICE_ID_INTEL_5400_ERR); 756 return -ENODEV; 757 } 758 759 /* Store device 16 func 1 */ 760 if (PCI_FUNC(pdev->devfn) == 1) 761 break; 762 } 763 pvt->branchmap_werrors = pdev; 764 765 pdev = NULL; 766 while (1) { 767 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 768 PCI_DEVICE_ID_INTEL_5400_ERR, pdev); 769 if (!pdev) { 770 /* End of list, leave */ 771 i5400_printk(KERN_ERR, 772 "'system address,Process Bus' " 773 "device not found:" 774 "vendor 0x%x device 0x%x ERR func 2 " 775 "(broken BIOS?)\n", 776 PCI_VENDOR_ID_INTEL, 777 PCI_DEVICE_ID_INTEL_5400_ERR); 778 779 pci_dev_put(pvt->branchmap_werrors); 780 return -ENODEV; 781 } 782 783 /* Store device 16 func 2 */ 784 if (PCI_FUNC(pdev->devfn) == 2) 785 break; 786 } 787 pvt->fsb_error_regs = pdev; 788 789 debugf1("System Address, processor bus- PCI Bus ID: %s %x:%x\n", 790 pci_name(pvt->system_address), 791 pvt->system_address->vendor, pvt->system_address->device); 792 debugf1("Branchmap, control and errors - PCI Bus ID: %s %x:%x\n", 793 pci_name(pvt->branchmap_werrors), 794 pvt->branchmap_werrors->vendor, pvt->branchmap_werrors->device); 795 debugf1("FSB Error Regs - PCI Bus ID: %s %x:%x\n", 796 pci_name(pvt->fsb_error_regs), 797 pvt->fsb_error_regs->vendor, pvt->fsb_error_regs->device); 798 799 pvt->branch_0 = pci_get_device(PCI_VENDOR_ID_INTEL, 800 PCI_DEVICE_ID_INTEL_5400_FBD0, NULL); 801 if (!pvt->branch_0) { 802 i5400_printk(KERN_ERR, 803 "MC: 'BRANCH 0' device not found:" 804 "vendor 0x%x device 0x%x Func 0 (broken BIOS?)\n", 805 PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5400_FBD0); 806 807 pci_dev_put(pvt->fsb_error_regs); 808 pci_dev_put(pvt->branchmap_werrors); 809 return -ENODEV; 810 } 811 812 /* If this device claims to have more than 2 channels then 813 * fetch Branch 1's information 814 */ 815 if (pvt->maxch < CHANNELS_PER_BRANCH) 816 return 0; 817 818 pvt->branch_1 = pci_get_device(PCI_VENDOR_ID_INTEL, 819 PCI_DEVICE_ID_INTEL_5400_FBD1, NULL); 820 if (!pvt->branch_1) { 821 i5400_printk(KERN_ERR, 822 "MC: 'BRANCH 1' device not found:" 823 "vendor 0x%x device 0x%x Func 0 " 824 "(broken BIOS?)\n", 825 PCI_VENDOR_ID_INTEL, 826 PCI_DEVICE_ID_INTEL_5400_FBD1); 827 828 pci_dev_put(pvt->branch_0); 829 pci_dev_put(pvt->fsb_error_regs); 830 pci_dev_put(pvt->branchmap_werrors); 831 return -ENODEV; 832 } 833 834 return 0; 835 } 836 837 /* 838 * determine_amb_present 839 * 840 * the information is contained in DIMMS_PER_CHANNEL different 841 * registers determining which of the DIMMS_PER_CHANNEL requires 842 * knowing which channel is in question 843 * 844 * 2 branches, each with 2 channels 845 * b0_ambpresent0 for channel '0' 846 * b0_ambpresent1 for channel '1' 847 * b1_ambpresent0 for channel '2' 848 * b1_ambpresent1 for channel '3' 849 */ 850 static int determine_amb_present_reg(struct i5400_pvt *pvt, int channel) 851 { 852 int amb_present; 853 854 if (channel < CHANNELS_PER_BRANCH) { 855 if (channel & 0x1) 856 amb_present = pvt->b0_ambpresent1; 857 else 858 amb_present = pvt->b0_ambpresent0; 859 } else { 860 if (channel & 0x1) 861 amb_present = pvt->b1_ambpresent1; 862 else 863 amb_present = pvt->b1_ambpresent0; 864 } 865 866 return amb_present; 867 } 868 869 /* 870 * determine_mtr(pvt, dimm, channel) 871 * 872 * return the proper MTR register as determine by the dimm and desired channel 873 */ 874 static int determine_mtr(struct i5400_pvt *pvt, int dimm, int channel) 875 { 876 int mtr; 877 int n; 878 879 /* There is one MTR for each slot pair of FB-DIMMs, 880 Each slot pair may be at branch 0 or branch 1. 881 */ 882 n = dimm; 883 884 if (n >= DIMMS_PER_CHANNEL) { 885 debugf0("ERROR: trying to access an invalid dimm: %d\n", 886 dimm); 887 return 0; 888 } 889 890 if (channel < CHANNELS_PER_BRANCH) 891 mtr = pvt->b0_mtr[n]; 892 else 893 mtr = pvt->b1_mtr[n]; 894 895 return mtr; 896 } 897 898 /* 899 */ 900 static void decode_mtr(int slot_row, u16 mtr) 901 { 902 int ans; 903 904 ans = MTR_DIMMS_PRESENT(mtr); 905 906 debugf2("\tMTR%d=0x%x: DIMMs are %s\n", slot_row, mtr, 907 ans ? "Present" : "NOT Present"); 908 if (!ans) 909 return; 910 911 debugf2("\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr)); 912 913 debugf2("\t\tELECTRICAL THROTTLING is %s\n", 914 MTR_DIMMS_ETHROTTLE(mtr) ? "enabled" : "disabled"); 915 916 debugf2("\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr)); 917 debugf2("\t\tNUMRANK: %s\n", MTR_DIMM_RANK(mtr) ? "double" : "single"); 918 debugf2("\t\tNUMROW: %s\n", numrow_toString[MTR_DIMM_ROWS(mtr)]); 919 debugf2("\t\tNUMCOL: %s\n", numcol_toString[MTR_DIMM_COLS(mtr)]); 920 } 921 922 static void handle_channel(struct i5400_pvt *pvt, int dimm, int channel, 923 struct i5400_dimm_info *dinfo) 924 { 925 int mtr; 926 int amb_present_reg; 927 int addrBits; 928 929 mtr = determine_mtr(pvt, dimm, channel); 930 if (MTR_DIMMS_PRESENT(mtr)) { 931 amb_present_reg = determine_amb_present_reg(pvt, channel); 932 933 /* Determine if there is a DIMM present in this DIMM slot */ 934 if (amb_present_reg & (1 << dimm)) { 935 /* Start with the number of bits for a Bank 936 * on the DRAM */ 937 addrBits = MTR_DRAM_BANKS_ADDR_BITS(mtr); 938 /* Add thenumber of ROW bits */ 939 addrBits += MTR_DIMM_ROWS_ADDR_BITS(mtr); 940 /* add the number of COLUMN bits */ 941 addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr); 942 /* add the number of RANK bits */ 943 addrBits += MTR_DIMM_RANK(mtr); 944 945 addrBits += 6; /* add 64 bits per DIMM */ 946 addrBits -= 20; /* divide by 2^^20 */ 947 addrBits -= 3; /* 8 bits per bytes */ 948 949 dinfo->megabytes = 1 << addrBits; 950 } 951 } 952 } 953 954 /* 955 * calculate_dimm_size 956 * 957 * also will output a DIMM matrix map, if debug is enabled, for viewing 958 * how the DIMMs are populated 959 */ 960 static void calculate_dimm_size(struct i5400_pvt *pvt) 961 { 962 struct i5400_dimm_info *dinfo; 963 int dimm, max_dimms; 964 char *p, *mem_buffer; 965 int space, n; 966 int channel, branch; 967 968 /* ================= Generate some debug output ================= */ 969 space = PAGE_SIZE; 970 mem_buffer = p = kmalloc(space, GFP_KERNEL); 971 if (p == NULL) { 972 i5400_printk(KERN_ERR, "MC: %s:%s() kmalloc() failed\n", 973 __FILE__, __func__); 974 return; 975 } 976 977 /* Scan all the actual DIMMS 978 * and calculate the information for each DIMM 979 * Start with the highest dimm first, to display it first 980 * and work toward the 0th dimm 981 */ 982 max_dimms = pvt->maxdimmperch; 983 for (dimm = max_dimms - 1; dimm >= 0; dimm--) { 984 985 /* on an odd dimm, first output a 'boundary' marker, 986 * then reset the message buffer */ 987 if (dimm & 0x1) { 988 n = snprintf(p, space, "---------------------------" 989 "-------------------------------"); 990 p += n; 991 space -= n; 992 debugf2("%s\n", mem_buffer); 993 p = mem_buffer; 994 space = PAGE_SIZE; 995 } 996 n = snprintf(p, space, "dimm %2d ", dimm); 997 p += n; 998 space -= n; 999 1000 for (channel = 0; channel < pvt->maxch; channel++) { 1001 dinfo = &pvt->dimm_info[dimm][channel]; 1002 handle_channel(pvt, dimm, channel, dinfo); 1003 n = snprintf(p, space, "%4d MB | ", dinfo->megabytes); 1004 p += n; 1005 space -= n; 1006 } 1007 debugf2("%s\n", mem_buffer); 1008 p = mem_buffer; 1009 space = PAGE_SIZE; 1010 } 1011 1012 /* Output the last bottom 'boundary' marker */ 1013 n = snprintf(p, space, "---------------------------" 1014 "-------------------------------"); 1015 p += n; 1016 space -= n; 1017 debugf2("%s\n", mem_buffer); 1018 p = mem_buffer; 1019 space = PAGE_SIZE; 1020 1021 /* now output the 'channel' labels */ 1022 n = snprintf(p, space, " "); 1023 p += n; 1024 space -= n; 1025 for (channel = 0; channel < pvt->maxch; channel++) { 1026 n = snprintf(p, space, "channel %d | ", channel); 1027 p += n; 1028 space -= n; 1029 } 1030 1031 space -= n; 1032 debugf2("%s\n", mem_buffer); 1033 p = mem_buffer; 1034 space = PAGE_SIZE; 1035 1036 n = snprintf(p, space, " "); 1037 p += n; 1038 for (branch = 0; branch < MAX_BRANCHES; branch++) { 1039 n = snprintf(p, space, " branch %d | ", branch); 1040 p += n; 1041 space -= n; 1042 } 1043 1044 /* output the last message and free buffer */ 1045 debugf2("%s\n", mem_buffer); 1046 kfree(mem_buffer); 1047 } 1048 1049 /* 1050 * i5400_get_mc_regs read in the necessary registers and 1051 * cache locally 1052 * 1053 * Fills in the private data members 1054 */ 1055 static void i5400_get_mc_regs(struct mem_ctl_info *mci) 1056 { 1057 struct i5400_pvt *pvt; 1058 u32 actual_tolm; 1059 u16 limit; 1060 int slot_row; 1061 int maxch; 1062 int maxdimmperch; 1063 int way0, way1; 1064 1065 pvt = mci->pvt_info; 1066 1067 pci_read_config_dword(pvt->system_address, AMBASE, 1068 (u32 *) &pvt->ambase); 1069 pci_read_config_dword(pvt->system_address, AMBASE + sizeof(u32), 1070 ((u32 *) &pvt->ambase) + sizeof(u32)); 1071 1072 maxdimmperch = pvt->maxdimmperch; 1073 maxch = pvt->maxch; 1074 1075 debugf2("AMBASE= 0x%lx MAXCH= %d MAX-DIMM-Per-CH= %d\n", 1076 (long unsigned int)pvt->ambase, pvt->maxch, pvt->maxdimmperch); 1077 1078 /* Get the Branch Map regs */ 1079 pci_read_config_word(pvt->branchmap_werrors, TOLM, &pvt->tolm); 1080 pvt->tolm >>= 12; 1081 debugf2("\nTOLM (number of 256M regions) =%u (0x%x)\n", pvt->tolm, 1082 pvt->tolm); 1083 1084 actual_tolm = (u32) ((1000l * pvt->tolm) >> (30 - 28)); 1085 debugf2("Actual TOLM byte addr=%u.%03u GB (0x%x)\n", 1086 actual_tolm/1000, actual_tolm % 1000, pvt->tolm << 28); 1087 1088 pci_read_config_word(pvt->branchmap_werrors, MIR0, &pvt->mir0); 1089 pci_read_config_word(pvt->branchmap_werrors, MIR1, &pvt->mir1); 1090 1091 /* Get the MIR[0-1] regs */ 1092 limit = (pvt->mir0 >> 4) & 0x0fff; 1093 way0 = pvt->mir0 & 0x1; 1094 way1 = pvt->mir0 & 0x2; 1095 debugf2("MIR0: limit= 0x%x WAY1= %u WAY0= %x\n", limit, way1, way0); 1096 limit = (pvt->mir1 >> 4) & 0xfff; 1097 way0 = pvt->mir1 & 0x1; 1098 way1 = pvt->mir1 & 0x2; 1099 debugf2("MIR1: limit= 0x%x WAY1= %u WAY0= %x\n", limit, way1, way0); 1100 1101 /* Get the set of MTR[0-3] regs by each branch */ 1102 for (slot_row = 0; slot_row < DIMMS_PER_CHANNEL; slot_row++) { 1103 int where = MTR0 + (slot_row * sizeof(u16)); 1104 1105 /* Branch 0 set of MTR registers */ 1106 pci_read_config_word(pvt->branch_0, where, 1107 &pvt->b0_mtr[slot_row]); 1108 1109 debugf2("MTR%d where=0x%x B0 value=0x%x\n", slot_row, where, 1110 pvt->b0_mtr[slot_row]); 1111 1112 if (pvt->maxch < CHANNELS_PER_BRANCH) { 1113 pvt->b1_mtr[slot_row] = 0; 1114 continue; 1115 } 1116 1117 /* Branch 1 set of MTR registers */ 1118 pci_read_config_word(pvt->branch_1, where, 1119 &pvt->b1_mtr[slot_row]); 1120 debugf2("MTR%d where=0x%x B1 value=0x%x\n", slot_row, where, 1121 pvt->b1_mtr[slot_row]); 1122 } 1123 1124 /* Read and dump branch 0's MTRs */ 1125 debugf2("\nMemory Technology Registers:\n"); 1126 debugf2(" Branch 0:\n"); 1127 for (slot_row = 0; slot_row < DIMMS_PER_CHANNEL; slot_row++) 1128 decode_mtr(slot_row, pvt->b0_mtr[slot_row]); 1129 1130 pci_read_config_word(pvt->branch_0, AMBPRESENT_0, 1131 &pvt->b0_ambpresent0); 1132 debugf2("\t\tAMB-Branch 0-present0 0x%x:\n", pvt->b0_ambpresent0); 1133 pci_read_config_word(pvt->branch_0, AMBPRESENT_1, 1134 &pvt->b0_ambpresent1); 1135 debugf2("\t\tAMB-Branch 0-present1 0x%x:\n", pvt->b0_ambpresent1); 1136 1137 /* Only if we have 2 branchs (4 channels) */ 1138 if (pvt->maxch < CHANNELS_PER_BRANCH) { 1139 pvt->b1_ambpresent0 = 0; 1140 pvt->b1_ambpresent1 = 0; 1141 } else { 1142 /* Read and dump branch 1's MTRs */ 1143 debugf2(" Branch 1:\n"); 1144 for (slot_row = 0; slot_row < DIMMS_PER_CHANNEL; slot_row++) 1145 decode_mtr(slot_row, pvt->b1_mtr[slot_row]); 1146 1147 pci_read_config_word(pvt->branch_1, AMBPRESENT_0, 1148 &pvt->b1_ambpresent0); 1149 debugf2("\t\tAMB-Branch 1-present0 0x%x:\n", 1150 pvt->b1_ambpresent0); 1151 pci_read_config_word(pvt->branch_1, AMBPRESENT_1, 1152 &pvt->b1_ambpresent1); 1153 debugf2("\t\tAMB-Branch 1-present1 0x%x:\n", 1154 pvt->b1_ambpresent1); 1155 } 1156 1157 /* Go and determine the size of each DIMM and place in an 1158 * orderly matrix */ 1159 calculate_dimm_size(pvt); 1160 } 1161 1162 /* 1163 * i5400_init_dimms Initialize the 'dimms' table within 1164 * the mci control structure with the 1165 * addressing of memory. 1166 * 1167 * return: 1168 * 0 success 1169 * 1 no actual memory found on this MC 1170 */ 1171 static int i5400_init_dimms(struct mem_ctl_info *mci) 1172 { 1173 struct i5400_pvt *pvt; 1174 struct dimm_info *dimm; 1175 int ndimms, channel_count; 1176 int max_dimms; 1177 int mtr; 1178 int size_mb; 1179 int channel, slot; 1180 1181 pvt = mci->pvt_info; 1182 1183 channel_count = pvt->maxch; 1184 max_dimms = pvt->maxdimmperch; 1185 1186 ndimms = 0; 1187 1188 /* 1189 * FIXME: remove pvt->dimm_info[slot][channel] and use the 3 1190 * layers here. 1191 */ 1192 for (channel = 0; channel < mci->layers[0].size * mci->layers[1].size; 1193 channel++) { 1194 for (slot = 0; slot < mci->layers[2].size; slot++) { 1195 mtr = determine_mtr(pvt, slot, channel); 1196 1197 /* if no DIMMS on this slot, continue */ 1198 if (!MTR_DIMMS_PRESENT(mtr)) 1199 continue; 1200 1201 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, 1202 channel / 2, channel % 2, slot); 1203 1204 size_mb = pvt->dimm_info[slot][channel].megabytes; 1205 1206 debugf2("%s: dimm (branch %d channel %d slot %d): %d.%03d GB\n", 1207 __func__, 1208 channel / 2, channel % 2, slot, 1209 size_mb / 1000, size_mb % 1000); 1210 1211 dimm->nr_pages = size_mb << 8; 1212 dimm->grain = 8; 1213 dimm->dtype = MTR_DRAM_WIDTH(mtr) ? DEV_X8 : DEV_X4; 1214 dimm->mtype = MEM_FB_DDR2; 1215 /* 1216 * The eccc mechanism is SDDC (aka SECC), with 1217 * is similar to Chipkill. 1218 */ 1219 dimm->edac_mode = MTR_DRAM_WIDTH(mtr) ? 1220 EDAC_S8ECD8ED : EDAC_S4ECD4ED; 1221 ndimms++; 1222 } 1223 } 1224 1225 /* 1226 * When just one memory is provided, it should be at location (0,0,0). 1227 * With such single-DIMM mode, the SDCC algorithm degrades to SECDEC+. 1228 */ 1229 if (ndimms == 1) 1230 mci->dimms[0]->edac_mode = EDAC_SECDED; 1231 1232 return (ndimms == 0); 1233 } 1234 1235 /* 1236 * i5400_enable_error_reporting 1237 * Turn on the memory reporting features of the hardware 1238 */ 1239 static void i5400_enable_error_reporting(struct mem_ctl_info *mci) 1240 { 1241 struct i5400_pvt *pvt; 1242 u32 fbd_error_mask; 1243 1244 pvt = mci->pvt_info; 1245 1246 /* Read the FBD Error Mask Register */ 1247 pci_read_config_dword(pvt->branchmap_werrors, EMASK_FBD, 1248 &fbd_error_mask); 1249 1250 /* Enable with a '0' */ 1251 fbd_error_mask &= ~(ENABLE_EMASK_ALL); 1252 1253 pci_write_config_dword(pvt->branchmap_werrors, EMASK_FBD, 1254 fbd_error_mask); 1255 } 1256 1257 /* 1258 * i5400_probe1 Probe for ONE instance of device to see if it is 1259 * present. 1260 * return: 1261 * 0 for FOUND a device 1262 * < 0 for error code 1263 */ 1264 static int i5400_probe1(struct pci_dev *pdev, int dev_idx) 1265 { 1266 struct mem_ctl_info *mci; 1267 struct i5400_pvt *pvt; 1268 struct edac_mc_layer layers[3]; 1269 1270 if (dev_idx >= ARRAY_SIZE(i5400_devs)) 1271 return -EINVAL; 1272 1273 debugf0("MC: %s: %s(), pdev bus %u dev=0x%x fn=0x%x\n", 1274 __FILE__, __func__, 1275 pdev->bus->number, 1276 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); 1277 1278 /* We only are looking for func 0 of the set */ 1279 if (PCI_FUNC(pdev->devfn) != 0) 1280 return -ENODEV; 1281 1282 /* 1283 * allocate a new MC control structure 1284 * 1285 * This drivers uses the DIMM slot as "csrow" and the rest as "channel". 1286 */ 1287 layers[0].type = EDAC_MC_LAYER_BRANCH; 1288 layers[0].size = MAX_BRANCHES; 1289 layers[0].is_virt_csrow = false; 1290 layers[1].type = EDAC_MC_LAYER_CHANNEL; 1291 layers[1].size = CHANNELS_PER_BRANCH; 1292 layers[1].is_virt_csrow = false; 1293 layers[2].type = EDAC_MC_LAYER_SLOT; 1294 layers[2].size = DIMMS_PER_CHANNEL; 1295 layers[2].is_virt_csrow = true; 1296 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt)); 1297 if (mci == NULL) 1298 return -ENOMEM; 1299 1300 debugf0("MC: %s: %s(): mci = %p\n", __FILE__, __func__, mci); 1301 1302 mci->pdev = &pdev->dev; /* record ptr to the generic device */ 1303 1304 pvt = mci->pvt_info; 1305 pvt->system_address = pdev; /* Record this device in our private */ 1306 pvt->maxch = MAX_CHANNELS; 1307 pvt->maxdimmperch = DIMMS_PER_CHANNEL; 1308 1309 /* 'get' the pci devices we want to reserve for our use */ 1310 if (i5400_get_devices(mci, dev_idx)) 1311 goto fail0; 1312 1313 /* Time to get serious */ 1314 i5400_get_mc_regs(mci); /* retrieve the hardware registers */ 1315 1316 mci->mc_idx = 0; 1317 mci->mtype_cap = MEM_FLAG_FB_DDR2; 1318 mci->edac_ctl_cap = EDAC_FLAG_NONE; 1319 mci->edac_cap = EDAC_FLAG_NONE; 1320 mci->mod_name = "i5400_edac.c"; 1321 mci->mod_ver = I5400_REVISION; 1322 mci->ctl_name = i5400_devs[dev_idx].ctl_name; 1323 mci->dev_name = pci_name(pdev); 1324 mci->ctl_page_to_phys = NULL; 1325 1326 /* Set the function pointer to an actual operation function */ 1327 mci->edac_check = i5400_check_error; 1328 1329 /* initialize the MC control structure 'dimms' table 1330 * with the mapping and control information */ 1331 if (i5400_init_dimms(mci)) { 1332 debugf0("MC: Setting mci->edac_cap to EDAC_FLAG_NONE\n" 1333 " because i5400_init_dimms() returned nonzero " 1334 "value\n"); 1335 mci->edac_cap = EDAC_FLAG_NONE; /* no dimms found */ 1336 } else { 1337 debugf1("MC: Enable error reporting now\n"); 1338 i5400_enable_error_reporting(mci); 1339 } 1340 1341 /* add this new MC control structure to EDAC's list of MCs */ 1342 if (edac_mc_add_mc(mci)) { 1343 debugf0("MC: %s: %s(): failed edac_mc_add_mc()\n", 1344 __FILE__, __func__); 1345 /* FIXME: perhaps some code should go here that disables error 1346 * reporting if we just enabled it 1347 */ 1348 goto fail1; 1349 } 1350 1351 i5400_clear_error(mci); 1352 1353 /* allocating generic PCI control info */ 1354 i5400_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR); 1355 if (!i5400_pci) { 1356 printk(KERN_WARNING 1357 "%s(): Unable to create PCI control\n", 1358 __func__); 1359 printk(KERN_WARNING 1360 "%s(): PCI error report via EDAC not setup\n", 1361 __func__); 1362 } 1363 1364 return 0; 1365 1366 /* Error exit unwinding stack */ 1367 fail1: 1368 1369 i5400_put_devices(mci); 1370 1371 fail0: 1372 edac_mc_free(mci); 1373 return -ENODEV; 1374 } 1375 1376 /* 1377 * i5400_init_one constructor for one instance of device 1378 * 1379 * returns: 1380 * negative on error 1381 * count (>= 0) 1382 */ 1383 static int __devinit i5400_init_one(struct pci_dev *pdev, 1384 const struct pci_device_id *id) 1385 { 1386 int rc; 1387 1388 debugf0("MC: %s: %s()\n", __FILE__, __func__); 1389 1390 /* wake up device */ 1391 rc = pci_enable_device(pdev); 1392 if (rc) 1393 return rc; 1394 1395 /* now probe and enable the device */ 1396 return i5400_probe1(pdev, id->driver_data); 1397 } 1398 1399 /* 1400 * i5400_remove_one destructor for one instance of device 1401 * 1402 */ 1403 static void __devexit i5400_remove_one(struct pci_dev *pdev) 1404 { 1405 struct mem_ctl_info *mci; 1406 1407 debugf0("%s: %s()\n", __FILE__, __func__); 1408 1409 if (i5400_pci) 1410 edac_pci_release_generic_ctl(i5400_pci); 1411 1412 mci = edac_mc_del_mc(&pdev->dev); 1413 if (!mci) 1414 return; 1415 1416 /* retrieve references to resources, and free those resources */ 1417 i5400_put_devices(mci); 1418 1419 edac_mc_free(mci); 1420 } 1421 1422 /* 1423 * pci_device_id table for which devices we are looking for 1424 * 1425 * The "E500P" device is the first device supported. 1426 */ 1427 static DEFINE_PCI_DEVICE_TABLE(i5400_pci_tbl) = { 1428 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5400_ERR)}, 1429 {0,} /* 0 terminated list. */ 1430 }; 1431 1432 MODULE_DEVICE_TABLE(pci, i5400_pci_tbl); 1433 1434 /* 1435 * i5400_driver pci_driver structure for this module 1436 * 1437 */ 1438 static struct pci_driver i5400_driver = { 1439 .name = "i5400_edac", 1440 .probe = i5400_init_one, 1441 .remove = __devexit_p(i5400_remove_one), 1442 .id_table = i5400_pci_tbl, 1443 }; 1444 1445 /* 1446 * i5400_init Module entry function 1447 * Try to initialize this module for its devices 1448 */ 1449 static int __init i5400_init(void) 1450 { 1451 int pci_rc; 1452 1453 debugf2("MC: %s: %s()\n", __FILE__, __func__); 1454 1455 /* Ensure that the OPSTATE is set correctly for POLL or NMI */ 1456 opstate_init(); 1457 1458 pci_rc = pci_register_driver(&i5400_driver); 1459 1460 return (pci_rc < 0) ? pci_rc : 0; 1461 } 1462 1463 /* 1464 * i5400_exit() Module exit function 1465 * Unregister the driver 1466 */ 1467 static void __exit i5400_exit(void) 1468 { 1469 debugf2("MC: %s: %s()\n", __FILE__, __func__); 1470 pci_unregister_driver(&i5400_driver); 1471 } 1472 1473 module_init(i5400_init); 1474 module_exit(i5400_exit); 1475 1476 MODULE_LICENSE("GPL"); 1477 MODULE_AUTHOR("Ben Woodard <woodard@redhat.com>"); 1478 MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); 1479 MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)"); 1480 MODULE_DESCRIPTION("MC Driver for Intel I5400 memory controllers - " 1481 I5400_REVISION); 1482 1483 module_param(edac_op_state, int, 0444); 1484 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); 1485