1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * GPIO controller in LSI ZEVIO SoCs. 4 * 5 * Author: Fabian Vogt <fabian@ritter-vogt.de> 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/errno.h> 10 #include <linux/init.h> 11 #include <linux/io.h> 12 #include <linux/mod_devicetable.h> 13 #include <linux/platform_device.h> 14 #include <linux/slab.h> 15 #include <linux/spinlock.h> 16 17 #include <linux/gpio/driver.h> 18 19 /* 20 * Memory layout: 21 * This chip has four gpio sections, each controls 8 GPIOs. 22 * Bit 0 in section 0 is GPIO 0, bit 2 in section 1 is GPIO 10. 23 * Disclaimer: Reverse engineered! 24 * For more information refer to: 25 * http://hackspire.unsads.com/wiki/index.php/Memory-mapped_I/O_ports#90000000_-_General_Purpose_I.2FO_.28GPIO.29 26 * 27 * 0x00-0x3F: Section 0 28 * +0x00: Masked interrupt status (read-only) 29 * +0x04: R: Interrupt status W: Reset interrupt status 30 * +0x08: R: Interrupt mask W: Mask interrupt 31 * +0x0C: W: Unmask interrupt (write-only) 32 * +0x10: Direction: I/O=1/0 33 * +0x14: Output 34 * +0x18: Input (read-only) 35 * +0x20: R: Level interrupt W: Set as level interrupt 36 * 0x40-0x7F: Section 1 37 * 0x80-0xBF: Section 2 38 * 0xC0-0xFF: Section 3 39 */ 40 41 #define ZEVIO_GPIO_SECTION_SIZE 0x40 42 43 /* Offsets to various registers */ 44 #define ZEVIO_GPIO_INT_MASKED_STATUS 0x00 45 #define ZEVIO_GPIO_INT_STATUS 0x04 46 #define ZEVIO_GPIO_INT_UNMASK 0x08 47 #define ZEVIO_GPIO_INT_MASK 0x0C 48 #define ZEVIO_GPIO_DIRECTION 0x10 49 #define ZEVIO_GPIO_OUTPUT 0x14 50 #define ZEVIO_GPIO_INPUT 0x18 51 #define ZEVIO_GPIO_INT_STICKY 0x20 52 53 /* Bit number of GPIO in its section */ 54 #define ZEVIO_GPIO_BIT(gpio) (gpio&7) 55 56 struct zevio_gpio { 57 struct gpio_chip chip; 58 spinlock_t lock; 59 void __iomem *regs; 60 }; 61 62 static inline u32 zevio_gpio_port_get(struct zevio_gpio *c, unsigned pin, 63 unsigned port_offset) 64 { 65 unsigned section_offset = ((pin >> 3) & 3)*ZEVIO_GPIO_SECTION_SIZE; 66 return readl(IOMEM(c->regs + section_offset + port_offset)); 67 } 68 69 static inline void zevio_gpio_port_set(struct zevio_gpio *c, unsigned pin, 70 unsigned port_offset, u32 val) 71 { 72 unsigned section_offset = ((pin >> 3) & 3)*ZEVIO_GPIO_SECTION_SIZE; 73 writel(val, IOMEM(c->regs + section_offset + port_offset)); 74 } 75 76 /* Functions for struct gpio_chip */ 77 static int zevio_gpio_get(struct gpio_chip *chip, unsigned pin) 78 { 79 struct zevio_gpio *controller = gpiochip_get_data(chip); 80 u32 val, dir; 81 82 spin_lock(&controller->lock); 83 dir = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_DIRECTION); 84 if (dir & BIT(ZEVIO_GPIO_BIT(pin))) 85 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_INPUT); 86 else 87 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_OUTPUT); 88 spin_unlock(&controller->lock); 89 90 return (val >> ZEVIO_GPIO_BIT(pin)) & 0x1; 91 } 92 93 static void zevio_gpio_set(struct gpio_chip *chip, unsigned pin, int value) 94 { 95 struct zevio_gpio *controller = gpiochip_get_data(chip); 96 u32 val; 97 98 spin_lock(&controller->lock); 99 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_OUTPUT); 100 if (value) 101 val |= BIT(ZEVIO_GPIO_BIT(pin)); 102 else 103 val &= ~BIT(ZEVIO_GPIO_BIT(pin)); 104 105 zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_OUTPUT, val); 106 spin_unlock(&controller->lock); 107 } 108 109 static int zevio_gpio_direction_input(struct gpio_chip *chip, unsigned pin) 110 { 111 struct zevio_gpio *controller = gpiochip_get_data(chip); 112 u32 val; 113 114 spin_lock(&controller->lock); 115 116 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_DIRECTION); 117 val |= BIT(ZEVIO_GPIO_BIT(pin)); 118 zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_DIRECTION, val); 119 120 spin_unlock(&controller->lock); 121 122 return 0; 123 } 124 125 static int zevio_gpio_direction_output(struct gpio_chip *chip, 126 unsigned pin, int value) 127 { 128 struct zevio_gpio *controller = gpiochip_get_data(chip); 129 u32 val; 130 131 spin_lock(&controller->lock); 132 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_OUTPUT); 133 if (value) 134 val |= BIT(ZEVIO_GPIO_BIT(pin)); 135 else 136 val &= ~BIT(ZEVIO_GPIO_BIT(pin)); 137 138 zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_OUTPUT, val); 139 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_DIRECTION); 140 val &= ~BIT(ZEVIO_GPIO_BIT(pin)); 141 zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_DIRECTION, val); 142 143 spin_unlock(&controller->lock); 144 145 return 0; 146 } 147 148 static int zevio_gpio_to_irq(struct gpio_chip *chip, unsigned pin) 149 { 150 /* 151 * TODO: Implement IRQs. 152 * Not implemented yet due to weird lockups 153 */ 154 155 return -ENXIO; 156 } 157 158 static const struct gpio_chip zevio_gpio_chip = { 159 .direction_input = zevio_gpio_direction_input, 160 .direction_output = zevio_gpio_direction_output, 161 .set = zevio_gpio_set, 162 .get = zevio_gpio_get, 163 .to_irq = zevio_gpio_to_irq, 164 .base = 0, 165 .owner = THIS_MODULE, 166 .ngpio = 32, 167 }; 168 169 /* Initialization */ 170 static int zevio_gpio_probe(struct platform_device *pdev) 171 { 172 struct zevio_gpio *controller; 173 int status, i; 174 175 controller = devm_kzalloc(&pdev->dev, sizeof(*controller), GFP_KERNEL); 176 if (!controller) 177 return -ENOMEM; 178 179 platform_set_drvdata(pdev, controller); 180 181 /* Copy our reference */ 182 controller->chip = zevio_gpio_chip; 183 controller->chip.parent = &pdev->dev; 184 185 controller->regs = devm_platform_ioremap_resource(pdev, 0); 186 if (IS_ERR(controller->regs)) 187 return dev_err_probe(&pdev->dev, PTR_ERR(controller->regs), 188 "failed to ioremap memory resource\n"); 189 190 status = devm_gpiochip_add_data(&pdev->dev, &controller->chip, controller); 191 if (status) { 192 dev_err(&pdev->dev, "failed to add gpiochip: %d\n", status); 193 return status; 194 } 195 196 spin_lock_init(&controller->lock); 197 198 /* Disable interrupts, they only cause errors */ 199 for (i = 0; i < controller->chip.ngpio; i += 8) 200 zevio_gpio_port_set(controller, i, ZEVIO_GPIO_INT_MASK, 0xFF); 201 202 dev_dbg(controller->chip.parent, "ZEVIO GPIO controller set up!\n"); 203 204 return 0; 205 } 206 207 static const struct of_device_id zevio_gpio_of_match[] = { 208 { .compatible = "lsi,zevio-gpio", }, 209 { }, 210 }; 211 212 static struct platform_driver zevio_gpio_driver = { 213 .driver = { 214 .name = "gpio-zevio", 215 .of_match_table = zevio_gpio_of_match, 216 .suppress_bind_attrs = true, 217 }, 218 .probe = zevio_gpio_probe, 219 }; 220 builtin_platform_driver(zevio_gpio_driver); 221