1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Dave Airlie 30 */ 31 #include <linux/seq_file.h> 32 #include <linux/atomic.h> 33 #include <linux/wait.h> 34 #include <linux/kref.h> 35 #include <linux/slab.h> 36 #include <linux/firmware.h> 37 #include <drm/drmP.h> 38 #include "amdgpu.h" 39 #include "amdgpu_trace.h" 40 41 /* 42 * Fences 43 * Fences mark an event in the GPUs pipeline and are used 44 * for GPU/CPU synchronization. When the fence is written, 45 * it is expected that all buffers associated with that fence 46 * are no longer in use by the associated ring on the GPU and 47 * that the the relevant GPU caches have been flushed. 48 */ 49 50 struct amdgpu_fence { 51 struct dma_fence base; 52 53 /* RB, DMA, etc. */ 54 struct amdgpu_ring *ring; 55 }; 56 57 static struct kmem_cache *amdgpu_fence_slab; 58 59 int amdgpu_fence_slab_init(void) 60 { 61 amdgpu_fence_slab = kmem_cache_create( 62 "amdgpu_fence", sizeof(struct amdgpu_fence), 0, 63 SLAB_HWCACHE_ALIGN, NULL); 64 if (!amdgpu_fence_slab) 65 return -ENOMEM; 66 return 0; 67 } 68 69 void amdgpu_fence_slab_fini(void) 70 { 71 rcu_barrier(); 72 kmem_cache_destroy(amdgpu_fence_slab); 73 } 74 /* 75 * Cast helper 76 */ 77 static const struct dma_fence_ops amdgpu_fence_ops; 78 static inline struct amdgpu_fence *to_amdgpu_fence(struct dma_fence *f) 79 { 80 struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base); 81 82 if (__f->base.ops == &amdgpu_fence_ops) 83 return __f; 84 85 return NULL; 86 } 87 88 /** 89 * amdgpu_fence_write - write a fence value 90 * 91 * @ring: ring the fence is associated with 92 * @seq: sequence number to write 93 * 94 * Writes a fence value to memory (all asics). 95 */ 96 static void amdgpu_fence_write(struct amdgpu_ring *ring, u32 seq) 97 { 98 struct amdgpu_fence_driver *drv = &ring->fence_drv; 99 100 if (drv->cpu_addr) 101 *drv->cpu_addr = cpu_to_le32(seq); 102 } 103 104 /** 105 * amdgpu_fence_read - read a fence value 106 * 107 * @ring: ring the fence is associated with 108 * 109 * Reads a fence value from memory (all asics). 110 * Returns the value of the fence read from memory. 111 */ 112 static u32 amdgpu_fence_read(struct amdgpu_ring *ring) 113 { 114 struct amdgpu_fence_driver *drv = &ring->fence_drv; 115 u32 seq = 0; 116 117 if (drv->cpu_addr) 118 seq = le32_to_cpu(*drv->cpu_addr); 119 else 120 seq = atomic_read(&drv->last_seq); 121 122 return seq; 123 } 124 125 /** 126 * amdgpu_fence_emit - emit a fence on the requested ring 127 * 128 * @ring: ring the fence is associated with 129 * @f: resulting fence object 130 * 131 * Emits a fence command on the requested ring (all asics). 132 * Returns 0 on success, -ENOMEM on failure. 133 */ 134 int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f, 135 unsigned flags) 136 { 137 struct amdgpu_device *adev = ring->adev; 138 struct amdgpu_fence *fence; 139 struct dma_fence __rcu **ptr; 140 uint32_t seq; 141 int r; 142 143 fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_KERNEL); 144 if (fence == NULL) 145 return -ENOMEM; 146 147 seq = ++ring->fence_drv.sync_seq; 148 fence->ring = ring; 149 dma_fence_init(&fence->base, &amdgpu_fence_ops, 150 &ring->fence_drv.lock, 151 adev->fence_context + ring->idx, 152 seq); 153 amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr, 154 seq, flags | AMDGPU_FENCE_FLAG_INT); 155 156 ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask]; 157 if (unlikely(rcu_dereference_protected(*ptr, 1))) { 158 struct dma_fence *old; 159 160 rcu_read_lock(); 161 old = dma_fence_get_rcu_safe(ptr); 162 rcu_read_unlock(); 163 164 if (old) { 165 r = dma_fence_wait(old, false); 166 dma_fence_put(old); 167 if (r) 168 return r; 169 } 170 } 171 172 /* This function can't be called concurrently anyway, otherwise 173 * emitting the fence would mess up the hardware ring buffer. 174 */ 175 rcu_assign_pointer(*ptr, dma_fence_get(&fence->base)); 176 177 *f = &fence->base; 178 179 return 0; 180 } 181 182 /** 183 * amdgpu_fence_emit_polling - emit a fence on the requeste ring 184 * 185 * @ring: ring the fence is associated with 186 * @s: resulting sequence number 187 * 188 * Emits a fence command on the requested ring (all asics). 189 * Used For polling fence. 190 * Returns 0 on success, -ENOMEM on failure. 191 */ 192 int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s) 193 { 194 uint32_t seq; 195 196 if (!s) 197 return -EINVAL; 198 199 seq = ++ring->fence_drv.sync_seq; 200 amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr, 201 seq, 0); 202 203 *s = seq; 204 205 return 0; 206 } 207 208 /** 209 * amdgpu_fence_schedule_fallback - schedule fallback check 210 * 211 * @ring: pointer to struct amdgpu_ring 212 * 213 * Start a timer as fallback to our interrupts. 214 */ 215 static void amdgpu_fence_schedule_fallback(struct amdgpu_ring *ring) 216 { 217 mod_timer(&ring->fence_drv.fallback_timer, 218 jiffies + AMDGPU_FENCE_JIFFIES_TIMEOUT); 219 } 220 221 /** 222 * amdgpu_fence_process - check for fence activity 223 * 224 * @ring: pointer to struct amdgpu_ring 225 * 226 * Checks the current fence value and calculates the last 227 * signalled fence value. Wakes the fence queue if the 228 * sequence number has increased. 229 * 230 * Returns true if fence was processed 231 */ 232 bool amdgpu_fence_process(struct amdgpu_ring *ring) 233 { 234 struct amdgpu_fence_driver *drv = &ring->fence_drv; 235 uint32_t seq, last_seq; 236 int r; 237 238 do { 239 last_seq = atomic_read(&ring->fence_drv.last_seq); 240 seq = amdgpu_fence_read(ring); 241 242 } while (atomic_cmpxchg(&drv->last_seq, last_seq, seq) != last_seq); 243 244 if (del_timer(&ring->fence_drv.fallback_timer) && 245 seq != ring->fence_drv.sync_seq) 246 amdgpu_fence_schedule_fallback(ring); 247 248 if (unlikely(seq == last_seq)) 249 return false; 250 251 last_seq &= drv->num_fences_mask; 252 seq &= drv->num_fences_mask; 253 254 do { 255 struct dma_fence *fence, **ptr; 256 257 ++last_seq; 258 last_seq &= drv->num_fences_mask; 259 ptr = &drv->fences[last_seq]; 260 261 /* There is always exactly one thread signaling this fence slot */ 262 fence = rcu_dereference_protected(*ptr, 1); 263 RCU_INIT_POINTER(*ptr, NULL); 264 265 if (!fence) 266 continue; 267 268 r = dma_fence_signal(fence); 269 if (!r) 270 DMA_FENCE_TRACE(fence, "signaled from irq context\n"); 271 else 272 BUG(); 273 274 dma_fence_put(fence); 275 } while (last_seq != seq); 276 277 return true; 278 } 279 280 /** 281 * amdgpu_fence_fallback - fallback for hardware interrupts 282 * 283 * @work: delayed work item 284 * 285 * Checks for fence activity. 286 */ 287 static void amdgpu_fence_fallback(struct timer_list *t) 288 { 289 struct amdgpu_ring *ring = from_timer(ring, t, 290 fence_drv.fallback_timer); 291 292 if (amdgpu_fence_process(ring)) 293 DRM_WARN("Fence fallback timer expired on ring %s\n", ring->name); 294 } 295 296 /** 297 * amdgpu_fence_wait_empty - wait for all fences to signal 298 * 299 * @adev: amdgpu device pointer 300 * @ring: ring index the fence is associated with 301 * 302 * Wait for all fences on the requested ring to signal (all asics). 303 * Returns 0 if the fences have passed, error for all other cases. 304 */ 305 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring) 306 { 307 uint64_t seq = READ_ONCE(ring->fence_drv.sync_seq); 308 struct dma_fence *fence, **ptr; 309 int r; 310 311 if (!seq) 312 return 0; 313 314 ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask]; 315 rcu_read_lock(); 316 fence = rcu_dereference(*ptr); 317 if (!fence || !dma_fence_get_rcu(fence)) { 318 rcu_read_unlock(); 319 return 0; 320 } 321 rcu_read_unlock(); 322 323 r = dma_fence_wait(fence, false); 324 dma_fence_put(fence); 325 return r; 326 } 327 328 /** 329 * amdgpu_fence_wait_polling - busy wait for givn sequence number 330 * 331 * @ring: ring index the fence is associated with 332 * @wait_seq: sequence number to wait 333 * @timeout: the timeout for waiting in usecs 334 * 335 * Wait for all fences on the requested ring to signal (all asics). 336 * Returns left time if no timeout, 0 or minus if timeout. 337 */ 338 signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring, 339 uint32_t wait_seq, 340 signed long timeout) 341 { 342 uint32_t seq; 343 344 do { 345 seq = amdgpu_fence_read(ring); 346 udelay(5); 347 timeout -= 5; 348 } while ((int32_t)(wait_seq - seq) > 0 && timeout > 0); 349 350 return timeout > 0 ? timeout : 0; 351 } 352 /** 353 * amdgpu_fence_count_emitted - get the count of emitted fences 354 * 355 * @ring: ring the fence is associated with 356 * 357 * Get the number of fences emitted on the requested ring (all asics). 358 * Returns the number of emitted fences on the ring. Used by the 359 * dynpm code to ring track activity. 360 */ 361 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring) 362 { 363 uint64_t emitted; 364 365 /* We are not protected by ring lock when reading the last sequence 366 * but it's ok to report slightly wrong fence count here. 367 */ 368 amdgpu_fence_process(ring); 369 emitted = 0x100000000ull; 370 emitted -= atomic_read(&ring->fence_drv.last_seq); 371 emitted += READ_ONCE(ring->fence_drv.sync_seq); 372 return lower_32_bits(emitted); 373 } 374 375 /** 376 * amdgpu_fence_driver_start_ring - make the fence driver 377 * ready for use on the requested ring. 378 * 379 * @ring: ring to start the fence driver on 380 * @irq_src: interrupt source to use for this ring 381 * @irq_type: interrupt type to use for this ring 382 * 383 * Make the fence driver ready for processing (all asics). 384 * Not all asics have all rings, so each asic will only 385 * start the fence driver on the rings it has. 386 * Returns 0 for success, errors for failure. 387 */ 388 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, 389 struct amdgpu_irq_src *irq_src, 390 unsigned irq_type) 391 { 392 struct amdgpu_device *adev = ring->adev; 393 uint64_t index; 394 395 if (ring->funcs->type != AMDGPU_RING_TYPE_UVD) { 396 ring->fence_drv.cpu_addr = &adev->wb.wb[ring->fence_offs]; 397 ring->fence_drv.gpu_addr = adev->wb.gpu_addr + (ring->fence_offs * 4); 398 } else { 399 /* put fence directly behind firmware */ 400 index = ALIGN(adev->uvd.fw->size, 8); 401 ring->fence_drv.cpu_addr = adev->uvd.inst[ring->me].cpu_addr + index; 402 ring->fence_drv.gpu_addr = adev->uvd.inst[ring->me].gpu_addr + index; 403 } 404 amdgpu_fence_write(ring, atomic_read(&ring->fence_drv.last_seq)); 405 amdgpu_irq_get(adev, irq_src, irq_type); 406 407 ring->fence_drv.irq_src = irq_src; 408 ring->fence_drv.irq_type = irq_type; 409 ring->fence_drv.initialized = true; 410 411 DRM_DEV_DEBUG(adev->dev, "fence driver on ring %s use gpu addr " 412 "0x%016llx, cpu addr 0x%p\n", ring->name, 413 ring->fence_drv.gpu_addr, ring->fence_drv.cpu_addr); 414 return 0; 415 } 416 417 /** 418 * amdgpu_fence_driver_init_ring - init the fence driver 419 * for the requested ring. 420 * 421 * @ring: ring to init the fence driver on 422 * @num_hw_submission: number of entries on the hardware queue 423 * 424 * Init the fence driver for the requested ring (all asics). 425 * Helper function for amdgpu_fence_driver_init(). 426 */ 427 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring, 428 unsigned num_hw_submission) 429 { 430 long timeout; 431 int r; 432 433 /* Check that num_hw_submission is a power of two */ 434 if ((num_hw_submission & (num_hw_submission - 1)) != 0) 435 return -EINVAL; 436 437 ring->fence_drv.cpu_addr = NULL; 438 ring->fence_drv.gpu_addr = 0; 439 ring->fence_drv.sync_seq = 0; 440 atomic_set(&ring->fence_drv.last_seq, 0); 441 ring->fence_drv.initialized = false; 442 443 timer_setup(&ring->fence_drv.fallback_timer, amdgpu_fence_fallback, 0); 444 445 ring->fence_drv.num_fences_mask = num_hw_submission * 2 - 1; 446 spin_lock_init(&ring->fence_drv.lock); 447 ring->fence_drv.fences = kcalloc(num_hw_submission * 2, sizeof(void *), 448 GFP_KERNEL); 449 if (!ring->fence_drv.fences) 450 return -ENOMEM; 451 452 /* No need to setup the GPU scheduler for KIQ ring */ 453 if (ring->funcs->type != AMDGPU_RING_TYPE_KIQ) { 454 /* for non-sriov case, no timeout enforce on compute ring */ 455 if ((ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) 456 && !amdgpu_sriov_vf(ring->adev)) 457 timeout = MAX_SCHEDULE_TIMEOUT; 458 else 459 timeout = msecs_to_jiffies(amdgpu_lockup_timeout); 460 461 r = drm_sched_init(&ring->sched, &amdgpu_sched_ops, 462 num_hw_submission, amdgpu_job_hang_limit, 463 timeout, ring->name); 464 if (r) { 465 DRM_ERROR("Failed to create scheduler on ring %s.\n", 466 ring->name); 467 return r; 468 } 469 } 470 471 return 0; 472 } 473 474 /** 475 * amdgpu_fence_driver_init - init the fence driver 476 * for all possible rings. 477 * 478 * @adev: amdgpu device pointer 479 * 480 * Init the fence driver for all possible rings (all asics). 481 * Not all asics have all rings, so each asic will only 482 * start the fence driver on the rings it has using 483 * amdgpu_fence_driver_start_ring(). 484 * Returns 0 for success. 485 */ 486 int amdgpu_fence_driver_init(struct amdgpu_device *adev) 487 { 488 if (amdgpu_debugfs_fence_init(adev)) 489 dev_err(adev->dev, "fence debugfs file creation failed\n"); 490 491 return 0; 492 } 493 494 /** 495 * amdgpu_fence_driver_fini - tear down the fence driver 496 * for all possible rings. 497 * 498 * @adev: amdgpu device pointer 499 * 500 * Tear down the fence driver for all possible rings (all asics). 501 */ 502 void amdgpu_fence_driver_fini(struct amdgpu_device *adev) 503 { 504 unsigned i, j; 505 int r; 506 507 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 508 struct amdgpu_ring *ring = adev->rings[i]; 509 510 if (!ring || !ring->fence_drv.initialized) 511 continue; 512 r = amdgpu_fence_wait_empty(ring); 513 if (r) { 514 /* no need to trigger GPU reset as we are unloading */ 515 amdgpu_fence_driver_force_completion(ring); 516 } 517 amdgpu_irq_put(adev, ring->fence_drv.irq_src, 518 ring->fence_drv.irq_type); 519 drm_sched_fini(&ring->sched); 520 del_timer_sync(&ring->fence_drv.fallback_timer); 521 for (j = 0; j <= ring->fence_drv.num_fences_mask; ++j) 522 dma_fence_put(ring->fence_drv.fences[j]); 523 kfree(ring->fence_drv.fences); 524 ring->fence_drv.fences = NULL; 525 ring->fence_drv.initialized = false; 526 } 527 } 528 529 /** 530 * amdgpu_fence_driver_suspend - suspend the fence driver 531 * for all possible rings. 532 * 533 * @adev: amdgpu device pointer 534 * 535 * Suspend the fence driver for all possible rings (all asics). 536 */ 537 void amdgpu_fence_driver_suspend(struct amdgpu_device *adev) 538 { 539 int i, r; 540 541 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 542 struct amdgpu_ring *ring = adev->rings[i]; 543 if (!ring || !ring->fence_drv.initialized) 544 continue; 545 546 /* wait for gpu to finish processing current batch */ 547 r = amdgpu_fence_wait_empty(ring); 548 if (r) { 549 /* delay GPU reset to resume */ 550 amdgpu_fence_driver_force_completion(ring); 551 } 552 553 /* disable the interrupt */ 554 amdgpu_irq_put(adev, ring->fence_drv.irq_src, 555 ring->fence_drv.irq_type); 556 } 557 } 558 559 /** 560 * amdgpu_fence_driver_resume - resume the fence driver 561 * for all possible rings. 562 * 563 * @adev: amdgpu device pointer 564 * 565 * Resume the fence driver for all possible rings (all asics). 566 * Not all asics have all rings, so each asic will only 567 * start the fence driver on the rings it has using 568 * amdgpu_fence_driver_start_ring(). 569 * Returns 0 for success. 570 */ 571 void amdgpu_fence_driver_resume(struct amdgpu_device *adev) 572 { 573 int i; 574 575 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 576 struct amdgpu_ring *ring = adev->rings[i]; 577 if (!ring || !ring->fence_drv.initialized) 578 continue; 579 580 /* enable the interrupt */ 581 amdgpu_irq_get(adev, ring->fence_drv.irq_src, 582 ring->fence_drv.irq_type); 583 } 584 } 585 586 /** 587 * amdgpu_fence_driver_force_completion - force signal latest fence of ring 588 * 589 * @ring: fence of the ring to signal 590 * 591 */ 592 void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring) 593 { 594 amdgpu_fence_write(ring, ring->fence_drv.sync_seq); 595 amdgpu_fence_process(ring); 596 } 597 598 /* 599 * Common fence implementation 600 */ 601 602 static const char *amdgpu_fence_get_driver_name(struct dma_fence *fence) 603 { 604 return "amdgpu"; 605 } 606 607 static const char *amdgpu_fence_get_timeline_name(struct dma_fence *f) 608 { 609 struct amdgpu_fence *fence = to_amdgpu_fence(f); 610 return (const char *)fence->ring->name; 611 } 612 613 /** 614 * amdgpu_fence_enable_signaling - enable signalling on fence 615 * @fence: fence 616 * 617 * This function is called with fence_queue lock held, and adds a callback 618 * to fence_queue that checks if this fence is signaled, and if so it 619 * signals the fence and removes itself. 620 */ 621 static bool amdgpu_fence_enable_signaling(struct dma_fence *f) 622 { 623 struct amdgpu_fence *fence = to_amdgpu_fence(f); 624 struct amdgpu_ring *ring = fence->ring; 625 626 if (!timer_pending(&ring->fence_drv.fallback_timer)) 627 amdgpu_fence_schedule_fallback(ring); 628 629 DMA_FENCE_TRACE(&fence->base, "armed on ring %i!\n", ring->idx); 630 631 return true; 632 } 633 634 /** 635 * amdgpu_fence_free - free up the fence memory 636 * 637 * @rcu: RCU callback head 638 * 639 * Free up the fence memory after the RCU grace period. 640 */ 641 static void amdgpu_fence_free(struct rcu_head *rcu) 642 { 643 struct dma_fence *f = container_of(rcu, struct dma_fence, rcu); 644 struct amdgpu_fence *fence = to_amdgpu_fence(f); 645 kmem_cache_free(amdgpu_fence_slab, fence); 646 } 647 648 /** 649 * amdgpu_fence_release - callback that fence can be freed 650 * 651 * @fence: fence 652 * 653 * This function is called when the reference count becomes zero. 654 * It just RCU schedules freeing up the fence. 655 */ 656 static void amdgpu_fence_release(struct dma_fence *f) 657 { 658 call_rcu(&f->rcu, amdgpu_fence_free); 659 } 660 661 static const struct dma_fence_ops amdgpu_fence_ops = { 662 .get_driver_name = amdgpu_fence_get_driver_name, 663 .get_timeline_name = amdgpu_fence_get_timeline_name, 664 .enable_signaling = amdgpu_fence_enable_signaling, 665 .release = amdgpu_fence_release, 666 }; 667 668 /* 669 * Fence debugfs 670 */ 671 #if defined(CONFIG_DEBUG_FS) 672 static int amdgpu_debugfs_fence_info(struct seq_file *m, void *data) 673 { 674 struct drm_info_node *node = (struct drm_info_node *)m->private; 675 struct drm_device *dev = node->minor->dev; 676 struct amdgpu_device *adev = dev->dev_private; 677 int i; 678 679 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { 680 struct amdgpu_ring *ring = adev->rings[i]; 681 if (!ring || !ring->fence_drv.initialized) 682 continue; 683 684 amdgpu_fence_process(ring); 685 686 seq_printf(m, "--- ring %d (%s) ---\n", i, ring->name); 687 seq_printf(m, "Last signaled fence 0x%08x\n", 688 atomic_read(&ring->fence_drv.last_seq)); 689 seq_printf(m, "Last emitted 0x%08x\n", 690 ring->fence_drv.sync_seq); 691 692 if (ring->funcs->type != AMDGPU_RING_TYPE_GFX) 693 continue; 694 695 /* set in CP_VMID_PREEMPT and preemption occurred */ 696 seq_printf(m, "Last preempted 0x%08x\n", 697 le32_to_cpu(*(ring->fence_drv.cpu_addr + 2))); 698 /* set in CP_VMID_RESET and reset occurred */ 699 seq_printf(m, "Last reset 0x%08x\n", 700 le32_to_cpu(*(ring->fence_drv.cpu_addr + 4))); 701 /* Both preemption and reset occurred */ 702 seq_printf(m, "Last both 0x%08x\n", 703 le32_to_cpu(*(ring->fence_drv.cpu_addr + 6))); 704 } 705 return 0; 706 } 707 708 /** 709 * amdgpu_debugfs_gpu_recover - manually trigger a gpu reset & recover 710 * 711 * Manually trigger a gpu reset at the next fence wait. 712 */ 713 static int amdgpu_debugfs_gpu_recover(struct seq_file *m, void *data) 714 { 715 struct drm_info_node *node = (struct drm_info_node *) m->private; 716 struct drm_device *dev = node->minor->dev; 717 struct amdgpu_device *adev = dev->dev_private; 718 719 seq_printf(m, "gpu recover\n"); 720 amdgpu_device_gpu_recover(adev, NULL); 721 722 return 0; 723 } 724 725 static const struct drm_info_list amdgpu_debugfs_fence_list[] = { 726 {"amdgpu_fence_info", &amdgpu_debugfs_fence_info, 0, NULL}, 727 {"amdgpu_gpu_recover", &amdgpu_debugfs_gpu_recover, 0, NULL} 728 }; 729 730 static const struct drm_info_list amdgpu_debugfs_fence_list_sriov[] = { 731 {"amdgpu_fence_info", &amdgpu_debugfs_fence_info, 0, NULL}, 732 }; 733 #endif 734 735 int amdgpu_debugfs_fence_init(struct amdgpu_device *adev) 736 { 737 #if defined(CONFIG_DEBUG_FS) 738 if (amdgpu_sriov_vf(adev)) 739 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_fence_list_sriov, 1); 740 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_fence_list, 2); 741 #else 742 return 0; 743 #endif 744 } 745 746