1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drm_drv.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_xgmi.h" 33 #include "soc15_common.h" 34 #include "psp_v3_1.h" 35 #include "psp_v10_0.h" 36 #include "psp_v11_0.h" 37 #include "psp_v11_0_8.h" 38 #include "psp_v12_0.h" 39 #include "psp_v13_0.h" 40 #include "psp_v13_0_4.h" 41 42 #include "amdgpu_ras.h" 43 #include "amdgpu_securedisplay.h" 44 #include "amdgpu_atomfirmware.h" 45 46 #define AMD_VBIOS_FILE_MAX_SIZE_B (1024*1024*3) 47 48 static int psp_sysfs_init(struct amdgpu_device *adev); 49 static void psp_sysfs_fini(struct amdgpu_device *adev); 50 51 static int psp_load_smu_fw(struct psp_context *psp); 52 static int psp_rap_terminate(struct psp_context *psp); 53 static int psp_securedisplay_terminate(struct psp_context *psp); 54 55 static int psp_ring_init(struct psp_context *psp, 56 enum psp_ring_type ring_type) 57 { 58 int ret = 0; 59 struct psp_ring *ring; 60 struct amdgpu_device *adev = psp->adev; 61 62 ring = &psp->km_ring; 63 64 ring->ring_type = ring_type; 65 66 /* allocate 4k Page of Local Frame Buffer memory for ring */ 67 ring->ring_size = 0x1000; 68 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 69 AMDGPU_GEM_DOMAIN_VRAM | 70 AMDGPU_GEM_DOMAIN_GTT, 71 &adev->firmware.rbuf, 72 &ring->ring_mem_mc_addr, 73 (void **)&ring->ring_mem); 74 if (ret) { 75 ring->ring_size = 0; 76 return ret; 77 } 78 79 return 0; 80 } 81 82 /* 83 * Due to DF Cstate management centralized to PMFW, the firmware 84 * loading sequence will be updated as below: 85 * - Load KDB 86 * - Load SYS_DRV 87 * - Load tOS 88 * - Load PMFW 89 * - Setup TMR 90 * - Load other non-psp fw 91 * - Load ASD 92 * - Load XGMI/RAS/HDCP/DTM TA if any 93 * 94 * This new sequence is required for 95 * - Arcturus and onwards 96 */ 97 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 98 { 99 struct amdgpu_device *adev = psp->adev; 100 101 if (amdgpu_sriov_vf(adev)) { 102 psp->pmfw_centralized_cstate_management = false; 103 return; 104 } 105 106 switch (adev->ip_versions[MP0_HWIP][0]) { 107 case IP_VERSION(11, 0, 0): 108 case IP_VERSION(11, 0, 4): 109 case IP_VERSION(11, 0, 5): 110 case IP_VERSION(11, 0, 7): 111 case IP_VERSION(11, 0, 9): 112 case IP_VERSION(11, 0, 11): 113 case IP_VERSION(11, 0, 12): 114 case IP_VERSION(11, 0, 13): 115 case IP_VERSION(13, 0, 0): 116 case IP_VERSION(13, 0, 2): 117 case IP_VERSION(13, 0, 7): 118 psp->pmfw_centralized_cstate_management = true; 119 break; 120 default: 121 psp->pmfw_centralized_cstate_management = false; 122 break; 123 } 124 } 125 126 static int psp_init_sriov_microcode(struct psp_context *psp) 127 { 128 struct amdgpu_device *adev = psp->adev; 129 char ucode_prefix[30]; 130 int ret = 0; 131 132 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 133 134 switch (adev->ip_versions[MP0_HWIP][0]) { 135 case IP_VERSION(9, 0, 0): 136 case IP_VERSION(11, 0, 7): 137 case IP_VERSION(11, 0, 9): 138 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 139 ret = psp_init_cap_microcode(psp, ucode_prefix); 140 break; 141 case IP_VERSION(13, 0, 2): 142 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 143 ret = psp_init_cap_microcode(psp, ucode_prefix); 144 ret &= psp_init_ta_microcode(psp, ucode_prefix); 145 break; 146 case IP_VERSION(13, 0, 0): 147 adev->virt.autoload_ucode_id = 0; 148 break; 149 case IP_VERSION(13, 0, 10): 150 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA; 151 ret = psp_init_cap_microcode(psp, ucode_prefix); 152 break; 153 default: 154 return -EINVAL; 155 } 156 return ret; 157 } 158 159 static int psp_early_init(void *handle) 160 { 161 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 162 struct psp_context *psp = &adev->psp; 163 164 switch (adev->ip_versions[MP0_HWIP][0]) { 165 case IP_VERSION(9, 0, 0): 166 psp_v3_1_set_psp_funcs(psp); 167 psp->autoload_supported = false; 168 break; 169 case IP_VERSION(10, 0, 0): 170 case IP_VERSION(10, 0, 1): 171 psp_v10_0_set_psp_funcs(psp); 172 psp->autoload_supported = false; 173 break; 174 case IP_VERSION(11, 0, 2): 175 case IP_VERSION(11, 0, 4): 176 psp_v11_0_set_psp_funcs(psp); 177 psp->autoload_supported = false; 178 break; 179 case IP_VERSION(11, 0, 0): 180 case IP_VERSION(11, 0, 5): 181 case IP_VERSION(11, 0, 9): 182 case IP_VERSION(11, 0, 7): 183 case IP_VERSION(11, 0, 11): 184 case IP_VERSION(11, 5, 0): 185 case IP_VERSION(11, 0, 12): 186 case IP_VERSION(11, 0, 13): 187 psp_v11_0_set_psp_funcs(psp); 188 psp->autoload_supported = true; 189 break; 190 case IP_VERSION(11, 0, 3): 191 case IP_VERSION(12, 0, 1): 192 psp_v12_0_set_psp_funcs(psp); 193 break; 194 case IP_VERSION(13, 0, 2): 195 case IP_VERSION(13, 0, 6): 196 psp_v13_0_set_psp_funcs(psp); 197 break; 198 case IP_VERSION(13, 0, 1): 199 case IP_VERSION(13, 0, 3): 200 case IP_VERSION(13, 0, 5): 201 case IP_VERSION(13, 0, 8): 202 case IP_VERSION(13, 0, 10): 203 case IP_VERSION(13, 0, 11): 204 psp_v13_0_set_psp_funcs(psp); 205 psp->autoload_supported = true; 206 break; 207 case IP_VERSION(11, 0, 8): 208 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 209 psp_v11_0_8_set_psp_funcs(psp); 210 psp->autoload_supported = false; 211 } 212 break; 213 case IP_VERSION(13, 0, 0): 214 case IP_VERSION(13, 0, 7): 215 psp_v13_0_set_psp_funcs(psp); 216 psp->autoload_supported = true; 217 break; 218 case IP_VERSION(13, 0, 4): 219 psp_v13_0_4_set_psp_funcs(psp); 220 psp->autoload_supported = true; 221 break; 222 default: 223 return -EINVAL; 224 } 225 226 psp->adev = adev; 227 228 psp_check_pmfw_centralized_cstate_management(psp); 229 230 if (amdgpu_sriov_vf(adev)) 231 return psp_init_sriov_microcode(psp); 232 else 233 return psp_init_microcode(psp); 234 } 235 236 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx) 237 { 238 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr, 239 &mem_ctx->shared_buf); 240 mem_ctx->shared_bo = NULL; 241 } 242 243 static void psp_free_shared_bufs(struct psp_context *psp) 244 { 245 void *tmr_buf; 246 void **pptr; 247 248 /* free TMR memory buffer */ 249 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 250 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 251 psp->tmr_bo = NULL; 252 253 /* free xgmi shared memory */ 254 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context); 255 256 /* free ras shared memory */ 257 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context); 258 259 /* free hdcp shared memory */ 260 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context); 261 262 /* free dtm shared memory */ 263 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context); 264 265 /* free rap shared memory */ 266 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 267 268 /* free securedisplay shared memory */ 269 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 270 271 272 } 273 274 static void psp_memory_training_fini(struct psp_context *psp) 275 { 276 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 277 278 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 279 kfree(ctx->sys_cache); 280 ctx->sys_cache = NULL; 281 } 282 283 static int psp_memory_training_init(struct psp_context *psp) 284 { 285 int ret; 286 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 287 288 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 289 DRM_DEBUG("memory training is not supported!\n"); 290 return 0; 291 } 292 293 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 294 if (ctx->sys_cache == NULL) { 295 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n"); 296 ret = -ENOMEM; 297 goto Err_out; 298 } 299 300 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 301 ctx->train_data_size, 302 ctx->p2c_train_data_offset, 303 ctx->c2p_train_data_offset); 304 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 305 return 0; 306 307 Err_out: 308 psp_memory_training_fini(psp); 309 return ret; 310 } 311 312 /* 313 * Helper funciton to query psp runtime database entry 314 * 315 * @adev: amdgpu_device pointer 316 * @entry_type: the type of psp runtime database entry 317 * @db_entry: runtime database entry pointer 318 * 319 * Return false if runtime database doesn't exit or entry is invalid 320 * or true if the specific database entry is found, and copy to @db_entry 321 */ 322 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, 323 enum psp_runtime_entry_type entry_type, 324 void *db_entry) 325 { 326 uint64_t db_header_pos, db_dir_pos; 327 struct psp_runtime_data_header db_header = {0}; 328 struct psp_runtime_data_directory db_dir = {0}; 329 bool ret = false; 330 int i; 331 332 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET; 333 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header); 334 335 /* read runtime db header from vram */ 336 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header, 337 sizeof(struct psp_runtime_data_header), false); 338 339 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) { 340 /* runtime db doesn't exist, exit */ 341 dev_dbg(adev->dev, "PSP runtime database doesn't exist\n"); 342 return false; 343 } 344 345 /* read runtime database entry from vram */ 346 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir, 347 sizeof(struct psp_runtime_data_directory), false); 348 349 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) { 350 /* invalid db entry count, exit */ 351 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n"); 352 return false; 353 } 354 355 /* look up for requested entry type */ 356 for (i = 0; i < db_dir.entry_count && !ret; i++) { 357 if (db_dir.entry_list[i].entry_type == entry_type) { 358 switch (entry_type) { 359 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG: 360 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) { 361 /* invalid db entry size */ 362 dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n"); 363 return false; 364 } 365 /* read runtime database entry */ 366 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 367 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false); 368 ret = true; 369 break; 370 case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS: 371 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) { 372 /* invalid db entry size */ 373 dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n"); 374 return false; 375 } 376 /* read runtime database entry */ 377 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 378 (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false); 379 ret = true; 380 break; 381 default: 382 ret = false; 383 break; 384 } 385 } 386 } 387 388 return ret; 389 } 390 391 static int psp_sw_init(void *handle) 392 { 393 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 394 struct psp_context *psp = &adev->psp; 395 int ret; 396 struct psp_runtime_boot_cfg_entry boot_cfg_entry; 397 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx; 398 struct psp_runtime_scpm_entry scpm_entry; 399 400 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 401 if (!psp->cmd) { 402 DRM_ERROR("Failed to allocate memory to command buffer!\n"); 403 ret = -ENOMEM; 404 } 405 406 adev->psp.xgmi_context.supports_extended_data = 407 !adev->gmc.xgmi.connected_to_cpu && 408 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2); 409 410 memset(&scpm_entry, 0, sizeof(scpm_entry)); 411 if ((psp_get_runtime_db_entry(adev, 412 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS, 413 &scpm_entry)) && 414 (SCPM_DISABLE != scpm_entry.scpm_status)) { 415 adev->scpm_enabled = true; 416 adev->scpm_status = scpm_entry.scpm_status; 417 } else { 418 adev->scpm_enabled = false; 419 adev->scpm_status = SCPM_DISABLE; 420 } 421 422 /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */ 423 424 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry)); 425 if (psp_get_runtime_db_entry(adev, 426 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG, 427 &boot_cfg_entry)) { 428 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask; 429 if ((psp->boot_cfg_bitmask) & 430 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) { 431 /* If psp runtime database exists, then 432 * only enable two stage memory training 433 * when TWO_STAGE_DRAM_TRAINING bit is set 434 * in runtime database */ 435 mem_training_ctx->enable_mem_training = true; 436 } 437 438 } else { 439 /* If psp runtime database doesn't exist or 440 * is invalid, force enable two stage memory 441 * training */ 442 mem_training_ctx->enable_mem_training = true; 443 } 444 445 if (mem_training_ctx->enable_mem_training) { 446 ret = psp_memory_training_init(psp); 447 if (ret) { 448 DRM_ERROR("Failed to initialize memory training!\n"); 449 return ret; 450 } 451 452 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 453 if (ret) { 454 DRM_ERROR("Failed to process memory training!\n"); 455 return ret; 456 } 457 } 458 459 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) || 460 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) { 461 ret= psp_sysfs_init(adev); 462 if (ret) { 463 return ret; 464 } 465 } 466 467 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 468 amdgpu_sriov_vf(adev) ? 469 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, 470 &psp->fw_pri_bo, 471 &psp->fw_pri_mc_addr, 472 &psp->fw_pri_buf); 473 if (ret) 474 return ret; 475 476 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 477 AMDGPU_GEM_DOMAIN_VRAM, 478 &psp->fence_buf_bo, 479 &psp->fence_buf_mc_addr, 480 &psp->fence_buf); 481 if (ret) 482 goto failed1; 483 484 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 485 AMDGPU_GEM_DOMAIN_VRAM, 486 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 487 (void **)&psp->cmd_buf_mem); 488 if (ret) 489 goto failed2; 490 491 return 0; 492 493 failed2: 494 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 495 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 496 failed1: 497 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 498 &psp->fence_buf_mc_addr, &psp->fence_buf); 499 return ret; 500 } 501 502 static int psp_sw_fini(void *handle) 503 { 504 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 505 struct psp_context *psp = &adev->psp; 506 struct psp_gfx_cmd_resp *cmd = psp->cmd; 507 508 psp_memory_training_fini(psp); 509 510 amdgpu_ucode_release(&psp->sos_fw); 511 amdgpu_ucode_release(&psp->asd_fw); 512 amdgpu_ucode_release(&psp->ta_fw); 513 amdgpu_ucode_release(&psp->cap_fw); 514 amdgpu_ucode_release(&psp->toc_fw); 515 516 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) || 517 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) 518 psp_sysfs_fini(adev); 519 520 kfree(cmd); 521 cmd = NULL; 522 523 if (psp->km_ring.ring_mem) 524 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 525 &psp->km_ring.ring_mem_mc_addr, 526 (void **)&psp->km_ring.ring_mem); 527 528 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 529 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 530 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 531 &psp->fence_buf_mc_addr, &psp->fence_buf); 532 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 533 (void **)&psp->cmd_buf_mem); 534 535 return 0; 536 } 537 538 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 539 uint32_t reg_val, uint32_t mask, bool check_changed) 540 { 541 uint32_t val; 542 int i; 543 struct amdgpu_device *adev = psp->adev; 544 545 if (psp->adev->no_hw_access) 546 return 0; 547 548 for (i = 0; i < adev->usec_timeout; i++) { 549 val = RREG32(reg_index); 550 if (check_changed) { 551 if (val != reg_val) 552 return 0; 553 } else { 554 if ((val & mask) == reg_val) 555 return 0; 556 } 557 udelay(1); 558 } 559 560 return -ETIME; 561 } 562 563 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) 564 { 565 switch (cmd_id) { 566 case GFX_CMD_ID_LOAD_TA: 567 return "LOAD_TA"; 568 case GFX_CMD_ID_UNLOAD_TA: 569 return "UNLOAD_TA"; 570 case GFX_CMD_ID_INVOKE_CMD: 571 return "INVOKE_CMD"; 572 case GFX_CMD_ID_LOAD_ASD: 573 return "LOAD_ASD"; 574 case GFX_CMD_ID_SETUP_TMR: 575 return "SETUP_TMR"; 576 case GFX_CMD_ID_LOAD_IP_FW: 577 return "LOAD_IP_FW"; 578 case GFX_CMD_ID_DESTROY_TMR: 579 return "DESTROY_TMR"; 580 case GFX_CMD_ID_SAVE_RESTORE: 581 return "SAVE_RESTORE_IP_FW"; 582 case GFX_CMD_ID_SETUP_VMR: 583 return "SETUP_VMR"; 584 case GFX_CMD_ID_DESTROY_VMR: 585 return "DESTROY_VMR"; 586 case GFX_CMD_ID_PROG_REG: 587 return "PROG_REG"; 588 case GFX_CMD_ID_GET_FW_ATTESTATION: 589 return "GET_FW_ATTESTATION"; 590 case GFX_CMD_ID_LOAD_TOC: 591 return "ID_LOAD_TOC"; 592 case GFX_CMD_ID_AUTOLOAD_RLC: 593 return "AUTOLOAD_RLC"; 594 case GFX_CMD_ID_BOOT_CFG: 595 return "BOOT_CFG"; 596 default: 597 return "UNKNOWN CMD"; 598 } 599 } 600 601 static int 602 psp_cmd_submit_buf(struct psp_context *psp, 603 struct amdgpu_firmware_info *ucode, 604 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 605 { 606 int ret; 607 int index; 608 int timeout = 20000; 609 bool ras_intr = false; 610 bool skip_unsupport = false; 611 612 if (psp->adev->no_hw_access) 613 return 0; 614 615 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 616 617 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 618 619 index = atomic_inc_return(&psp->fence_value); 620 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 621 if (ret) { 622 atomic_dec(&psp->fence_value); 623 goto exit; 624 } 625 626 amdgpu_device_invalidate_hdp(psp->adev, NULL); 627 while (*((unsigned int *)psp->fence_buf) != index) { 628 if (--timeout == 0) 629 break; 630 /* 631 * Shouldn't wait for timeout when err_event_athub occurs, 632 * because gpu reset thread triggered and lock resource should 633 * be released for psp resume sequence. 634 */ 635 ras_intr = amdgpu_ras_intr_triggered(); 636 if (ras_intr) 637 break; 638 usleep_range(10, 100); 639 amdgpu_device_invalidate_hdp(psp->adev, NULL); 640 } 641 642 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 643 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 644 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 645 646 memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 647 648 /* In some cases, psp response status is not 0 even there is no 649 * problem while the command is submitted. Some version of PSP FW 650 * doesn't write 0 to that field. 651 * So here we would like to only print a warning instead of an error 652 * during psp initialization to avoid breaking hw_init and it doesn't 653 * return -EINVAL. 654 */ 655 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 656 if (ucode) 657 DRM_WARN("failed to load ucode %s(0x%X) ", 658 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id); 659 DRM_WARN("psp gfx command %s(0x%X) failed and response status is (0x%X)\n", 660 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id, 661 psp->cmd_buf_mem->resp.status); 662 /* If any firmware (including CAP) load fails under SRIOV, it should 663 * return failure to stop the VF from initializing. 664 * Also return failure in case of timeout 665 */ 666 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) { 667 ret = -EINVAL; 668 goto exit; 669 } 670 } 671 672 if (ucode) { 673 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 674 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 675 } 676 677 exit: 678 return ret; 679 } 680 681 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp) 682 { 683 struct psp_gfx_cmd_resp *cmd = psp->cmd; 684 685 mutex_lock(&psp->mutex); 686 687 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 688 689 return cmd; 690 } 691 692 static void release_psp_cmd_buf(struct psp_context *psp) 693 { 694 mutex_unlock(&psp->mutex); 695 } 696 697 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 698 struct psp_gfx_cmd_resp *cmd, 699 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 700 { 701 struct amdgpu_device *adev = psp->adev; 702 uint32_t size = amdgpu_bo_size(tmr_bo); 703 uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 704 705 if (amdgpu_sriov_vf(psp->adev)) 706 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 707 else 708 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 709 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 710 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 711 cmd->cmd.cmd_setup_tmr.buf_size = size; 712 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 713 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 714 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 715 } 716 717 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 718 uint64_t pri_buf_mc, uint32_t size) 719 { 720 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 721 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 722 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 723 cmd->cmd.cmd_load_toc.toc_size = size; 724 } 725 726 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 727 static int psp_load_toc(struct psp_context *psp, 728 uint32_t *tmr_size) 729 { 730 int ret; 731 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 732 733 /* Copy toc to psp firmware private buffer */ 734 psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes); 735 736 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes); 737 738 ret = psp_cmd_submit_buf(psp, NULL, cmd, 739 psp->fence_buf_mc_addr); 740 if (!ret) 741 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 742 743 release_psp_cmd_buf(psp); 744 745 return ret; 746 } 747 748 /* Set up Trusted Memory Region */ 749 static int psp_tmr_init(struct psp_context *psp) 750 { 751 int ret = 0; 752 int tmr_size; 753 void *tmr_buf; 754 void **pptr; 755 756 /* 757 * According to HW engineer, they prefer the TMR address be "naturally 758 * aligned" , e.g. the start address be an integer divide of TMR size. 759 * 760 * Note: this memory need be reserved till the driver 761 * uninitializes. 762 */ 763 tmr_size = PSP_TMR_SIZE(psp->adev); 764 765 /* For ASICs support RLC autoload, psp will parse the toc 766 * and calculate the total size of TMR needed */ 767 if (!amdgpu_sriov_vf(psp->adev) && 768 psp->toc.start_addr && 769 psp->toc.size_bytes && 770 psp->fw_pri_buf) { 771 ret = psp_load_toc(psp, &tmr_size); 772 if (ret) { 773 DRM_ERROR("Failed to load toc\n"); 774 return ret; 775 } 776 } 777 778 if (!psp->tmr_bo) { 779 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 780 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, 781 PSP_TMR_ALIGNMENT, 782 AMDGPU_HAS_VRAM(psp->adev) ? 783 AMDGPU_GEM_DOMAIN_VRAM : 784 AMDGPU_GEM_DOMAIN_GTT, 785 &psp->tmr_bo, &psp->tmr_mc_addr, 786 pptr); 787 } 788 789 return ret; 790 } 791 792 static bool psp_skip_tmr(struct psp_context *psp) 793 { 794 switch (psp->adev->ip_versions[MP0_HWIP][0]) { 795 case IP_VERSION(11, 0, 9): 796 case IP_VERSION(11, 0, 7): 797 case IP_VERSION(13, 0, 2): 798 case IP_VERSION(13, 0, 10): 799 return true; 800 default: 801 return false; 802 } 803 } 804 805 static int psp_tmr_load(struct psp_context *psp) 806 { 807 int ret; 808 struct psp_gfx_cmd_resp *cmd; 809 810 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR. 811 * Already set up by host driver. 812 */ 813 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 814 return 0; 815 816 cmd = acquire_psp_cmd_buf(psp); 817 818 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 819 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n", 820 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 821 822 ret = psp_cmd_submit_buf(psp, NULL, cmd, 823 psp->fence_buf_mc_addr); 824 825 release_psp_cmd_buf(psp); 826 827 return ret; 828 } 829 830 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 831 struct psp_gfx_cmd_resp *cmd) 832 { 833 if (amdgpu_sriov_vf(psp->adev)) 834 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 835 else 836 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 837 } 838 839 static int psp_tmr_unload(struct psp_context *psp) 840 { 841 int ret; 842 struct psp_gfx_cmd_resp *cmd; 843 844 /* skip TMR unload for Navi12 and CHIP_SIENNA_CICHLID SRIOV, 845 * as TMR is not loaded at all 846 */ 847 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 848 return 0; 849 850 cmd = acquire_psp_cmd_buf(psp); 851 852 psp_prep_tmr_unload_cmd_buf(psp, cmd); 853 dev_dbg(psp->adev->dev, "free PSP TMR buffer\n"); 854 855 ret = psp_cmd_submit_buf(psp, NULL, cmd, 856 psp->fence_buf_mc_addr); 857 858 release_psp_cmd_buf(psp); 859 860 return ret; 861 } 862 863 static int psp_tmr_terminate(struct psp_context *psp) 864 { 865 return psp_tmr_unload(psp); 866 } 867 868 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 869 uint64_t *output_ptr) 870 { 871 int ret; 872 struct psp_gfx_cmd_resp *cmd; 873 874 if (!output_ptr) 875 return -EINVAL; 876 877 if (amdgpu_sriov_vf(psp->adev)) 878 return 0; 879 880 cmd = acquire_psp_cmd_buf(psp); 881 882 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 883 884 ret = psp_cmd_submit_buf(psp, NULL, cmd, 885 psp->fence_buf_mc_addr); 886 887 if (!ret) { 888 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 889 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 890 } 891 892 release_psp_cmd_buf(psp); 893 894 return ret; 895 } 896 897 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg) 898 { 899 struct psp_context *psp = &adev->psp; 900 struct psp_gfx_cmd_resp *cmd; 901 int ret; 902 903 if (amdgpu_sriov_vf(adev)) 904 return 0; 905 906 cmd = acquire_psp_cmd_buf(psp); 907 908 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 909 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET; 910 911 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 912 if (!ret) { 913 *boot_cfg = 914 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0; 915 } 916 917 release_psp_cmd_buf(psp); 918 919 return ret; 920 } 921 922 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg) 923 { 924 int ret; 925 struct psp_context *psp = &adev->psp; 926 struct psp_gfx_cmd_resp *cmd; 927 928 if (amdgpu_sriov_vf(adev)) 929 return 0; 930 931 cmd = acquire_psp_cmd_buf(psp); 932 933 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 934 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 935 cmd->cmd.boot_cfg.boot_config = boot_cfg; 936 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg; 937 938 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 939 940 release_psp_cmd_buf(psp); 941 942 return ret; 943 } 944 945 static int psp_rl_load(struct amdgpu_device *adev) 946 { 947 int ret; 948 struct psp_context *psp = &adev->psp; 949 struct psp_gfx_cmd_resp *cmd; 950 951 if (!is_psp_fw_valid(psp->rl)) 952 return 0; 953 954 cmd = acquire_psp_cmd_buf(psp); 955 956 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 957 memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes); 958 959 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 960 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 961 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 962 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes; 963 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 964 965 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 966 967 release_psp_cmd_buf(psp); 968 969 return ret; 970 } 971 972 static int psp_asd_initialize(struct psp_context *psp) 973 { 974 int ret; 975 976 /* If PSP version doesn't match ASD version, asd loading will be failed. 977 * add workaround to bypass it for sriov now. 978 * TODO: add version check to make it common 979 */ 980 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes) 981 return 0; 982 983 psp->asd_context.mem_context.shared_mc_addr = 0; 984 psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE; 985 psp->asd_context.ta_load_type = GFX_CMD_ID_LOAD_ASD; 986 987 ret = psp_ta_load(psp, &psp->asd_context); 988 if (!ret) 989 psp->asd_context.initialized = true; 990 991 return ret; 992 } 993 994 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 995 uint32_t session_id) 996 { 997 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 998 cmd->cmd.cmd_unload_ta.session_id = session_id; 999 } 1000 1001 int psp_ta_unload(struct psp_context *psp, struct ta_context *context) 1002 { 1003 int ret; 1004 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1005 1006 psp_prep_ta_unload_cmd_buf(cmd, context->session_id); 1007 1008 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1009 1010 context->resp_status = cmd->resp.status; 1011 1012 release_psp_cmd_buf(psp); 1013 1014 return ret; 1015 } 1016 1017 static int psp_asd_terminate(struct psp_context *psp) 1018 { 1019 int ret; 1020 1021 if (amdgpu_sriov_vf(psp->adev)) 1022 return 0; 1023 1024 if (!psp->asd_context.initialized) 1025 return 0; 1026 1027 ret = psp_ta_unload(psp, &psp->asd_context); 1028 if (!ret) 1029 psp->asd_context.initialized = false; 1030 1031 return ret; 1032 } 1033 1034 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1035 uint32_t id, uint32_t value) 1036 { 1037 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 1038 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 1039 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 1040 } 1041 1042 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 1043 uint32_t value) 1044 { 1045 struct psp_gfx_cmd_resp *cmd; 1046 int ret = 0; 1047 1048 if (reg >= PSP_REG_LAST) 1049 return -EINVAL; 1050 1051 cmd = acquire_psp_cmd_buf(psp); 1052 1053 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 1054 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1055 if (ret) 1056 DRM_ERROR("PSP failed to program reg id %d", reg); 1057 1058 release_psp_cmd_buf(psp); 1059 1060 return ret; 1061 } 1062 1063 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1064 uint64_t ta_bin_mc, 1065 struct ta_context *context) 1066 { 1067 cmd->cmd_id = context->ta_load_type; 1068 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 1069 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 1070 cmd->cmd.cmd_load_ta.app_len = context->bin_desc.size_bytes; 1071 1072 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 1073 lower_32_bits(context->mem_context.shared_mc_addr); 1074 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 1075 upper_32_bits(context->mem_context.shared_mc_addr); 1076 cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size; 1077 } 1078 1079 int psp_ta_init_shared_buf(struct psp_context *psp, 1080 struct ta_mem_context *mem_ctx) 1081 { 1082 /* 1083 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1084 * physical) for ta to host memory 1085 */ 1086 return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size, 1087 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM | 1088 AMDGPU_GEM_DOMAIN_GTT, 1089 &mem_ctx->shared_bo, 1090 &mem_ctx->shared_mc_addr, 1091 &mem_ctx->shared_buf); 1092 } 1093 1094 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1095 uint32_t ta_cmd_id, 1096 uint32_t session_id) 1097 { 1098 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 1099 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 1100 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 1101 } 1102 1103 int psp_ta_invoke(struct psp_context *psp, 1104 uint32_t ta_cmd_id, 1105 struct ta_context *context) 1106 { 1107 int ret; 1108 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1109 1110 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id); 1111 1112 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1113 psp->fence_buf_mc_addr); 1114 1115 context->resp_status = cmd->resp.status; 1116 1117 release_psp_cmd_buf(psp); 1118 1119 return ret; 1120 } 1121 1122 int psp_ta_load(struct psp_context *psp, struct ta_context *context) 1123 { 1124 int ret; 1125 struct psp_gfx_cmd_resp *cmd; 1126 1127 cmd = acquire_psp_cmd_buf(psp); 1128 1129 psp_copy_fw(psp, context->bin_desc.start_addr, 1130 context->bin_desc.size_bytes); 1131 1132 psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context); 1133 1134 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1135 psp->fence_buf_mc_addr); 1136 1137 context->resp_status = cmd->resp.status; 1138 1139 if (!ret) { 1140 context->session_id = cmd->resp.session_id; 1141 } 1142 1143 release_psp_cmd_buf(psp); 1144 1145 return ret; 1146 } 1147 1148 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1149 { 1150 return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context); 1151 } 1152 1153 int psp_xgmi_terminate(struct psp_context *psp) 1154 { 1155 int ret; 1156 struct amdgpu_device *adev = psp->adev; 1157 1158 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 1159 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || 1160 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && 1161 adev->gmc.xgmi.connected_to_cpu)) 1162 return 0; 1163 1164 if (!psp->xgmi_context.context.initialized) 1165 return 0; 1166 1167 ret = psp_ta_unload(psp, &psp->xgmi_context.context); 1168 1169 psp->xgmi_context.context.initialized = false; 1170 1171 return ret; 1172 } 1173 1174 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta) 1175 { 1176 struct ta_xgmi_shared_memory *xgmi_cmd; 1177 int ret; 1178 1179 if (!psp->ta_fw || 1180 !psp->xgmi_context.context.bin_desc.size_bytes || 1181 !psp->xgmi_context.context.bin_desc.start_addr) 1182 return -ENOENT; 1183 1184 if (!load_ta) 1185 goto invoke; 1186 1187 psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE; 1188 psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1189 1190 if (!psp->xgmi_context.context.mem_context.shared_buf) { 1191 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context); 1192 if (ret) 1193 return ret; 1194 } 1195 1196 /* Load XGMI TA */ 1197 ret = psp_ta_load(psp, &psp->xgmi_context.context); 1198 if (!ret) 1199 psp->xgmi_context.context.initialized = true; 1200 else 1201 return ret; 1202 1203 invoke: 1204 /* Initialize XGMI session */ 1205 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf); 1206 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1207 xgmi_cmd->flag_extend_link_record = set_extended_data; 1208 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 1209 1210 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1211 1212 return ret; 1213 } 1214 1215 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 1216 { 1217 struct ta_xgmi_shared_memory *xgmi_cmd; 1218 int ret; 1219 1220 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1221 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1222 1223 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 1224 1225 /* Invoke xgmi ta to get hive id */ 1226 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1227 if (ret) 1228 return ret; 1229 1230 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 1231 1232 return 0; 1233 } 1234 1235 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 1236 { 1237 struct ta_xgmi_shared_memory *xgmi_cmd; 1238 int ret; 1239 1240 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1241 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1242 1243 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 1244 1245 /* Invoke xgmi ta to get the node id */ 1246 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1247 if (ret) 1248 return ret; 1249 1250 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 1251 1252 return 0; 1253 } 1254 1255 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp) 1256 { 1257 return psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && 1258 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b; 1259 } 1260 1261 /* 1262 * Chips that support extended topology information require the driver to 1263 * reflect topology information in the opposite direction. This is 1264 * because the TA has already exceeded its link record limit and if the 1265 * TA holds bi-directional information, the driver would have to do 1266 * multiple fetches instead of just two. 1267 */ 1268 static void psp_xgmi_reflect_topology_info(struct psp_context *psp, 1269 struct psp_xgmi_node_info node_info) 1270 { 1271 struct amdgpu_device *mirror_adev; 1272 struct amdgpu_hive_info *hive; 1273 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id; 1274 uint64_t dst_node_id = node_info.node_id; 1275 uint8_t dst_num_hops = node_info.num_hops; 1276 uint8_t dst_num_links = node_info.num_links; 1277 1278 hive = amdgpu_get_xgmi_hive(psp->adev); 1279 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) { 1280 struct psp_xgmi_topology_info *mirror_top_info; 1281 int j; 1282 1283 if (mirror_adev->gmc.xgmi.node_id != dst_node_id) 1284 continue; 1285 1286 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info; 1287 for (j = 0; j < mirror_top_info->num_nodes; j++) { 1288 if (mirror_top_info->nodes[j].node_id != src_node_id) 1289 continue; 1290 1291 mirror_top_info->nodes[j].num_hops = dst_num_hops; 1292 /* 1293 * prevent 0 num_links value re-reflection since reflection 1294 * criteria is based on num_hops (direct or indirect). 1295 * 1296 */ 1297 if (dst_num_links) 1298 mirror_top_info->nodes[j].num_links = dst_num_links; 1299 1300 break; 1301 } 1302 1303 break; 1304 } 1305 1306 amdgpu_put_xgmi_hive(hive); 1307 } 1308 1309 int psp_xgmi_get_topology_info(struct psp_context *psp, 1310 int number_devices, 1311 struct psp_xgmi_topology_info *topology, 1312 bool get_extended_data) 1313 { 1314 struct ta_xgmi_shared_memory *xgmi_cmd; 1315 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1316 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 1317 int i; 1318 int ret; 1319 1320 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1321 return -EINVAL; 1322 1323 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1324 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1325 xgmi_cmd->flag_extend_link_record = get_extended_data; 1326 1327 /* Fill in the shared memory with topology information as input */ 1328 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1329 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 1330 topology_info_input->num_nodes = number_devices; 1331 1332 for (i = 0; i < topology_info_input->num_nodes; i++) { 1333 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1334 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1335 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 1336 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1337 } 1338 1339 /* Invoke xgmi ta to get the topology information */ 1340 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 1341 if (ret) 1342 return ret; 1343 1344 /* Read the output topology information from the shared memory */ 1345 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 1346 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 1347 for (i = 0; i < topology->num_nodes; i++) { 1348 /* extended data will either be 0 or equal to non-extended data */ 1349 if (topology_info_output->nodes[i].num_hops) 1350 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 1351 1352 /* non-extended data gets everything here so no need to update */ 1353 if (!get_extended_data) { 1354 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 1355 topology->nodes[i].is_sharing_enabled = 1356 topology_info_output->nodes[i].is_sharing_enabled; 1357 topology->nodes[i].sdma_engine = 1358 topology_info_output->nodes[i].sdma_engine; 1359 } 1360 1361 } 1362 1363 /* Invoke xgmi ta again to get the link information */ 1364 if (psp_xgmi_peer_link_info_supported(psp)) { 1365 struct ta_xgmi_cmd_get_peer_link_info_output *link_info_output; 1366 1367 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS; 1368 1369 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_PEER_LINKS); 1370 1371 if (ret) 1372 return ret; 1373 1374 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info; 1375 for (i = 0; i < topology->num_nodes; i++) { 1376 /* accumulate num_links on extended data */ 1377 topology->nodes[i].num_links = get_extended_data ? 1378 topology->nodes[i].num_links + 1379 link_info_output->nodes[i].num_links : 1380 link_info_output->nodes[i].num_links; 1381 1382 /* reflect the topology information for bi-directionality */ 1383 if (psp->xgmi_context.supports_extended_data && 1384 get_extended_data && topology->nodes[i].num_hops) 1385 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]); 1386 } 1387 } 1388 1389 return 0; 1390 } 1391 1392 int psp_xgmi_set_topology_info(struct psp_context *psp, 1393 int number_devices, 1394 struct psp_xgmi_topology_info *topology) 1395 { 1396 struct ta_xgmi_shared_memory *xgmi_cmd; 1397 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1398 int i; 1399 1400 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1401 return -EINVAL; 1402 1403 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1404 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1405 1406 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1407 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 1408 topology_info_input->num_nodes = number_devices; 1409 1410 for (i = 0; i < topology_info_input->num_nodes; i++) { 1411 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1412 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1413 topology_info_input->nodes[i].is_sharing_enabled = 1; 1414 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1415 } 1416 1417 /* Invoke xgmi ta to set topology information */ 1418 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 1419 } 1420 1421 // ras begin 1422 static void psp_ras_ta_check_status(struct psp_context *psp) 1423 { 1424 struct ta_ras_shared_memory *ras_cmd = 1425 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1426 1427 switch (ras_cmd->ras_status) { 1428 case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP: 1429 dev_warn(psp->adev->dev, 1430 "RAS WARNING: cmd failed due to unsupported ip\n"); 1431 break; 1432 case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ: 1433 dev_warn(psp->adev->dev, 1434 "RAS WARNING: cmd failed due to unsupported error injection\n"); 1435 break; 1436 case TA_RAS_STATUS__SUCCESS: 1437 break; 1438 case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED: 1439 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR) 1440 dev_warn(psp->adev->dev, 1441 "RAS WARNING: Inject error to critical region is not allowed\n"); 1442 break; 1443 default: 1444 dev_warn(psp->adev->dev, 1445 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status); 1446 break; 1447 } 1448 } 1449 1450 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1451 { 1452 struct ta_ras_shared_memory *ras_cmd; 1453 int ret; 1454 1455 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1456 1457 /* 1458 * TODO: bypass the loading in sriov for now 1459 */ 1460 if (amdgpu_sriov_vf(psp->adev)) 1461 return 0; 1462 1463 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context); 1464 1465 if (amdgpu_ras_intr_triggered()) 1466 return ret; 1467 1468 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) 1469 { 1470 DRM_WARN("RAS: Unsupported Interface"); 1471 return -EINVAL; 1472 } 1473 1474 if (!ret) { 1475 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 1476 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 1477 1478 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 1479 } 1480 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1481 dev_warn(psp->adev->dev, 1482 "RAS internal register access blocked\n"); 1483 1484 psp_ras_ta_check_status(psp); 1485 } 1486 1487 return ret; 1488 } 1489 1490 int psp_ras_enable_features(struct psp_context *psp, 1491 union ta_ras_cmd_input *info, bool enable) 1492 { 1493 struct ta_ras_shared_memory *ras_cmd; 1494 int ret; 1495 1496 if (!psp->ras_context.context.initialized) 1497 return -EINVAL; 1498 1499 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1500 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1501 1502 if (enable) 1503 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 1504 else 1505 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 1506 1507 ras_cmd->ras_in_message = *info; 1508 1509 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1510 if (ret) 1511 return -EINVAL; 1512 1513 return 0; 1514 } 1515 1516 int psp_ras_terminate(struct psp_context *psp) 1517 { 1518 int ret; 1519 1520 /* 1521 * TODO: bypass the terminate in sriov for now 1522 */ 1523 if (amdgpu_sriov_vf(psp->adev)) 1524 return 0; 1525 1526 if (!psp->ras_context.context.initialized) 1527 return 0; 1528 1529 ret = psp_ta_unload(psp, &psp->ras_context.context); 1530 1531 psp->ras_context.context.initialized = false; 1532 1533 return ret; 1534 } 1535 1536 int psp_ras_initialize(struct psp_context *psp) 1537 { 1538 int ret; 1539 uint32_t boot_cfg = 0xFF; 1540 struct amdgpu_device *adev = psp->adev; 1541 struct ta_ras_shared_memory *ras_cmd; 1542 1543 /* 1544 * TODO: bypass the initialize in sriov for now 1545 */ 1546 if (amdgpu_sriov_vf(adev)) 1547 return 0; 1548 1549 if (!adev->psp.ras_context.context.bin_desc.size_bytes || 1550 !adev->psp.ras_context.context.bin_desc.start_addr) { 1551 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n"); 1552 return 0; 1553 } 1554 1555 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 1556 /* query GECC enablement status from boot config 1557 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled 1558 */ 1559 ret = psp_boot_config_get(adev, &boot_cfg); 1560 if (ret) 1561 dev_warn(adev->dev, "PSP get boot config failed\n"); 1562 1563 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) { 1564 if (!boot_cfg) { 1565 dev_info(adev->dev, "GECC is disabled\n"); 1566 } else { 1567 /* disable GECC in next boot cycle if ras is 1568 * disabled by module parameter amdgpu_ras_enable 1569 * and/or amdgpu_ras_mask, or boot_config_get call 1570 * is failed 1571 */ 1572 ret = psp_boot_config_set(adev, 0); 1573 if (ret) 1574 dev_warn(adev->dev, "PSP set boot config failed\n"); 1575 else 1576 dev_warn(adev->dev, "GECC will be disabled in next boot cycle " 1577 "if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n"); 1578 } 1579 } else { 1580 if (1 == boot_cfg) { 1581 dev_info(adev->dev, "GECC is enabled\n"); 1582 } else { 1583 /* enable GECC in next boot cycle if it is disabled 1584 * in boot config, or force enable GECC if failed to 1585 * get boot configuration 1586 */ 1587 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC); 1588 if (ret) 1589 dev_warn(adev->dev, "PSP set boot config failed\n"); 1590 else 1591 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n"); 1592 } 1593 } 1594 } 1595 1596 psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE; 1597 psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1598 1599 if (!psp->ras_context.context.mem_context.shared_buf) { 1600 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context); 1601 if (ret) 1602 return ret; 1603 } 1604 1605 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1606 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1607 1608 if (amdgpu_ras_is_poison_mode_supported(adev)) 1609 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 1610 if (!adev->gmc.xgmi.connected_to_cpu) 1611 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 1612 1613 ret = psp_ta_load(psp, &psp->ras_context.context); 1614 1615 if (!ret && !ras_cmd->ras_status) 1616 psp->ras_context.context.initialized = true; 1617 else { 1618 if (ras_cmd->ras_status) 1619 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 1620 1621 /* fail to load RAS TA */ 1622 psp->ras_context.context.initialized = false; 1623 } 1624 1625 return ret; 1626 } 1627 1628 int psp_ras_trigger_error(struct psp_context *psp, 1629 struct ta_ras_trigger_error_input *info) 1630 { 1631 struct ta_ras_shared_memory *ras_cmd; 1632 int ret; 1633 1634 if (!psp->ras_context.context.initialized) 1635 return -EINVAL; 1636 1637 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1638 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1639 1640 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 1641 ras_cmd->ras_in_message.trigger_error = *info; 1642 1643 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1644 if (ret) 1645 return -EINVAL; 1646 1647 /* If err_event_athub occurs error inject was successful, however 1648 return status from TA is no long reliable */ 1649 if (amdgpu_ras_intr_triggered()) 1650 return 0; 1651 1652 if (ras_cmd->ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED) 1653 return -EACCES; 1654 else if (ras_cmd->ras_status) 1655 return -EINVAL; 1656 1657 return 0; 1658 } 1659 // ras end 1660 1661 // HDCP start 1662 static int psp_hdcp_initialize(struct psp_context *psp) 1663 { 1664 int ret; 1665 1666 /* 1667 * TODO: bypass the initialize in sriov for now 1668 */ 1669 if (amdgpu_sriov_vf(psp->adev)) 1670 return 0; 1671 1672 if (!psp->hdcp_context.context.bin_desc.size_bytes || 1673 !psp->hdcp_context.context.bin_desc.start_addr) { 1674 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 1675 return 0; 1676 } 1677 1678 psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE; 1679 psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1680 1681 if (!psp->hdcp_context.context.mem_context.shared_buf) { 1682 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context); 1683 if (ret) 1684 return ret; 1685 } 1686 1687 ret = psp_ta_load(psp, &psp->hdcp_context.context); 1688 if (!ret) { 1689 psp->hdcp_context.context.initialized = true; 1690 mutex_init(&psp->hdcp_context.mutex); 1691 } 1692 1693 return ret; 1694 } 1695 1696 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1697 { 1698 /* 1699 * TODO: bypass the loading in sriov for now 1700 */ 1701 if (amdgpu_sriov_vf(psp->adev)) 1702 return 0; 1703 1704 return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context); 1705 } 1706 1707 static int psp_hdcp_terminate(struct psp_context *psp) 1708 { 1709 int ret; 1710 1711 /* 1712 * TODO: bypass the terminate in sriov for now 1713 */ 1714 if (amdgpu_sriov_vf(psp->adev)) 1715 return 0; 1716 1717 if (!psp->hdcp_context.context.initialized) 1718 return 0; 1719 1720 ret = psp_ta_unload(psp, &psp->hdcp_context.context); 1721 1722 psp->hdcp_context.context.initialized = false; 1723 1724 return ret; 1725 } 1726 // HDCP end 1727 1728 // DTM start 1729 static int psp_dtm_initialize(struct psp_context *psp) 1730 { 1731 int ret; 1732 1733 /* 1734 * TODO: bypass the initialize in sriov for now 1735 */ 1736 if (amdgpu_sriov_vf(psp->adev)) 1737 return 0; 1738 1739 if (!psp->dtm_context.context.bin_desc.size_bytes || 1740 !psp->dtm_context.context.bin_desc.start_addr) { 1741 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 1742 return 0; 1743 } 1744 1745 psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE; 1746 psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1747 1748 if (!psp->dtm_context.context.mem_context.shared_buf) { 1749 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context); 1750 if (ret) 1751 return ret; 1752 } 1753 1754 ret = psp_ta_load(psp, &psp->dtm_context.context); 1755 if (!ret) { 1756 psp->dtm_context.context.initialized = true; 1757 mutex_init(&psp->dtm_context.mutex); 1758 } 1759 1760 return ret; 1761 } 1762 1763 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1764 { 1765 /* 1766 * TODO: bypass the loading in sriov for now 1767 */ 1768 if (amdgpu_sriov_vf(psp->adev)) 1769 return 0; 1770 1771 return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context); 1772 } 1773 1774 static int psp_dtm_terminate(struct psp_context *psp) 1775 { 1776 int ret; 1777 1778 /* 1779 * TODO: bypass the terminate in sriov for now 1780 */ 1781 if (amdgpu_sriov_vf(psp->adev)) 1782 return 0; 1783 1784 if (!psp->dtm_context.context.initialized) 1785 return 0; 1786 1787 ret = psp_ta_unload(psp, &psp->dtm_context.context); 1788 1789 psp->dtm_context.context.initialized = false; 1790 1791 return ret; 1792 } 1793 // DTM end 1794 1795 // RAP start 1796 static int psp_rap_initialize(struct psp_context *psp) 1797 { 1798 int ret; 1799 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 1800 1801 /* 1802 * TODO: bypass the initialize in sriov for now 1803 */ 1804 if (amdgpu_sriov_vf(psp->adev)) 1805 return 0; 1806 1807 if (!psp->rap_context.context.bin_desc.size_bytes || 1808 !psp->rap_context.context.bin_desc.start_addr) { 1809 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 1810 return 0; 1811 } 1812 1813 psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE; 1814 psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1815 1816 if (!psp->rap_context.context.mem_context.shared_buf) { 1817 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context); 1818 if (ret) 1819 return ret; 1820 } 1821 1822 ret = psp_ta_load(psp, &psp->rap_context.context); 1823 if (!ret) { 1824 psp->rap_context.context.initialized = true; 1825 mutex_init(&psp->rap_context.mutex); 1826 } else 1827 return ret; 1828 1829 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 1830 if (ret || status != TA_RAP_STATUS__SUCCESS) { 1831 psp_rap_terminate(psp); 1832 /* free rap shared memory */ 1833 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 1834 1835 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 1836 ret, status); 1837 1838 return ret; 1839 } 1840 1841 return 0; 1842 } 1843 1844 static int psp_rap_terminate(struct psp_context *psp) 1845 { 1846 int ret; 1847 1848 if (!psp->rap_context.context.initialized) 1849 return 0; 1850 1851 ret = psp_ta_unload(psp, &psp->rap_context.context); 1852 1853 psp->rap_context.context.initialized = false; 1854 1855 return ret; 1856 } 1857 1858 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 1859 { 1860 struct ta_rap_shared_memory *rap_cmd; 1861 int ret = 0; 1862 1863 if (!psp->rap_context.context.initialized) 1864 return 0; 1865 1866 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 1867 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 1868 return -EINVAL; 1869 1870 mutex_lock(&psp->rap_context.mutex); 1871 1872 rap_cmd = (struct ta_rap_shared_memory *) 1873 psp->rap_context.context.mem_context.shared_buf; 1874 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 1875 1876 rap_cmd->cmd_id = ta_cmd_id; 1877 rap_cmd->validation_method_id = METHOD_A; 1878 1879 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context); 1880 if (ret) 1881 goto out_unlock; 1882 1883 if (status) 1884 *status = rap_cmd->rap_status; 1885 1886 out_unlock: 1887 mutex_unlock(&psp->rap_context.mutex); 1888 1889 return ret; 1890 } 1891 // RAP end 1892 1893 /* securedisplay start */ 1894 static int psp_securedisplay_initialize(struct psp_context *psp) 1895 { 1896 int ret; 1897 struct ta_securedisplay_cmd *securedisplay_cmd; 1898 1899 /* 1900 * TODO: bypass the initialize in sriov for now 1901 */ 1902 if (amdgpu_sriov_vf(psp->adev)) 1903 return 0; 1904 1905 if (!psp->securedisplay_context.context.bin_desc.size_bytes || 1906 !psp->securedisplay_context.context.bin_desc.start_addr) { 1907 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n"); 1908 return 0; 1909 } 1910 1911 psp->securedisplay_context.context.mem_context.shared_mem_size = 1912 PSP_SECUREDISPLAY_SHARED_MEM_SIZE; 1913 psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1914 1915 if (!psp->securedisplay_context.context.initialized) { 1916 ret = psp_ta_init_shared_buf(psp, 1917 &psp->securedisplay_context.context.mem_context); 1918 if (ret) 1919 return ret; 1920 } 1921 1922 ret = psp_ta_load(psp, &psp->securedisplay_context.context); 1923 if (!ret) { 1924 psp->securedisplay_context.context.initialized = true; 1925 mutex_init(&psp->securedisplay_context.mutex); 1926 } else 1927 return ret; 1928 1929 mutex_lock(&psp->securedisplay_context.mutex); 1930 1931 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 1932 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1933 1934 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1935 1936 mutex_unlock(&psp->securedisplay_context.mutex); 1937 1938 if (ret) { 1939 psp_securedisplay_terminate(psp); 1940 /* free securedisplay shared memory */ 1941 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 1942 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 1943 return -EINVAL; 1944 } 1945 1946 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 1947 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 1948 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 1949 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 1950 } 1951 1952 return 0; 1953 } 1954 1955 static int psp_securedisplay_terminate(struct psp_context *psp) 1956 { 1957 int ret; 1958 1959 /* 1960 * TODO:bypass the terminate in sriov for now 1961 */ 1962 if (amdgpu_sriov_vf(psp->adev)) 1963 return 0; 1964 1965 if (!psp->securedisplay_context.context.initialized) 1966 return 0; 1967 1968 ret = psp_ta_unload(psp, &psp->securedisplay_context.context); 1969 1970 psp->securedisplay_context.context.initialized = false; 1971 1972 return ret; 1973 } 1974 1975 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1976 { 1977 int ret; 1978 1979 if (!psp->securedisplay_context.context.initialized) 1980 return -EINVAL; 1981 1982 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 1983 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC) 1984 return -EINVAL; 1985 1986 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context); 1987 1988 return ret; 1989 } 1990 /* SECUREDISPLAY end */ 1991 1992 static int psp_hw_start(struct psp_context *psp) 1993 { 1994 struct amdgpu_device *adev = psp->adev; 1995 int ret; 1996 1997 if (!amdgpu_sriov_vf(adev)) { 1998 if ((is_psp_fw_valid(psp->kdb)) && 1999 (psp->funcs->bootloader_load_kdb != NULL)) { 2000 ret = psp_bootloader_load_kdb(psp); 2001 if (ret) { 2002 DRM_ERROR("PSP load kdb failed!\n"); 2003 return ret; 2004 } 2005 } 2006 2007 if ((is_psp_fw_valid(psp->spl)) && 2008 (psp->funcs->bootloader_load_spl != NULL)) { 2009 ret = psp_bootloader_load_spl(psp); 2010 if (ret) { 2011 DRM_ERROR("PSP load spl failed!\n"); 2012 return ret; 2013 } 2014 } 2015 2016 if ((is_psp_fw_valid(psp->sys)) && 2017 (psp->funcs->bootloader_load_sysdrv != NULL)) { 2018 ret = psp_bootloader_load_sysdrv(psp); 2019 if (ret) { 2020 DRM_ERROR("PSP load sys drv failed!\n"); 2021 return ret; 2022 } 2023 } 2024 2025 if ((is_psp_fw_valid(psp->soc_drv)) && 2026 (psp->funcs->bootloader_load_soc_drv != NULL)) { 2027 ret = psp_bootloader_load_soc_drv(psp); 2028 if (ret) { 2029 DRM_ERROR("PSP load soc drv failed!\n"); 2030 return ret; 2031 } 2032 } 2033 2034 if ((is_psp_fw_valid(psp->intf_drv)) && 2035 (psp->funcs->bootloader_load_intf_drv != NULL)) { 2036 ret = psp_bootloader_load_intf_drv(psp); 2037 if (ret) { 2038 DRM_ERROR("PSP load intf drv failed!\n"); 2039 return ret; 2040 } 2041 } 2042 2043 if ((is_psp_fw_valid(psp->dbg_drv)) && 2044 (psp->funcs->bootloader_load_dbg_drv != NULL)) { 2045 ret = psp_bootloader_load_dbg_drv(psp); 2046 if (ret) { 2047 DRM_ERROR("PSP load dbg drv failed!\n"); 2048 return ret; 2049 } 2050 } 2051 2052 if ((is_psp_fw_valid(psp->ras_drv)) && 2053 (psp->funcs->bootloader_load_ras_drv != NULL)) { 2054 ret = psp_bootloader_load_ras_drv(psp); 2055 if (ret) { 2056 DRM_ERROR("PSP load ras_drv failed!\n"); 2057 return ret; 2058 } 2059 } 2060 2061 if ((is_psp_fw_valid(psp->sos)) && 2062 (psp->funcs->bootloader_load_sos != NULL)) { 2063 ret = psp_bootloader_load_sos(psp); 2064 if (ret) { 2065 DRM_ERROR("PSP load sos failed!\n"); 2066 return ret; 2067 } 2068 } 2069 } 2070 2071 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 2072 if (ret) { 2073 DRM_ERROR("PSP create ring failed!\n"); 2074 return ret; 2075 } 2076 2077 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 2078 goto skip_pin_bo; 2079 2080 ret = psp_tmr_init(psp); 2081 if (ret) { 2082 DRM_ERROR("PSP tmr init failed!\n"); 2083 return ret; 2084 } 2085 2086 skip_pin_bo: 2087 /* 2088 * For ASICs with DF Cstate management centralized 2089 * to PMFW, TMR setup should be performed after PMFW 2090 * loaded and before other non-psp firmware loaded. 2091 */ 2092 if (psp->pmfw_centralized_cstate_management) { 2093 ret = psp_load_smu_fw(psp); 2094 if (ret) 2095 return ret; 2096 } 2097 2098 ret = psp_tmr_load(psp); 2099 if (ret) { 2100 DRM_ERROR("PSP load tmr failed!\n"); 2101 return ret; 2102 } 2103 2104 return 0; 2105 } 2106 2107 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 2108 enum psp_gfx_fw_type *type) 2109 { 2110 switch (ucode->ucode_id) { 2111 case AMDGPU_UCODE_ID_CAP: 2112 *type = GFX_FW_TYPE_CAP; 2113 break; 2114 case AMDGPU_UCODE_ID_SDMA0: 2115 *type = GFX_FW_TYPE_SDMA0; 2116 break; 2117 case AMDGPU_UCODE_ID_SDMA1: 2118 *type = GFX_FW_TYPE_SDMA1; 2119 break; 2120 case AMDGPU_UCODE_ID_SDMA2: 2121 *type = GFX_FW_TYPE_SDMA2; 2122 break; 2123 case AMDGPU_UCODE_ID_SDMA3: 2124 *type = GFX_FW_TYPE_SDMA3; 2125 break; 2126 case AMDGPU_UCODE_ID_SDMA4: 2127 *type = GFX_FW_TYPE_SDMA4; 2128 break; 2129 case AMDGPU_UCODE_ID_SDMA5: 2130 *type = GFX_FW_TYPE_SDMA5; 2131 break; 2132 case AMDGPU_UCODE_ID_SDMA6: 2133 *type = GFX_FW_TYPE_SDMA6; 2134 break; 2135 case AMDGPU_UCODE_ID_SDMA7: 2136 *type = GFX_FW_TYPE_SDMA7; 2137 break; 2138 case AMDGPU_UCODE_ID_CP_MES: 2139 *type = GFX_FW_TYPE_CP_MES; 2140 break; 2141 case AMDGPU_UCODE_ID_CP_MES_DATA: 2142 *type = GFX_FW_TYPE_MES_STACK; 2143 break; 2144 case AMDGPU_UCODE_ID_CP_MES1: 2145 *type = GFX_FW_TYPE_CP_MES_KIQ; 2146 break; 2147 case AMDGPU_UCODE_ID_CP_MES1_DATA: 2148 *type = GFX_FW_TYPE_MES_KIQ_STACK; 2149 break; 2150 case AMDGPU_UCODE_ID_CP_CE: 2151 *type = GFX_FW_TYPE_CP_CE; 2152 break; 2153 case AMDGPU_UCODE_ID_CP_PFP: 2154 *type = GFX_FW_TYPE_CP_PFP; 2155 break; 2156 case AMDGPU_UCODE_ID_CP_ME: 2157 *type = GFX_FW_TYPE_CP_ME; 2158 break; 2159 case AMDGPU_UCODE_ID_CP_MEC1: 2160 *type = GFX_FW_TYPE_CP_MEC; 2161 break; 2162 case AMDGPU_UCODE_ID_CP_MEC1_JT: 2163 *type = GFX_FW_TYPE_CP_MEC_ME1; 2164 break; 2165 case AMDGPU_UCODE_ID_CP_MEC2: 2166 *type = GFX_FW_TYPE_CP_MEC; 2167 break; 2168 case AMDGPU_UCODE_ID_CP_MEC2_JT: 2169 *type = GFX_FW_TYPE_CP_MEC_ME2; 2170 break; 2171 case AMDGPU_UCODE_ID_RLC_P: 2172 *type = GFX_FW_TYPE_RLC_P; 2173 break; 2174 case AMDGPU_UCODE_ID_RLC_V: 2175 *type = GFX_FW_TYPE_RLC_V; 2176 break; 2177 case AMDGPU_UCODE_ID_RLC_G: 2178 *type = GFX_FW_TYPE_RLC_G; 2179 break; 2180 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 2181 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 2182 break; 2183 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 2184 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 2185 break; 2186 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 2187 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 2188 break; 2189 case AMDGPU_UCODE_ID_RLC_IRAM: 2190 *type = GFX_FW_TYPE_RLC_IRAM; 2191 break; 2192 case AMDGPU_UCODE_ID_RLC_DRAM: 2193 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 2194 break; 2195 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS: 2196 *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS; 2197 break; 2198 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS: 2199 *type = GFX_FW_TYPE_SE0_TAP_DELAYS; 2200 break; 2201 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS: 2202 *type = GFX_FW_TYPE_SE1_TAP_DELAYS; 2203 break; 2204 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS: 2205 *type = GFX_FW_TYPE_SE2_TAP_DELAYS; 2206 break; 2207 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS: 2208 *type = GFX_FW_TYPE_SE3_TAP_DELAYS; 2209 break; 2210 case AMDGPU_UCODE_ID_SMC: 2211 *type = GFX_FW_TYPE_SMU; 2212 break; 2213 case AMDGPU_UCODE_ID_PPTABLE: 2214 *type = GFX_FW_TYPE_PPTABLE; 2215 break; 2216 case AMDGPU_UCODE_ID_UVD: 2217 *type = GFX_FW_TYPE_UVD; 2218 break; 2219 case AMDGPU_UCODE_ID_UVD1: 2220 *type = GFX_FW_TYPE_UVD1; 2221 break; 2222 case AMDGPU_UCODE_ID_VCE: 2223 *type = GFX_FW_TYPE_VCE; 2224 break; 2225 case AMDGPU_UCODE_ID_VCN: 2226 *type = GFX_FW_TYPE_VCN; 2227 break; 2228 case AMDGPU_UCODE_ID_VCN1: 2229 *type = GFX_FW_TYPE_VCN1; 2230 break; 2231 case AMDGPU_UCODE_ID_DMCU_ERAM: 2232 *type = GFX_FW_TYPE_DMCU_ERAM; 2233 break; 2234 case AMDGPU_UCODE_ID_DMCU_INTV: 2235 *type = GFX_FW_TYPE_DMCU_ISR; 2236 break; 2237 case AMDGPU_UCODE_ID_VCN0_RAM: 2238 *type = GFX_FW_TYPE_VCN0_RAM; 2239 break; 2240 case AMDGPU_UCODE_ID_VCN1_RAM: 2241 *type = GFX_FW_TYPE_VCN1_RAM; 2242 break; 2243 case AMDGPU_UCODE_ID_DMCUB: 2244 *type = GFX_FW_TYPE_DMUB; 2245 break; 2246 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0: 2247 *type = GFX_FW_TYPE_SDMA_UCODE_TH0; 2248 break; 2249 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1: 2250 *type = GFX_FW_TYPE_SDMA_UCODE_TH1; 2251 break; 2252 case AMDGPU_UCODE_ID_IMU_I: 2253 *type = GFX_FW_TYPE_IMU_I; 2254 break; 2255 case AMDGPU_UCODE_ID_IMU_D: 2256 *type = GFX_FW_TYPE_IMU_D; 2257 break; 2258 case AMDGPU_UCODE_ID_CP_RS64_PFP: 2259 *type = GFX_FW_TYPE_RS64_PFP; 2260 break; 2261 case AMDGPU_UCODE_ID_CP_RS64_ME: 2262 *type = GFX_FW_TYPE_RS64_ME; 2263 break; 2264 case AMDGPU_UCODE_ID_CP_RS64_MEC: 2265 *type = GFX_FW_TYPE_RS64_MEC; 2266 break; 2267 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK: 2268 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK; 2269 break; 2270 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK: 2271 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK; 2272 break; 2273 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK: 2274 *type = GFX_FW_TYPE_RS64_ME_P0_STACK; 2275 break; 2276 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK: 2277 *type = GFX_FW_TYPE_RS64_ME_P1_STACK; 2278 break; 2279 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK: 2280 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK; 2281 break; 2282 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: 2283 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK; 2284 break; 2285 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: 2286 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK; 2287 break; 2288 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: 2289 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK; 2290 break; 2291 case AMDGPU_UCODE_ID_MAXIMUM: 2292 default: 2293 return -EINVAL; 2294 } 2295 2296 return 0; 2297 } 2298 2299 static void psp_print_fw_hdr(struct psp_context *psp, 2300 struct amdgpu_firmware_info *ucode) 2301 { 2302 struct amdgpu_device *adev = psp->adev; 2303 struct common_firmware_header *hdr; 2304 2305 switch (ucode->ucode_id) { 2306 case AMDGPU_UCODE_ID_SDMA0: 2307 case AMDGPU_UCODE_ID_SDMA1: 2308 case AMDGPU_UCODE_ID_SDMA2: 2309 case AMDGPU_UCODE_ID_SDMA3: 2310 case AMDGPU_UCODE_ID_SDMA4: 2311 case AMDGPU_UCODE_ID_SDMA5: 2312 case AMDGPU_UCODE_ID_SDMA6: 2313 case AMDGPU_UCODE_ID_SDMA7: 2314 hdr = (struct common_firmware_header *) 2315 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 2316 amdgpu_ucode_print_sdma_hdr(hdr); 2317 break; 2318 case AMDGPU_UCODE_ID_CP_CE: 2319 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 2320 amdgpu_ucode_print_gfx_hdr(hdr); 2321 break; 2322 case AMDGPU_UCODE_ID_CP_PFP: 2323 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 2324 amdgpu_ucode_print_gfx_hdr(hdr); 2325 break; 2326 case AMDGPU_UCODE_ID_CP_ME: 2327 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 2328 amdgpu_ucode_print_gfx_hdr(hdr); 2329 break; 2330 case AMDGPU_UCODE_ID_CP_MEC1: 2331 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 2332 amdgpu_ucode_print_gfx_hdr(hdr); 2333 break; 2334 case AMDGPU_UCODE_ID_RLC_G: 2335 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 2336 amdgpu_ucode_print_rlc_hdr(hdr); 2337 break; 2338 case AMDGPU_UCODE_ID_SMC: 2339 hdr = (struct common_firmware_header *)adev->pm.fw->data; 2340 amdgpu_ucode_print_smc_hdr(hdr); 2341 break; 2342 default: 2343 break; 2344 } 2345 } 2346 2347 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 2348 struct psp_gfx_cmd_resp *cmd) 2349 { 2350 int ret; 2351 uint64_t fw_mem_mc_addr = ucode->mc_addr; 2352 2353 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 2354 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 2355 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 2356 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 2357 2358 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 2359 if (ret) 2360 DRM_ERROR("Unknown firmware type\n"); 2361 2362 return ret; 2363 } 2364 2365 static int psp_execute_non_psp_fw_load(struct psp_context *psp, 2366 struct amdgpu_firmware_info *ucode) 2367 { 2368 int ret = 0; 2369 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2370 2371 ret = psp_prep_load_ip_fw_cmd_buf(ucode, cmd); 2372 if (!ret) { 2373 ret = psp_cmd_submit_buf(psp, ucode, cmd, 2374 psp->fence_buf_mc_addr); 2375 } 2376 2377 release_psp_cmd_buf(psp); 2378 2379 return ret; 2380 } 2381 2382 static int psp_load_smu_fw(struct psp_context *psp) 2383 { 2384 int ret; 2385 struct amdgpu_device *adev = psp->adev; 2386 struct amdgpu_firmware_info *ucode = 2387 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 2388 struct amdgpu_ras *ras = psp->ras_context.ras; 2389 2390 /* 2391 * Skip SMU FW reloading in case of using BACO for runpm only, 2392 * as SMU is always alive. 2393 */ 2394 if (adev->in_runpm && (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO)) 2395 return 0; 2396 2397 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2398 return 0; 2399 2400 if ((amdgpu_in_reset(adev) && 2401 ras && adev->ras_enabled && 2402 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || 2403 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 2)))) { 2404 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 2405 if (ret) { 2406 DRM_WARN("Failed to set MP1 state prepare for reload\n"); 2407 } 2408 } 2409 2410 ret = psp_execute_non_psp_fw_load(psp, ucode); 2411 2412 if (ret) 2413 DRM_ERROR("PSP load smu failed!\n"); 2414 2415 return ret; 2416 } 2417 2418 static bool fw_load_skip_check(struct psp_context *psp, 2419 struct amdgpu_firmware_info *ucode) 2420 { 2421 if (!ucode->fw || !ucode->ucode_size) 2422 return true; 2423 2424 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2425 (psp_smu_reload_quirk(psp) || 2426 psp->autoload_supported || 2427 psp->pmfw_centralized_cstate_management)) 2428 return true; 2429 2430 if (amdgpu_sriov_vf(psp->adev) && 2431 amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id)) 2432 return true; 2433 2434 if (psp->autoload_supported && 2435 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 2436 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 2437 /* skip mec JT when autoload is enabled */ 2438 return true; 2439 2440 return false; 2441 } 2442 2443 int psp_load_fw_list(struct psp_context *psp, 2444 struct amdgpu_firmware_info **ucode_list, int ucode_count) 2445 { 2446 int ret = 0, i; 2447 struct amdgpu_firmware_info *ucode; 2448 2449 for (i = 0; i < ucode_count; ++i) { 2450 ucode = ucode_list[i]; 2451 psp_print_fw_hdr(psp, ucode); 2452 ret = psp_execute_non_psp_fw_load(psp, ucode); 2453 if (ret) 2454 return ret; 2455 } 2456 return ret; 2457 } 2458 2459 static int psp_load_non_psp_fw(struct psp_context *psp) 2460 { 2461 int i, ret; 2462 struct amdgpu_firmware_info *ucode; 2463 struct amdgpu_device *adev = psp->adev; 2464 2465 if (psp->autoload_supported && 2466 !psp->pmfw_centralized_cstate_management) { 2467 ret = psp_load_smu_fw(psp); 2468 if (ret) 2469 return ret; 2470 } 2471 2472 for (i = 0; i < adev->firmware.max_ucodes; i++) { 2473 ucode = &adev->firmware.ucode[i]; 2474 2475 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2476 !fw_load_skip_check(psp, ucode)) { 2477 ret = psp_load_smu_fw(psp); 2478 if (ret) 2479 return ret; 2480 continue; 2481 } 2482 2483 if (fw_load_skip_check(psp, ucode)) 2484 continue; 2485 2486 if (psp->autoload_supported && 2487 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7) || 2488 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 11) || 2489 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 12)) && 2490 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 2491 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 2492 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 2493 /* PSP only receive one SDMA fw for sienna_cichlid, 2494 * as all four sdma fw are same */ 2495 continue; 2496 2497 psp_print_fw_hdr(psp, ucode); 2498 2499 ret = psp_execute_non_psp_fw_load(psp, ucode); 2500 if (ret) 2501 return ret; 2502 2503 /* Start rlc autoload after psp recieved all the gfx firmware */ 2504 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 2505 adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) { 2506 ret = psp_rlc_autoload_start(psp); 2507 if (ret) { 2508 DRM_ERROR("Failed to start rlc autoload\n"); 2509 return ret; 2510 } 2511 } 2512 } 2513 2514 return 0; 2515 } 2516 2517 static int psp_load_fw(struct amdgpu_device *adev) 2518 { 2519 int ret; 2520 struct psp_context *psp = &adev->psp; 2521 2522 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2523 /* should not destroy ring, only stop */ 2524 psp_ring_stop(psp, PSP_RING_TYPE__KM); 2525 } else { 2526 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 2527 2528 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 2529 if (ret) { 2530 DRM_ERROR("PSP ring init failed!\n"); 2531 goto failed; 2532 } 2533 } 2534 2535 ret = psp_hw_start(psp); 2536 if (ret) 2537 goto failed; 2538 2539 ret = psp_load_non_psp_fw(psp); 2540 if (ret) 2541 goto failed1; 2542 2543 ret = psp_asd_initialize(psp); 2544 if (ret) { 2545 DRM_ERROR("PSP load asd failed!\n"); 2546 goto failed1; 2547 } 2548 2549 ret = psp_rl_load(adev); 2550 if (ret) { 2551 DRM_ERROR("PSP load RL failed!\n"); 2552 goto failed1; 2553 } 2554 2555 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2556 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2557 ret = psp_xgmi_initialize(psp, false, true); 2558 /* Warning the XGMI seesion initialize failure 2559 * Instead of stop driver initialization 2560 */ 2561 if (ret) 2562 dev_err(psp->adev->dev, 2563 "XGMI: Failed to initialize XGMI session\n"); 2564 } 2565 } 2566 2567 if (psp->ta_fw) { 2568 ret = psp_ras_initialize(psp); 2569 if (ret) 2570 dev_err(psp->adev->dev, 2571 "RAS: Failed to initialize RAS\n"); 2572 2573 ret = psp_hdcp_initialize(psp); 2574 if (ret) 2575 dev_err(psp->adev->dev, 2576 "HDCP: Failed to initialize HDCP\n"); 2577 2578 ret = psp_dtm_initialize(psp); 2579 if (ret) 2580 dev_err(psp->adev->dev, 2581 "DTM: Failed to initialize DTM\n"); 2582 2583 ret = psp_rap_initialize(psp); 2584 if (ret) 2585 dev_err(psp->adev->dev, 2586 "RAP: Failed to initialize RAP\n"); 2587 2588 ret = psp_securedisplay_initialize(psp); 2589 if (ret) 2590 dev_err(psp->adev->dev, 2591 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2592 } 2593 2594 return 0; 2595 2596 failed1: 2597 psp_free_shared_bufs(psp); 2598 failed: 2599 /* 2600 * all cleanup jobs (xgmi terminate, ras terminate, 2601 * ring destroy, cmd/fence/fw buffers destory, 2602 * psp->cmd destory) are delayed to psp_hw_fini 2603 */ 2604 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2605 return ret; 2606 } 2607 2608 static int psp_hw_init(void *handle) 2609 { 2610 int ret; 2611 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2612 2613 mutex_lock(&adev->firmware.mutex); 2614 /* 2615 * This sequence is just used on hw_init only once, no need on 2616 * resume. 2617 */ 2618 ret = amdgpu_ucode_init_bo(adev); 2619 if (ret) 2620 goto failed; 2621 2622 ret = psp_load_fw(adev); 2623 if (ret) { 2624 DRM_ERROR("PSP firmware loading failed\n"); 2625 goto failed; 2626 } 2627 2628 mutex_unlock(&adev->firmware.mutex); 2629 return 0; 2630 2631 failed: 2632 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 2633 mutex_unlock(&adev->firmware.mutex); 2634 return -EINVAL; 2635 } 2636 2637 static int psp_hw_fini(void *handle) 2638 { 2639 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2640 struct psp_context *psp = &adev->psp; 2641 2642 if (psp->ta_fw) { 2643 psp_ras_terminate(psp); 2644 psp_securedisplay_terminate(psp); 2645 psp_rap_terminate(psp); 2646 psp_dtm_terminate(psp); 2647 psp_hdcp_terminate(psp); 2648 2649 if (adev->gmc.xgmi.num_physical_nodes > 1) 2650 psp_xgmi_terminate(psp); 2651 } 2652 2653 psp_asd_terminate(psp); 2654 psp_tmr_terminate(psp); 2655 2656 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2657 2658 psp_free_shared_bufs(psp); 2659 2660 return 0; 2661 } 2662 2663 static int psp_suspend(void *handle) 2664 { 2665 int ret = 0; 2666 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2667 struct psp_context *psp = &adev->psp; 2668 2669 if (adev->gmc.xgmi.num_physical_nodes > 1 && 2670 psp->xgmi_context.context.initialized) { 2671 ret = psp_xgmi_terminate(psp); 2672 if (ret) { 2673 DRM_ERROR("Failed to terminate xgmi ta\n"); 2674 goto out; 2675 } 2676 } 2677 2678 if (psp->ta_fw) { 2679 ret = psp_ras_terminate(psp); 2680 if (ret) { 2681 DRM_ERROR("Failed to terminate ras ta\n"); 2682 goto out; 2683 } 2684 ret = psp_hdcp_terminate(psp); 2685 if (ret) { 2686 DRM_ERROR("Failed to terminate hdcp ta\n"); 2687 goto out; 2688 } 2689 ret = psp_dtm_terminate(psp); 2690 if (ret) { 2691 DRM_ERROR("Failed to terminate dtm ta\n"); 2692 goto out; 2693 } 2694 ret = psp_rap_terminate(psp); 2695 if (ret) { 2696 DRM_ERROR("Failed to terminate rap ta\n"); 2697 goto out; 2698 } 2699 ret = psp_securedisplay_terminate(psp); 2700 if (ret) { 2701 DRM_ERROR("Failed to terminate securedisplay ta\n"); 2702 goto out; 2703 } 2704 } 2705 2706 ret = psp_asd_terminate(psp); 2707 if (ret) { 2708 DRM_ERROR("Failed to terminate asd\n"); 2709 goto out; 2710 } 2711 2712 ret = psp_tmr_terminate(psp); 2713 if (ret) { 2714 DRM_ERROR("Failed to terminate tmr\n"); 2715 goto out; 2716 } 2717 2718 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 2719 if (ret) { 2720 DRM_ERROR("PSP ring stop failed\n"); 2721 } 2722 2723 out: 2724 return ret; 2725 } 2726 2727 static int psp_resume(void *handle) 2728 { 2729 int ret; 2730 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2731 struct psp_context *psp = &adev->psp; 2732 2733 DRM_INFO("PSP is resuming...\n"); 2734 2735 if (psp->mem_train_ctx.enable_mem_training) { 2736 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 2737 if (ret) { 2738 DRM_ERROR("Failed to process memory training!\n"); 2739 return ret; 2740 } 2741 } 2742 2743 mutex_lock(&adev->firmware.mutex); 2744 2745 ret = psp_hw_start(psp); 2746 if (ret) 2747 goto failed; 2748 2749 ret = psp_load_non_psp_fw(psp); 2750 if (ret) 2751 goto failed; 2752 2753 ret = psp_asd_initialize(psp); 2754 if (ret) { 2755 DRM_ERROR("PSP load asd failed!\n"); 2756 goto failed; 2757 } 2758 2759 ret = psp_rl_load(adev); 2760 if (ret) { 2761 dev_err(adev->dev, "PSP load RL failed!\n"); 2762 goto failed; 2763 } 2764 2765 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2766 ret = psp_xgmi_initialize(psp, false, true); 2767 /* Warning the XGMI seesion initialize failure 2768 * Instead of stop driver initialization 2769 */ 2770 if (ret) 2771 dev_err(psp->adev->dev, 2772 "XGMI: Failed to initialize XGMI session\n"); 2773 } 2774 2775 if (psp->ta_fw) { 2776 ret = psp_ras_initialize(psp); 2777 if (ret) 2778 dev_err(psp->adev->dev, 2779 "RAS: Failed to initialize RAS\n"); 2780 2781 ret = psp_hdcp_initialize(psp); 2782 if (ret) 2783 dev_err(psp->adev->dev, 2784 "HDCP: Failed to initialize HDCP\n"); 2785 2786 ret = psp_dtm_initialize(psp); 2787 if (ret) 2788 dev_err(psp->adev->dev, 2789 "DTM: Failed to initialize DTM\n"); 2790 2791 ret = psp_rap_initialize(psp); 2792 if (ret) 2793 dev_err(psp->adev->dev, 2794 "RAP: Failed to initialize RAP\n"); 2795 2796 ret = psp_securedisplay_initialize(psp); 2797 if (ret) 2798 dev_err(psp->adev->dev, 2799 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2800 } 2801 2802 mutex_unlock(&adev->firmware.mutex); 2803 2804 return 0; 2805 2806 failed: 2807 DRM_ERROR("PSP resume failed\n"); 2808 mutex_unlock(&adev->firmware.mutex); 2809 return ret; 2810 } 2811 2812 int psp_gpu_reset(struct amdgpu_device *adev) 2813 { 2814 int ret; 2815 2816 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 2817 return 0; 2818 2819 mutex_lock(&adev->psp.mutex); 2820 ret = psp_mode1_reset(&adev->psp); 2821 mutex_unlock(&adev->psp.mutex); 2822 2823 return ret; 2824 } 2825 2826 int psp_rlc_autoload_start(struct psp_context *psp) 2827 { 2828 int ret; 2829 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2830 2831 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 2832 2833 ret = psp_cmd_submit_buf(psp, NULL, cmd, 2834 psp->fence_buf_mc_addr); 2835 2836 release_psp_cmd_buf(psp); 2837 2838 return ret; 2839 } 2840 2841 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 2842 uint64_t cmd_gpu_addr, int cmd_size) 2843 { 2844 struct amdgpu_firmware_info ucode = {0}; 2845 2846 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 2847 AMDGPU_UCODE_ID_VCN0_RAM; 2848 ucode.mc_addr = cmd_gpu_addr; 2849 ucode.ucode_size = cmd_size; 2850 2851 return psp_execute_non_psp_fw_load(&adev->psp, &ucode); 2852 } 2853 2854 int psp_ring_cmd_submit(struct psp_context *psp, 2855 uint64_t cmd_buf_mc_addr, 2856 uint64_t fence_mc_addr, 2857 int index) 2858 { 2859 unsigned int psp_write_ptr_reg = 0; 2860 struct psp_gfx_rb_frame *write_frame; 2861 struct psp_ring *ring = &psp->km_ring; 2862 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 2863 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 2864 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 2865 struct amdgpu_device *adev = psp->adev; 2866 uint32_t ring_size_dw = ring->ring_size / 4; 2867 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 2868 2869 /* KM (GPCOM) prepare write pointer */ 2870 psp_write_ptr_reg = psp_ring_get_wptr(psp); 2871 2872 /* Update KM RB frame pointer to new frame */ 2873 /* write_frame ptr increments by size of rb_frame in bytes */ 2874 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 2875 if ((psp_write_ptr_reg % ring_size_dw) == 0) 2876 write_frame = ring_buffer_start; 2877 else 2878 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 2879 /* Check invalid write_frame ptr address */ 2880 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 2881 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 2882 ring_buffer_start, ring_buffer_end, write_frame); 2883 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 2884 return -EINVAL; 2885 } 2886 2887 /* Initialize KM RB frame */ 2888 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 2889 2890 /* Update KM RB frame */ 2891 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 2892 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 2893 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 2894 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 2895 write_frame->fence_value = index; 2896 amdgpu_device_flush_hdp(adev, NULL); 2897 2898 /* Update the write Pointer in DWORDs */ 2899 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 2900 psp_ring_set_wptr(psp, psp_write_ptr_reg); 2901 return 0; 2902 } 2903 2904 int psp_init_asd_microcode(struct psp_context *psp, const char *chip_name) 2905 { 2906 struct amdgpu_device *adev = psp->adev; 2907 char fw_name[PSP_FW_NAME_LEN]; 2908 const struct psp_firmware_header_v1_0 *asd_hdr; 2909 int err = 0; 2910 2911 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 2912 err = amdgpu_ucode_request(adev, &adev->psp.asd_fw, fw_name); 2913 if (err) 2914 goto out; 2915 2916 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 2917 adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 2918 adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version); 2919 adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 2920 adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr + 2921 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 2922 return 0; 2923 out: 2924 amdgpu_ucode_release(&adev->psp.asd_fw); 2925 return err; 2926 } 2927 2928 int psp_init_toc_microcode(struct psp_context *psp, const char *chip_name) 2929 { 2930 struct amdgpu_device *adev = psp->adev; 2931 char fw_name[PSP_FW_NAME_LEN]; 2932 const struct psp_firmware_header_v1_0 *toc_hdr; 2933 int err = 0; 2934 2935 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name); 2936 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, fw_name); 2937 if (err) 2938 goto out; 2939 2940 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 2941 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 2942 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 2943 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 2944 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 2945 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 2946 return 0; 2947 out: 2948 amdgpu_ucode_release(&adev->psp.toc_fw); 2949 return err; 2950 } 2951 2952 static int parse_sos_bin_descriptor(struct psp_context *psp, 2953 const struct psp_fw_bin_desc *desc, 2954 const struct psp_firmware_header_v2_0 *sos_hdr) 2955 { 2956 uint8_t *ucode_start_addr = NULL; 2957 2958 if (!psp || !desc || !sos_hdr) 2959 return -EINVAL; 2960 2961 ucode_start_addr = (uint8_t *)sos_hdr + 2962 le32_to_cpu(desc->offset_bytes) + 2963 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 2964 2965 switch (desc->fw_type) { 2966 case PSP_FW_TYPE_PSP_SOS: 2967 psp->sos.fw_version = le32_to_cpu(desc->fw_version); 2968 psp->sos.feature_version = le32_to_cpu(desc->fw_version); 2969 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes); 2970 psp->sos.start_addr = ucode_start_addr; 2971 break; 2972 case PSP_FW_TYPE_PSP_SYS_DRV: 2973 psp->sys.fw_version = le32_to_cpu(desc->fw_version); 2974 psp->sys.feature_version = le32_to_cpu(desc->fw_version); 2975 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes); 2976 psp->sys.start_addr = ucode_start_addr; 2977 break; 2978 case PSP_FW_TYPE_PSP_KDB: 2979 psp->kdb.fw_version = le32_to_cpu(desc->fw_version); 2980 psp->kdb.feature_version = le32_to_cpu(desc->fw_version); 2981 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes); 2982 psp->kdb.start_addr = ucode_start_addr; 2983 break; 2984 case PSP_FW_TYPE_PSP_TOC: 2985 psp->toc.fw_version = le32_to_cpu(desc->fw_version); 2986 psp->toc.feature_version = le32_to_cpu(desc->fw_version); 2987 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes); 2988 psp->toc.start_addr = ucode_start_addr; 2989 break; 2990 case PSP_FW_TYPE_PSP_SPL: 2991 psp->spl.fw_version = le32_to_cpu(desc->fw_version); 2992 psp->spl.feature_version = le32_to_cpu(desc->fw_version); 2993 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes); 2994 psp->spl.start_addr = ucode_start_addr; 2995 break; 2996 case PSP_FW_TYPE_PSP_RL: 2997 psp->rl.fw_version = le32_to_cpu(desc->fw_version); 2998 psp->rl.feature_version = le32_to_cpu(desc->fw_version); 2999 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes); 3000 psp->rl.start_addr = ucode_start_addr; 3001 break; 3002 case PSP_FW_TYPE_PSP_SOC_DRV: 3003 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version); 3004 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version); 3005 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3006 psp->soc_drv.start_addr = ucode_start_addr; 3007 break; 3008 case PSP_FW_TYPE_PSP_INTF_DRV: 3009 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version); 3010 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version); 3011 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3012 psp->intf_drv.start_addr = ucode_start_addr; 3013 break; 3014 case PSP_FW_TYPE_PSP_DBG_DRV: 3015 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version); 3016 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version); 3017 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3018 psp->dbg_drv.start_addr = ucode_start_addr; 3019 break; 3020 case PSP_FW_TYPE_PSP_RAS_DRV: 3021 psp->ras_drv.fw_version = le32_to_cpu(desc->fw_version); 3022 psp->ras_drv.feature_version = le32_to_cpu(desc->fw_version); 3023 psp->ras_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3024 psp->ras_drv.start_addr = ucode_start_addr; 3025 break; 3026 default: 3027 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type); 3028 break; 3029 } 3030 3031 return 0; 3032 } 3033 3034 static int psp_init_sos_base_fw(struct amdgpu_device *adev) 3035 { 3036 const struct psp_firmware_header_v1_0 *sos_hdr; 3037 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3038 uint8_t *ucode_array_start_addr; 3039 3040 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3041 ucode_array_start_addr = (uint8_t *)sos_hdr + 3042 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3043 3044 if (adev->gmc.xgmi.connected_to_cpu || 3045 (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2))) { 3046 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 3047 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version); 3048 3049 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes); 3050 adev->psp.sys.start_addr = ucode_array_start_addr; 3051 3052 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes); 3053 adev->psp.sos.start_addr = ucode_array_start_addr + 3054 le32_to_cpu(sos_hdr->sos.offset_bytes); 3055 } else { 3056 /* Load alternate PSP SOS FW */ 3057 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3058 3059 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3060 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3061 3062 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes); 3063 adev->psp.sys.start_addr = ucode_array_start_addr + 3064 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes); 3065 3066 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes); 3067 adev->psp.sos.start_addr = ucode_array_start_addr + 3068 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes); 3069 } 3070 3071 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) { 3072 dev_warn(adev->dev, "PSP SOS FW not available"); 3073 return -EINVAL; 3074 } 3075 3076 return 0; 3077 } 3078 3079 int psp_init_sos_microcode(struct psp_context *psp, const char *chip_name) 3080 { 3081 struct amdgpu_device *adev = psp->adev; 3082 char fw_name[PSP_FW_NAME_LEN]; 3083 const struct psp_firmware_header_v1_0 *sos_hdr; 3084 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 3085 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 3086 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3087 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0; 3088 int err = 0; 3089 uint8_t *ucode_array_start_addr; 3090 int fw_index = 0; 3091 3092 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 3093 err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, fw_name); 3094 if (err) 3095 goto out; 3096 3097 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3098 ucode_array_start_addr = (uint8_t *)sos_hdr + 3099 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3100 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 3101 3102 switch (sos_hdr->header.header_version_major) { 3103 case 1: 3104 err = psp_init_sos_base_fw(adev); 3105 if (err) 3106 goto out; 3107 3108 if (sos_hdr->header.header_version_minor == 1) { 3109 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 3110 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes); 3111 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3112 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes); 3113 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes); 3114 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3115 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes); 3116 } 3117 if (sos_hdr->header.header_version_minor == 2) { 3118 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 3119 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes); 3120 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3121 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes); 3122 } 3123 if (sos_hdr->header.header_version_minor == 3) { 3124 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3125 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes); 3126 adev->psp.toc.start_addr = ucode_array_start_addr + 3127 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes); 3128 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes); 3129 adev->psp.kdb.start_addr = ucode_array_start_addr + 3130 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes); 3131 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes); 3132 adev->psp.spl.start_addr = ucode_array_start_addr + 3133 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes); 3134 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes); 3135 adev->psp.rl.start_addr = ucode_array_start_addr + 3136 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes); 3137 } 3138 break; 3139 case 2: 3140 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data; 3141 3142 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3143 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n"); 3144 err = -EINVAL; 3145 goto out; 3146 } 3147 3148 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) { 3149 err = parse_sos_bin_descriptor(psp, 3150 &sos_hdr_v2_0->psp_fw_bin[fw_index], 3151 sos_hdr_v2_0); 3152 if (err) 3153 goto out; 3154 } 3155 break; 3156 default: 3157 dev_err(adev->dev, 3158 "unsupported psp sos firmware\n"); 3159 err = -EINVAL; 3160 goto out; 3161 } 3162 3163 return 0; 3164 out: 3165 amdgpu_ucode_release(&adev->psp.sos_fw); 3166 3167 return err; 3168 } 3169 3170 static int parse_ta_bin_descriptor(struct psp_context *psp, 3171 const struct psp_fw_bin_desc *desc, 3172 const struct ta_firmware_header_v2_0 *ta_hdr) 3173 { 3174 uint8_t *ucode_start_addr = NULL; 3175 3176 if (!psp || !desc || !ta_hdr) 3177 return -EINVAL; 3178 3179 ucode_start_addr = (uint8_t *)ta_hdr + 3180 le32_to_cpu(desc->offset_bytes) + 3181 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3182 3183 switch (desc->fw_type) { 3184 case TA_FW_TYPE_PSP_ASD: 3185 psp->asd_context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3186 psp->asd_context.bin_desc.feature_version = le32_to_cpu(desc->fw_version); 3187 psp->asd_context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3188 psp->asd_context.bin_desc.start_addr = ucode_start_addr; 3189 break; 3190 case TA_FW_TYPE_PSP_XGMI: 3191 psp->xgmi_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3192 psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3193 psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr; 3194 break; 3195 case TA_FW_TYPE_PSP_RAS: 3196 psp->ras_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3197 psp->ras_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3198 psp->ras_context.context.bin_desc.start_addr = ucode_start_addr; 3199 break; 3200 case TA_FW_TYPE_PSP_HDCP: 3201 psp->hdcp_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3202 psp->hdcp_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3203 psp->hdcp_context.context.bin_desc.start_addr = ucode_start_addr; 3204 break; 3205 case TA_FW_TYPE_PSP_DTM: 3206 psp->dtm_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3207 psp->dtm_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3208 psp->dtm_context.context.bin_desc.start_addr = ucode_start_addr; 3209 break; 3210 case TA_FW_TYPE_PSP_RAP: 3211 psp->rap_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3212 psp->rap_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3213 psp->rap_context.context.bin_desc.start_addr = ucode_start_addr; 3214 break; 3215 case TA_FW_TYPE_PSP_SECUREDISPLAY: 3216 psp->securedisplay_context.context.bin_desc.fw_version = 3217 le32_to_cpu(desc->fw_version); 3218 psp->securedisplay_context.context.bin_desc.size_bytes = 3219 le32_to_cpu(desc->size_bytes); 3220 psp->securedisplay_context.context.bin_desc.start_addr = 3221 ucode_start_addr; 3222 break; 3223 default: 3224 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 3225 break; 3226 } 3227 3228 return 0; 3229 } 3230 3231 static int parse_ta_v1_microcode(struct psp_context *psp) 3232 { 3233 const struct ta_firmware_header_v1_0 *ta_hdr; 3234 struct amdgpu_device *adev = psp->adev; 3235 3236 ta_hdr = (const struct ta_firmware_header_v1_0 *) adev->psp.ta_fw->data; 3237 3238 if (le16_to_cpu(ta_hdr->header.header_version_major) != 1) 3239 return -EINVAL; 3240 3241 adev->psp.xgmi_context.context.bin_desc.fw_version = 3242 le32_to_cpu(ta_hdr->xgmi.fw_version); 3243 adev->psp.xgmi_context.context.bin_desc.size_bytes = 3244 le32_to_cpu(ta_hdr->xgmi.size_bytes); 3245 adev->psp.xgmi_context.context.bin_desc.start_addr = 3246 (uint8_t *)ta_hdr + 3247 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3248 3249 adev->psp.ras_context.context.bin_desc.fw_version = 3250 le32_to_cpu(ta_hdr->ras.fw_version); 3251 adev->psp.ras_context.context.bin_desc.size_bytes = 3252 le32_to_cpu(ta_hdr->ras.size_bytes); 3253 adev->psp.ras_context.context.bin_desc.start_addr = 3254 (uint8_t *)adev->psp.xgmi_context.context.bin_desc.start_addr + 3255 le32_to_cpu(ta_hdr->ras.offset_bytes); 3256 3257 adev->psp.hdcp_context.context.bin_desc.fw_version = 3258 le32_to_cpu(ta_hdr->hdcp.fw_version); 3259 adev->psp.hdcp_context.context.bin_desc.size_bytes = 3260 le32_to_cpu(ta_hdr->hdcp.size_bytes); 3261 adev->psp.hdcp_context.context.bin_desc.start_addr = 3262 (uint8_t *)ta_hdr + 3263 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3264 3265 adev->psp.dtm_context.context.bin_desc.fw_version = 3266 le32_to_cpu(ta_hdr->dtm.fw_version); 3267 adev->psp.dtm_context.context.bin_desc.size_bytes = 3268 le32_to_cpu(ta_hdr->dtm.size_bytes); 3269 adev->psp.dtm_context.context.bin_desc.start_addr = 3270 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + 3271 le32_to_cpu(ta_hdr->dtm.offset_bytes); 3272 3273 adev->psp.securedisplay_context.context.bin_desc.fw_version = 3274 le32_to_cpu(ta_hdr->securedisplay.fw_version); 3275 adev->psp.securedisplay_context.context.bin_desc.size_bytes = 3276 le32_to_cpu(ta_hdr->securedisplay.size_bytes); 3277 adev->psp.securedisplay_context.context.bin_desc.start_addr = 3278 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + 3279 le32_to_cpu(ta_hdr->securedisplay.offset_bytes); 3280 3281 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); 3282 3283 return 0; 3284 } 3285 3286 static int parse_ta_v2_microcode(struct psp_context *psp) 3287 { 3288 const struct ta_firmware_header_v2_0 *ta_hdr; 3289 struct amdgpu_device *adev = psp->adev; 3290 int err = 0; 3291 int ta_index = 0; 3292 3293 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 3294 3295 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) 3296 return -EINVAL; 3297 3298 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3299 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 3300 return -EINVAL; 3301 } 3302 3303 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 3304 err = parse_ta_bin_descriptor(psp, 3305 &ta_hdr->ta_fw_bin[ta_index], 3306 ta_hdr); 3307 if (err) 3308 return err; 3309 } 3310 3311 return 0; 3312 } 3313 3314 int psp_init_ta_microcode(struct psp_context *psp, const char *chip_name) 3315 { 3316 const struct common_firmware_header *hdr; 3317 struct amdgpu_device *adev = psp->adev; 3318 char fw_name[PSP_FW_NAME_LEN]; 3319 int err; 3320 3321 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 3322 err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, fw_name); 3323 if (err) 3324 return err; 3325 3326 hdr = (const struct common_firmware_header *)adev->psp.ta_fw->data; 3327 switch (le16_to_cpu(hdr->header_version_major)) { 3328 case 1: 3329 err = parse_ta_v1_microcode(psp); 3330 break; 3331 case 2: 3332 err = parse_ta_v2_microcode(psp); 3333 break; 3334 default: 3335 dev_err(adev->dev, "unsupported TA header version\n"); 3336 err = -EINVAL; 3337 } 3338 3339 if (err) 3340 amdgpu_ucode_release(&adev->psp.ta_fw); 3341 3342 return err; 3343 } 3344 3345 int psp_init_cap_microcode(struct psp_context *psp, const char *chip_name) 3346 { 3347 struct amdgpu_device *adev = psp->adev; 3348 char fw_name[PSP_FW_NAME_LEN]; 3349 const struct psp_firmware_header_v1_0 *cap_hdr_v1_0; 3350 struct amdgpu_firmware_info *info = NULL; 3351 int err = 0; 3352 3353 if (!amdgpu_sriov_vf(adev)) { 3354 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n"); 3355 return -EINVAL; 3356 } 3357 3358 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_cap.bin", chip_name); 3359 err = amdgpu_ucode_request(adev, &adev->psp.cap_fw, fw_name); 3360 if (err) { 3361 if (err == -ENODEV) { 3362 dev_warn(adev->dev, "cap microcode does not exist, skip\n"); 3363 err = 0; 3364 goto out; 3365 } 3366 dev_err(adev->dev, "fail to initialize cap microcode\n"); 3367 } 3368 3369 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP]; 3370 info->ucode_id = AMDGPU_UCODE_ID_CAP; 3371 info->fw = adev->psp.cap_fw; 3372 cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *) 3373 adev->psp.cap_fw->data; 3374 adev->firmware.fw_size += ALIGN( 3375 le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE); 3376 adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version); 3377 adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version); 3378 adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes); 3379 3380 return 0; 3381 3382 out: 3383 amdgpu_ucode_release(&adev->psp.cap_fw); 3384 return err; 3385 } 3386 3387 static int psp_set_clockgating_state(void *handle, 3388 enum amd_clockgating_state state) 3389 { 3390 return 0; 3391 } 3392 3393 static int psp_set_powergating_state(void *handle, 3394 enum amd_powergating_state state) 3395 { 3396 return 0; 3397 } 3398 3399 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 3400 struct device_attribute *attr, 3401 char *buf) 3402 { 3403 struct drm_device *ddev = dev_get_drvdata(dev); 3404 struct amdgpu_device *adev = drm_to_adev(ddev); 3405 uint32_t fw_ver; 3406 int ret; 3407 3408 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3409 DRM_INFO("PSP block is not ready yet."); 3410 return -EBUSY; 3411 } 3412 3413 mutex_lock(&adev->psp.mutex); 3414 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 3415 mutex_unlock(&adev->psp.mutex); 3416 3417 if (ret) { 3418 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret); 3419 return ret; 3420 } 3421 3422 return sysfs_emit(buf, "%x\n", fw_ver); 3423 } 3424 3425 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 3426 struct device_attribute *attr, 3427 const char *buf, 3428 size_t count) 3429 { 3430 struct drm_device *ddev = dev_get_drvdata(dev); 3431 struct amdgpu_device *adev = drm_to_adev(ddev); 3432 int ret, idx; 3433 char fw_name[100]; 3434 const struct firmware *usbc_pd_fw; 3435 struct amdgpu_bo *fw_buf_bo = NULL; 3436 uint64_t fw_pri_mc_addr; 3437 void *fw_pri_cpu_addr; 3438 3439 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3440 DRM_INFO("PSP block is not ready yet."); 3441 return -EBUSY; 3442 } 3443 3444 if (!drm_dev_enter(ddev, &idx)) 3445 return -ENODEV; 3446 3447 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf); 3448 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev); 3449 if (ret) 3450 goto fail; 3451 3452 /* LFB address which is aligned to 1MB boundary per PSP request */ 3453 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000, 3454 AMDGPU_GEM_DOMAIN_VRAM | 3455 AMDGPU_GEM_DOMAIN_GTT, 3456 &fw_buf_bo, &fw_pri_mc_addr, 3457 &fw_pri_cpu_addr); 3458 if (ret) 3459 goto rel_buf; 3460 3461 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 3462 3463 mutex_lock(&adev->psp.mutex); 3464 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr); 3465 mutex_unlock(&adev->psp.mutex); 3466 3467 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3468 3469 rel_buf: 3470 release_firmware(usbc_pd_fw); 3471 fail: 3472 if (ret) { 3473 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret); 3474 count = ret; 3475 } 3476 3477 drm_dev_exit(idx); 3478 return count; 3479 } 3480 3481 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) 3482 { 3483 int idx; 3484 3485 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 3486 return; 3487 3488 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 3489 memcpy(psp->fw_pri_buf, start_addr, bin_size); 3490 3491 drm_dev_exit(idx); 3492 } 3493 3494 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR, 3495 psp_usbc_pd_fw_sysfs_read, 3496 psp_usbc_pd_fw_sysfs_write); 3497 3498 int is_psp_fw_valid(struct psp_bin_desc bin) 3499 { 3500 return bin.size_bytes; 3501 } 3502 3503 static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj, 3504 struct bin_attribute *bin_attr, 3505 char *buffer, loff_t pos, size_t count) 3506 { 3507 struct device *dev = kobj_to_dev(kobj); 3508 struct drm_device *ddev = dev_get_drvdata(dev); 3509 struct amdgpu_device *adev = drm_to_adev(ddev); 3510 3511 adev->psp.vbflash_done = false; 3512 3513 /* Safeguard against memory drain */ 3514 if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) { 3515 dev_err(adev->dev, "File size cannot exceed %u", AMD_VBIOS_FILE_MAX_SIZE_B); 3516 kvfree(adev->psp.vbflash_tmp_buf); 3517 adev->psp.vbflash_tmp_buf = NULL; 3518 adev->psp.vbflash_image_size = 0; 3519 return -ENOMEM; 3520 } 3521 3522 /* TODO Just allocate max for now and optimize to realloc later if needed */ 3523 if (!adev->psp.vbflash_tmp_buf) { 3524 adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL); 3525 if (!adev->psp.vbflash_tmp_buf) 3526 return -ENOMEM; 3527 } 3528 3529 mutex_lock(&adev->psp.mutex); 3530 memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count); 3531 adev->psp.vbflash_image_size += count; 3532 mutex_unlock(&adev->psp.mutex); 3533 3534 dev_info(adev->dev, "VBIOS flash write PSP done"); 3535 3536 return count; 3537 } 3538 3539 static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj, 3540 struct bin_attribute *bin_attr, char *buffer, 3541 loff_t pos, size_t count) 3542 { 3543 struct device *dev = kobj_to_dev(kobj); 3544 struct drm_device *ddev = dev_get_drvdata(dev); 3545 struct amdgpu_device *adev = drm_to_adev(ddev); 3546 struct amdgpu_bo *fw_buf_bo = NULL; 3547 uint64_t fw_pri_mc_addr; 3548 void *fw_pri_cpu_addr; 3549 int ret; 3550 3551 dev_info(adev->dev, "VBIOS flash to PSP started"); 3552 3553 ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size, 3554 AMDGPU_GPU_PAGE_SIZE, 3555 AMDGPU_GEM_DOMAIN_VRAM, 3556 &fw_buf_bo, 3557 &fw_pri_mc_addr, 3558 &fw_pri_cpu_addr); 3559 if (ret) 3560 goto rel_buf; 3561 3562 memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size); 3563 3564 mutex_lock(&adev->psp.mutex); 3565 ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr); 3566 mutex_unlock(&adev->psp.mutex); 3567 3568 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3569 3570 rel_buf: 3571 kvfree(adev->psp.vbflash_tmp_buf); 3572 adev->psp.vbflash_tmp_buf = NULL; 3573 adev->psp.vbflash_image_size = 0; 3574 3575 if (ret) { 3576 dev_err(adev->dev, "Failed to load VBIOS FW, err = %d", ret); 3577 return ret; 3578 } 3579 3580 dev_info(adev->dev, "VBIOS flash to PSP done"); 3581 return 0; 3582 } 3583 3584 static ssize_t amdgpu_psp_vbflash_status(struct device *dev, 3585 struct device_attribute *attr, 3586 char *buf) 3587 { 3588 struct drm_device *ddev = dev_get_drvdata(dev); 3589 struct amdgpu_device *adev = drm_to_adev(ddev); 3590 uint32_t vbflash_status; 3591 3592 vbflash_status = psp_vbflash_status(&adev->psp); 3593 if (!adev->psp.vbflash_done) 3594 vbflash_status = 0; 3595 else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000)) 3596 vbflash_status = 1; 3597 3598 return sysfs_emit(buf, "0x%x\n", vbflash_status); 3599 } 3600 3601 static const struct bin_attribute psp_vbflash_bin_attr = { 3602 .attr = {.name = "psp_vbflash", .mode = 0664}, 3603 .size = 0, 3604 .write = amdgpu_psp_vbflash_write, 3605 .read = amdgpu_psp_vbflash_read, 3606 }; 3607 3608 static DEVICE_ATTR(psp_vbflash_status, 0444, amdgpu_psp_vbflash_status, NULL); 3609 3610 int amdgpu_psp_sysfs_init(struct amdgpu_device *adev) 3611 { 3612 int ret = 0; 3613 struct psp_context *psp = &adev->psp; 3614 3615 if (amdgpu_sriov_vf(adev)) 3616 return -EINVAL; 3617 3618 switch (adev->ip_versions[MP0_HWIP][0]) { 3619 case IP_VERSION(13, 0, 0): 3620 case IP_VERSION(13, 0, 7): 3621 if (!psp->adev) { 3622 psp->adev = adev; 3623 psp_v13_0_set_psp_funcs(psp); 3624 } 3625 ret = sysfs_create_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr); 3626 if (ret) 3627 dev_err(adev->dev, "Failed to create device file psp_vbflash"); 3628 ret = device_create_file(adev->dev, &dev_attr_psp_vbflash_status); 3629 if (ret) 3630 dev_err(adev->dev, "Failed to create device file psp_vbflash_status"); 3631 return ret; 3632 default: 3633 return 0; 3634 } 3635 } 3636 3637 const struct amd_ip_funcs psp_ip_funcs = { 3638 .name = "psp", 3639 .early_init = psp_early_init, 3640 .late_init = NULL, 3641 .sw_init = psp_sw_init, 3642 .sw_fini = psp_sw_fini, 3643 .hw_init = psp_hw_init, 3644 .hw_fini = psp_hw_fini, 3645 .suspend = psp_suspend, 3646 .resume = psp_resume, 3647 .is_idle = NULL, 3648 .check_soft_reset = NULL, 3649 .wait_for_idle = NULL, 3650 .soft_reset = NULL, 3651 .set_clockgating_state = psp_set_clockgating_state, 3652 .set_powergating_state = psp_set_powergating_state, 3653 }; 3654 3655 static int psp_sysfs_init(struct amdgpu_device *adev) 3656 { 3657 int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw); 3658 3659 if (ret) 3660 DRM_ERROR("Failed to create USBC PD FW control file!"); 3661 3662 return ret; 3663 } 3664 3665 void amdgpu_psp_sysfs_fini(struct amdgpu_device *adev) 3666 { 3667 sysfs_remove_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr); 3668 device_remove_file(adev->dev, &dev_attr_psp_vbflash_status); 3669 } 3670 3671 static void psp_sysfs_fini(struct amdgpu_device *adev) 3672 { 3673 device_remove_file(adev->dev, &dev_attr_usbc_pd_fw); 3674 } 3675 3676 const struct amdgpu_ip_block_version psp_v3_1_ip_block = 3677 { 3678 .type = AMD_IP_BLOCK_TYPE_PSP, 3679 .major = 3, 3680 .minor = 1, 3681 .rev = 0, 3682 .funcs = &psp_ip_funcs, 3683 }; 3684 3685 const struct amdgpu_ip_block_version psp_v10_0_ip_block = 3686 { 3687 .type = AMD_IP_BLOCK_TYPE_PSP, 3688 .major = 10, 3689 .minor = 0, 3690 .rev = 0, 3691 .funcs = &psp_ip_funcs, 3692 }; 3693 3694 const struct amdgpu_ip_block_version psp_v11_0_ip_block = 3695 { 3696 .type = AMD_IP_BLOCK_TYPE_PSP, 3697 .major = 11, 3698 .minor = 0, 3699 .rev = 0, 3700 .funcs = &psp_ip_funcs, 3701 }; 3702 3703 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = { 3704 .type = AMD_IP_BLOCK_TYPE_PSP, 3705 .major = 11, 3706 .minor = 0, 3707 .rev = 8, 3708 .funcs = &psp_ip_funcs, 3709 }; 3710 3711 const struct amdgpu_ip_block_version psp_v12_0_ip_block = 3712 { 3713 .type = AMD_IP_BLOCK_TYPE_PSP, 3714 .major = 12, 3715 .minor = 0, 3716 .rev = 0, 3717 .funcs = &psp_ip_funcs, 3718 }; 3719 3720 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 3721 .type = AMD_IP_BLOCK_TYPE_PSP, 3722 .major = 13, 3723 .minor = 0, 3724 .rev = 0, 3725 .funcs = &psp_ip_funcs, 3726 }; 3727 3728 const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = { 3729 .type = AMD_IP_BLOCK_TYPE_PSP, 3730 .major = 13, 3731 .minor = 0, 3732 .rev = 4, 3733 .funcs = &psp_ip_funcs, 3734 }; 3735