1 /* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Christian König <deathsimple@vodafone.de> 29 */ 30 31 #include <linux/firmware.h> 32 #include <linux/module.h> 33 34 #include <drm/drm.h> 35 36 #include "amdgpu.h" 37 #include "amdgpu_pm.h" 38 #include "amdgpu_uvd.h" 39 #include "cikd.h" 40 #include "uvd/uvd_4_2_d.h" 41 42 #include "amdgpu_ras.h" 43 44 /* 1 second timeout */ 45 #define UVD_IDLE_TIMEOUT msecs_to_jiffies(1000) 46 47 /* Firmware versions for VI */ 48 #define FW_1_65_10 ((1 << 24) | (65 << 16) | (10 << 8)) 49 #define FW_1_87_11 ((1 << 24) | (87 << 16) | (11 << 8)) 50 #define FW_1_87_12 ((1 << 24) | (87 << 16) | (12 << 8)) 51 #define FW_1_37_15 ((1 << 24) | (37 << 16) | (15 << 8)) 52 53 /* Polaris10/11 firmware version */ 54 #define FW_1_66_16 ((1 << 24) | (66 << 16) | (16 << 8)) 55 56 /* Firmware Names */ 57 #ifdef CONFIG_DRM_AMDGPU_CIK 58 #define FIRMWARE_BONAIRE "amdgpu/bonaire_uvd.bin" 59 #define FIRMWARE_KABINI "amdgpu/kabini_uvd.bin" 60 #define FIRMWARE_KAVERI "amdgpu/kaveri_uvd.bin" 61 #define FIRMWARE_HAWAII "amdgpu/hawaii_uvd.bin" 62 #define FIRMWARE_MULLINS "amdgpu/mullins_uvd.bin" 63 #endif 64 #define FIRMWARE_TONGA "amdgpu/tonga_uvd.bin" 65 #define FIRMWARE_CARRIZO "amdgpu/carrizo_uvd.bin" 66 #define FIRMWARE_FIJI "amdgpu/fiji_uvd.bin" 67 #define FIRMWARE_STONEY "amdgpu/stoney_uvd.bin" 68 #define FIRMWARE_POLARIS10 "amdgpu/polaris10_uvd.bin" 69 #define FIRMWARE_POLARIS11 "amdgpu/polaris11_uvd.bin" 70 #define FIRMWARE_POLARIS12 "amdgpu/polaris12_uvd.bin" 71 #define FIRMWARE_VEGAM "amdgpu/vegam_uvd.bin" 72 73 #define FIRMWARE_VEGA10 "amdgpu/vega10_uvd.bin" 74 #define FIRMWARE_VEGA12 "amdgpu/vega12_uvd.bin" 75 #define FIRMWARE_VEGA20 "amdgpu/vega20_uvd.bin" 76 77 /* These are common relative offsets for all asics, from uvd_7_0_offset.h, */ 78 #define UVD_GPCOM_VCPU_CMD 0x03c3 79 #define UVD_GPCOM_VCPU_DATA0 0x03c4 80 #define UVD_GPCOM_VCPU_DATA1 0x03c5 81 #define UVD_NO_OP 0x03ff 82 #define UVD_BASE_SI 0x3800 83 84 /** 85 * amdgpu_uvd_cs_ctx - Command submission parser context 86 * 87 * Used for emulating virtual memory support on UVD 4.2. 88 */ 89 struct amdgpu_uvd_cs_ctx { 90 struct amdgpu_cs_parser *parser; 91 unsigned reg, count; 92 unsigned data0, data1; 93 unsigned idx; 94 unsigned ib_idx; 95 96 /* does the IB has a msg command */ 97 bool has_msg_cmd; 98 99 /* minimum buffer sizes */ 100 unsigned *buf_sizes; 101 }; 102 103 #ifdef CONFIG_DRM_AMDGPU_CIK 104 MODULE_FIRMWARE(FIRMWARE_BONAIRE); 105 MODULE_FIRMWARE(FIRMWARE_KABINI); 106 MODULE_FIRMWARE(FIRMWARE_KAVERI); 107 MODULE_FIRMWARE(FIRMWARE_HAWAII); 108 MODULE_FIRMWARE(FIRMWARE_MULLINS); 109 #endif 110 MODULE_FIRMWARE(FIRMWARE_TONGA); 111 MODULE_FIRMWARE(FIRMWARE_CARRIZO); 112 MODULE_FIRMWARE(FIRMWARE_FIJI); 113 MODULE_FIRMWARE(FIRMWARE_STONEY); 114 MODULE_FIRMWARE(FIRMWARE_POLARIS10); 115 MODULE_FIRMWARE(FIRMWARE_POLARIS11); 116 MODULE_FIRMWARE(FIRMWARE_POLARIS12); 117 MODULE_FIRMWARE(FIRMWARE_VEGAM); 118 119 MODULE_FIRMWARE(FIRMWARE_VEGA10); 120 MODULE_FIRMWARE(FIRMWARE_VEGA12); 121 MODULE_FIRMWARE(FIRMWARE_VEGA20); 122 123 static void amdgpu_uvd_idle_work_handler(struct work_struct *work); 124 125 int amdgpu_uvd_sw_init(struct amdgpu_device *adev) 126 { 127 unsigned long bo_size; 128 const char *fw_name; 129 const struct common_firmware_header *hdr; 130 unsigned family_id; 131 int i, j, r; 132 133 INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler); 134 135 switch (adev->asic_type) { 136 #ifdef CONFIG_DRM_AMDGPU_CIK 137 case CHIP_BONAIRE: 138 fw_name = FIRMWARE_BONAIRE; 139 break; 140 case CHIP_KABINI: 141 fw_name = FIRMWARE_KABINI; 142 break; 143 case CHIP_KAVERI: 144 fw_name = FIRMWARE_KAVERI; 145 break; 146 case CHIP_HAWAII: 147 fw_name = FIRMWARE_HAWAII; 148 break; 149 case CHIP_MULLINS: 150 fw_name = FIRMWARE_MULLINS; 151 break; 152 #endif 153 case CHIP_TONGA: 154 fw_name = FIRMWARE_TONGA; 155 break; 156 case CHIP_FIJI: 157 fw_name = FIRMWARE_FIJI; 158 break; 159 case CHIP_CARRIZO: 160 fw_name = FIRMWARE_CARRIZO; 161 break; 162 case CHIP_STONEY: 163 fw_name = FIRMWARE_STONEY; 164 break; 165 case CHIP_POLARIS10: 166 fw_name = FIRMWARE_POLARIS10; 167 break; 168 case CHIP_POLARIS11: 169 fw_name = FIRMWARE_POLARIS11; 170 break; 171 case CHIP_POLARIS12: 172 fw_name = FIRMWARE_POLARIS12; 173 break; 174 case CHIP_VEGA10: 175 fw_name = FIRMWARE_VEGA10; 176 break; 177 case CHIP_VEGA12: 178 fw_name = FIRMWARE_VEGA12; 179 break; 180 case CHIP_VEGAM: 181 fw_name = FIRMWARE_VEGAM; 182 break; 183 case CHIP_VEGA20: 184 fw_name = FIRMWARE_VEGA20; 185 break; 186 default: 187 return -EINVAL; 188 } 189 190 r = request_firmware(&adev->uvd.fw, fw_name, adev->dev); 191 if (r) { 192 dev_err(adev->dev, "amdgpu_uvd: Can't load firmware \"%s\"\n", 193 fw_name); 194 return r; 195 } 196 197 r = amdgpu_ucode_validate(adev->uvd.fw); 198 if (r) { 199 dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n", 200 fw_name); 201 release_firmware(adev->uvd.fw); 202 adev->uvd.fw = NULL; 203 return r; 204 } 205 206 /* Set the default UVD handles that the firmware can handle */ 207 adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES; 208 209 hdr = (const struct common_firmware_header *)adev->uvd.fw->data; 210 family_id = le32_to_cpu(hdr->ucode_version) & 0xff; 211 212 if (adev->asic_type < CHIP_VEGA20) { 213 unsigned version_major, version_minor; 214 215 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; 216 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 217 DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n", 218 version_major, version_minor, family_id); 219 220 /* 221 * Limit the number of UVD handles depending on microcode major 222 * and minor versions. The firmware version which has 40 UVD 223 * instances support is 1.80. So all subsequent versions should 224 * also have the same support. 225 */ 226 if ((version_major > 0x01) || 227 ((version_major == 0x01) && (version_minor >= 0x50))) 228 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES; 229 230 adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) | 231 (family_id << 8)); 232 233 if ((adev->asic_type == CHIP_POLARIS10 || 234 adev->asic_type == CHIP_POLARIS11) && 235 (adev->uvd.fw_version < FW_1_66_16)) 236 DRM_ERROR("POLARIS10/11 UVD firmware version %hu.%hu is too old.\n", 237 version_major, version_minor); 238 } else { 239 unsigned int enc_major, enc_minor, dec_minor; 240 241 dec_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 242 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 24) & 0x3f; 243 enc_major = (le32_to_cpu(hdr->ucode_version) >> 30) & 0x3; 244 DRM_INFO("Found UVD firmware ENC: %hu.%hu DEC: .%hu Family ID: %hu\n", 245 enc_major, enc_minor, dec_minor, family_id); 246 247 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES; 248 249 adev->uvd.fw_version = le32_to_cpu(hdr->ucode_version); 250 } 251 252 bo_size = AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE 253 + AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles; 254 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 255 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 256 257 for (j = 0; j < adev->uvd.num_uvd_inst; j++) { 258 if (adev->uvd.harvest_config & (1 << j)) 259 continue; 260 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, 261 AMDGPU_GEM_DOMAIN_VRAM, &adev->uvd.inst[j].vcpu_bo, 262 &adev->uvd.inst[j].gpu_addr, &adev->uvd.inst[j].cpu_addr); 263 if (r) { 264 dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r); 265 return r; 266 } 267 } 268 269 for (i = 0; i < adev->uvd.max_handles; ++i) { 270 atomic_set(&adev->uvd.handles[i], 0); 271 adev->uvd.filp[i] = NULL; 272 } 273 274 /* from uvd v5.0 HW addressing capacity increased to 64 bits */ 275 if (!amdgpu_device_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0)) 276 adev->uvd.address_64_bit = true; 277 278 switch (adev->asic_type) { 279 case CHIP_TONGA: 280 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_65_10; 281 break; 282 case CHIP_CARRIZO: 283 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_11; 284 break; 285 case CHIP_FIJI: 286 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_12; 287 break; 288 case CHIP_STONEY: 289 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_37_15; 290 break; 291 default: 292 adev->uvd.use_ctx_buf = adev->asic_type >= CHIP_POLARIS10; 293 } 294 295 return 0; 296 } 297 298 int amdgpu_uvd_sw_fini(struct amdgpu_device *adev) 299 { 300 int i, j; 301 302 cancel_delayed_work_sync(&adev->uvd.idle_work); 303 drm_sched_entity_destroy(&adev->uvd.entity); 304 305 for (j = 0; j < adev->uvd.num_uvd_inst; ++j) { 306 if (adev->uvd.harvest_config & (1 << j)) 307 continue; 308 kvfree(adev->uvd.inst[j].saved_bo); 309 310 amdgpu_bo_free_kernel(&adev->uvd.inst[j].vcpu_bo, 311 &adev->uvd.inst[j].gpu_addr, 312 (void **)&adev->uvd.inst[j].cpu_addr); 313 314 amdgpu_ring_fini(&adev->uvd.inst[j].ring); 315 316 for (i = 0; i < AMDGPU_MAX_UVD_ENC_RINGS; ++i) 317 amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]); 318 } 319 release_firmware(adev->uvd.fw); 320 321 return 0; 322 } 323 324 /** 325 * amdgpu_uvd_entity_init - init entity 326 * 327 * @adev: amdgpu_device pointer 328 * 329 */ 330 int amdgpu_uvd_entity_init(struct amdgpu_device *adev) 331 { 332 struct amdgpu_ring *ring; 333 struct drm_sched_rq *rq; 334 int r; 335 336 ring = &adev->uvd.inst[0].ring; 337 rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL]; 338 r = drm_sched_entity_init(&adev->uvd.entity, &rq, 1, NULL); 339 if (r) { 340 DRM_ERROR("Failed setting up UVD kernel entity.\n"); 341 return r; 342 } 343 344 return 0; 345 } 346 347 int amdgpu_uvd_suspend(struct amdgpu_device *adev) 348 { 349 unsigned size; 350 void *ptr; 351 int i, j; 352 353 cancel_delayed_work_sync(&adev->uvd.idle_work); 354 355 /* only valid for physical mode */ 356 if (adev->asic_type < CHIP_POLARIS10) { 357 for (i = 0; i < adev->uvd.max_handles; ++i) 358 if (atomic_read(&adev->uvd.handles[i])) 359 break; 360 361 if (i == adev->uvd.max_handles) 362 return 0; 363 } 364 365 for (j = 0; j < adev->uvd.num_uvd_inst; ++j) { 366 if (adev->uvd.harvest_config & (1 << j)) 367 continue; 368 if (adev->uvd.inst[j].vcpu_bo == NULL) 369 continue; 370 371 size = amdgpu_bo_size(adev->uvd.inst[j].vcpu_bo); 372 ptr = adev->uvd.inst[j].cpu_addr; 373 374 adev->uvd.inst[j].saved_bo = kvmalloc(size, GFP_KERNEL); 375 if (!adev->uvd.inst[j].saved_bo) 376 return -ENOMEM; 377 378 /* re-write 0 since err_event_athub will corrupt VCPU buffer */ 379 if (amdgpu_ras_intr_triggered()) { 380 DRM_WARN("UVD VCPU state may lost due to RAS ERREVENT_ATHUB_INTERRUPT\n"); 381 memset(adev->uvd.inst[j].saved_bo, 0, size); 382 } else { 383 memcpy_fromio(adev->uvd.inst[j].saved_bo, ptr, size); 384 } 385 } 386 return 0; 387 } 388 389 int amdgpu_uvd_resume(struct amdgpu_device *adev) 390 { 391 unsigned size; 392 void *ptr; 393 int i; 394 395 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 396 if (adev->uvd.harvest_config & (1 << i)) 397 continue; 398 if (adev->uvd.inst[i].vcpu_bo == NULL) 399 return -EINVAL; 400 401 size = amdgpu_bo_size(adev->uvd.inst[i].vcpu_bo); 402 ptr = adev->uvd.inst[i].cpu_addr; 403 404 if (adev->uvd.inst[i].saved_bo != NULL) { 405 memcpy_toio(ptr, adev->uvd.inst[i].saved_bo, size); 406 kvfree(adev->uvd.inst[i].saved_bo); 407 adev->uvd.inst[i].saved_bo = NULL; 408 } else { 409 const struct common_firmware_header *hdr; 410 unsigned offset; 411 412 hdr = (const struct common_firmware_header *)adev->uvd.fw->data; 413 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 414 offset = le32_to_cpu(hdr->ucode_array_offset_bytes); 415 memcpy_toio(adev->uvd.inst[i].cpu_addr, adev->uvd.fw->data + offset, 416 le32_to_cpu(hdr->ucode_size_bytes)); 417 size -= le32_to_cpu(hdr->ucode_size_bytes); 418 ptr += le32_to_cpu(hdr->ucode_size_bytes); 419 } 420 memset_io(ptr, 0, size); 421 /* to restore uvd fence seq */ 422 amdgpu_fence_driver_force_completion(&adev->uvd.inst[i].ring); 423 } 424 } 425 return 0; 426 } 427 428 void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp) 429 { 430 struct amdgpu_ring *ring = &adev->uvd.inst[0].ring; 431 int i, r; 432 433 for (i = 0; i < adev->uvd.max_handles; ++i) { 434 uint32_t handle = atomic_read(&adev->uvd.handles[i]); 435 436 if (handle != 0 && adev->uvd.filp[i] == filp) { 437 struct dma_fence *fence; 438 439 r = amdgpu_uvd_get_destroy_msg(ring, handle, false, 440 &fence); 441 if (r) { 442 DRM_ERROR("Error destroying UVD %d!\n", r); 443 continue; 444 } 445 446 dma_fence_wait(fence, false); 447 dma_fence_put(fence); 448 449 adev->uvd.filp[i] = NULL; 450 atomic_set(&adev->uvd.handles[i], 0); 451 } 452 } 453 } 454 455 static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo) 456 { 457 int i; 458 for (i = 0; i < abo->placement.num_placement; ++i) { 459 abo->placements[i].fpfn = 0 >> PAGE_SHIFT; 460 abo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT; 461 } 462 } 463 464 static u64 amdgpu_uvd_get_addr_from_ctx(struct amdgpu_uvd_cs_ctx *ctx) 465 { 466 uint32_t lo, hi; 467 uint64_t addr; 468 469 lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0); 470 hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1); 471 addr = ((uint64_t)lo) | (((uint64_t)hi) << 32); 472 473 return addr; 474 } 475 476 /** 477 * amdgpu_uvd_cs_pass1 - first parsing round 478 * 479 * @ctx: UVD parser context 480 * 481 * Make sure UVD message and feedback buffers are in VRAM and 482 * nobody is violating an 256MB boundary. 483 */ 484 static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx) 485 { 486 struct ttm_operation_ctx tctx = { false, false }; 487 struct amdgpu_bo_va_mapping *mapping; 488 struct amdgpu_bo *bo; 489 uint32_t cmd; 490 uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx); 491 int r = 0; 492 493 r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping); 494 if (r) { 495 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); 496 return r; 497 } 498 499 if (!ctx->parser->adev->uvd.address_64_bit) { 500 /* check if it's a message or feedback command */ 501 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1; 502 if (cmd == 0x0 || cmd == 0x3) { 503 /* yes, force it into VRAM */ 504 uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM; 505 amdgpu_bo_placement_from_domain(bo, domain); 506 } 507 amdgpu_uvd_force_into_uvd_segment(bo); 508 509 r = ttm_bo_validate(&bo->tbo, &bo->placement, &tctx); 510 } 511 512 return r; 513 } 514 515 /** 516 * amdgpu_uvd_cs_msg_decode - handle UVD decode message 517 * 518 * @msg: pointer to message structure 519 * @buf_sizes: returned buffer sizes 520 * 521 * Peek into the decode message and calculate the necessary buffer sizes. 522 */ 523 static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device *adev, uint32_t *msg, 524 unsigned buf_sizes[]) 525 { 526 unsigned stream_type = msg[4]; 527 unsigned width = msg[6]; 528 unsigned height = msg[7]; 529 unsigned dpb_size = msg[9]; 530 unsigned pitch = msg[28]; 531 unsigned level = msg[57]; 532 533 unsigned width_in_mb = width / 16; 534 unsigned height_in_mb = ALIGN(height / 16, 2); 535 unsigned fs_in_mb = width_in_mb * height_in_mb; 536 537 unsigned image_size, tmp, min_dpb_size, num_dpb_buffer; 538 unsigned min_ctx_size = ~0; 539 540 image_size = width * height; 541 image_size += image_size / 2; 542 image_size = ALIGN(image_size, 1024); 543 544 switch (stream_type) { 545 case 0: /* H264 */ 546 switch(level) { 547 case 30: 548 num_dpb_buffer = 8100 / fs_in_mb; 549 break; 550 case 31: 551 num_dpb_buffer = 18000 / fs_in_mb; 552 break; 553 case 32: 554 num_dpb_buffer = 20480 / fs_in_mb; 555 break; 556 case 41: 557 num_dpb_buffer = 32768 / fs_in_mb; 558 break; 559 case 42: 560 num_dpb_buffer = 34816 / fs_in_mb; 561 break; 562 case 50: 563 num_dpb_buffer = 110400 / fs_in_mb; 564 break; 565 case 51: 566 num_dpb_buffer = 184320 / fs_in_mb; 567 break; 568 default: 569 num_dpb_buffer = 184320 / fs_in_mb; 570 break; 571 } 572 num_dpb_buffer++; 573 if (num_dpb_buffer > 17) 574 num_dpb_buffer = 17; 575 576 /* reference picture buffer */ 577 min_dpb_size = image_size * num_dpb_buffer; 578 579 /* macroblock context buffer */ 580 min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192; 581 582 /* IT surface buffer */ 583 min_dpb_size += width_in_mb * height_in_mb * 32; 584 break; 585 586 case 1: /* VC1 */ 587 588 /* reference picture buffer */ 589 min_dpb_size = image_size * 3; 590 591 /* CONTEXT_BUFFER */ 592 min_dpb_size += width_in_mb * height_in_mb * 128; 593 594 /* IT surface buffer */ 595 min_dpb_size += width_in_mb * 64; 596 597 /* DB surface buffer */ 598 min_dpb_size += width_in_mb * 128; 599 600 /* BP */ 601 tmp = max(width_in_mb, height_in_mb); 602 min_dpb_size += ALIGN(tmp * 7 * 16, 64); 603 break; 604 605 case 3: /* MPEG2 */ 606 607 /* reference picture buffer */ 608 min_dpb_size = image_size * 3; 609 break; 610 611 case 4: /* MPEG4 */ 612 613 /* reference picture buffer */ 614 min_dpb_size = image_size * 3; 615 616 /* CM */ 617 min_dpb_size += width_in_mb * height_in_mb * 64; 618 619 /* IT surface buffer */ 620 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64); 621 break; 622 623 case 7: /* H264 Perf */ 624 switch(level) { 625 case 30: 626 num_dpb_buffer = 8100 / fs_in_mb; 627 break; 628 case 31: 629 num_dpb_buffer = 18000 / fs_in_mb; 630 break; 631 case 32: 632 num_dpb_buffer = 20480 / fs_in_mb; 633 break; 634 case 41: 635 num_dpb_buffer = 32768 / fs_in_mb; 636 break; 637 case 42: 638 num_dpb_buffer = 34816 / fs_in_mb; 639 break; 640 case 50: 641 num_dpb_buffer = 110400 / fs_in_mb; 642 break; 643 case 51: 644 num_dpb_buffer = 184320 / fs_in_mb; 645 break; 646 default: 647 num_dpb_buffer = 184320 / fs_in_mb; 648 break; 649 } 650 num_dpb_buffer++; 651 if (num_dpb_buffer > 17) 652 num_dpb_buffer = 17; 653 654 /* reference picture buffer */ 655 min_dpb_size = image_size * num_dpb_buffer; 656 657 if (!adev->uvd.use_ctx_buf){ 658 /* macroblock context buffer */ 659 min_dpb_size += 660 width_in_mb * height_in_mb * num_dpb_buffer * 192; 661 662 /* IT surface buffer */ 663 min_dpb_size += width_in_mb * height_in_mb * 32; 664 } else { 665 /* macroblock context buffer */ 666 min_ctx_size = 667 width_in_mb * height_in_mb * num_dpb_buffer * 192; 668 } 669 break; 670 671 case 8: /* MJPEG */ 672 min_dpb_size = 0; 673 break; 674 675 case 16: /* H265 */ 676 image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2; 677 image_size = ALIGN(image_size, 256); 678 679 num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2; 680 min_dpb_size = image_size * num_dpb_buffer; 681 min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16) 682 * 16 * num_dpb_buffer + 52 * 1024; 683 break; 684 685 default: 686 DRM_ERROR("UVD codec not handled %d!\n", stream_type); 687 return -EINVAL; 688 } 689 690 if (width > pitch) { 691 DRM_ERROR("Invalid UVD decoding target pitch!\n"); 692 return -EINVAL; 693 } 694 695 if (dpb_size < min_dpb_size) { 696 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n", 697 dpb_size, min_dpb_size); 698 return -EINVAL; 699 } 700 701 buf_sizes[0x1] = dpb_size; 702 buf_sizes[0x2] = image_size; 703 buf_sizes[0x4] = min_ctx_size; 704 /* store image width to adjust nb memory pstate */ 705 adev->uvd.decode_image_width = width; 706 return 0; 707 } 708 709 /** 710 * amdgpu_uvd_cs_msg - handle UVD message 711 * 712 * @ctx: UVD parser context 713 * @bo: buffer object containing the message 714 * @offset: offset into the buffer object 715 * 716 * Peek into the UVD message and extract the session id. 717 * Make sure that we don't open up to many sessions. 718 */ 719 static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx, 720 struct amdgpu_bo *bo, unsigned offset) 721 { 722 struct amdgpu_device *adev = ctx->parser->adev; 723 int32_t *msg, msg_type, handle; 724 void *ptr; 725 long r; 726 int i; 727 728 if (offset & 0x3F) { 729 DRM_ERROR("UVD messages must be 64 byte aligned!\n"); 730 return -EINVAL; 731 } 732 733 r = amdgpu_bo_kmap(bo, &ptr); 734 if (r) { 735 DRM_ERROR("Failed mapping the UVD) message (%ld)!\n", r); 736 return r; 737 } 738 739 msg = ptr + offset; 740 741 msg_type = msg[1]; 742 handle = msg[2]; 743 744 if (handle == 0) { 745 DRM_ERROR("Invalid UVD handle!\n"); 746 return -EINVAL; 747 } 748 749 switch (msg_type) { 750 case 0: 751 /* it's a create msg, calc image size (width * height) */ 752 amdgpu_bo_kunmap(bo); 753 754 /* try to alloc a new handle */ 755 for (i = 0; i < adev->uvd.max_handles; ++i) { 756 if (atomic_read(&adev->uvd.handles[i]) == handle) { 757 DRM_ERROR(")Handle 0x%x already in use!\n", 758 handle); 759 return -EINVAL; 760 } 761 762 if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) { 763 adev->uvd.filp[i] = ctx->parser->filp; 764 return 0; 765 } 766 } 767 768 DRM_ERROR("No more free UVD handles!\n"); 769 return -ENOSPC; 770 771 case 1: 772 /* it's a decode msg, calc buffer sizes */ 773 r = amdgpu_uvd_cs_msg_decode(adev, msg, ctx->buf_sizes); 774 amdgpu_bo_kunmap(bo); 775 if (r) 776 return r; 777 778 /* validate the handle */ 779 for (i = 0; i < adev->uvd.max_handles; ++i) { 780 if (atomic_read(&adev->uvd.handles[i]) == handle) { 781 if (adev->uvd.filp[i] != ctx->parser->filp) { 782 DRM_ERROR("UVD handle collision detected!\n"); 783 return -EINVAL; 784 } 785 return 0; 786 } 787 } 788 789 DRM_ERROR("Invalid UVD handle 0x%x!\n", handle); 790 return -ENOENT; 791 792 case 2: 793 /* it's a destroy msg, free the handle */ 794 for (i = 0; i < adev->uvd.max_handles; ++i) 795 atomic_cmpxchg(&adev->uvd.handles[i], handle, 0); 796 amdgpu_bo_kunmap(bo); 797 return 0; 798 799 default: 800 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type); 801 return -EINVAL; 802 } 803 BUG(); 804 return -EINVAL; 805 } 806 807 /** 808 * amdgpu_uvd_cs_pass2 - second parsing round 809 * 810 * @ctx: UVD parser context 811 * 812 * Patch buffer addresses, make sure buffer sizes are correct. 813 */ 814 static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx) 815 { 816 struct amdgpu_bo_va_mapping *mapping; 817 struct amdgpu_bo *bo; 818 uint32_t cmd; 819 uint64_t start, end; 820 uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx); 821 int r; 822 823 r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping); 824 if (r) { 825 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); 826 return r; 827 } 828 829 start = amdgpu_bo_gpu_offset(bo); 830 831 end = (mapping->last + 1 - mapping->start); 832 end = end * AMDGPU_GPU_PAGE_SIZE + start; 833 834 addr -= mapping->start * AMDGPU_GPU_PAGE_SIZE; 835 start += addr; 836 837 amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data0, 838 lower_32_bits(start)); 839 amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data1, 840 upper_32_bits(start)); 841 842 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1; 843 if (cmd < 0x4) { 844 if ((end - start) < ctx->buf_sizes[cmd]) { 845 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, 846 (unsigned)(end - start), 847 ctx->buf_sizes[cmd]); 848 return -EINVAL; 849 } 850 851 } else if (cmd == 0x206) { 852 if ((end - start) < ctx->buf_sizes[4]) { 853 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, 854 (unsigned)(end - start), 855 ctx->buf_sizes[4]); 856 return -EINVAL; 857 } 858 } else if ((cmd != 0x100) && (cmd != 0x204)) { 859 DRM_ERROR("invalid UVD command %X!\n", cmd); 860 return -EINVAL; 861 } 862 863 if (!ctx->parser->adev->uvd.address_64_bit) { 864 if ((start >> 28) != ((end - 1) >> 28)) { 865 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n", 866 start, end); 867 return -EINVAL; 868 } 869 870 if ((cmd == 0 || cmd == 0x3) && 871 (start >> 28) != (ctx->parser->adev->uvd.inst->gpu_addr >> 28)) { 872 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n", 873 start, end); 874 return -EINVAL; 875 } 876 } 877 878 if (cmd == 0) { 879 ctx->has_msg_cmd = true; 880 r = amdgpu_uvd_cs_msg(ctx, bo, addr); 881 if (r) 882 return r; 883 } else if (!ctx->has_msg_cmd) { 884 DRM_ERROR("Message needed before other commands are send!\n"); 885 return -EINVAL; 886 } 887 888 return 0; 889 } 890 891 /** 892 * amdgpu_uvd_cs_reg - parse register writes 893 * 894 * @ctx: UVD parser context 895 * @cb: callback function 896 * 897 * Parse the register writes, call cb on each complete command. 898 */ 899 static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx, 900 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) 901 { 902 struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx]; 903 int i, r; 904 905 ctx->idx++; 906 for (i = 0; i <= ctx->count; ++i) { 907 unsigned reg = ctx->reg + i; 908 909 if (ctx->idx >= ib->length_dw) { 910 DRM_ERROR("Register command after end of CS!\n"); 911 return -EINVAL; 912 } 913 914 switch (reg) { 915 case mmUVD_GPCOM_VCPU_DATA0: 916 ctx->data0 = ctx->idx; 917 break; 918 case mmUVD_GPCOM_VCPU_DATA1: 919 ctx->data1 = ctx->idx; 920 break; 921 case mmUVD_GPCOM_VCPU_CMD: 922 r = cb(ctx); 923 if (r) 924 return r; 925 break; 926 case mmUVD_ENGINE_CNTL: 927 case mmUVD_NO_OP: 928 break; 929 default: 930 DRM_ERROR("Invalid reg 0x%X!\n", reg); 931 return -EINVAL; 932 } 933 ctx->idx++; 934 } 935 return 0; 936 } 937 938 /** 939 * amdgpu_uvd_cs_packets - parse UVD packets 940 * 941 * @ctx: UVD parser context 942 * @cb: callback function 943 * 944 * Parse the command stream packets. 945 */ 946 static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx, 947 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) 948 { 949 struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx]; 950 int r; 951 952 for (ctx->idx = 0 ; ctx->idx < ib->length_dw; ) { 953 uint32_t cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx); 954 unsigned type = CP_PACKET_GET_TYPE(cmd); 955 switch (type) { 956 case PACKET_TYPE0: 957 ctx->reg = CP_PACKET0_GET_REG(cmd); 958 ctx->count = CP_PACKET_GET_COUNT(cmd); 959 r = amdgpu_uvd_cs_reg(ctx, cb); 960 if (r) 961 return r; 962 break; 963 case PACKET_TYPE2: 964 ++ctx->idx; 965 break; 966 default: 967 DRM_ERROR("Unknown packet type %d !\n", type); 968 return -EINVAL; 969 } 970 } 971 return 0; 972 } 973 974 /** 975 * amdgpu_uvd_ring_parse_cs - UVD command submission parser 976 * 977 * @parser: Command submission parser context 978 * 979 * Parse the command stream, patch in addresses as necessary. 980 */ 981 int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx) 982 { 983 struct amdgpu_uvd_cs_ctx ctx = {}; 984 unsigned buf_sizes[] = { 985 [0x00000000] = 2048, 986 [0x00000001] = 0xFFFFFFFF, 987 [0x00000002] = 0xFFFFFFFF, 988 [0x00000003] = 2048, 989 [0x00000004] = 0xFFFFFFFF, 990 }; 991 struct amdgpu_ib *ib = &parser->job->ibs[ib_idx]; 992 int r; 993 994 parser->job->vm = NULL; 995 ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo); 996 997 if (ib->length_dw % 16) { 998 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n", 999 ib->length_dw); 1000 return -EINVAL; 1001 } 1002 1003 ctx.parser = parser; 1004 ctx.buf_sizes = buf_sizes; 1005 ctx.ib_idx = ib_idx; 1006 1007 /* first round only required on chips without UVD 64 bit address support */ 1008 if (!parser->adev->uvd.address_64_bit) { 1009 /* first round, make sure the buffers are actually in the UVD segment */ 1010 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1); 1011 if (r) 1012 return r; 1013 } 1014 1015 /* second round, patch buffer addresses into the command stream */ 1016 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2); 1017 if (r) 1018 return r; 1019 1020 if (!ctx.has_msg_cmd) { 1021 DRM_ERROR("UVD-IBs need a msg command!\n"); 1022 return -EINVAL; 1023 } 1024 1025 return 0; 1026 } 1027 1028 static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, 1029 bool direct, struct dma_fence **fence) 1030 { 1031 struct amdgpu_device *adev = ring->adev; 1032 struct dma_fence *f = NULL; 1033 struct amdgpu_job *job; 1034 struct amdgpu_ib *ib; 1035 uint32_t data[4]; 1036 uint64_t addr; 1037 long r; 1038 int i; 1039 unsigned offset_idx = 0; 1040 unsigned offset[3] = { UVD_BASE_SI, 0, 0 }; 1041 1042 amdgpu_bo_kunmap(bo); 1043 amdgpu_bo_unpin(bo); 1044 1045 if (!ring->adev->uvd.address_64_bit) { 1046 struct ttm_operation_ctx ctx = { true, false }; 1047 1048 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM); 1049 amdgpu_uvd_force_into_uvd_segment(bo); 1050 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 1051 if (r) 1052 goto err; 1053 } 1054 1055 r = amdgpu_job_alloc_with_ib(adev, 64, &job); 1056 if (r) 1057 goto err; 1058 1059 if (adev->asic_type >= CHIP_VEGA10) { 1060 offset_idx = 1 + ring->me; 1061 offset[1] = adev->reg_offset[UVD_HWIP][0][1]; 1062 offset[2] = adev->reg_offset[UVD_HWIP][1][1]; 1063 } 1064 1065 data[0] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_DATA0, 0); 1066 data[1] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_DATA1, 0); 1067 data[2] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_CMD, 0); 1068 data[3] = PACKET0(offset[offset_idx] + UVD_NO_OP, 0); 1069 1070 ib = &job->ibs[0]; 1071 addr = amdgpu_bo_gpu_offset(bo); 1072 ib->ptr[0] = data[0]; 1073 ib->ptr[1] = addr; 1074 ib->ptr[2] = data[1]; 1075 ib->ptr[3] = addr >> 32; 1076 ib->ptr[4] = data[2]; 1077 ib->ptr[5] = 0; 1078 for (i = 6; i < 16; i += 2) { 1079 ib->ptr[i] = data[3]; 1080 ib->ptr[i+1] = 0; 1081 } 1082 ib->length_dw = 16; 1083 1084 if (direct) { 1085 r = dma_resv_wait_timeout_rcu(bo->tbo.base.resv, 1086 true, false, 1087 msecs_to_jiffies(10)); 1088 if (r == 0) 1089 r = -ETIMEDOUT; 1090 if (r < 0) 1091 goto err_free; 1092 1093 r = amdgpu_job_submit_direct(job, ring, &f); 1094 if (r) 1095 goto err_free; 1096 } else { 1097 r = amdgpu_sync_resv(adev, &job->sync, bo->tbo.base.resv, 1098 AMDGPU_FENCE_OWNER_UNDEFINED, false); 1099 if (r) 1100 goto err_free; 1101 1102 r = amdgpu_job_submit(job, &adev->uvd.entity, 1103 AMDGPU_FENCE_OWNER_UNDEFINED, &f); 1104 if (r) 1105 goto err_free; 1106 } 1107 1108 amdgpu_bo_fence(bo, f, false); 1109 amdgpu_bo_unreserve(bo); 1110 amdgpu_bo_unref(&bo); 1111 1112 if (fence) 1113 *fence = dma_fence_get(f); 1114 dma_fence_put(f); 1115 1116 return 0; 1117 1118 err_free: 1119 amdgpu_job_free(job); 1120 1121 err: 1122 amdgpu_bo_unreserve(bo); 1123 amdgpu_bo_unref(&bo); 1124 return r; 1125 } 1126 1127 /* multiple fence commands without any stream commands in between can 1128 crash the vcpu so just try to emmit a dummy create/destroy msg to 1129 avoid this */ 1130 int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 1131 struct dma_fence **fence) 1132 { 1133 struct amdgpu_device *adev = ring->adev; 1134 struct amdgpu_bo *bo = NULL; 1135 uint32_t *msg; 1136 int r, i; 1137 1138 r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE, 1139 AMDGPU_GEM_DOMAIN_VRAM, 1140 &bo, NULL, (void **)&msg); 1141 if (r) 1142 return r; 1143 1144 /* stitch together an UVD create msg */ 1145 msg[0] = cpu_to_le32(0x00000de4); 1146 msg[1] = cpu_to_le32(0x00000000); 1147 msg[2] = cpu_to_le32(handle); 1148 msg[3] = cpu_to_le32(0x00000000); 1149 msg[4] = cpu_to_le32(0x00000000); 1150 msg[5] = cpu_to_le32(0x00000000); 1151 msg[6] = cpu_to_le32(0x00000000); 1152 msg[7] = cpu_to_le32(0x00000780); 1153 msg[8] = cpu_to_le32(0x00000440); 1154 msg[9] = cpu_to_le32(0x00000000); 1155 msg[10] = cpu_to_le32(0x01b37000); 1156 for (i = 11; i < 1024; ++i) 1157 msg[i] = cpu_to_le32(0x0); 1158 1159 return amdgpu_uvd_send_msg(ring, bo, true, fence); 1160 } 1161 1162 int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 1163 bool direct, struct dma_fence **fence) 1164 { 1165 struct amdgpu_device *adev = ring->adev; 1166 struct amdgpu_bo *bo = NULL; 1167 uint32_t *msg; 1168 int r, i; 1169 1170 r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE, 1171 AMDGPU_GEM_DOMAIN_VRAM, 1172 &bo, NULL, (void **)&msg); 1173 if (r) 1174 return r; 1175 1176 /* stitch together an UVD destroy msg */ 1177 msg[0] = cpu_to_le32(0x00000de4); 1178 msg[1] = cpu_to_le32(0x00000002); 1179 msg[2] = cpu_to_le32(handle); 1180 msg[3] = cpu_to_le32(0x00000000); 1181 for (i = 4; i < 1024; ++i) 1182 msg[i] = cpu_to_le32(0x0); 1183 1184 return amdgpu_uvd_send_msg(ring, bo, direct, fence); 1185 } 1186 1187 static void amdgpu_uvd_idle_work_handler(struct work_struct *work) 1188 { 1189 struct amdgpu_device *adev = 1190 container_of(work, struct amdgpu_device, uvd.idle_work.work); 1191 unsigned fences = 0, i, j; 1192 1193 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) { 1194 if (adev->uvd.harvest_config & (1 << i)) 1195 continue; 1196 fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring); 1197 for (j = 0; j < adev->uvd.num_enc_rings; ++j) { 1198 fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring_enc[j]); 1199 } 1200 } 1201 1202 if (fences == 0) { 1203 if (adev->pm.dpm_enabled) { 1204 amdgpu_dpm_enable_uvd(adev, false); 1205 } else { 1206 amdgpu_asic_set_uvd_clocks(adev, 0, 0); 1207 /* shutdown the UVD block */ 1208 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1209 AMD_PG_STATE_GATE); 1210 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1211 AMD_CG_STATE_GATE); 1212 } 1213 } else { 1214 schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT); 1215 } 1216 } 1217 1218 void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring) 1219 { 1220 struct amdgpu_device *adev = ring->adev; 1221 bool set_clocks; 1222 1223 if (amdgpu_sriov_vf(adev)) 1224 return; 1225 1226 set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work); 1227 if (set_clocks) { 1228 if (adev->pm.dpm_enabled) { 1229 amdgpu_dpm_enable_uvd(adev, true); 1230 } else { 1231 amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); 1232 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1233 AMD_CG_STATE_UNGATE); 1234 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1235 AMD_PG_STATE_UNGATE); 1236 } 1237 } 1238 } 1239 1240 void amdgpu_uvd_ring_end_use(struct amdgpu_ring *ring) 1241 { 1242 if (!amdgpu_sriov_vf(ring->adev)) 1243 schedule_delayed_work(&ring->adev->uvd.idle_work, UVD_IDLE_TIMEOUT); 1244 } 1245 1246 /** 1247 * amdgpu_uvd_ring_test_ib - test ib execution 1248 * 1249 * @ring: amdgpu_ring pointer 1250 * 1251 * Test if we can successfully execute an IB 1252 */ 1253 int amdgpu_uvd_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1254 { 1255 struct dma_fence *fence; 1256 long r; 1257 1258 r = amdgpu_uvd_get_create_msg(ring, 1, NULL); 1259 if (r) 1260 goto error; 1261 1262 r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence); 1263 if (r) 1264 goto error; 1265 1266 r = dma_fence_wait_timeout(fence, false, timeout); 1267 if (r == 0) 1268 r = -ETIMEDOUT; 1269 else if (r > 0) 1270 r = 0; 1271 1272 dma_fence_put(fence); 1273 1274 error: 1275 return r; 1276 } 1277 1278 /** 1279 * amdgpu_uvd_used_handles - returns used UVD handles 1280 * 1281 * @adev: amdgpu_device pointer 1282 * 1283 * Returns the number of UVD handles in use 1284 */ 1285 uint32_t amdgpu_uvd_used_handles(struct amdgpu_device *adev) 1286 { 1287 unsigned i; 1288 uint32_t used_handles = 0; 1289 1290 for (i = 0; i < adev->uvd.max_handles; ++i) { 1291 /* 1292 * Handles can be freed in any order, and not 1293 * necessarily linear. So we need to count 1294 * all non-zero handles. 1295 */ 1296 if (atomic_read(&adev->uvd.handles[i])) 1297 used_handles++; 1298 } 1299 1300 return used_handles; 1301 } 1302