1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 * Jerome Glisse 26 */ 27 28 #include <drm/amdgpu_drm.h> 29 #include "amdgpu.h" 30 31 #include "atom.h" 32 #include "atom-bits.h" 33 #include "atombios_encoders.h" 34 #include "atombios_dp.h" 35 #include "amdgpu_connectors.h" 36 #include "amdgpu_atombios.h" 37 #include <drm/dp/drm_dp_helper.h> 38 39 /* move these to drm_dp_helper.c/h */ 40 #define DP_LINK_CONFIGURATION_SIZE 9 41 #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE 42 43 static char *voltage_names[] = { 44 "0.4V", "0.6V", "0.8V", "1.2V" 45 }; 46 static char *pre_emph_names[] = { 47 "0dB", "3.5dB", "6dB", "9.5dB" 48 }; 49 50 /***** amdgpu AUX functions *****/ 51 52 union aux_channel_transaction { 53 PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1; 54 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2; 55 }; 56 57 static int amdgpu_atombios_dp_process_aux_ch(struct amdgpu_i2c_chan *chan, 58 u8 *send, int send_bytes, 59 u8 *recv, int recv_size, 60 u8 delay, u8 *ack) 61 { 62 struct drm_device *dev = chan->dev; 63 struct amdgpu_device *adev = drm_to_adev(dev); 64 union aux_channel_transaction args; 65 int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction); 66 unsigned char *base; 67 int recv_bytes; 68 int r = 0; 69 70 memset(&args, 0, sizeof(args)); 71 72 mutex_lock(&chan->mutex); 73 74 base = (unsigned char *)(adev->mode_info.atom_context->scratch + 1); 75 76 amdgpu_atombios_copy_swap(base, send, send_bytes, true); 77 78 args.v2.lpAuxRequest = cpu_to_le16((u16)(0 + 4)); 79 args.v2.lpDataOut = cpu_to_le16((u16)(16 + 4)); 80 args.v2.ucDataOutLen = 0; 81 args.v2.ucChannelID = chan->rec.i2c_id; 82 args.v2.ucDelay = delay / 10; 83 args.v2.ucHPD_ID = chan->rec.hpd; 84 85 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); 86 87 *ack = args.v2.ucReplyStatus; 88 89 /* timeout */ 90 if (args.v2.ucReplyStatus == 1) { 91 r = -ETIMEDOUT; 92 goto done; 93 } 94 95 /* flags not zero */ 96 if (args.v2.ucReplyStatus == 2) { 97 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n"); 98 r = -EIO; 99 goto done; 100 } 101 102 /* error */ 103 if (args.v2.ucReplyStatus == 3) { 104 DRM_DEBUG_KMS("dp_aux_ch error\n"); 105 r = -EIO; 106 goto done; 107 } 108 109 recv_bytes = args.v1.ucDataOutLen; 110 if (recv_bytes > recv_size) 111 recv_bytes = recv_size; 112 113 if (recv && recv_size) 114 amdgpu_atombios_copy_swap(recv, base + 16, recv_bytes, false); 115 116 r = recv_bytes; 117 done: 118 mutex_unlock(&chan->mutex); 119 120 return r; 121 } 122 123 #define BARE_ADDRESS_SIZE 3 124 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) 125 126 static ssize_t 127 amdgpu_atombios_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) 128 { 129 struct amdgpu_i2c_chan *chan = 130 container_of(aux, struct amdgpu_i2c_chan, aux); 131 int ret; 132 u8 tx_buf[20]; 133 size_t tx_size; 134 u8 ack, delay = 0; 135 136 if (WARN_ON(msg->size > 16)) 137 return -E2BIG; 138 139 tx_buf[0] = msg->address & 0xff; 140 tx_buf[1] = msg->address >> 8; 141 tx_buf[2] = (msg->request << 4) | 142 ((msg->address >> 16) & 0xf); 143 tx_buf[3] = msg->size ? (msg->size - 1) : 0; 144 145 switch (msg->request & ~DP_AUX_I2C_MOT) { 146 case DP_AUX_NATIVE_WRITE: 147 case DP_AUX_I2C_WRITE: 148 /* tx_size needs to be 4 even for bare address packets since the atom 149 * table needs the info in tx_buf[3]. 150 */ 151 tx_size = HEADER_SIZE + msg->size; 152 if (msg->size == 0) 153 tx_buf[3] |= BARE_ADDRESS_SIZE << 4; 154 else 155 tx_buf[3] |= tx_size << 4; 156 memcpy(tx_buf + HEADER_SIZE, msg->buffer, msg->size); 157 ret = amdgpu_atombios_dp_process_aux_ch(chan, 158 tx_buf, tx_size, NULL, 0, delay, &ack); 159 if (ret >= 0) 160 /* Return payload size. */ 161 ret = msg->size; 162 break; 163 case DP_AUX_NATIVE_READ: 164 case DP_AUX_I2C_READ: 165 /* tx_size needs to be 4 even for bare address packets since the atom 166 * table needs the info in tx_buf[3]. 167 */ 168 tx_size = HEADER_SIZE; 169 if (msg->size == 0) 170 tx_buf[3] |= BARE_ADDRESS_SIZE << 4; 171 else 172 tx_buf[3] |= tx_size << 4; 173 ret = amdgpu_atombios_dp_process_aux_ch(chan, 174 tx_buf, tx_size, msg->buffer, msg->size, delay, &ack); 175 break; 176 default: 177 ret = -EINVAL; 178 break; 179 } 180 181 if (ret >= 0) 182 msg->reply = ack >> 4; 183 184 return ret; 185 } 186 187 void amdgpu_atombios_dp_aux_init(struct amdgpu_connector *amdgpu_connector) 188 { 189 amdgpu_connector->ddc_bus->rec.hpd = amdgpu_connector->hpd.hpd; 190 amdgpu_connector->ddc_bus->aux.transfer = amdgpu_atombios_dp_aux_transfer; 191 amdgpu_connector->ddc_bus->aux.drm_dev = amdgpu_connector->base.dev; 192 193 drm_dp_aux_init(&amdgpu_connector->ddc_bus->aux); 194 amdgpu_connector->ddc_bus->has_aux = true; 195 } 196 197 /***** general DP utility functions *****/ 198 199 #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_LEVEL_3 200 #define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPH_LEVEL_3 201 202 static void amdgpu_atombios_dp_get_adjust_train(const u8 link_status[DP_LINK_STATUS_SIZE], 203 int lane_count, 204 u8 train_set[4]) 205 { 206 u8 v = 0; 207 u8 p = 0; 208 int lane; 209 210 for (lane = 0; lane < lane_count; lane++) { 211 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane); 212 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); 213 214 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n", 215 lane, 216 voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT], 217 pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); 218 219 if (this_v > v) 220 v = this_v; 221 if (this_p > p) 222 p = this_p; 223 } 224 225 if (v >= DP_VOLTAGE_MAX) 226 v |= DP_TRAIN_MAX_SWING_REACHED; 227 228 if (p >= DP_PRE_EMPHASIS_MAX) 229 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 230 231 DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n", 232 voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT], 233 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); 234 235 for (lane = 0; lane < 4; lane++) 236 train_set[lane] = v | p; 237 } 238 239 /* convert bits per color to bits per pixel */ 240 /* get bpc from the EDID */ 241 static unsigned amdgpu_atombios_dp_convert_bpc_to_bpp(int bpc) 242 { 243 if (bpc == 0) 244 return 24; 245 else 246 return bpc * 3; 247 } 248 249 /***** amdgpu specific DP functions *****/ 250 251 static int amdgpu_atombios_dp_get_dp_link_config(struct drm_connector *connector, 252 const u8 dpcd[DP_DPCD_SIZE], 253 unsigned pix_clock, 254 unsigned *dp_lanes, unsigned *dp_rate) 255 { 256 unsigned bpp = 257 amdgpu_atombios_dp_convert_bpc_to_bpp(amdgpu_connector_get_monitor_bpc(connector)); 258 static const unsigned link_rates[3] = { 162000, 270000, 540000 }; 259 unsigned max_link_rate = drm_dp_max_link_rate(dpcd); 260 unsigned max_lane_num = drm_dp_max_lane_count(dpcd); 261 unsigned lane_num, i, max_pix_clock; 262 263 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) == 264 ENCODER_OBJECT_ID_NUTMEG) { 265 for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) { 266 max_pix_clock = (lane_num * 270000 * 8) / bpp; 267 if (max_pix_clock >= pix_clock) { 268 *dp_lanes = lane_num; 269 *dp_rate = 270000; 270 return 0; 271 } 272 } 273 } else { 274 for (i = 0; i < ARRAY_SIZE(link_rates) && link_rates[i] <= max_link_rate; i++) { 275 for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) { 276 max_pix_clock = (lane_num * link_rates[i] * 8) / bpp; 277 if (max_pix_clock >= pix_clock) { 278 *dp_lanes = lane_num; 279 *dp_rate = link_rates[i]; 280 return 0; 281 } 282 } 283 } 284 } 285 286 return -EINVAL; 287 } 288 289 static u8 amdgpu_atombios_dp_encoder_service(struct amdgpu_device *adev, 290 int action, int dp_clock, 291 u8 ucconfig, u8 lane_num) 292 { 293 DP_ENCODER_SERVICE_PARAMETERS args; 294 int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService); 295 296 memset(&args, 0, sizeof(args)); 297 args.ucLinkClock = dp_clock / 10; 298 args.ucConfig = ucconfig; 299 args.ucAction = action; 300 args.ucLaneNum = lane_num; 301 args.ucStatus = 0; 302 303 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); 304 return args.ucStatus; 305 } 306 307 u8 amdgpu_atombios_dp_get_sinktype(struct amdgpu_connector *amdgpu_connector) 308 { 309 struct drm_device *dev = amdgpu_connector->base.dev; 310 struct amdgpu_device *adev = drm_to_adev(dev); 311 312 return amdgpu_atombios_dp_encoder_service(adev, ATOM_DP_ACTION_GET_SINK_TYPE, 0, 313 amdgpu_connector->ddc_bus->rec.i2c_id, 0); 314 } 315 316 static void amdgpu_atombios_dp_probe_oui(struct amdgpu_connector *amdgpu_connector) 317 { 318 struct amdgpu_connector_atom_dig *dig_connector = amdgpu_connector->con_priv; 319 u8 buf[3]; 320 321 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) 322 return; 323 324 if (drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3) == 3) 325 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", 326 buf[0], buf[1], buf[2]); 327 328 if (drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3) == 3) 329 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", 330 buf[0], buf[1], buf[2]); 331 } 332 333 static void amdgpu_atombios_dp_ds_ports(struct amdgpu_connector *amdgpu_connector) 334 { 335 struct amdgpu_connector_atom_dig *dig_connector = amdgpu_connector->con_priv; 336 int ret; 337 338 if (dig_connector->dpcd[DP_DPCD_REV] > 0x10) { 339 ret = drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux, 340 DP_DOWNSTREAM_PORT_0, 341 dig_connector->downstream_ports, 342 DP_MAX_DOWNSTREAM_PORTS); 343 if (ret) 344 memset(dig_connector->downstream_ports, 0, 345 DP_MAX_DOWNSTREAM_PORTS); 346 } 347 } 348 349 int amdgpu_atombios_dp_get_dpcd(struct amdgpu_connector *amdgpu_connector) 350 { 351 struct amdgpu_connector_atom_dig *dig_connector = amdgpu_connector->con_priv; 352 u8 msg[DP_DPCD_SIZE]; 353 int ret; 354 355 ret = drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux, DP_DPCD_REV, 356 msg, DP_DPCD_SIZE); 357 if (ret == DP_DPCD_SIZE) { 358 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); 359 360 DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd), 361 dig_connector->dpcd); 362 363 amdgpu_atombios_dp_probe_oui(amdgpu_connector); 364 amdgpu_atombios_dp_ds_ports(amdgpu_connector); 365 return 0; 366 } 367 368 dig_connector->dpcd[0] = 0; 369 return -EINVAL; 370 } 371 372 int amdgpu_atombios_dp_get_panel_mode(struct drm_encoder *encoder, 373 struct drm_connector *connector) 374 { 375 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 376 int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; 377 u16 dp_bridge = amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector); 378 u8 tmp; 379 380 if (!amdgpu_connector->con_priv) 381 return panel_mode; 382 383 if (dp_bridge != ENCODER_OBJECT_ID_NONE) { 384 /* DP bridge chips */ 385 if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux, 386 DP_EDP_CONFIGURATION_CAP, &tmp) == 1) { 387 if (tmp & 1) 388 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; 389 else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) || 390 (dp_bridge == ENCODER_OBJECT_ID_TRAVIS)) 391 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE; 392 else 393 panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; 394 } 395 } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 396 /* eDP */ 397 if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux, 398 DP_EDP_CONFIGURATION_CAP, &tmp) == 1) { 399 if (tmp & 1) 400 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; 401 } 402 } 403 404 return panel_mode; 405 } 406 407 void amdgpu_atombios_dp_set_link_config(struct drm_connector *connector, 408 const struct drm_display_mode *mode) 409 { 410 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 411 struct amdgpu_connector_atom_dig *dig_connector; 412 int ret; 413 414 if (!amdgpu_connector->con_priv) 415 return; 416 dig_connector = amdgpu_connector->con_priv; 417 418 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 419 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 420 ret = amdgpu_atombios_dp_get_dp_link_config(connector, dig_connector->dpcd, 421 mode->clock, 422 &dig_connector->dp_lane_count, 423 &dig_connector->dp_clock); 424 if (ret) { 425 dig_connector->dp_clock = 0; 426 dig_connector->dp_lane_count = 0; 427 } 428 } 429 } 430 431 int amdgpu_atombios_dp_mode_valid_helper(struct drm_connector *connector, 432 struct drm_display_mode *mode) 433 { 434 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 435 struct amdgpu_connector_atom_dig *dig_connector; 436 unsigned dp_lanes, dp_clock; 437 int ret; 438 439 if (!amdgpu_connector->con_priv) 440 return MODE_CLOCK_HIGH; 441 dig_connector = amdgpu_connector->con_priv; 442 443 ret = amdgpu_atombios_dp_get_dp_link_config(connector, dig_connector->dpcd, 444 mode->clock, &dp_lanes, &dp_clock); 445 if (ret) 446 return MODE_CLOCK_HIGH; 447 448 if ((dp_clock == 540000) && 449 (!amdgpu_connector_is_dp12_capable(connector))) 450 return MODE_CLOCK_HIGH; 451 452 return MODE_OK; 453 } 454 455 bool amdgpu_atombios_dp_needs_link_train(struct amdgpu_connector *amdgpu_connector) 456 { 457 u8 link_status[DP_LINK_STATUS_SIZE]; 458 struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv; 459 460 if (drm_dp_dpcd_read_link_status(&amdgpu_connector->ddc_bus->aux, link_status) 461 <= 0) 462 return false; 463 if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count)) 464 return false; 465 return true; 466 } 467 468 void amdgpu_atombios_dp_set_rx_power_state(struct drm_connector *connector, 469 u8 power_state) 470 { 471 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 472 struct amdgpu_connector_atom_dig *dig_connector; 473 474 if (!amdgpu_connector->con_priv) 475 return; 476 477 dig_connector = amdgpu_connector->con_priv; 478 479 /* power up/down the sink */ 480 if (dig_connector->dpcd[0] >= 0x11) { 481 drm_dp_dpcd_writeb(&amdgpu_connector->ddc_bus->aux, 482 DP_SET_POWER, power_state); 483 usleep_range(1000, 2000); 484 } 485 } 486 487 struct amdgpu_atombios_dp_link_train_info { 488 struct amdgpu_device *adev; 489 struct drm_encoder *encoder; 490 struct drm_connector *connector; 491 int dp_clock; 492 int dp_lane_count; 493 bool tp3_supported; 494 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 495 u8 train_set[4]; 496 u8 link_status[DP_LINK_STATUS_SIZE]; 497 u8 tries; 498 struct drm_dp_aux *aux; 499 }; 500 501 static void 502 amdgpu_atombios_dp_update_vs_emph(struct amdgpu_atombios_dp_link_train_info *dp_info) 503 { 504 /* set the initial vs/emph on the source */ 505 amdgpu_atombios_encoder_setup_dig_transmitter(dp_info->encoder, 506 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH, 507 0, dp_info->train_set[0]); /* sets all lanes at once */ 508 509 /* set the vs/emph on the sink */ 510 drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET, 511 dp_info->train_set, dp_info->dp_lane_count); 512 } 513 514 static void 515 amdgpu_atombios_dp_set_tp(struct amdgpu_atombios_dp_link_train_info *dp_info, int tp) 516 { 517 int rtp = 0; 518 519 /* set training pattern on the source */ 520 switch (tp) { 521 case DP_TRAINING_PATTERN_1: 522 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1; 523 break; 524 case DP_TRAINING_PATTERN_2: 525 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2; 526 break; 527 case DP_TRAINING_PATTERN_3: 528 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3; 529 break; 530 } 531 amdgpu_atombios_encoder_setup_dig_encoder(dp_info->encoder, rtp, 0); 532 533 /* enable training pattern on the sink */ 534 drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp); 535 } 536 537 static int 538 amdgpu_atombios_dp_link_train_init(struct amdgpu_atombios_dp_link_train_info *dp_info) 539 { 540 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(dp_info->encoder); 541 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 542 u8 tmp; 543 544 /* power up the sink */ 545 amdgpu_atombios_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0); 546 547 /* possibly enable downspread on the sink */ 548 if (dp_info->dpcd[3] & 0x1) 549 drm_dp_dpcd_writeb(dp_info->aux, 550 DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5); 551 else 552 drm_dp_dpcd_writeb(dp_info->aux, 553 DP_DOWNSPREAD_CTRL, 0); 554 555 if (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE) 556 drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1); 557 558 /* set the lane count on the sink */ 559 tmp = dp_info->dp_lane_count; 560 if (drm_dp_enhanced_frame_cap(dp_info->dpcd)) 561 tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 562 drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp); 563 564 /* set the link rate on the sink */ 565 tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock); 566 drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp); 567 568 /* start training on the source */ 569 amdgpu_atombios_encoder_setup_dig_encoder(dp_info->encoder, 570 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0); 571 572 /* disable the training pattern on the sink */ 573 drm_dp_dpcd_writeb(dp_info->aux, 574 DP_TRAINING_PATTERN_SET, 575 DP_TRAINING_PATTERN_DISABLE); 576 577 return 0; 578 } 579 580 static int 581 amdgpu_atombios_dp_link_train_finish(struct amdgpu_atombios_dp_link_train_info *dp_info) 582 { 583 udelay(400); 584 585 /* disable the training pattern on the sink */ 586 drm_dp_dpcd_writeb(dp_info->aux, 587 DP_TRAINING_PATTERN_SET, 588 DP_TRAINING_PATTERN_DISABLE); 589 590 /* disable the training pattern on the source */ 591 amdgpu_atombios_encoder_setup_dig_encoder(dp_info->encoder, 592 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0); 593 594 return 0; 595 } 596 597 static int 598 amdgpu_atombios_dp_link_train_cr(struct amdgpu_atombios_dp_link_train_info *dp_info) 599 { 600 bool clock_recovery; 601 u8 voltage; 602 int i; 603 604 amdgpu_atombios_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1); 605 memset(dp_info->train_set, 0, 4); 606 amdgpu_atombios_dp_update_vs_emph(dp_info); 607 608 udelay(400); 609 610 /* clock recovery loop */ 611 clock_recovery = false; 612 dp_info->tries = 0; 613 voltage = 0xff; 614 while (1) { 615 drm_dp_link_train_clock_recovery_delay(dp_info->aux, dp_info->dpcd); 616 617 if (drm_dp_dpcd_read_link_status(dp_info->aux, 618 dp_info->link_status) <= 0) { 619 DRM_ERROR("displayport link status failed\n"); 620 break; 621 } 622 623 if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) { 624 clock_recovery = true; 625 break; 626 } 627 628 for (i = 0; i < dp_info->dp_lane_count; i++) { 629 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) 630 break; 631 } 632 if (i == dp_info->dp_lane_count) { 633 DRM_ERROR("clock recovery reached max voltage\n"); 634 break; 635 } 636 637 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { 638 ++dp_info->tries; 639 if (dp_info->tries == 5) { 640 DRM_ERROR("clock recovery tried 5 times\n"); 641 break; 642 } 643 } else 644 dp_info->tries = 0; 645 646 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 647 648 /* Compute new train_set as requested by sink */ 649 amdgpu_atombios_dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, 650 dp_info->train_set); 651 652 amdgpu_atombios_dp_update_vs_emph(dp_info); 653 } 654 if (!clock_recovery) { 655 DRM_ERROR("clock recovery failed\n"); 656 return -1; 657 } else { 658 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n", 659 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, 660 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> 661 DP_TRAIN_PRE_EMPHASIS_SHIFT); 662 return 0; 663 } 664 } 665 666 static int 667 amdgpu_atombios_dp_link_train_ce(struct amdgpu_atombios_dp_link_train_info *dp_info) 668 { 669 bool channel_eq; 670 671 if (dp_info->tp3_supported) 672 amdgpu_atombios_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3); 673 else 674 amdgpu_atombios_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2); 675 676 /* channel equalization loop */ 677 dp_info->tries = 0; 678 channel_eq = false; 679 while (1) { 680 drm_dp_link_train_channel_eq_delay(dp_info->aux, dp_info->dpcd); 681 682 if (drm_dp_dpcd_read_link_status(dp_info->aux, 683 dp_info->link_status) <= 0) { 684 DRM_ERROR("displayport link status failed\n"); 685 break; 686 } 687 688 if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) { 689 channel_eq = true; 690 break; 691 } 692 693 /* Try 5 times */ 694 if (dp_info->tries > 5) { 695 DRM_ERROR("channel eq failed: 5 tries\n"); 696 break; 697 } 698 699 /* Compute new train_set as requested by sink */ 700 amdgpu_atombios_dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, 701 dp_info->train_set); 702 703 amdgpu_atombios_dp_update_vs_emph(dp_info); 704 dp_info->tries++; 705 } 706 707 if (!channel_eq) { 708 DRM_ERROR("channel eq failed\n"); 709 return -1; 710 } else { 711 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n", 712 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, 713 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) 714 >> DP_TRAIN_PRE_EMPHASIS_SHIFT); 715 return 0; 716 } 717 } 718 719 void amdgpu_atombios_dp_link_train(struct drm_encoder *encoder, 720 struct drm_connector *connector) 721 { 722 struct drm_device *dev = encoder->dev; 723 struct amdgpu_device *adev = drm_to_adev(dev); 724 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 725 struct amdgpu_connector *amdgpu_connector; 726 struct amdgpu_connector_atom_dig *dig_connector; 727 struct amdgpu_atombios_dp_link_train_info dp_info; 728 u8 tmp; 729 730 if (!amdgpu_encoder->enc_priv) 731 return; 732 733 amdgpu_connector = to_amdgpu_connector(connector); 734 if (!amdgpu_connector->con_priv) 735 return; 736 dig_connector = amdgpu_connector->con_priv; 737 738 if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) && 739 (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP)) 740 return; 741 742 if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp) 743 == 1) { 744 if (tmp & DP_TPS3_SUPPORTED) 745 dp_info.tp3_supported = true; 746 else 747 dp_info.tp3_supported = false; 748 } else { 749 dp_info.tp3_supported = false; 750 } 751 752 memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE); 753 dp_info.adev = adev; 754 dp_info.encoder = encoder; 755 dp_info.connector = connector; 756 dp_info.dp_lane_count = dig_connector->dp_lane_count; 757 dp_info.dp_clock = dig_connector->dp_clock; 758 dp_info.aux = &amdgpu_connector->ddc_bus->aux; 759 760 if (amdgpu_atombios_dp_link_train_init(&dp_info)) 761 goto done; 762 if (amdgpu_atombios_dp_link_train_cr(&dp_info)) 763 goto done; 764 if (amdgpu_atombios_dp_link_train_ce(&dp_info)) 765 goto done; 766 done: 767 if (amdgpu_atombios_dp_link_train_finish(&dp_info)) 768 return; 769 } 770