1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #include <linux/firmware.h> 25 #include <drm/drmP.h> 26 #include "amdgpu.h" 27 #include "amdgpu_ucode.h" 28 #include "amdgpu_trace.h" 29 #include "cikd.h" 30 #include "cik.h" 31 32 #include "bif/bif_4_1_d.h" 33 #include "bif/bif_4_1_sh_mask.h" 34 35 #include "gca/gfx_7_2_d.h" 36 #include "gca/gfx_7_2_enum.h" 37 #include "gca/gfx_7_2_sh_mask.h" 38 39 #include "gmc/gmc_7_1_d.h" 40 #include "gmc/gmc_7_1_sh_mask.h" 41 42 #include "oss/oss_2_0_d.h" 43 #include "oss/oss_2_0_sh_mask.h" 44 45 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = 46 { 47 SDMA0_REGISTER_OFFSET, 48 SDMA1_REGISTER_OFFSET 49 }; 50 51 static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev); 52 static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev); 53 static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev); 54 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev); 55 static int cik_sdma_soft_reset(void *handle); 56 57 MODULE_FIRMWARE("amdgpu/bonaire_sdma.bin"); 58 MODULE_FIRMWARE("amdgpu/bonaire_sdma1.bin"); 59 MODULE_FIRMWARE("amdgpu/hawaii_sdma.bin"); 60 MODULE_FIRMWARE("amdgpu/hawaii_sdma1.bin"); 61 MODULE_FIRMWARE("amdgpu/kaveri_sdma.bin"); 62 MODULE_FIRMWARE("amdgpu/kaveri_sdma1.bin"); 63 MODULE_FIRMWARE("amdgpu/kabini_sdma.bin"); 64 MODULE_FIRMWARE("amdgpu/kabini_sdma1.bin"); 65 MODULE_FIRMWARE("amdgpu/mullins_sdma.bin"); 66 MODULE_FIRMWARE("amdgpu/mullins_sdma1.bin"); 67 68 u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev); 69 70 71 static void cik_sdma_free_microcode(struct amdgpu_device *adev) 72 { 73 int i; 74 for (i = 0; i < adev->sdma.num_instances; i++) { 75 release_firmware(adev->sdma.instance[i].fw); 76 adev->sdma.instance[i].fw = NULL; 77 } 78 } 79 80 /* 81 * sDMA - System DMA 82 * Starting with CIK, the GPU has new asynchronous 83 * DMA engines. These engines are used for compute 84 * and gfx. There are two DMA engines (SDMA0, SDMA1) 85 * and each one supports 1 ring buffer used for gfx 86 * and 2 queues used for compute. 87 * 88 * The programming model is very similar to the CP 89 * (ring buffer, IBs, etc.), but sDMA has it's own 90 * packet format that is different from the PM4 format 91 * used by the CP. sDMA supports copying data, writing 92 * embedded data, solid fills, and a number of other 93 * things. It also has support for tiling/detiling of 94 * buffers. 95 */ 96 97 /** 98 * cik_sdma_init_microcode - load ucode images from disk 99 * 100 * @adev: amdgpu_device pointer 101 * 102 * Use the firmware interface to load the ucode images into 103 * the driver (not loaded into hw). 104 * Returns 0 on success, error on failure. 105 */ 106 static int cik_sdma_init_microcode(struct amdgpu_device *adev) 107 { 108 const char *chip_name; 109 char fw_name[30]; 110 int err = 0, i; 111 112 DRM_DEBUG("\n"); 113 114 switch (adev->asic_type) { 115 case CHIP_BONAIRE: 116 chip_name = "bonaire"; 117 break; 118 case CHIP_HAWAII: 119 chip_name = "hawaii"; 120 break; 121 case CHIP_KAVERI: 122 chip_name = "kaveri"; 123 break; 124 case CHIP_KABINI: 125 chip_name = "kabini"; 126 break; 127 case CHIP_MULLINS: 128 chip_name = "mullins"; 129 break; 130 default: BUG(); 131 } 132 133 for (i = 0; i < adev->sdma.num_instances; i++) { 134 if (i == 0) 135 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 136 else 137 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); 138 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); 139 if (err) 140 goto out; 141 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); 142 } 143 out: 144 if (err) { 145 pr_err("cik_sdma: Failed to load firmware \"%s\"\n", fw_name); 146 for (i = 0; i < adev->sdma.num_instances; i++) { 147 release_firmware(adev->sdma.instance[i].fw); 148 adev->sdma.instance[i].fw = NULL; 149 } 150 } 151 return err; 152 } 153 154 /** 155 * cik_sdma_ring_get_rptr - get the current read pointer 156 * 157 * @ring: amdgpu ring pointer 158 * 159 * Get the current rptr from the hardware (CIK+). 160 */ 161 static uint64_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring) 162 { 163 u32 rptr; 164 165 rptr = ring->adev->wb.wb[ring->rptr_offs]; 166 167 return (rptr & 0x3fffc) >> 2; 168 } 169 170 /** 171 * cik_sdma_ring_get_wptr - get the current write pointer 172 * 173 * @ring: amdgpu ring pointer 174 * 175 * Get the current wptr from the hardware (CIK+). 176 */ 177 static uint64_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring) 178 { 179 struct amdgpu_device *adev = ring->adev; 180 181 return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) & 0x3fffc) >> 2; 182 } 183 184 /** 185 * cik_sdma_ring_set_wptr - commit the write pointer 186 * 187 * @ring: amdgpu ring pointer 188 * 189 * Write the wptr back to the hardware (CIK+). 190 */ 191 static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring) 192 { 193 struct amdgpu_device *adev = ring->adev; 194 195 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], 196 (lower_32_bits(ring->wptr) << 2) & 0x3fffc); 197 } 198 199 static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 200 { 201 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 202 int i; 203 204 for (i = 0; i < count; i++) 205 if (sdma && sdma->burst_nop && (i == 0)) 206 amdgpu_ring_write(ring, ring->funcs->nop | 207 SDMA_NOP_COUNT(count - 1)); 208 else 209 amdgpu_ring_write(ring, ring->funcs->nop); 210 } 211 212 /** 213 * cik_sdma_ring_emit_ib - Schedule an IB on the DMA engine 214 * 215 * @ring: amdgpu ring pointer 216 * @ib: IB object to schedule 217 * 218 * Schedule an IB in the DMA ring (CIK). 219 */ 220 static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring, 221 struct amdgpu_job *job, 222 struct amdgpu_ib *ib, 223 uint32_t flags) 224 { 225 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 226 u32 extra_bits = vmid & 0xf; 227 228 /* IB packet must end on a 8 DW boundary */ 229 cik_sdma_ring_insert_nop(ring, (12 - (lower_32_bits(ring->wptr) & 7)) % 8); 230 231 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits)); 232 amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */ 233 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff); 234 amdgpu_ring_write(ring, ib->length_dw); 235 236 } 237 238 /** 239 * cik_sdma_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 240 * 241 * @ring: amdgpu ring pointer 242 * 243 * Emit an hdp flush packet on the requested DMA ring. 244 */ 245 static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring *ring) 246 { 247 u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) | 248 SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */ 249 u32 ref_and_mask; 250 251 if (ring->me == 0) 252 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK; 253 else 254 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK; 255 256 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); 257 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); 258 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2); 259 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 260 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 261 amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */ 262 } 263 264 /** 265 * cik_sdma_ring_emit_fence - emit a fence on the DMA ring 266 * 267 * @ring: amdgpu ring pointer 268 * @fence: amdgpu fence object 269 * 270 * Add a DMA fence packet to the ring to write 271 * the fence seq number and DMA trap packet to generate 272 * an interrupt if needed (CIK). 273 */ 274 static void cik_sdma_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 275 unsigned flags) 276 { 277 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 278 /* write the fence */ 279 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0)); 280 amdgpu_ring_write(ring, lower_32_bits(addr)); 281 amdgpu_ring_write(ring, upper_32_bits(addr)); 282 amdgpu_ring_write(ring, lower_32_bits(seq)); 283 284 /* optionally write high bits as well */ 285 if (write64bit) { 286 addr += 4; 287 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0)); 288 amdgpu_ring_write(ring, lower_32_bits(addr)); 289 amdgpu_ring_write(ring, upper_32_bits(addr)); 290 amdgpu_ring_write(ring, upper_32_bits(seq)); 291 } 292 293 /* generate an interrupt */ 294 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0)); 295 } 296 297 /** 298 * cik_sdma_gfx_stop - stop the gfx async dma engines 299 * 300 * @adev: amdgpu_device pointer 301 * 302 * Stop the gfx async dma ring buffers (CIK). 303 */ 304 static void cik_sdma_gfx_stop(struct amdgpu_device *adev) 305 { 306 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; 307 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; 308 u32 rb_cntl; 309 int i; 310 311 if ((adev->mman.buffer_funcs_ring == sdma0) || 312 (adev->mman.buffer_funcs_ring == sdma1)) 313 amdgpu_ttm_set_buffer_funcs_status(adev, false); 314 315 for (i = 0; i < adev->sdma.num_instances; i++) { 316 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 317 rb_cntl &= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK; 318 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 319 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0); 320 } 321 sdma0->sched.ready = false; 322 sdma1->sched.ready = false; 323 } 324 325 /** 326 * cik_sdma_rlc_stop - stop the compute async dma engines 327 * 328 * @adev: amdgpu_device pointer 329 * 330 * Stop the compute async dma queues (CIK). 331 */ 332 static void cik_sdma_rlc_stop(struct amdgpu_device *adev) 333 { 334 /* XXX todo */ 335 } 336 337 /** 338 * cik_ctx_switch_enable - stop the async dma engines context switch 339 * 340 * @adev: amdgpu_device pointer 341 * @enable: enable/disable the DMA MEs context switch. 342 * 343 * Halt or unhalt the async dma engines context switch (VI). 344 */ 345 static void cik_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 346 { 347 u32 f32_cntl, phase_quantum = 0; 348 int i; 349 350 if (amdgpu_sdma_phase_quantum) { 351 unsigned value = amdgpu_sdma_phase_quantum; 352 unsigned unit = 0; 353 354 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 355 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 356 value = (value + 1) >> 1; 357 unit++; 358 } 359 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 360 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 361 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 362 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 363 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 364 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 365 WARN_ONCE(1, 366 "clamping sdma_phase_quantum to %uK clock cycles\n", 367 value << unit); 368 } 369 phase_quantum = 370 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 371 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 372 } 373 374 for (i = 0; i < adev->sdma.num_instances; i++) { 375 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); 376 if (enable) { 377 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 378 AUTO_CTXSW_ENABLE, 1); 379 if (amdgpu_sdma_phase_quantum) { 380 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i], 381 phase_quantum); 382 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i], 383 phase_quantum); 384 } 385 } else { 386 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 387 AUTO_CTXSW_ENABLE, 0); 388 } 389 390 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl); 391 } 392 } 393 394 /** 395 * cik_sdma_enable - stop the async dma engines 396 * 397 * @adev: amdgpu_device pointer 398 * @enable: enable/disable the DMA MEs. 399 * 400 * Halt or unhalt the async dma engines (CIK). 401 */ 402 static void cik_sdma_enable(struct amdgpu_device *adev, bool enable) 403 { 404 u32 me_cntl; 405 int i; 406 407 if (!enable) { 408 cik_sdma_gfx_stop(adev); 409 cik_sdma_rlc_stop(adev); 410 } 411 412 for (i = 0; i < adev->sdma.num_instances; i++) { 413 me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); 414 if (enable) 415 me_cntl &= ~SDMA0_F32_CNTL__HALT_MASK; 416 else 417 me_cntl |= SDMA0_F32_CNTL__HALT_MASK; 418 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl); 419 } 420 } 421 422 /** 423 * cik_sdma_gfx_resume - setup and start the async dma engines 424 * 425 * @adev: amdgpu_device pointer 426 * 427 * Set up the gfx DMA ring buffers and enable them (CIK). 428 * Returns 0 for success, error for failure. 429 */ 430 static int cik_sdma_gfx_resume(struct amdgpu_device *adev) 431 { 432 struct amdgpu_ring *ring; 433 u32 rb_cntl, ib_cntl; 434 u32 rb_bufsz; 435 u32 wb_offset; 436 int i, j, r; 437 438 for (i = 0; i < adev->sdma.num_instances; i++) { 439 ring = &adev->sdma.instance[i].ring; 440 wb_offset = (ring->rptr_offs * 4); 441 442 mutex_lock(&adev->srbm_mutex); 443 for (j = 0; j < 16; j++) { 444 cik_srbm_select(adev, 0, 0, 0, j); 445 /* SDMA GFX */ 446 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0); 447 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0); 448 /* XXX SDMA RLC - todo */ 449 } 450 cik_srbm_select(adev, 0, 0, 0, 0); 451 mutex_unlock(&adev->srbm_mutex); 452 453 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i], 454 adev->gfx.config.gb_addr_config & 0x70); 455 456 WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0); 457 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); 458 459 /* Set ring buffer size in dwords */ 460 rb_bufsz = order_base_2(ring->ring_size / 4); 461 rb_cntl = rb_bufsz << 1; 462 #ifdef __BIG_ENDIAN 463 rb_cntl |= SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK | 464 SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK; 465 #endif 466 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 467 468 /* Initialize the ring buffer's read and write pointers */ 469 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); 470 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); 471 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0); 472 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0); 473 474 /* set the wb address whether it's enabled or not */ 475 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], 476 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 477 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i], 478 ((adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC)); 479 480 rb_cntl |= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK; 481 482 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); 483 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); 484 485 ring->wptr = 0; 486 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2); 487 488 /* enable DMA RB */ 489 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], 490 rb_cntl | SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK); 491 492 ib_cntl = SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK; 493 #ifdef __BIG_ENDIAN 494 ib_cntl |= SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK; 495 #endif 496 /* enable DMA IBs */ 497 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 498 499 ring->sched.ready = true; 500 } 501 502 cik_sdma_enable(adev, true); 503 504 for (i = 0; i < adev->sdma.num_instances; i++) { 505 ring = &adev->sdma.instance[i].ring; 506 r = amdgpu_ring_test_helper(ring); 507 if (r) 508 return r; 509 510 if (adev->mman.buffer_funcs_ring == ring) 511 amdgpu_ttm_set_buffer_funcs_status(adev, true); 512 } 513 514 return 0; 515 } 516 517 /** 518 * cik_sdma_rlc_resume - setup and start the async dma engines 519 * 520 * @adev: amdgpu_device pointer 521 * 522 * Set up the compute DMA queues and enable them (CIK). 523 * Returns 0 for success, error for failure. 524 */ 525 static int cik_sdma_rlc_resume(struct amdgpu_device *adev) 526 { 527 /* XXX todo */ 528 return 0; 529 } 530 531 /** 532 * cik_sdma_load_microcode - load the sDMA ME ucode 533 * 534 * @adev: amdgpu_device pointer 535 * 536 * Loads the sDMA0/1 ucode. 537 * Returns 0 for success, -EINVAL if the ucode is not available. 538 */ 539 static int cik_sdma_load_microcode(struct amdgpu_device *adev) 540 { 541 const struct sdma_firmware_header_v1_0 *hdr; 542 const __le32 *fw_data; 543 u32 fw_size; 544 int i, j; 545 546 /* halt the MEs */ 547 cik_sdma_enable(adev, false); 548 549 for (i = 0; i < adev->sdma.num_instances; i++) { 550 if (!adev->sdma.instance[i].fw) 551 return -EINVAL; 552 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 553 amdgpu_ucode_print_sdma_hdr(&hdr->header); 554 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 555 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); 556 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); 557 if (adev->sdma.instance[i].feature_version >= 20) 558 adev->sdma.instance[i].burst_nop = true; 559 fw_data = (const __le32 *) 560 (adev->sdma.instance[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 561 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0); 562 for (j = 0; j < fw_size; j++) 563 WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++)); 564 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version); 565 } 566 567 return 0; 568 } 569 570 /** 571 * cik_sdma_start - setup and start the async dma engines 572 * 573 * @adev: amdgpu_device pointer 574 * 575 * Set up the DMA engines and enable them (CIK). 576 * Returns 0 for success, error for failure. 577 */ 578 static int cik_sdma_start(struct amdgpu_device *adev) 579 { 580 int r; 581 582 r = cik_sdma_load_microcode(adev); 583 if (r) 584 return r; 585 586 /* halt the engine before programing */ 587 cik_sdma_enable(adev, false); 588 /* enable sdma ring preemption */ 589 cik_ctx_switch_enable(adev, true); 590 591 /* start the gfx rings and rlc compute queues */ 592 r = cik_sdma_gfx_resume(adev); 593 if (r) 594 return r; 595 r = cik_sdma_rlc_resume(adev); 596 if (r) 597 return r; 598 599 return 0; 600 } 601 602 /** 603 * cik_sdma_ring_test_ring - simple async dma engine test 604 * 605 * @ring: amdgpu_ring structure holding ring information 606 * 607 * Test the DMA engine by writing using it to write an 608 * value to memory. (CIK). 609 * Returns 0 for success, error for failure. 610 */ 611 static int cik_sdma_ring_test_ring(struct amdgpu_ring *ring) 612 { 613 struct amdgpu_device *adev = ring->adev; 614 unsigned i; 615 unsigned index; 616 int r; 617 u32 tmp; 618 u64 gpu_addr; 619 620 r = amdgpu_device_wb_get(adev, &index); 621 if (r) 622 return r; 623 624 gpu_addr = adev->wb.gpu_addr + (index * 4); 625 tmp = 0xCAFEDEAD; 626 adev->wb.wb[index] = cpu_to_le32(tmp); 627 628 r = amdgpu_ring_alloc(ring, 5); 629 if (r) 630 goto error_free_wb; 631 632 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0)); 633 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 634 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 635 amdgpu_ring_write(ring, 1); /* number of DWs to follow */ 636 amdgpu_ring_write(ring, 0xDEADBEEF); 637 amdgpu_ring_commit(ring); 638 639 for (i = 0; i < adev->usec_timeout; i++) { 640 tmp = le32_to_cpu(adev->wb.wb[index]); 641 if (tmp == 0xDEADBEEF) 642 break; 643 DRM_UDELAY(1); 644 } 645 646 if (i >= adev->usec_timeout) 647 r = -ETIMEDOUT; 648 649 error_free_wb: 650 amdgpu_device_wb_free(adev, index); 651 return r; 652 } 653 654 /** 655 * cik_sdma_ring_test_ib - test an IB on the DMA engine 656 * 657 * @ring: amdgpu_ring structure holding ring information 658 * 659 * Test a simple IB in the DMA ring (CIK). 660 * Returns 0 on success, error on failure. 661 */ 662 static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring, long timeout) 663 { 664 struct amdgpu_device *adev = ring->adev; 665 struct amdgpu_ib ib; 666 struct dma_fence *f = NULL; 667 unsigned index; 668 u32 tmp = 0; 669 u64 gpu_addr; 670 long r; 671 672 r = amdgpu_device_wb_get(adev, &index); 673 if (r) 674 return r; 675 676 gpu_addr = adev->wb.gpu_addr + (index * 4); 677 tmp = 0xCAFEDEAD; 678 adev->wb.wb[index] = cpu_to_le32(tmp); 679 memset(&ib, 0, sizeof(ib)); 680 r = amdgpu_ib_get(adev, NULL, 256, &ib); 681 if (r) 682 goto err0; 683 684 ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, 685 SDMA_WRITE_SUB_OPCODE_LINEAR, 0); 686 ib.ptr[1] = lower_32_bits(gpu_addr); 687 ib.ptr[2] = upper_32_bits(gpu_addr); 688 ib.ptr[3] = 1; 689 ib.ptr[4] = 0xDEADBEEF; 690 ib.length_dw = 5; 691 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 692 if (r) 693 goto err1; 694 695 r = dma_fence_wait_timeout(f, false, timeout); 696 if (r == 0) { 697 r = -ETIMEDOUT; 698 goto err1; 699 } else if (r < 0) { 700 goto err1; 701 } 702 tmp = le32_to_cpu(adev->wb.wb[index]); 703 if (tmp == 0xDEADBEEF) 704 r = 0; 705 else 706 r = -EINVAL; 707 708 err1: 709 amdgpu_ib_free(adev, &ib, NULL); 710 dma_fence_put(f); 711 err0: 712 amdgpu_device_wb_free(adev, index); 713 return r; 714 } 715 716 /** 717 * cik_sdma_vm_copy_pages - update PTEs by copying them from the GART 718 * 719 * @ib: indirect buffer to fill with commands 720 * @pe: addr of the page entry 721 * @src: src addr to copy from 722 * @count: number of page entries to update 723 * 724 * Update PTEs by copying them from the GART using sDMA (CIK). 725 */ 726 static void cik_sdma_vm_copy_pte(struct amdgpu_ib *ib, 727 uint64_t pe, uint64_t src, 728 unsigned count) 729 { 730 unsigned bytes = count * 8; 731 732 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, 733 SDMA_WRITE_SUB_OPCODE_LINEAR, 0); 734 ib->ptr[ib->length_dw++] = bytes; 735 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 736 ib->ptr[ib->length_dw++] = lower_32_bits(src); 737 ib->ptr[ib->length_dw++] = upper_32_bits(src); 738 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 739 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 740 } 741 742 /** 743 * cik_sdma_vm_write_pages - update PTEs by writing them manually 744 * 745 * @ib: indirect buffer to fill with commands 746 * @pe: addr of the page entry 747 * @value: dst addr to write into pe 748 * @count: number of page entries to update 749 * @incr: increase next addr by incr bytes 750 * 751 * Update PTEs by writing them manually using sDMA (CIK). 752 */ 753 static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 754 uint64_t value, unsigned count, 755 uint32_t incr) 756 { 757 unsigned ndw = count * 2; 758 759 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE, 760 SDMA_WRITE_SUB_OPCODE_LINEAR, 0); 761 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 762 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 763 ib->ptr[ib->length_dw++] = ndw; 764 for (; ndw > 0; ndw -= 2) { 765 ib->ptr[ib->length_dw++] = lower_32_bits(value); 766 ib->ptr[ib->length_dw++] = upper_32_bits(value); 767 value += incr; 768 } 769 } 770 771 /** 772 * cik_sdma_vm_set_pages - update the page tables using sDMA 773 * 774 * @ib: indirect buffer to fill with commands 775 * @pe: addr of the page entry 776 * @addr: dst addr to write into pe 777 * @count: number of page entries to update 778 * @incr: increase next addr by incr bytes 779 * @flags: access flags 780 * 781 * Update the page tables using sDMA (CIK). 782 */ 783 static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe, 784 uint64_t addr, unsigned count, 785 uint32_t incr, uint64_t flags) 786 { 787 /* for physically contiguous pages (vram) */ 788 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0); 789 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 790 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 791 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 792 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 793 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 794 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 795 ib->ptr[ib->length_dw++] = incr; /* increment size */ 796 ib->ptr[ib->length_dw++] = 0; 797 ib->ptr[ib->length_dw++] = count; /* number of entries */ 798 } 799 800 /** 801 * cik_sdma_vm_pad_ib - pad the IB to the required number of dw 802 * 803 * @ib: indirect buffer to fill with padding 804 * 805 */ 806 static void cik_sdma_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 807 { 808 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 809 u32 pad_count; 810 int i; 811 812 pad_count = (8 - (ib->length_dw & 0x7)) % 8; 813 for (i = 0; i < pad_count; i++) 814 if (sdma && sdma->burst_nop && (i == 0)) 815 ib->ptr[ib->length_dw++] = 816 SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0) | 817 SDMA_NOP_COUNT(pad_count - 1); 818 else 819 ib->ptr[ib->length_dw++] = 820 SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0); 821 } 822 823 /** 824 * cik_sdma_ring_emit_pipeline_sync - sync the pipeline 825 * 826 * @ring: amdgpu_ring pointer 827 * 828 * Make sure all previous operations are completed (CIK). 829 */ 830 static void cik_sdma_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 831 { 832 uint32_t seq = ring->fence_drv.sync_seq; 833 uint64_t addr = ring->fence_drv.gpu_addr; 834 835 /* wait for idle */ 836 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, 837 SDMA_POLL_REG_MEM_EXTRA_OP(0) | 838 SDMA_POLL_REG_MEM_EXTRA_FUNC(3) | /* equal */ 839 SDMA_POLL_REG_MEM_EXTRA_M)); 840 amdgpu_ring_write(ring, addr & 0xfffffffc); 841 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 842 amdgpu_ring_write(ring, seq); /* reference */ 843 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 844 amdgpu_ring_write(ring, (0xfff << 16) | 4); /* retry count, poll interval */ 845 } 846 847 /** 848 * cik_sdma_ring_emit_vm_flush - cik vm flush using sDMA 849 * 850 * @ring: amdgpu_ring pointer 851 * @vm: amdgpu_vm pointer 852 * 853 * Update the page table base and flush the VM TLB 854 * using sDMA (CIK). 855 */ 856 static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring, 857 unsigned vmid, uint64_t pd_addr) 858 { 859 u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) | 860 SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */ 861 862 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 863 864 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); 865 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2); 866 amdgpu_ring_write(ring, 0); 867 amdgpu_ring_write(ring, 0); /* reference */ 868 amdgpu_ring_write(ring, 0); /* mask */ 869 amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */ 870 } 871 872 static void cik_sdma_ring_emit_wreg(struct amdgpu_ring *ring, 873 uint32_t reg, uint32_t val) 874 { 875 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 876 amdgpu_ring_write(ring, reg); 877 amdgpu_ring_write(ring, val); 878 } 879 880 static void cik_enable_sdma_mgcg(struct amdgpu_device *adev, 881 bool enable) 882 { 883 u32 orig, data; 884 885 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 886 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100); 887 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100); 888 } else { 889 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET); 890 data |= 0xff000000; 891 if (data != orig) 892 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data); 893 894 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET); 895 data |= 0xff000000; 896 if (data != orig) 897 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data); 898 } 899 } 900 901 static void cik_enable_sdma_mgls(struct amdgpu_device *adev, 902 bool enable) 903 { 904 u32 orig, data; 905 906 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 907 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET); 908 data |= 0x100; 909 if (orig != data) 910 WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data); 911 912 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET); 913 data |= 0x100; 914 if (orig != data) 915 WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); 916 } else { 917 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET); 918 data &= ~0x100; 919 if (orig != data) 920 WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data); 921 922 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET); 923 data &= ~0x100; 924 if (orig != data) 925 WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); 926 } 927 } 928 929 static int cik_sdma_early_init(void *handle) 930 { 931 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 932 933 adev->sdma.num_instances = SDMA_MAX_INSTANCE; 934 935 cik_sdma_set_ring_funcs(adev); 936 cik_sdma_set_irq_funcs(adev); 937 cik_sdma_set_buffer_funcs(adev); 938 cik_sdma_set_vm_pte_funcs(adev); 939 940 return 0; 941 } 942 943 static int cik_sdma_sw_init(void *handle) 944 { 945 struct amdgpu_ring *ring; 946 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 947 int r, i; 948 949 r = cik_sdma_init_microcode(adev); 950 if (r) { 951 DRM_ERROR("Failed to load sdma firmware!\n"); 952 return r; 953 } 954 955 /* SDMA trap event */ 956 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 224, 957 &adev->sdma.trap_irq); 958 if (r) 959 return r; 960 961 /* SDMA Privileged inst */ 962 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 241, 963 &adev->sdma.illegal_inst_irq); 964 if (r) 965 return r; 966 967 /* SDMA Privileged inst */ 968 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 247, 969 &adev->sdma.illegal_inst_irq); 970 if (r) 971 return r; 972 973 for (i = 0; i < adev->sdma.num_instances; i++) { 974 ring = &adev->sdma.instance[i].ring; 975 ring->ring_obj = NULL; 976 sprintf(ring->name, "sdma%d", i); 977 r = amdgpu_ring_init(adev, ring, 1024, 978 &adev->sdma.trap_irq, 979 (i == 0) ? 980 AMDGPU_SDMA_IRQ_INSTANCE0 : 981 AMDGPU_SDMA_IRQ_INSTANCE1); 982 if (r) 983 return r; 984 } 985 986 return r; 987 } 988 989 static int cik_sdma_sw_fini(void *handle) 990 { 991 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 992 int i; 993 994 for (i = 0; i < adev->sdma.num_instances; i++) 995 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 996 997 cik_sdma_free_microcode(adev); 998 return 0; 999 } 1000 1001 static int cik_sdma_hw_init(void *handle) 1002 { 1003 int r; 1004 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1005 1006 r = cik_sdma_start(adev); 1007 if (r) 1008 return r; 1009 1010 return r; 1011 } 1012 1013 static int cik_sdma_hw_fini(void *handle) 1014 { 1015 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1016 1017 cik_ctx_switch_enable(adev, false); 1018 cik_sdma_enable(adev, false); 1019 1020 return 0; 1021 } 1022 1023 static int cik_sdma_suspend(void *handle) 1024 { 1025 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1026 1027 return cik_sdma_hw_fini(adev); 1028 } 1029 1030 static int cik_sdma_resume(void *handle) 1031 { 1032 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1033 1034 cik_sdma_soft_reset(handle); 1035 1036 return cik_sdma_hw_init(adev); 1037 } 1038 1039 static bool cik_sdma_is_idle(void *handle) 1040 { 1041 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1042 u32 tmp = RREG32(mmSRBM_STATUS2); 1043 1044 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK | 1045 SRBM_STATUS2__SDMA1_BUSY_MASK)) 1046 return false; 1047 1048 return true; 1049 } 1050 1051 static int cik_sdma_wait_for_idle(void *handle) 1052 { 1053 unsigned i; 1054 u32 tmp; 1055 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1056 1057 for (i = 0; i < adev->usec_timeout; i++) { 1058 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | 1059 SRBM_STATUS2__SDMA1_BUSY_MASK); 1060 1061 if (!tmp) 1062 return 0; 1063 udelay(1); 1064 } 1065 return -ETIMEDOUT; 1066 } 1067 1068 static int cik_sdma_soft_reset(void *handle) 1069 { 1070 u32 srbm_soft_reset = 0; 1071 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1072 u32 tmp = RREG32(mmSRBM_STATUS2); 1073 1074 if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) { 1075 /* sdma0 */ 1076 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); 1077 tmp |= SDMA0_F32_CNTL__HALT_MASK; 1078 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); 1079 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK; 1080 } 1081 if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) { 1082 /* sdma1 */ 1083 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); 1084 tmp |= SDMA0_F32_CNTL__HALT_MASK; 1085 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); 1086 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK; 1087 } 1088 1089 if (srbm_soft_reset) { 1090 tmp = RREG32(mmSRBM_SOFT_RESET); 1091 tmp |= srbm_soft_reset; 1092 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1093 WREG32(mmSRBM_SOFT_RESET, tmp); 1094 tmp = RREG32(mmSRBM_SOFT_RESET); 1095 1096 udelay(50); 1097 1098 tmp &= ~srbm_soft_reset; 1099 WREG32(mmSRBM_SOFT_RESET, tmp); 1100 tmp = RREG32(mmSRBM_SOFT_RESET); 1101 1102 /* Wait a little for things to settle down */ 1103 udelay(50); 1104 } 1105 1106 return 0; 1107 } 1108 1109 static int cik_sdma_set_trap_irq_state(struct amdgpu_device *adev, 1110 struct amdgpu_irq_src *src, 1111 unsigned type, 1112 enum amdgpu_interrupt_state state) 1113 { 1114 u32 sdma_cntl; 1115 1116 switch (type) { 1117 case AMDGPU_SDMA_IRQ_INSTANCE0: 1118 switch (state) { 1119 case AMDGPU_IRQ_STATE_DISABLE: 1120 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1121 sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK; 1122 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1123 break; 1124 case AMDGPU_IRQ_STATE_ENABLE: 1125 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1126 sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK; 1127 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1128 break; 1129 default: 1130 break; 1131 } 1132 break; 1133 case AMDGPU_SDMA_IRQ_INSTANCE1: 1134 switch (state) { 1135 case AMDGPU_IRQ_STATE_DISABLE: 1136 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1137 sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK; 1138 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1139 break; 1140 case AMDGPU_IRQ_STATE_ENABLE: 1141 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1142 sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK; 1143 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1144 break; 1145 default: 1146 break; 1147 } 1148 break; 1149 default: 1150 break; 1151 } 1152 return 0; 1153 } 1154 1155 static int cik_sdma_process_trap_irq(struct amdgpu_device *adev, 1156 struct amdgpu_irq_src *source, 1157 struct amdgpu_iv_entry *entry) 1158 { 1159 u8 instance_id, queue_id; 1160 1161 instance_id = (entry->ring_id & 0x3) >> 0; 1162 queue_id = (entry->ring_id & 0xc) >> 2; 1163 DRM_DEBUG("IH: SDMA trap\n"); 1164 switch (instance_id) { 1165 case 0: 1166 switch (queue_id) { 1167 case 0: 1168 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1169 break; 1170 case 1: 1171 /* XXX compute */ 1172 break; 1173 case 2: 1174 /* XXX compute */ 1175 break; 1176 } 1177 break; 1178 case 1: 1179 switch (queue_id) { 1180 case 0: 1181 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1182 break; 1183 case 1: 1184 /* XXX compute */ 1185 break; 1186 case 2: 1187 /* XXX compute */ 1188 break; 1189 } 1190 break; 1191 } 1192 1193 return 0; 1194 } 1195 1196 static int cik_sdma_process_illegal_inst_irq(struct amdgpu_device *adev, 1197 struct amdgpu_irq_src *source, 1198 struct amdgpu_iv_entry *entry) 1199 { 1200 u8 instance_id; 1201 1202 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1203 instance_id = (entry->ring_id & 0x3) >> 0; 1204 drm_sched_fault(&adev->sdma.instance[instance_id].ring.sched); 1205 return 0; 1206 } 1207 1208 static int cik_sdma_set_clockgating_state(void *handle, 1209 enum amd_clockgating_state state) 1210 { 1211 bool gate = false; 1212 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1213 1214 if (state == AMD_CG_STATE_GATE) 1215 gate = true; 1216 1217 cik_enable_sdma_mgcg(adev, gate); 1218 cik_enable_sdma_mgls(adev, gate); 1219 1220 return 0; 1221 } 1222 1223 static int cik_sdma_set_powergating_state(void *handle, 1224 enum amd_powergating_state state) 1225 { 1226 return 0; 1227 } 1228 1229 static const struct amd_ip_funcs cik_sdma_ip_funcs = { 1230 .name = "cik_sdma", 1231 .early_init = cik_sdma_early_init, 1232 .late_init = NULL, 1233 .sw_init = cik_sdma_sw_init, 1234 .sw_fini = cik_sdma_sw_fini, 1235 .hw_init = cik_sdma_hw_init, 1236 .hw_fini = cik_sdma_hw_fini, 1237 .suspend = cik_sdma_suspend, 1238 .resume = cik_sdma_resume, 1239 .is_idle = cik_sdma_is_idle, 1240 .wait_for_idle = cik_sdma_wait_for_idle, 1241 .soft_reset = cik_sdma_soft_reset, 1242 .set_clockgating_state = cik_sdma_set_clockgating_state, 1243 .set_powergating_state = cik_sdma_set_powergating_state, 1244 }; 1245 1246 static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = { 1247 .type = AMDGPU_RING_TYPE_SDMA, 1248 .align_mask = 0xf, 1249 .nop = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), 1250 .support_64bit_ptrs = false, 1251 .get_rptr = cik_sdma_ring_get_rptr, 1252 .get_wptr = cik_sdma_ring_get_wptr, 1253 .set_wptr = cik_sdma_ring_set_wptr, 1254 .emit_frame_size = 1255 6 + /* cik_sdma_ring_emit_hdp_flush */ 1256 3 + /* hdp invalidate */ 1257 6 + /* cik_sdma_ring_emit_pipeline_sync */ 1258 CIK_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* cik_sdma_ring_emit_vm_flush */ 1259 9 + 9 + 9, /* cik_sdma_ring_emit_fence x3 for user fence, vm fence */ 1260 .emit_ib_size = 7 + 4, /* cik_sdma_ring_emit_ib */ 1261 .emit_ib = cik_sdma_ring_emit_ib, 1262 .emit_fence = cik_sdma_ring_emit_fence, 1263 .emit_pipeline_sync = cik_sdma_ring_emit_pipeline_sync, 1264 .emit_vm_flush = cik_sdma_ring_emit_vm_flush, 1265 .emit_hdp_flush = cik_sdma_ring_emit_hdp_flush, 1266 .test_ring = cik_sdma_ring_test_ring, 1267 .test_ib = cik_sdma_ring_test_ib, 1268 .insert_nop = cik_sdma_ring_insert_nop, 1269 .pad_ib = cik_sdma_ring_pad_ib, 1270 .emit_wreg = cik_sdma_ring_emit_wreg, 1271 }; 1272 1273 static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev) 1274 { 1275 int i; 1276 1277 for (i = 0; i < adev->sdma.num_instances; i++) { 1278 adev->sdma.instance[i].ring.funcs = &cik_sdma_ring_funcs; 1279 adev->sdma.instance[i].ring.me = i; 1280 } 1281 } 1282 1283 static const struct amdgpu_irq_src_funcs cik_sdma_trap_irq_funcs = { 1284 .set = cik_sdma_set_trap_irq_state, 1285 .process = cik_sdma_process_trap_irq, 1286 }; 1287 1288 static const struct amdgpu_irq_src_funcs cik_sdma_illegal_inst_irq_funcs = { 1289 .process = cik_sdma_process_illegal_inst_irq, 1290 }; 1291 1292 static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev) 1293 { 1294 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 1295 adev->sdma.trap_irq.funcs = &cik_sdma_trap_irq_funcs; 1296 adev->sdma.illegal_inst_irq.funcs = &cik_sdma_illegal_inst_irq_funcs; 1297 } 1298 1299 /** 1300 * cik_sdma_emit_copy_buffer - copy buffer using the sDMA engine 1301 * 1302 * @ring: amdgpu_ring structure holding ring information 1303 * @src_offset: src GPU address 1304 * @dst_offset: dst GPU address 1305 * @byte_count: number of bytes to xfer 1306 * 1307 * Copy GPU buffers using the DMA engine (CIK). 1308 * Used by the amdgpu ttm implementation to move pages if 1309 * registered as the asic copy callback. 1310 */ 1311 static void cik_sdma_emit_copy_buffer(struct amdgpu_ib *ib, 1312 uint64_t src_offset, 1313 uint64_t dst_offset, 1314 uint32_t byte_count) 1315 { 1316 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0); 1317 ib->ptr[ib->length_dw++] = byte_count; 1318 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1319 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1320 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1321 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1322 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1323 } 1324 1325 /** 1326 * cik_sdma_emit_fill_buffer - fill buffer using the sDMA engine 1327 * 1328 * @ring: amdgpu_ring structure holding ring information 1329 * @src_data: value to write to buffer 1330 * @dst_offset: dst GPU address 1331 * @byte_count: number of bytes to xfer 1332 * 1333 * Fill GPU buffers using the DMA engine (CIK). 1334 */ 1335 static void cik_sdma_emit_fill_buffer(struct amdgpu_ib *ib, 1336 uint32_t src_data, 1337 uint64_t dst_offset, 1338 uint32_t byte_count) 1339 { 1340 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, 0); 1341 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1342 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1343 ib->ptr[ib->length_dw++] = src_data; 1344 ib->ptr[ib->length_dw++] = byte_count; 1345 } 1346 1347 static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs = { 1348 .copy_max_bytes = 0x1fffff, 1349 .copy_num_dw = 7, 1350 .emit_copy_buffer = cik_sdma_emit_copy_buffer, 1351 1352 .fill_max_bytes = 0x1fffff, 1353 .fill_num_dw = 5, 1354 .emit_fill_buffer = cik_sdma_emit_fill_buffer, 1355 }; 1356 1357 static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev) 1358 { 1359 adev->mman.buffer_funcs = &cik_sdma_buffer_funcs; 1360 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1361 } 1362 1363 static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = { 1364 .copy_pte_num_dw = 7, 1365 .copy_pte = cik_sdma_vm_copy_pte, 1366 1367 .write_pte = cik_sdma_vm_write_pte, 1368 .set_pte_pde = cik_sdma_vm_set_pte_pde, 1369 }; 1370 1371 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev) 1372 { 1373 struct drm_gpu_scheduler *sched; 1374 unsigned i; 1375 1376 adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs; 1377 for (i = 0; i < adev->sdma.num_instances; i++) { 1378 sched = &adev->sdma.instance[i].ring.sched; 1379 adev->vm_manager.vm_pte_rqs[i] = 1380 &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL]; 1381 } 1382 adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances; 1383 } 1384 1385 const struct amdgpu_ip_block_version cik_sdma_ip_block = 1386 { 1387 .type = AMD_IP_BLOCK_TYPE_SDMA, 1388 .major = 2, 1389 .minor = 0, 1390 .rev = 0, 1391 .funcs = &cik_sdma_ip_funcs, 1392 }; 1393