1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_ucode.h" 30 #include "amdgpu_trace.h" 31 #include "cikd.h" 32 #include "cik.h" 33 34 #include "bif/bif_4_1_d.h" 35 #include "bif/bif_4_1_sh_mask.h" 36 37 #include "gca/gfx_7_2_d.h" 38 #include "gca/gfx_7_2_enum.h" 39 #include "gca/gfx_7_2_sh_mask.h" 40 41 #include "gmc/gmc_7_1_d.h" 42 #include "gmc/gmc_7_1_sh_mask.h" 43 44 #include "oss/oss_2_0_d.h" 45 #include "oss/oss_2_0_sh_mask.h" 46 47 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = 48 { 49 SDMA0_REGISTER_OFFSET, 50 SDMA1_REGISTER_OFFSET 51 }; 52 53 static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev); 54 static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev); 55 static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev); 56 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev); 57 static int cik_sdma_soft_reset(void *handle); 58 59 MODULE_FIRMWARE("amdgpu/bonaire_sdma.bin"); 60 MODULE_FIRMWARE("amdgpu/bonaire_sdma1.bin"); 61 MODULE_FIRMWARE("amdgpu/hawaii_sdma.bin"); 62 MODULE_FIRMWARE("amdgpu/hawaii_sdma1.bin"); 63 MODULE_FIRMWARE("amdgpu/kaveri_sdma.bin"); 64 MODULE_FIRMWARE("amdgpu/kaveri_sdma1.bin"); 65 MODULE_FIRMWARE("amdgpu/kabini_sdma.bin"); 66 MODULE_FIRMWARE("amdgpu/kabini_sdma1.bin"); 67 MODULE_FIRMWARE("amdgpu/mullins_sdma.bin"); 68 MODULE_FIRMWARE("amdgpu/mullins_sdma1.bin"); 69 70 u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev); 71 72 73 static void cik_sdma_free_microcode(struct amdgpu_device *adev) 74 { 75 int i; 76 for (i = 0; i < adev->sdma.num_instances; i++) { 77 release_firmware(adev->sdma.instance[i].fw); 78 adev->sdma.instance[i].fw = NULL; 79 } 80 } 81 82 /* 83 * sDMA - System DMA 84 * Starting with CIK, the GPU has new asynchronous 85 * DMA engines. These engines are used for compute 86 * and gfx. There are two DMA engines (SDMA0, SDMA1) 87 * and each one supports 1 ring buffer used for gfx 88 * and 2 queues used for compute. 89 * 90 * The programming model is very similar to the CP 91 * (ring buffer, IBs, etc.), but sDMA has it's own 92 * packet format that is different from the PM4 format 93 * used by the CP. sDMA supports copying data, writing 94 * embedded data, solid fills, and a number of other 95 * things. It also has support for tiling/detiling of 96 * buffers. 97 */ 98 99 /** 100 * cik_sdma_init_microcode - load ucode images from disk 101 * 102 * @adev: amdgpu_device pointer 103 * 104 * Use the firmware interface to load the ucode images into 105 * the driver (not loaded into hw). 106 * Returns 0 on success, error on failure. 107 */ 108 static int cik_sdma_init_microcode(struct amdgpu_device *adev) 109 { 110 const char *chip_name; 111 char fw_name[30]; 112 int err = 0, i; 113 114 DRM_DEBUG("\n"); 115 116 switch (adev->asic_type) { 117 case CHIP_BONAIRE: 118 chip_name = "bonaire"; 119 break; 120 case CHIP_HAWAII: 121 chip_name = "hawaii"; 122 break; 123 case CHIP_KAVERI: 124 chip_name = "kaveri"; 125 break; 126 case CHIP_KABINI: 127 chip_name = "kabini"; 128 break; 129 case CHIP_MULLINS: 130 chip_name = "mullins"; 131 break; 132 default: BUG(); 133 } 134 135 for (i = 0; i < adev->sdma.num_instances; i++) { 136 if (i == 0) 137 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 138 else 139 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); 140 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); 141 if (err) 142 goto out; 143 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); 144 } 145 out: 146 if (err) { 147 pr_err("cik_sdma: Failed to load firmware \"%s\"\n", fw_name); 148 for (i = 0; i < adev->sdma.num_instances; i++) { 149 release_firmware(adev->sdma.instance[i].fw); 150 adev->sdma.instance[i].fw = NULL; 151 } 152 } 153 return err; 154 } 155 156 /** 157 * cik_sdma_ring_get_rptr - get the current read pointer 158 * 159 * @ring: amdgpu ring pointer 160 * 161 * Get the current rptr from the hardware (CIK+). 162 */ 163 static uint64_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring) 164 { 165 u32 rptr; 166 167 rptr = *ring->rptr_cpu_addr; 168 169 return (rptr & 0x3fffc) >> 2; 170 } 171 172 /** 173 * cik_sdma_ring_get_wptr - get the current write pointer 174 * 175 * @ring: amdgpu ring pointer 176 * 177 * Get the current wptr from the hardware (CIK+). 178 */ 179 static uint64_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring) 180 { 181 struct amdgpu_device *adev = ring->adev; 182 183 return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) & 0x3fffc) >> 2; 184 } 185 186 /** 187 * cik_sdma_ring_set_wptr - commit the write pointer 188 * 189 * @ring: amdgpu ring pointer 190 * 191 * Write the wptr back to the hardware (CIK+). 192 */ 193 static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring) 194 { 195 struct amdgpu_device *adev = ring->adev; 196 197 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], 198 (ring->wptr << 2) & 0x3fffc); 199 } 200 201 static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 202 { 203 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 204 int i; 205 206 for (i = 0; i < count; i++) 207 if (sdma && sdma->burst_nop && (i == 0)) 208 amdgpu_ring_write(ring, ring->funcs->nop | 209 SDMA_NOP_COUNT(count - 1)); 210 else 211 amdgpu_ring_write(ring, ring->funcs->nop); 212 } 213 214 /** 215 * cik_sdma_ring_emit_ib - Schedule an IB on the DMA engine 216 * 217 * @ring: amdgpu ring pointer 218 * @job: job to retrive vmid from 219 * @ib: IB object to schedule 220 * @flags: unused 221 * 222 * Schedule an IB in the DMA ring (CIK). 223 */ 224 static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring, 225 struct amdgpu_job *job, 226 struct amdgpu_ib *ib, 227 uint32_t flags) 228 { 229 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 230 u32 extra_bits = vmid & 0xf; 231 232 /* IB packet must end on a 8 DW boundary */ 233 cik_sdma_ring_insert_nop(ring, (4 - lower_32_bits(ring->wptr)) & 7); 234 235 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits)); 236 amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */ 237 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff); 238 amdgpu_ring_write(ring, ib->length_dw); 239 240 } 241 242 /** 243 * cik_sdma_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 244 * 245 * @ring: amdgpu ring pointer 246 * 247 * Emit an hdp flush packet on the requested DMA ring. 248 */ 249 static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring *ring) 250 { 251 u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) | 252 SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */ 253 u32 ref_and_mask; 254 255 if (ring->me == 0) 256 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK; 257 else 258 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK; 259 260 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); 261 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); 262 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2); 263 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 264 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 265 amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */ 266 } 267 268 /** 269 * cik_sdma_ring_emit_fence - emit a fence on the DMA ring 270 * 271 * @ring: amdgpu ring pointer 272 * @addr: address 273 * @seq: sequence number 274 * @flags: fence related flags 275 * 276 * Add a DMA fence packet to the ring to write 277 * the fence seq number and DMA trap packet to generate 278 * an interrupt if needed (CIK). 279 */ 280 static void cik_sdma_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 281 unsigned flags) 282 { 283 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 284 /* write the fence */ 285 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0)); 286 amdgpu_ring_write(ring, lower_32_bits(addr)); 287 amdgpu_ring_write(ring, upper_32_bits(addr)); 288 amdgpu_ring_write(ring, lower_32_bits(seq)); 289 290 /* optionally write high bits as well */ 291 if (write64bit) { 292 addr += 4; 293 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0)); 294 amdgpu_ring_write(ring, lower_32_bits(addr)); 295 amdgpu_ring_write(ring, upper_32_bits(addr)); 296 amdgpu_ring_write(ring, upper_32_bits(seq)); 297 } 298 299 /* generate an interrupt */ 300 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0)); 301 } 302 303 /** 304 * cik_sdma_gfx_stop - stop the gfx async dma engines 305 * 306 * @adev: amdgpu_device pointer 307 * 308 * Stop the gfx async dma ring buffers (CIK). 309 */ 310 static void cik_sdma_gfx_stop(struct amdgpu_device *adev) 311 { 312 u32 rb_cntl; 313 int i; 314 315 amdgpu_sdma_unset_buffer_funcs_helper(adev); 316 317 for (i = 0; i < adev->sdma.num_instances; i++) { 318 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 319 rb_cntl &= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK; 320 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 321 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0); 322 } 323 } 324 325 /** 326 * cik_sdma_rlc_stop - stop the compute async dma engines 327 * 328 * @adev: amdgpu_device pointer 329 * 330 * Stop the compute async dma queues (CIK). 331 */ 332 static void cik_sdma_rlc_stop(struct amdgpu_device *adev) 333 { 334 /* XXX todo */ 335 } 336 337 /** 338 * cik_ctx_switch_enable - stop the async dma engines context switch 339 * 340 * @adev: amdgpu_device pointer 341 * @enable: enable/disable the DMA MEs context switch. 342 * 343 * Halt or unhalt the async dma engines context switch (VI). 344 */ 345 static void cik_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 346 { 347 u32 f32_cntl, phase_quantum = 0; 348 int i; 349 350 if (amdgpu_sdma_phase_quantum) { 351 unsigned value = amdgpu_sdma_phase_quantum; 352 unsigned unit = 0; 353 354 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 355 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 356 value = (value + 1) >> 1; 357 unit++; 358 } 359 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 360 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 361 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 362 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 363 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 364 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 365 WARN_ONCE(1, 366 "clamping sdma_phase_quantum to %uK clock cycles\n", 367 value << unit); 368 } 369 phase_quantum = 370 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 371 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 372 } 373 374 for (i = 0; i < adev->sdma.num_instances; i++) { 375 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); 376 if (enable) { 377 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 378 AUTO_CTXSW_ENABLE, 1); 379 if (amdgpu_sdma_phase_quantum) { 380 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i], 381 phase_quantum); 382 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i], 383 phase_quantum); 384 } 385 } else { 386 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 387 AUTO_CTXSW_ENABLE, 0); 388 } 389 390 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl); 391 } 392 } 393 394 /** 395 * cik_sdma_enable - stop the async dma engines 396 * 397 * @adev: amdgpu_device pointer 398 * @enable: enable/disable the DMA MEs. 399 * 400 * Halt or unhalt the async dma engines (CIK). 401 */ 402 static void cik_sdma_enable(struct amdgpu_device *adev, bool enable) 403 { 404 u32 me_cntl; 405 int i; 406 407 if (!enable) { 408 cik_sdma_gfx_stop(adev); 409 cik_sdma_rlc_stop(adev); 410 } 411 412 for (i = 0; i < adev->sdma.num_instances; i++) { 413 me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); 414 if (enable) 415 me_cntl &= ~SDMA0_F32_CNTL__HALT_MASK; 416 else 417 me_cntl |= SDMA0_F32_CNTL__HALT_MASK; 418 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl); 419 } 420 } 421 422 /** 423 * cik_sdma_gfx_resume - setup and start the async dma engines 424 * 425 * @adev: amdgpu_device pointer 426 * 427 * Set up the gfx DMA ring buffers and enable them (CIK). 428 * Returns 0 for success, error for failure. 429 */ 430 static int cik_sdma_gfx_resume(struct amdgpu_device *adev) 431 { 432 struct amdgpu_ring *ring; 433 u32 rb_cntl, ib_cntl; 434 u32 rb_bufsz; 435 int i, j, r; 436 437 for (i = 0; i < adev->sdma.num_instances; i++) { 438 ring = &adev->sdma.instance[i].ring; 439 440 mutex_lock(&adev->srbm_mutex); 441 for (j = 0; j < 16; j++) { 442 cik_srbm_select(adev, 0, 0, 0, j); 443 /* SDMA GFX */ 444 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0); 445 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0); 446 /* XXX SDMA RLC - todo */ 447 } 448 cik_srbm_select(adev, 0, 0, 0, 0); 449 mutex_unlock(&adev->srbm_mutex); 450 451 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i], 452 adev->gfx.config.gb_addr_config & 0x70); 453 454 WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0); 455 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); 456 457 /* Set ring buffer size in dwords */ 458 rb_bufsz = order_base_2(ring->ring_size / 4); 459 rb_cntl = rb_bufsz << 1; 460 #ifdef __BIG_ENDIAN 461 rb_cntl |= SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK | 462 SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK; 463 #endif 464 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 465 466 /* Initialize the ring buffer's read and write pointers */ 467 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); 468 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); 469 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0); 470 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0); 471 472 /* set the wb address whether it's enabled or not */ 473 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], 474 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); 475 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i], 476 ((ring->rptr_gpu_addr) & 0xFFFFFFFC)); 477 478 rb_cntl |= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK; 479 480 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); 481 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); 482 483 ring->wptr = 0; 484 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2); 485 486 /* enable DMA RB */ 487 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], 488 rb_cntl | SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK); 489 490 ib_cntl = SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK; 491 #ifdef __BIG_ENDIAN 492 ib_cntl |= SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK; 493 #endif 494 /* enable DMA IBs */ 495 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 496 497 ring->sched.ready = true; 498 } 499 500 cik_sdma_enable(adev, true); 501 502 for (i = 0; i < adev->sdma.num_instances; i++) { 503 ring = &adev->sdma.instance[i].ring; 504 r = amdgpu_ring_test_helper(ring); 505 if (r) 506 return r; 507 508 if (adev->mman.buffer_funcs_ring == ring) 509 amdgpu_ttm_set_buffer_funcs_status(adev, true); 510 } 511 512 return 0; 513 } 514 515 /** 516 * cik_sdma_rlc_resume - setup and start the async dma engines 517 * 518 * @adev: amdgpu_device pointer 519 * 520 * Set up the compute DMA queues and enable them (CIK). 521 * Returns 0 for success, error for failure. 522 */ 523 static int cik_sdma_rlc_resume(struct amdgpu_device *adev) 524 { 525 /* XXX todo */ 526 return 0; 527 } 528 529 /** 530 * cik_sdma_load_microcode - load the sDMA ME ucode 531 * 532 * @adev: amdgpu_device pointer 533 * 534 * Loads the sDMA0/1 ucode. 535 * Returns 0 for success, -EINVAL if the ucode is not available. 536 */ 537 static int cik_sdma_load_microcode(struct amdgpu_device *adev) 538 { 539 const struct sdma_firmware_header_v1_0 *hdr; 540 const __le32 *fw_data; 541 u32 fw_size; 542 int i, j; 543 544 /* halt the MEs */ 545 cik_sdma_enable(adev, false); 546 547 for (i = 0; i < adev->sdma.num_instances; i++) { 548 if (!adev->sdma.instance[i].fw) 549 return -EINVAL; 550 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 551 amdgpu_ucode_print_sdma_hdr(&hdr->header); 552 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 553 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); 554 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); 555 if (adev->sdma.instance[i].feature_version >= 20) 556 adev->sdma.instance[i].burst_nop = true; 557 fw_data = (const __le32 *) 558 (adev->sdma.instance[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 559 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0); 560 for (j = 0; j < fw_size; j++) 561 WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++)); 562 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version); 563 } 564 565 return 0; 566 } 567 568 /** 569 * cik_sdma_start - setup and start the async dma engines 570 * 571 * @adev: amdgpu_device pointer 572 * 573 * Set up the DMA engines and enable them (CIK). 574 * Returns 0 for success, error for failure. 575 */ 576 static int cik_sdma_start(struct amdgpu_device *adev) 577 { 578 int r; 579 580 r = cik_sdma_load_microcode(adev); 581 if (r) 582 return r; 583 584 /* halt the engine before programing */ 585 cik_sdma_enable(adev, false); 586 /* enable sdma ring preemption */ 587 cik_ctx_switch_enable(adev, true); 588 589 /* start the gfx rings and rlc compute queues */ 590 r = cik_sdma_gfx_resume(adev); 591 if (r) 592 return r; 593 r = cik_sdma_rlc_resume(adev); 594 if (r) 595 return r; 596 597 return 0; 598 } 599 600 /** 601 * cik_sdma_ring_test_ring - simple async dma engine test 602 * 603 * @ring: amdgpu_ring structure holding ring information 604 * 605 * Test the DMA engine by writing using it to write an 606 * value to memory. (CIK). 607 * Returns 0 for success, error for failure. 608 */ 609 static int cik_sdma_ring_test_ring(struct amdgpu_ring *ring) 610 { 611 struct amdgpu_device *adev = ring->adev; 612 unsigned i; 613 unsigned index; 614 int r; 615 u32 tmp; 616 u64 gpu_addr; 617 618 r = amdgpu_device_wb_get(adev, &index); 619 if (r) 620 return r; 621 622 gpu_addr = adev->wb.gpu_addr + (index * 4); 623 tmp = 0xCAFEDEAD; 624 adev->wb.wb[index] = cpu_to_le32(tmp); 625 626 r = amdgpu_ring_alloc(ring, 5); 627 if (r) 628 goto error_free_wb; 629 630 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0)); 631 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 632 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 633 amdgpu_ring_write(ring, 1); /* number of DWs to follow */ 634 amdgpu_ring_write(ring, 0xDEADBEEF); 635 amdgpu_ring_commit(ring); 636 637 for (i = 0; i < adev->usec_timeout; i++) { 638 tmp = le32_to_cpu(adev->wb.wb[index]); 639 if (tmp == 0xDEADBEEF) 640 break; 641 udelay(1); 642 } 643 644 if (i >= adev->usec_timeout) 645 r = -ETIMEDOUT; 646 647 error_free_wb: 648 amdgpu_device_wb_free(adev, index); 649 return r; 650 } 651 652 /** 653 * cik_sdma_ring_test_ib - test an IB on the DMA engine 654 * 655 * @ring: amdgpu_ring structure holding ring information 656 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 657 * 658 * Test a simple IB in the DMA ring (CIK). 659 * Returns 0 on success, error on failure. 660 */ 661 static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring, long timeout) 662 { 663 struct amdgpu_device *adev = ring->adev; 664 struct amdgpu_ib ib; 665 struct dma_fence *f = NULL; 666 unsigned index; 667 u32 tmp = 0; 668 u64 gpu_addr; 669 long r; 670 671 r = amdgpu_device_wb_get(adev, &index); 672 if (r) 673 return r; 674 675 gpu_addr = adev->wb.gpu_addr + (index * 4); 676 tmp = 0xCAFEDEAD; 677 adev->wb.wb[index] = cpu_to_le32(tmp); 678 memset(&ib, 0, sizeof(ib)); 679 r = amdgpu_ib_get(adev, NULL, 256, 680 AMDGPU_IB_POOL_DIRECT, &ib); 681 if (r) 682 goto err0; 683 684 ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, 685 SDMA_WRITE_SUB_OPCODE_LINEAR, 0); 686 ib.ptr[1] = lower_32_bits(gpu_addr); 687 ib.ptr[2] = upper_32_bits(gpu_addr); 688 ib.ptr[3] = 1; 689 ib.ptr[4] = 0xDEADBEEF; 690 ib.length_dw = 5; 691 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 692 if (r) 693 goto err1; 694 695 r = dma_fence_wait_timeout(f, false, timeout); 696 if (r == 0) { 697 r = -ETIMEDOUT; 698 goto err1; 699 } else if (r < 0) { 700 goto err1; 701 } 702 tmp = le32_to_cpu(adev->wb.wb[index]); 703 if (tmp == 0xDEADBEEF) 704 r = 0; 705 else 706 r = -EINVAL; 707 708 err1: 709 amdgpu_ib_free(adev, &ib, NULL); 710 dma_fence_put(f); 711 err0: 712 amdgpu_device_wb_free(adev, index); 713 return r; 714 } 715 716 /** 717 * cik_sdma_vm_copy_pte - update PTEs by copying them from the GART 718 * 719 * @ib: indirect buffer to fill with commands 720 * @pe: addr of the page entry 721 * @src: src addr to copy from 722 * @count: number of page entries to update 723 * 724 * Update PTEs by copying them from the GART using sDMA (CIK). 725 */ 726 static void cik_sdma_vm_copy_pte(struct amdgpu_ib *ib, 727 uint64_t pe, uint64_t src, 728 unsigned count) 729 { 730 unsigned bytes = count * 8; 731 732 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, 733 SDMA_WRITE_SUB_OPCODE_LINEAR, 0); 734 ib->ptr[ib->length_dw++] = bytes; 735 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 736 ib->ptr[ib->length_dw++] = lower_32_bits(src); 737 ib->ptr[ib->length_dw++] = upper_32_bits(src); 738 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 739 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 740 } 741 742 /** 743 * cik_sdma_vm_write_pte - update PTEs by writing them manually 744 * 745 * @ib: indirect buffer to fill with commands 746 * @pe: addr of the page entry 747 * @value: dst addr to write into pe 748 * @count: number of page entries to update 749 * @incr: increase next addr by incr bytes 750 * 751 * Update PTEs by writing them manually using sDMA (CIK). 752 */ 753 static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 754 uint64_t value, unsigned count, 755 uint32_t incr) 756 { 757 unsigned ndw = count * 2; 758 759 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE, 760 SDMA_WRITE_SUB_OPCODE_LINEAR, 0); 761 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 762 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 763 ib->ptr[ib->length_dw++] = ndw; 764 for (; ndw > 0; ndw -= 2) { 765 ib->ptr[ib->length_dw++] = lower_32_bits(value); 766 ib->ptr[ib->length_dw++] = upper_32_bits(value); 767 value += incr; 768 } 769 } 770 771 /** 772 * cik_sdma_vm_set_pte_pde - update the page tables using sDMA 773 * 774 * @ib: indirect buffer to fill with commands 775 * @pe: addr of the page entry 776 * @addr: dst addr to write into pe 777 * @count: number of page entries to update 778 * @incr: increase next addr by incr bytes 779 * @flags: access flags 780 * 781 * Update the page tables using sDMA (CIK). 782 */ 783 static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe, 784 uint64_t addr, unsigned count, 785 uint32_t incr, uint64_t flags) 786 { 787 /* for physically contiguous pages (vram) */ 788 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0); 789 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 790 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 791 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 792 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 793 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 794 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 795 ib->ptr[ib->length_dw++] = incr; /* increment size */ 796 ib->ptr[ib->length_dw++] = 0; 797 ib->ptr[ib->length_dw++] = count; /* number of entries */ 798 } 799 800 /** 801 * cik_sdma_ring_pad_ib - pad the IB to the required number of dw 802 * 803 * @ring: amdgpu_ring structure holding ring information 804 * @ib: indirect buffer to fill with padding 805 * 806 */ 807 static void cik_sdma_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 808 { 809 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 810 u32 pad_count; 811 int i; 812 813 pad_count = (-ib->length_dw) & 7; 814 for (i = 0; i < pad_count; i++) 815 if (sdma && sdma->burst_nop && (i == 0)) 816 ib->ptr[ib->length_dw++] = 817 SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0) | 818 SDMA_NOP_COUNT(pad_count - 1); 819 else 820 ib->ptr[ib->length_dw++] = 821 SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0); 822 } 823 824 /** 825 * cik_sdma_ring_emit_pipeline_sync - sync the pipeline 826 * 827 * @ring: amdgpu_ring pointer 828 * 829 * Make sure all previous operations are completed (CIK). 830 */ 831 static void cik_sdma_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 832 { 833 uint32_t seq = ring->fence_drv.sync_seq; 834 uint64_t addr = ring->fence_drv.gpu_addr; 835 836 /* wait for idle */ 837 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, 838 SDMA_POLL_REG_MEM_EXTRA_OP(0) | 839 SDMA_POLL_REG_MEM_EXTRA_FUNC(3) | /* equal */ 840 SDMA_POLL_REG_MEM_EXTRA_M)); 841 amdgpu_ring_write(ring, addr & 0xfffffffc); 842 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 843 amdgpu_ring_write(ring, seq); /* reference */ 844 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 845 amdgpu_ring_write(ring, (0xfff << 16) | 4); /* retry count, poll interval */ 846 } 847 848 /** 849 * cik_sdma_ring_emit_vm_flush - cik vm flush using sDMA 850 * 851 * @ring: amdgpu_ring pointer 852 * @vmid: vmid number to use 853 * @pd_addr: address 854 * 855 * Update the page table base and flush the VM TLB 856 * using sDMA (CIK). 857 */ 858 static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring, 859 unsigned vmid, uint64_t pd_addr) 860 { 861 u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) | 862 SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */ 863 864 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 865 866 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); 867 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2); 868 amdgpu_ring_write(ring, 0); 869 amdgpu_ring_write(ring, 0); /* reference */ 870 amdgpu_ring_write(ring, 0); /* mask */ 871 amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */ 872 } 873 874 static void cik_sdma_ring_emit_wreg(struct amdgpu_ring *ring, 875 uint32_t reg, uint32_t val) 876 { 877 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 878 amdgpu_ring_write(ring, reg); 879 amdgpu_ring_write(ring, val); 880 } 881 882 static void cik_enable_sdma_mgcg(struct amdgpu_device *adev, 883 bool enable) 884 { 885 u32 orig, data; 886 887 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 888 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100); 889 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100); 890 } else { 891 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET); 892 data |= 0xff000000; 893 if (data != orig) 894 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data); 895 896 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET); 897 data |= 0xff000000; 898 if (data != orig) 899 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data); 900 } 901 } 902 903 static void cik_enable_sdma_mgls(struct amdgpu_device *adev, 904 bool enable) 905 { 906 u32 orig, data; 907 908 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 909 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET); 910 data |= 0x100; 911 if (orig != data) 912 WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data); 913 914 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET); 915 data |= 0x100; 916 if (orig != data) 917 WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); 918 } else { 919 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET); 920 data &= ~0x100; 921 if (orig != data) 922 WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data); 923 924 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET); 925 data &= ~0x100; 926 if (orig != data) 927 WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); 928 } 929 } 930 931 static int cik_sdma_early_init(void *handle) 932 { 933 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 934 935 adev->sdma.num_instances = SDMA_MAX_INSTANCE; 936 937 cik_sdma_set_ring_funcs(adev); 938 cik_sdma_set_irq_funcs(adev); 939 cik_sdma_set_buffer_funcs(adev); 940 cik_sdma_set_vm_pte_funcs(adev); 941 942 return 0; 943 } 944 945 static int cik_sdma_sw_init(void *handle) 946 { 947 struct amdgpu_ring *ring; 948 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 949 int r, i; 950 951 r = cik_sdma_init_microcode(adev); 952 if (r) { 953 DRM_ERROR("Failed to load sdma firmware!\n"); 954 return r; 955 } 956 957 /* SDMA trap event */ 958 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 224, 959 &adev->sdma.trap_irq); 960 if (r) 961 return r; 962 963 /* SDMA Privileged inst */ 964 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 241, 965 &adev->sdma.illegal_inst_irq); 966 if (r) 967 return r; 968 969 /* SDMA Privileged inst */ 970 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 247, 971 &adev->sdma.illegal_inst_irq); 972 if (r) 973 return r; 974 975 for (i = 0; i < adev->sdma.num_instances; i++) { 976 ring = &adev->sdma.instance[i].ring; 977 ring->ring_obj = NULL; 978 sprintf(ring->name, "sdma%d", i); 979 r = amdgpu_ring_init(adev, ring, 1024, 980 &adev->sdma.trap_irq, 981 (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 : 982 AMDGPU_SDMA_IRQ_INSTANCE1, 983 AMDGPU_RING_PRIO_DEFAULT, NULL); 984 if (r) 985 return r; 986 } 987 988 return r; 989 } 990 991 static int cik_sdma_sw_fini(void *handle) 992 { 993 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 994 int i; 995 996 for (i = 0; i < adev->sdma.num_instances; i++) 997 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 998 999 cik_sdma_free_microcode(adev); 1000 return 0; 1001 } 1002 1003 static int cik_sdma_hw_init(void *handle) 1004 { 1005 int r; 1006 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1007 1008 r = cik_sdma_start(adev); 1009 if (r) 1010 return r; 1011 1012 return r; 1013 } 1014 1015 static int cik_sdma_hw_fini(void *handle) 1016 { 1017 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1018 1019 cik_ctx_switch_enable(adev, false); 1020 cik_sdma_enable(adev, false); 1021 1022 return 0; 1023 } 1024 1025 static int cik_sdma_suspend(void *handle) 1026 { 1027 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1028 1029 return cik_sdma_hw_fini(adev); 1030 } 1031 1032 static int cik_sdma_resume(void *handle) 1033 { 1034 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1035 1036 cik_sdma_soft_reset(handle); 1037 1038 return cik_sdma_hw_init(adev); 1039 } 1040 1041 static bool cik_sdma_is_idle(void *handle) 1042 { 1043 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1044 u32 tmp = RREG32(mmSRBM_STATUS2); 1045 1046 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK | 1047 SRBM_STATUS2__SDMA1_BUSY_MASK)) 1048 return false; 1049 1050 return true; 1051 } 1052 1053 static int cik_sdma_wait_for_idle(void *handle) 1054 { 1055 unsigned i; 1056 u32 tmp; 1057 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1058 1059 for (i = 0; i < adev->usec_timeout; i++) { 1060 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | 1061 SRBM_STATUS2__SDMA1_BUSY_MASK); 1062 1063 if (!tmp) 1064 return 0; 1065 udelay(1); 1066 } 1067 return -ETIMEDOUT; 1068 } 1069 1070 static int cik_sdma_soft_reset(void *handle) 1071 { 1072 u32 srbm_soft_reset = 0; 1073 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1074 u32 tmp; 1075 1076 /* sdma0 */ 1077 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); 1078 tmp |= SDMA0_F32_CNTL__HALT_MASK; 1079 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); 1080 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK; 1081 1082 /* sdma1 */ 1083 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); 1084 tmp |= SDMA0_F32_CNTL__HALT_MASK; 1085 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); 1086 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK; 1087 1088 if (srbm_soft_reset) { 1089 tmp = RREG32(mmSRBM_SOFT_RESET); 1090 tmp |= srbm_soft_reset; 1091 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1092 WREG32(mmSRBM_SOFT_RESET, tmp); 1093 tmp = RREG32(mmSRBM_SOFT_RESET); 1094 1095 udelay(50); 1096 1097 tmp &= ~srbm_soft_reset; 1098 WREG32(mmSRBM_SOFT_RESET, tmp); 1099 tmp = RREG32(mmSRBM_SOFT_RESET); 1100 1101 /* Wait a little for things to settle down */ 1102 udelay(50); 1103 } 1104 1105 return 0; 1106 } 1107 1108 static int cik_sdma_set_trap_irq_state(struct amdgpu_device *adev, 1109 struct amdgpu_irq_src *src, 1110 unsigned type, 1111 enum amdgpu_interrupt_state state) 1112 { 1113 u32 sdma_cntl; 1114 1115 switch (type) { 1116 case AMDGPU_SDMA_IRQ_INSTANCE0: 1117 switch (state) { 1118 case AMDGPU_IRQ_STATE_DISABLE: 1119 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1120 sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK; 1121 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1122 break; 1123 case AMDGPU_IRQ_STATE_ENABLE: 1124 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1125 sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK; 1126 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1127 break; 1128 default: 1129 break; 1130 } 1131 break; 1132 case AMDGPU_SDMA_IRQ_INSTANCE1: 1133 switch (state) { 1134 case AMDGPU_IRQ_STATE_DISABLE: 1135 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1136 sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK; 1137 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1138 break; 1139 case AMDGPU_IRQ_STATE_ENABLE: 1140 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1141 sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK; 1142 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1143 break; 1144 default: 1145 break; 1146 } 1147 break; 1148 default: 1149 break; 1150 } 1151 return 0; 1152 } 1153 1154 static int cik_sdma_process_trap_irq(struct amdgpu_device *adev, 1155 struct amdgpu_irq_src *source, 1156 struct amdgpu_iv_entry *entry) 1157 { 1158 u8 instance_id, queue_id; 1159 1160 instance_id = (entry->ring_id & 0x3) >> 0; 1161 queue_id = (entry->ring_id & 0xc) >> 2; 1162 DRM_DEBUG("IH: SDMA trap\n"); 1163 switch (instance_id) { 1164 case 0: 1165 switch (queue_id) { 1166 case 0: 1167 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1168 break; 1169 case 1: 1170 /* XXX compute */ 1171 break; 1172 case 2: 1173 /* XXX compute */ 1174 break; 1175 } 1176 break; 1177 case 1: 1178 switch (queue_id) { 1179 case 0: 1180 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1181 break; 1182 case 1: 1183 /* XXX compute */ 1184 break; 1185 case 2: 1186 /* XXX compute */ 1187 break; 1188 } 1189 break; 1190 } 1191 1192 return 0; 1193 } 1194 1195 static int cik_sdma_process_illegal_inst_irq(struct amdgpu_device *adev, 1196 struct amdgpu_irq_src *source, 1197 struct amdgpu_iv_entry *entry) 1198 { 1199 u8 instance_id; 1200 1201 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1202 instance_id = (entry->ring_id & 0x3) >> 0; 1203 drm_sched_fault(&adev->sdma.instance[instance_id].ring.sched); 1204 return 0; 1205 } 1206 1207 static int cik_sdma_set_clockgating_state(void *handle, 1208 enum amd_clockgating_state state) 1209 { 1210 bool gate = false; 1211 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1212 1213 if (state == AMD_CG_STATE_GATE) 1214 gate = true; 1215 1216 cik_enable_sdma_mgcg(adev, gate); 1217 cik_enable_sdma_mgls(adev, gate); 1218 1219 return 0; 1220 } 1221 1222 static int cik_sdma_set_powergating_state(void *handle, 1223 enum amd_powergating_state state) 1224 { 1225 return 0; 1226 } 1227 1228 static const struct amd_ip_funcs cik_sdma_ip_funcs = { 1229 .name = "cik_sdma", 1230 .early_init = cik_sdma_early_init, 1231 .late_init = NULL, 1232 .sw_init = cik_sdma_sw_init, 1233 .sw_fini = cik_sdma_sw_fini, 1234 .hw_init = cik_sdma_hw_init, 1235 .hw_fini = cik_sdma_hw_fini, 1236 .suspend = cik_sdma_suspend, 1237 .resume = cik_sdma_resume, 1238 .is_idle = cik_sdma_is_idle, 1239 .wait_for_idle = cik_sdma_wait_for_idle, 1240 .soft_reset = cik_sdma_soft_reset, 1241 .set_clockgating_state = cik_sdma_set_clockgating_state, 1242 .set_powergating_state = cik_sdma_set_powergating_state, 1243 }; 1244 1245 static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = { 1246 .type = AMDGPU_RING_TYPE_SDMA, 1247 .align_mask = 0xf, 1248 .nop = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), 1249 .support_64bit_ptrs = false, 1250 .get_rptr = cik_sdma_ring_get_rptr, 1251 .get_wptr = cik_sdma_ring_get_wptr, 1252 .set_wptr = cik_sdma_ring_set_wptr, 1253 .emit_frame_size = 1254 6 + /* cik_sdma_ring_emit_hdp_flush */ 1255 3 + /* hdp invalidate */ 1256 6 + /* cik_sdma_ring_emit_pipeline_sync */ 1257 CIK_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* cik_sdma_ring_emit_vm_flush */ 1258 9 + 9 + 9, /* cik_sdma_ring_emit_fence x3 for user fence, vm fence */ 1259 .emit_ib_size = 7 + 4, /* cik_sdma_ring_emit_ib */ 1260 .emit_ib = cik_sdma_ring_emit_ib, 1261 .emit_fence = cik_sdma_ring_emit_fence, 1262 .emit_pipeline_sync = cik_sdma_ring_emit_pipeline_sync, 1263 .emit_vm_flush = cik_sdma_ring_emit_vm_flush, 1264 .emit_hdp_flush = cik_sdma_ring_emit_hdp_flush, 1265 .test_ring = cik_sdma_ring_test_ring, 1266 .test_ib = cik_sdma_ring_test_ib, 1267 .insert_nop = cik_sdma_ring_insert_nop, 1268 .pad_ib = cik_sdma_ring_pad_ib, 1269 .emit_wreg = cik_sdma_ring_emit_wreg, 1270 }; 1271 1272 static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev) 1273 { 1274 int i; 1275 1276 for (i = 0; i < adev->sdma.num_instances; i++) { 1277 adev->sdma.instance[i].ring.funcs = &cik_sdma_ring_funcs; 1278 adev->sdma.instance[i].ring.me = i; 1279 } 1280 } 1281 1282 static const struct amdgpu_irq_src_funcs cik_sdma_trap_irq_funcs = { 1283 .set = cik_sdma_set_trap_irq_state, 1284 .process = cik_sdma_process_trap_irq, 1285 }; 1286 1287 static const struct amdgpu_irq_src_funcs cik_sdma_illegal_inst_irq_funcs = { 1288 .process = cik_sdma_process_illegal_inst_irq, 1289 }; 1290 1291 static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev) 1292 { 1293 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 1294 adev->sdma.trap_irq.funcs = &cik_sdma_trap_irq_funcs; 1295 adev->sdma.illegal_inst_irq.funcs = &cik_sdma_illegal_inst_irq_funcs; 1296 } 1297 1298 /** 1299 * cik_sdma_emit_copy_buffer - copy buffer using the sDMA engine 1300 * 1301 * @ib: indirect buffer to copy to 1302 * @src_offset: src GPU address 1303 * @dst_offset: dst GPU address 1304 * @byte_count: number of bytes to xfer 1305 * @tmz: is this a secure operation 1306 * 1307 * Copy GPU buffers using the DMA engine (CIK). 1308 * Used by the amdgpu ttm implementation to move pages if 1309 * registered as the asic copy callback. 1310 */ 1311 static void cik_sdma_emit_copy_buffer(struct amdgpu_ib *ib, 1312 uint64_t src_offset, 1313 uint64_t dst_offset, 1314 uint32_t byte_count, 1315 bool tmz) 1316 { 1317 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0); 1318 ib->ptr[ib->length_dw++] = byte_count; 1319 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1320 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1321 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1322 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1323 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1324 } 1325 1326 /** 1327 * cik_sdma_emit_fill_buffer - fill buffer using the sDMA engine 1328 * 1329 * @ib: indirect buffer to fill 1330 * @src_data: value to write to buffer 1331 * @dst_offset: dst GPU address 1332 * @byte_count: number of bytes to xfer 1333 * 1334 * Fill GPU buffers using the DMA engine (CIK). 1335 */ 1336 static void cik_sdma_emit_fill_buffer(struct amdgpu_ib *ib, 1337 uint32_t src_data, 1338 uint64_t dst_offset, 1339 uint32_t byte_count) 1340 { 1341 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, 0); 1342 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1343 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1344 ib->ptr[ib->length_dw++] = src_data; 1345 ib->ptr[ib->length_dw++] = byte_count; 1346 } 1347 1348 static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs = { 1349 .copy_max_bytes = 0x1fffff, 1350 .copy_num_dw = 7, 1351 .emit_copy_buffer = cik_sdma_emit_copy_buffer, 1352 1353 .fill_max_bytes = 0x1fffff, 1354 .fill_num_dw = 5, 1355 .emit_fill_buffer = cik_sdma_emit_fill_buffer, 1356 }; 1357 1358 static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev) 1359 { 1360 adev->mman.buffer_funcs = &cik_sdma_buffer_funcs; 1361 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1362 } 1363 1364 static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = { 1365 .copy_pte_num_dw = 7, 1366 .copy_pte = cik_sdma_vm_copy_pte, 1367 1368 .write_pte = cik_sdma_vm_write_pte, 1369 .set_pte_pde = cik_sdma_vm_set_pte_pde, 1370 }; 1371 1372 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev) 1373 { 1374 unsigned i; 1375 1376 adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs; 1377 for (i = 0; i < adev->sdma.num_instances; i++) { 1378 adev->vm_manager.vm_pte_scheds[i] = 1379 &adev->sdma.instance[i].ring.sched; 1380 } 1381 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 1382 } 1383 1384 const struct amdgpu_ip_block_version cik_sdma_ip_block = 1385 { 1386 .type = AMD_IP_BLOCK_TYPE_SDMA, 1387 .major = 2, 1388 .minor = 0, 1389 .rev = 0, 1390 .funcs = &cik_sdma_ip_funcs, 1391 }; 1392