1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/pci.h> 25 26 #include <drm/drm_edid.h> 27 #include <drm/drm_fourcc.h> 28 #include <drm/drm_modeset_helper.h> 29 #include <drm/drm_modeset_helper_vtables.h> 30 #include <drm/drm_vblank.h> 31 32 #include "amdgpu.h" 33 #include "amdgpu_pm.h" 34 #include "amdgpu_i2c.h" 35 #include "atom.h" 36 #include "amdgpu_atombios.h" 37 #include "atombios_crtc.h" 38 #include "atombios_encoders.h" 39 #include "amdgpu_pll.h" 40 #include "amdgpu_connectors.h" 41 #include "amdgpu_display.h" 42 43 #include "bif/bif_3_0_d.h" 44 #include "bif/bif_3_0_sh_mask.h" 45 #include "oss/oss_1_0_d.h" 46 #include "oss/oss_1_0_sh_mask.h" 47 #include "gca/gfx_6_0_d.h" 48 #include "gca/gfx_6_0_sh_mask.h" 49 #include "gmc/gmc_6_0_d.h" 50 #include "gmc/gmc_6_0_sh_mask.h" 51 #include "dce/dce_6_0_d.h" 52 #include "dce/dce_6_0_sh_mask.h" 53 #include "gca/gfx_7_2_enum.h" 54 #include "dce_v6_0.h" 55 #include "si_enums.h" 56 57 static void dce_v6_0_set_display_funcs(struct amdgpu_device *adev); 58 static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev); 59 60 static const u32 crtc_offsets[6] = 61 { 62 SI_CRTC0_REGISTER_OFFSET, 63 SI_CRTC1_REGISTER_OFFSET, 64 SI_CRTC2_REGISTER_OFFSET, 65 SI_CRTC3_REGISTER_OFFSET, 66 SI_CRTC4_REGISTER_OFFSET, 67 SI_CRTC5_REGISTER_OFFSET 68 }; 69 70 static const u32 hpd_offsets[] = 71 { 72 mmDC_HPD1_INT_STATUS - mmDC_HPD1_INT_STATUS, 73 mmDC_HPD2_INT_STATUS - mmDC_HPD1_INT_STATUS, 74 mmDC_HPD3_INT_STATUS - mmDC_HPD1_INT_STATUS, 75 mmDC_HPD4_INT_STATUS - mmDC_HPD1_INT_STATUS, 76 mmDC_HPD5_INT_STATUS - mmDC_HPD1_INT_STATUS, 77 mmDC_HPD6_INT_STATUS - mmDC_HPD1_INT_STATUS, 78 }; 79 80 static const uint32_t dig_offsets[] = { 81 SI_CRTC0_REGISTER_OFFSET, 82 SI_CRTC1_REGISTER_OFFSET, 83 SI_CRTC2_REGISTER_OFFSET, 84 SI_CRTC3_REGISTER_OFFSET, 85 SI_CRTC4_REGISTER_OFFSET, 86 SI_CRTC5_REGISTER_OFFSET, 87 (0x13830 - 0x7030) >> 2, 88 }; 89 90 static const struct { 91 uint32_t reg; 92 uint32_t vblank; 93 uint32_t vline; 94 uint32_t hpd; 95 96 } interrupt_status_offsets[6] = { { 97 .reg = mmDISP_INTERRUPT_STATUS, 98 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK, 99 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK, 100 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 101 }, { 102 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE, 103 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK, 104 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK, 105 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 106 }, { 107 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2, 108 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK, 109 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK, 110 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 111 }, { 112 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3, 113 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK, 114 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK, 115 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 116 }, { 117 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4, 118 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK, 119 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK, 120 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 121 }, { 122 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5, 123 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK, 124 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK, 125 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 126 } }; 127 128 static u32 dce_v6_0_audio_endpt_rreg(struct amdgpu_device *adev, 129 u32 block_offset, u32 reg) 130 { 131 unsigned long flags; 132 u32 r; 133 134 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 135 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 136 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); 137 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 138 139 return r; 140 } 141 142 static void dce_v6_0_audio_endpt_wreg(struct amdgpu_device *adev, 143 u32 block_offset, u32 reg, u32 v) 144 { 145 unsigned long flags; 146 147 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 148 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, 149 reg | AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_WRITE_EN_MASK); 150 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v); 151 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 152 } 153 154 static u32 dce_v6_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) 155 { 156 if (crtc >= adev->mode_info.num_crtc) 157 return 0; 158 else 159 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); 160 } 161 162 static void dce_v6_0_pageflip_interrupt_init(struct amdgpu_device *adev) 163 { 164 unsigned i; 165 166 /* Enable pflip interrupts */ 167 for (i = 0; i < adev->mode_info.num_crtc; i++) 168 amdgpu_irq_get(adev, &adev->pageflip_irq, i); 169 } 170 171 static void dce_v6_0_pageflip_interrupt_fini(struct amdgpu_device *adev) 172 { 173 unsigned i; 174 175 /* Disable pflip interrupts */ 176 for (i = 0; i < adev->mode_info.num_crtc; i++) 177 amdgpu_irq_put(adev, &adev->pageflip_irq, i); 178 } 179 180 /** 181 * dce_v6_0_page_flip - pageflip callback. 182 * 183 * @adev: amdgpu_device pointer 184 * @crtc_id: crtc to cleanup pageflip on 185 * @crtc_base: new address of the crtc (GPU MC address) 186 * @async: asynchronous flip 187 * 188 * Does the actual pageflip (evergreen+). 189 * During vblank we take the crtc lock and wait for the update_pending 190 * bit to go high, when it does, we release the lock, and allow the 191 * double buffered update to take place. 192 * Returns the current update pending status. 193 */ 194 static void dce_v6_0_page_flip(struct amdgpu_device *adev, 195 int crtc_id, u64 crtc_base, bool async) 196 { 197 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 198 struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb; 199 200 /* flip at hsync for async, default is vsync */ 201 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ? 202 GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0); 203 /* update pitch */ 204 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, 205 fb->pitches[0] / fb->format->cpp[0]); 206 /* update the scanout addresses */ 207 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 208 upper_32_bits(crtc_base)); 209 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 210 (u32)crtc_base); 211 212 /* post the write */ 213 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); 214 } 215 216 static int dce_v6_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 217 u32 *vbl, u32 *position) 218 { 219 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 220 return -EINVAL; 221 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); 222 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 223 224 return 0; 225 226 } 227 228 /** 229 * dce_v6_0_hpd_sense - hpd sense callback. 230 * 231 * @adev: amdgpu_device pointer 232 * @hpd: hpd (hotplug detect) pin 233 * 234 * Checks if a digital monitor is connected (evergreen+). 235 * Returns true if connected, false if not connected. 236 */ 237 static bool dce_v6_0_hpd_sense(struct amdgpu_device *adev, 238 enum amdgpu_hpd_id hpd) 239 { 240 bool connected = false; 241 242 if (hpd >= adev->mode_info.num_hpd) 243 return connected; 244 245 if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) & DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK) 246 connected = true; 247 248 return connected; 249 } 250 251 /** 252 * dce_v6_0_hpd_set_polarity - hpd set polarity callback. 253 * 254 * @adev: amdgpu_device pointer 255 * @hpd: hpd (hotplug detect) pin 256 * 257 * Set the polarity of the hpd pin (evergreen+). 258 */ 259 static void dce_v6_0_hpd_set_polarity(struct amdgpu_device *adev, 260 enum amdgpu_hpd_id hpd) 261 { 262 u32 tmp; 263 bool connected = dce_v6_0_hpd_sense(adev, hpd); 264 265 if (hpd >= adev->mode_info.num_hpd) 266 return; 267 268 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); 269 if (connected) 270 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK; 271 else 272 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK; 273 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); 274 } 275 276 static void dce_v6_0_hpd_int_ack(struct amdgpu_device *adev, 277 int hpd) 278 { 279 u32 tmp; 280 281 if (hpd >= adev->mode_info.num_hpd) { 282 DRM_DEBUG("invalid hdp %d\n", hpd); 283 return; 284 } 285 286 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); 287 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK; 288 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); 289 } 290 291 /** 292 * dce_v6_0_hpd_init - hpd setup callback. 293 * 294 * @adev: amdgpu_device pointer 295 * 296 * Setup the hpd pins used by the card (evergreen+). 297 * Enable the pin, set the polarity, and enable the hpd interrupts. 298 */ 299 static void dce_v6_0_hpd_init(struct amdgpu_device *adev) 300 { 301 struct drm_device *dev = adev_to_drm(adev); 302 struct drm_connector *connector; 303 struct drm_connector_list_iter iter; 304 u32 tmp; 305 306 drm_connector_list_iter_begin(dev, &iter); 307 drm_for_each_connector_iter(connector, &iter) { 308 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 309 310 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) 311 continue; 312 313 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 314 tmp |= DC_HPD1_CONTROL__DC_HPD1_EN_MASK; 315 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 316 317 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 318 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 319 /* don't try to enable hpd on eDP or LVDS avoid breaking the 320 * aux dp channel on imac and help (but not completely fix) 321 * https://bugzilla.redhat.com/show_bug.cgi?id=726143 322 * also avoid interrupt storms during dpms. 323 */ 324 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 325 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK; 326 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 327 continue; 328 } 329 330 dce_v6_0_hpd_int_ack(adev, amdgpu_connector->hpd.hpd); 331 dce_v6_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 332 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); 333 } 334 drm_connector_list_iter_end(&iter); 335 } 336 337 /** 338 * dce_v6_0_hpd_fini - hpd tear down callback. 339 * 340 * @adev: amdgpu_device pointer 341 * 342 * Tear down the hpd pins used by the card (evergreen+). 343 * Disable the hpd interrupts. 344 */ 345 static void dce_v6_0_hpd_fini(struct amdgpu_device *adev) 346 { 347 struct drm_device *dev = adev_to_drm(adev); 348 struct drm_connector *connector; 349 struct drm_connector_list_iter iter; 350 u32 tmp; 351 352 drm_connector_list_iter_begin(dev, &iter); 353 drm_for_each_connector_iter(connector, &iter) { 354 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 355 356 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) 357 continue; 358 359 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 360 tmp &= ~DC_HPD1_CONTROL__DC_HPD1_EN_MASK; 361 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 362 363 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); 364 } 365 drm_connector_list_iter_end(&iter); 366 } 367 368 static u32 dce_v6_0_hpd_get_gpio_reg(struct amdgpu_device *adev) 369 { 370 return mmDC_GPIO_HPD_A; 371 } 372 373 static void dce_v6_0_set_vga_render_state(struct amdgpu_device *adev, 374 bool render) 375 { 376 if (!render) 377 WREG32(mmVGA_RENDER_CONTROL, 378 RREG32(mmVGA_RENDER_CONTROL) & VGA_VSTATUS_CNTL); 379 380 } 381 382 static int dce_v6_0_get_num_crtc(struct amdgpu_device *adev) 383 { 384 switch (adev->asic_type) { 385 case CHIP_TAHITI: 386 case CHIP_PITCAIRN: 387 case CHIP_VERDE: 388 return 6; 389 case CHIP_OLAND: 390 return 2; 391 default: 392 return 0; 393 } 394 } 395 396 void dce_v6_0_disable_dce(struct amdgpu_device *adev) 397 { 398 /*Disable VGA render and enabled crtc, if has DCE engine*/ 399 if (amdgpu_atombios_has_dce_engine_info(adev)) { 400 u32 tmp; 401 int crtc_enabled, i; 402 403 dce_v6_0_set_vga_render_state(adev, false); 404 405 /*Disable crtc*/ 406 for (i = 0; i < dce_v6_0_get_num_crtc(adev); i++) { 407 crtc_enabled = RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & 408 CRTC_CONTROL__CRTC_MASTER_EN_MASK; 409 if (crtc_enabled) { 410 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 411 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); 412 tmp &= ~CRTC_CONTROL__CRTC_MASTER_EN_MASK; 413 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); 414 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 415 } 416 } 417 } 418 } 419 420 static void dce_v6_0_program_fmt(struct drm_encoder *encoder) 421 { 422 423 struct drm_device *dev = encoder->dev; 424 struct amdgpu_device *adev = drm_to_adev(dev); 425 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 426 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 427 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 428 int bpc = 0; 429 u32 tmp = 0; 430 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE; 431 432 if (connector) { 433 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 434 bpc = amdgpu_connector_get_monitor_bpc(connector); 435 dither = amdgpu_connector->dither; 436 } 437 438 /* LVDS FMT is set up by atom */ 439 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) 440 return; 441 442 if (bpc == 0) 443 return; 444 445 446 switch (bpc) { 447 case 6: 448 if (dither == AMDGPU_FMT_DITHER_ENABLE) 449 /* XXX sort out optimal dither settings */ 450 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK | 451 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK | 452 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK); 453 else 454 tmp |= FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK; 455 break; 456 case 8: 457 if (dither == AMDGPU_FMT_DITHER_ENABLE) 458 /* XXX sort out optimal dither settings */ 459 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK | 460 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK | 461 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK | 462 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK | 463 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK); 464 else 465 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK | 466 FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK); 467 break; 468 case 10: 469 default: 470 /* not needed */ 471 break; 472 } 473 474 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); 475 } 476 477 /** 478 * si_get_number_of_dram_channels - get the number of dram channels 479 * 480 * @adev: amdgpu_device pointer 481 * 482 * Look up the number of video ram channels (CIK). 483 * Used for display watermark bandwidth calculations 484 * Returns the number of dram channels 485 */ 486 static u32 si_get_number_of_dram_channels(struct amdgpu_device *adev) 487 { 488 u32 tmp = RREG32(mmMC_SHARED_CHMAP); 489 490 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) { 491 case 0: 492 default: 493 return 1; 494 case 1: 495 return 2; 496 case 2: 497 return 4; 498 case 3: 499 return 8; 500 case 4: 501 return 3; 502 case 5: 503 return 6; 504 case 6: 505 return 10; 506 case 7: 507 return 12; 508 case 8: 509 return 16; 510 } 511 } 512 513 struct dce6_wm_params { 514 u32 dram_channels; /* number of dram channels */ 515 u32 yclk; /* bandwidth per dram data pin in kHz */ 516 u32 sclk; /* engine clock in kHz */ 517 u32 disp_clk; /* display clock in kHz */ 518 u32 src_width; /* viewport width */ 519 u32 active_time; /* active display time in ns */ 520 u32 blank_time; /* blank time in ns */ 521 bool interlaced; /* mode is interlaced */ 522 fixed20_12 vsc; /* vertical scale ratio */ 523 u32 num_heads; /* number of active crtcs */ 524 u32 bytes_per_pixel; /* bytes per pixel display + overlay */ 525 u32 lb_size; /* line buffer allocated to pipe */ 526 u32 vtaps; /* vertical scaler taps */ 527 }; 528 529 /** 530 * dce_v6_0_dram_bandwidth - get the dram bandwidth 531 * 532 * @wm: watermark calculation data 533 * 534 * Calculate the raw dram bandwidth (CIK). 535 * Used for display watermark bandwidth calculations 536 * Returns the dram bandwidth in MBytes/s 537 */ 538 static u32 dce_v6_0_dram_bandwidth(struct dce6_wm_params *wm) 539 { 540 /* Calculate raw DRAM Bandwidth */ 541 fixed20_12 dram_efficiency; /* 0.7 */ 542 fixed20_12 yclk, dram_channels, bandwidth; 543 fixed20_12 a; 544 545 a.full = dfixed_const(1000); 546 yclk.full = dfixed_const(wm->yclk); 547 yclk.full = dfixed_div(yclk, a); 548 dram_channels.full = dfixed_const(wm->dram_channels * 4); 549 a.full = dfixed_const(10); 550 dram_efficiency.full = dfixed_const(7); 551 dram_efficiency.full = dfixed_div(dram_efficiency, a); 552 bandwidth.full = dfixed_mul(dram_channels, yclk); 553 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency); 554 555 return dfixed_trunc(bandwidth); 556 } 557 558 /** 559 * dce_v6_0_dram_bandwidth_for_display - get the dram bandwidth for display 560 * 561 * @wm: watermark calculation data 562 * 563 * Calculate the dram bandwidth used for display (CIK). 564 * Used for display watermark bandwidth calculations 565 * Returns the dram bandwidth for display in MBytes/s 566 */ 567 static u32 dce_v6_0_dram_bandwidth_for_display(struct dce6_wm_params *wm) 568 { 569 /* Calculate DRAM Bandwidth and the part allocated to display. */ 570 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */ 571 fixed20_12 yclk, dram_channels, bandwidth; 572 fixed20_12 a; 573 574 a.full = dfixed_const(1000); 575 yclk.full = dfixed_const(wm->yclk); 576 yclk.full = dfixed_div(yclk, a); 577 dram_channels.full = dfixed_const(wm->dram_channels * 4); 578 a.full = dfixed_const(10); 579 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ 580 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a); 581 bandwidth.full = dfixed_mul(dram_channels, yclk); 582 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation); 583 584 return dfixed_trunc(bandwidth); 585 } 586 587 /** 588 * dce_v6_0_data_return_bandwidth - get the data return bandwidth 589 * 590 * @wm: watermark calculation data 591 * 592 * Calculate the data return bandwidth used for display (CIK). 593 * Used for display watermark bandwidth calculations 594 * Returns the data return bandwidth in MBytes/s 595 */ 596 static u32 dce_v6_0_data_return_bandwidth(struct dce6_wm_params *wm) 597 { 598 /* Calculate the display Data return Bandwidth */ 599 fixed20_12 return_efficiency; /* 0.8 */ 600 fixed20_12 sclk, bandwidth; 601 fixed20_12 a; 602 603 a.full = dfixed_const(1000); 604 sclk.full = dfixed_const(wm->sclk); 605 sclk.full = dfixed_div(sclk, a); 606 a.full = dfixed_const(10); 607 return_efficiency.full = dfixed_const(8); 608 return_efficiency.full = dfixed_div(return_efficiency, a); 609 a.full = dfixed_const(32); 610 bandwidth.full = dfixed_mul(a, sclk); 611 bandwidth.full = dfixed_mul(bandwidth, return_efficiency); 612 613 return dfixed_trunc(bandwidth); 614 } 615 616 /** 617 * dce_v6_0_dmif_request_bandwidth - get the dmif bandwidth 618 * 619 * @wm: watermark calculation data 620 * 621 * Calculate the dmif bandwidth used for display (CIK). 622 * Used for display watermark bandwidth calculations 623 * Returns the dmif bandwidth in MBytes/s 624 */ 625 static u32 dce_v6_0_dmif_request_bandwidth(struct dce6_wm_params *wm) 626 { 627 /* Calculate the DMIF Request Bandwidth */ 628 fixed20_12 disp_clk_request_efficiency; /* 0.8 */ 629 fixed20_12 disp_clk, bandwidth; 630 fixed20_12 a, b; 631 632 a.full = dfixed_const(1000); 633 disp_clk.full = dfixed_const(wm->disp_clk); 634 disp_clk.full = dfixed_div(disp_clk, a); 635 a.full = dfixed_const(32); 636 b.full = dfixed_mul(a, disp_clk); 637 638 a.full = dfixed_const(10); 639 disp_clk_request_efficiency.full = dfixed_const(8); 640 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a); 641 642 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency); 643 644 return dfixed_trunc(bandwidth); 645 } 646 647 /** 648 * dce_v6_0_available_bandwidth - get the min available bandwidth 649 * 650 * @wm: watermark calculation data 651 * 652 * Calculate the min available bandwidth used for display (CIK). 653 * Used for display watermark bandwidth calculations 654 * Returns the min available bandwidth in MBytes/s 655 */ 656 static u32 dce_v6_0_available_bandwidth(struct dce6_wm_params *wm) 657 { 658 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */ 659 u32 dram_bandwidth = dce_v6_0_dram_bandwidth(wm); 660 u32 data_return_bandwidth = dce_v6_0_data_return_bandwidth(wm); 661 u32 dmif_req_bandwidth = dce_v6_0_dmif_request_bandwidth(wm); 662 663 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth)); 664 } 665 666 /** 667 * dce_v6_0_average_bandwidth - get the average available bandwidth 668 * 669 * @wm: watermark calculation data 670 * 671 * Calculate the average available bandwidth used for display (CIK). 672 * Used for display watermark bandwidth calculations 673 * Returns the average available bandwidth in MBytes/s 674 */ 675 static u32 dce_v6_0_average_bandwidth(struct dce6_wm_params *wm) 676 { 677 /* Calculate the display mode Average Bandwidth 678 * DisplayMode should contain the source and destination dimensions, 679 * timing, etc. 680 */ 681 fixed20_12 bpp; 682 fixed20_12 line_time; 683 fixed20_12 src_width; 684 fixed20_12 bandwidth; 685 fixed20_12 a; 686 687 a.full = dfixed_const(1000); 688 line_time.full = dfixed_const(wm->active_time + wm->blank_time); 689 line_time.full = dfixed_div(line_time, a); 690 bpp.full = dfixed_const(wm->bytes_per_pixel); 691 src_width.full = dfixed_const(wm->src_width); 692 bandwidth.full = dfixed_mul(src_width, bpp); 693 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); 694 bandwidth.full = dfixed_div(bandwidth, line_time); 695 696 return dfixed_trunc(bandwidth); 697 } 698 699 /** 700 * dce_v6_0_latency_watermark - get the latency watermark 701 * 702 * @wm: watermark calculation data 703 * 704 * Calculate the latency watermark (CIK). 705 * Used for display watermark bandwidth calculations 706 * Returns the latency watermark in ns 707 */ 708 static u32 dce_v6_0_latency_watermark(struct dce6_wm_params *wm) 709 { 710 /* First calculate the latency in ns */ 711 u32 mc_latency = 2000; /* 2000 ns. */ 712 u32 available_bandwidth = dce_v6_0_available_bandwidth(wm); 713 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth; 714 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth; 715 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ 716 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + 717 (wm->num_heads * cursor_line_pair_return_time); 718 u32 latency = mc_latency + other_heads_data_return_time + dc_latency; 719 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time; 720 u32 tmp, dmif_size = 12288; 721 fixed20_12 a, b, c; 722 723 if (wm->num_heads == 0) 724 return 0; 725 726 a.full = dfixed_const(2); 727 b.full = dfixed_const(1); 728 if ((wm->vsc.full > a.full) || 729 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || 730 (wm->vtaps >= 5) || 731 ((wm->vsc.full >= a.full) && wm->interlaced)) 732 max_src_lines_per_dst_line = 4; 733 else 734 max_src_lines_per_dst_line = 2; 735 736 a.full = dfixed_const(available_bandwidth); 737 b.full = dfixed_const(wm->num_heads); 738 a.full = dfixed_div(a, b); 739 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512); 740 tmp = min(dfixed_trunc(a), tmp); 741 742 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000); 743 744 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); 745 b.full = dfixed_const(1000); 746 c.full = dfixed_const(lb_fill_bw); 747 b.full = dfixed_div(c, b); 748 a.full = dfixed_div(a, b); 749 line_fill_time = dfixed_trunc(a); 750 751 if (line_fill_time < wm->active_time) 752 return latency; 753 else 754 return latency + (line_fill_time - wm->active_time); 755 756 } 757 758 /** 759 * dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display - check 760 * average and available dram bandwidth 761 * 762 * @wm: watermark calculation data 763 * 764 * Check if the display average bandwidth fits in the display 765 * dram bandwidth (CIK). 766 * Used for display watermark bandwidth calculations 767 * Returns true if the display fits, false if not. 768 */ 769 static bool dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce6_wm_params *wm) 770 { 771 if (dce_v6_0_average_bandwidth(wm) <= 772 (dce_v6_0_dram_bandwidth_for_display(wm) / wm->num_heads)) 773 return true; 774 else 775 return false; 776 } 777 778 /** 779 * dce_v6_0_average_bandwidth_vs_available_bandwidth - check 780 * average and available bandwidth 781 * 782 * @wm: watermark calculation data 783 * 784 * Check if the display average bandwidth fits in the display 785 * available bandwidth (CIK). 786 * Used for display watermark bandwidth calculations 787 * Returns true if the display fits, false if not. 788 */ 789 static bool dce_v6_0_average_bandwidth_vs_available_bandwidth(struct dce6_wm_params *wm) 790 { 791 if (dce_v6_0_average_bandwidth(wm) <= 792 (dce_v6_0_available_bandwidth(wm) / wm->num_heads)) 793 return true; 794 else 795 return false; 796 } 797 798 /** 799 * dce_v6_0_check_latency_hiding - check latency hiding 800 * 801 * @wm: watermark calculation data 802 * 803 * Check latency hiding (CIK). 804 * Used for display watermark bandwidth calculations 805 * Returns true if the display fits, false if not. 806 */ 807 static bool dce_v6_0_check_latency_hiding(struct dce6_wm_params *wm) 808 { 809 u32 lb_partitions = wm->lb_size / wm->src_width; 810 u32 line_time = wm->active_time + wm->blank_time; 811 u32 latency_tolerant_lines; 812 u32 latency_hiding; 813 fixed20_12 a; 814 815 a.full = dfixed_const(1); 816 if (wm->vsc.full > a.full) 817 latency_tolerant_lines = 1; 818 else { 819 if (lb_partitions <= (wm->vtaps + 1)) 820 latency_tolerant_lines = 1; 821 else 822 latency_tolerant_lines = 2; 823 } 824 825 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); 826 827 if (dce_v6_0_latency_watermark(wm) <= latency_hiding) 828 return true; 829 else 830 return false; 831 } 832 833 /** 834 * dce_v6_0_program_watermarks - program display watermarks 835 * 836 * @adev: amdgpu_device pointer 837 * @amdgpu_crtc: the selected display controller 838 * @lb_size: line buffer size 839 * @num_heads: number of display controllers in use 840 * 841 * Calculate and program the display watermarks for the 842 * selected display controller (CIK). 843 */ 844 static void dce_v6_0_program_watermarks(struct amdgpu_device *adev, 845 struct amdgpu_crtc *amdgpu_crtc, 846 u32 lb_size, u32 num_heads) 847 { 848 struct drm_display_mode *mode = &amdgpu_crtc->base.mode; 849 struct dce6_wm_params wm_low, wm_high; 850 u32 dram_channels; 851 u32 active_time; 852 u32 line_time = 0; 853 u32 latency_watermark_a = 0, latency_watermark_b = 0; 854 u32 priority_a_mark = 0, priority_b_mark = 0; 855 u32 priority_a_cnt = PRIORITY_OFF; 856 u32 priority_b_cnt = PRIORITY_OFF; 857 u32 tmp, arb_control3, lb_vblank_lead_lines = 0; 858 fixed20_12 a, b, c; 859 860 if (amdgpu_crtc->base.enabled && num_heads && mode) { 861 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000, 862 (u32)mode->clock); 863 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000, 864 (u32)mode->clock); 865 line_time = min_t(u32, line_time, 65535); 866 priority_a_cnt = 0; 867 priority_b_cnt = 0; 868 869 dram_channels = si_get_number_of_dram_channels(adev); 870 871 /* watermark for high clocks */ 872 if (adev->pm.dpm_enabled) { 873 wm_high.yclk = 874 amdgpu_dpm_get_mclk(adev, false) * 10; 875 wm_high.sclk = 876 amdgpu_dpm_get_sclk(adev, false) * 10; 877 } else { 878 wm_high.yclk = adev->pm.current_mclk * 10; 879 wm_high.sclk = adev->pm.current_sclk * 10; 880 } 881 882 wm_high.disp_clk = mode->clock; 883 wm_high.src_width = mode->crtc_hdisplay; 884 wm_high.active_time = active_time; 885 wm_high.blank_time = line_time - wm_high.active_time; 886 wm_high.interlaced = false; 887 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 888 wm_high.interlaced = true; 889 wm_high.vsc = amdgpu_crtc->vsc; 890 wm_high.vtaps = 1; 891 if (amdgpu_crtc->rmx_type != RMX_OFF) 892 wm_high.vtaps = 2; 893 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */ 894 wm_high.lb_size = lb_size; 895 wm_high.dram_channels = dram_channels; 896 wm_high.num_heads = num_heads; 897 898 if (adev->pm.dpm_enabled) { 899 /* watermark for low clocks */ 900 wm_low.yclk = 901 amdgpu_dpm_get_mclk(adev, true) * 10; 902 wm_low.sclk = 903 amdgpu_dpm_get_sclk(adev, true) * 10; 904 } else { 905 wm_low.yclk = adev->pm.current_mclk * 10; 906 wm_low.sclk = adev->pm.current_sclk * 10; 907 } 908 909 wm_low.disp_clk = mode->clock; 910 wm_low.src_width = mode->crtc_hdisplay; 911 wm_low.active_time = active_time; 912 wm_low.blank_time = line_time - wm_low.active_time; 913 wm_low.interlaced = false; 914 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 915 wm_low.interlaced = true; 916 wm_low.vsc = amdgpu_crtc->vsc; 917 wm_low.vtaps = 1; 918 if (amdgpu_crtc->rmx_type != RMX_OFF) 919 wm_low.vtaps = 2; 920 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */ 921 wm_low.lb_size = lb_size; 922 wm_low.dram_channels = dram_channels; 923 wm_low.num_heads = num_heads; 924 925 /* set for high clocks */ 926 latency_watermark_a = min_t(u32, dce_v6_0_latency_watermark(&wm_high), 65535); 927 /* set for low clocks */ 928 latency_watermark_b = min_t(u32, dce_v6_0_latency_watermark(&wm_low), 65535); 929 930 /* possibly force display priority to high */ 931 /* should really do this at mode validation time... */ 932 if (!dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) || 933 !dce_v6_0_average_bandwidth_vs_available_bandwidth(&wm_high) || 934 !dce_v6_0_check_latency_hiding(&wm_high) || 935 (adev->mode_info.disp_priority == 2)) { 936 DRM_DEBUG_KMS("force priority to high\n"); 937 priority_a_cnt |= PRIORITY_ALWAYS_ON; 938 priority_b_cnt |= PRIORITY_ALWAYS_ON; 939 } 940 if (!dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) || 941 !dce_v6_0_average_bandwidth_vs_available_bandwidth(&wm_low) || 942 !dce_v6_0_check_latency_hiding(&wm_low) || 943 (adev->mode_info.disp_priority == 2)) { 944 DRM_DEBUG_KMS("force priority to high\n"); 945 priority_a_cnt |= PRIORITY_ALWAYS_ON; 946 priority_b_cnt |= PRIORITY_ALWAYS_ON; 947 } 948 949 a.full = dfixed_const(1000); 950 b.full = dfixed_const(mode->clock); 951 b.full = dfixed_div(b, a); 952 c.full = dfixed_const(latency_watermark_a); 953 c.full = dfixed_mul(c, b); 954 c.full = dfixed_mul(c, amdgpu_crtc->hsc); 955 c.full = dfixed_div(c, a); 956 a.full = dfixed_const(16); 957 c.full = dfixed_div(c, a); 958 priority_a_mark = dfixed_trunc(c); 959 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK; 960 961 a.full = dfixed_const(1000); 962 b.full = dfixed_const(mode->clock); 963 b.full = dfixed_div(b, a); 964 c.full = dfixed_const(latency_watermark_b); 965 c.full = dfixed_mul(c, b); 966 c.full = dfixed_mul(c, amdgpu_crtc->hsc); 967 c.full = dfixed_div(c, a); 968 a.full = dfixed_const(16); 969 c.full = dfixed_div(c, a); 970 priority_b_mark = dfixed_trunc(c); 971 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK; 972 973 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); 974 } 975 976 /* select wm A */ 977 arb_control3 = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset); 978 tmp = arb_control3; 979 tmp &= ~LATENCY_WATERMARK_MASK(3); 980 tmp |= LATENCY_WATERMARK_MASK(1); 981 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp); 982 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, 983 ((latency_watermark_a << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) | 984 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT))); 985 /* select wm B */ 986 tmp = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset); 987 tmp &= ~LATENCY_WATERMARK_MASK(3); 988 tmp |= LATENCY_WATERMARK_MASK(2); 989 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp); 990 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, 991 ((latency_watermark_b << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) | 992 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT))); 993 /* restore original selection */ 994 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, arb_control3); 995 996 /* write the priority marks */ 997 WREG32(mmPRIORITY_A_CNT + amdgpu_crtc->crtc_offset, priority_a_cnt); 998 WREG32(mmPRIORITY_B_CNT + amdgpu_crtc->crtc_offset, priority_b_cnt); 999 1000 /* save values for DPM */ 1001 amdgpu_crtc->line_time = line_time; 1002 amdgpu_crtc->wm_high = latency_watermark_a; 1003 1004 /* Save number of lines the linebuffer leads before the scanout */ 1005 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines; 1006 } 1007 1008 /* watermark setup */ 1009 static u32 dce_v6_0_line_buffer_adjust(struct amdgpu_device *adev, 1010 struct amdgpu_crtc *amdgpu_crtc, 1011 struct drm_display_mode *mode, 1012 struct drm_display_mode *other_mode) 1013 { 1014 u32 tmp, buffer_alloc, i; 1015 u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8; 1016 /* 1017 * Line Buffer Setup 1018 * There are 3 line buffers, each one shared by 2 display controllers. 1019 * mmDC_LB_MEMORY_SPLIT controls how that line buffer is shared between 1020 * the display controllers. The paritioning is done via one of four 1021 * preset allocations specified in bits 21:20: 1022 * 0 - half lb 1023 * 2 - whole lb, other crtc must be disabled 1024 */ 1025 /* this can get tricky if we have two large displays on a paired group 1026 * of crtcs. Ideally for multiple large displays we'd assign them to 1027 * non-linked crtcs for maximum line buffer allocation. 1028 */ 1029 if (amdgpu_crtc->base.enabled && mode) { 1030 if (other_mode) { 1031 tmp = 0; /* 1/2 */ 1032 buffer_alloc = 1; 1033 } else { 1034 tmp = 2; /* whole */ 1035 buffer_alloc = 2; 1036 } 1037 } else { 1038 tmp = 0; 1039 buffer_alloc = 0; 1040 } 1041 1042 WREG32(mmDC_LB_MEMORY_SPLIT + amdgpu_crtc->crtc_offset, 1043 DC_LB_MEMORY_CONFIG(tmp)); 1044 1045 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, 1046 (buffer_alloc << PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT)); 1047 for (i = 0; i < adev->usec_timeout; i++) { 1048 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & 1049 PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK) 1050 break; 1051 udelay(1); 1052 } 1053 1054 if (amdgpu_crtc->base.enabled && mode) { 1055 switch (tmp) { 1056 case 0: 1057 default: 1058 return 4096 * 2; 1059 case 2: 1060 return 8192 * 2; 1061 } 1062 } 1063 1064 /* controller not enabled, so no lb used */ 1065 return 0; 1066 } 1067 1068 1069 /** 1070 * dce_v6_0_bandwidth_update - program display watermarks 1071 * 1072 * @adev: amdgpu_device pointer 1073 * 1074 * Calculate and program the display watermarks and line 1075 * buffer allocation (CIK). 1076 */ 1077 static void dce_v6_0_bandwidth_update(struct amdgpu_device *adev) 1078 { 1079 struct drm_display_mode *mode0 = NULL; 1080 struct drm_display_mode *mode1 = NULL; 1081 u32 num_heads = 0, lb_size; 1082 int i; 1083 1084 if (!adev->mode_info.mode_config_initialized) 1085 return; 1086 1087 amdgpu_display_update_priority(adev); 1088 1089 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1090 if (adev->mode_info.crtcs[i]->base.enabled) 1091 num_heads++; 1092 } 1093 for (i = 0; i < adev->mode_info.num_crtc; i += 2) { 1094 mode0 = &adev->mode_info.crtcs[i]->base.mode; 1095 mode1 = &adev->mode_info.crtcs[i+1]->base.mode; 1096 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode0, mode1); 1097 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i], lb_size, num_heads); 1098 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i+1], mode1, mode0); 1099 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i+1], lb_size, num_heads); 1100 } 1101 } 1102 1103 static void dce_v6_0_audio_get_connected_pins(struct amdgpu_device *adev) 1104 { 1105 int i; 1106 u32 tmp; 1107 1108 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1109 tmp = RREG32_AUDIO_ENDPT(adev->mode_info.audio.pin[i].offset, 1110 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); 1111 if (REG_GET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT, 1112 PORT_CONNECTIVITY)) 1113 adev->mode_info.audio.pin[i].connected = false; 1114 else 1115 adev->mode_info.audio.pin[i].connected = true; 1116 } 1117 1118 } 1119 1120 static struct amdgpu_audio_pin *dce_v6_0_audio_get_pin(struct amdgpu_device *adev) 1121 { 1122 int i; 1123 1124 dce_v6_0_audio_get_connected_pins(adev); 1125 1126 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1127 if (adev->mode_info.audio.pin[i].connected) 1128 return &adev->mode_info.audio.pin[i]; 1129 } 1130 DRM_ERROR("No connected audio pins found!\n"); 1131 return NULL; 1132 } 1133 1134 static void dce_v6_0_audio_select_pin(struct drm_encoder *encoder) 1135 { 1136 struct amdgpu_device *adev = drm_to_adev(encoder->dev); 1137 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1138 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1139 1140 if (!dig || !dig->afmt || !dig->afmt->pin) 1141 return; 1142 1143 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, 1144 REG_SET_FIELD(0, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, 1145 dig->afmt->pin->id)); 1146 } 1147 1148 static void dce_v6_0_audio_write_latency_fields(struct drm_encoder *encoder, 1149 struct drm_display_mode *mode) 1150 { 1151 struct drm_device *dev = encoder->dev; 1152 struct amdgpu_device *adev = drm_to_adev(dev); 1153 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1154 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1155 struct drm_connector *connector; 1156 struct drm_connector_list_iter iter; 1157 struct amdgpu_connector *amdgpu_connector = NULL; 1158 int interlace = 0; 1159 u32 tmp; 1160 1161 drm_connector_list_iter_begin(dev, &iter); 1162 drm_for_each_connector_iter(connector, &iter) { 1163 if (connector->encoder == encoder) { 1164 amdgpu_connector = to_amdgpu_connector(connector); 1165 break; 1166 } 1167 } 1168 drm_connector_list_iter_end(&iter); 1169 1170 if (!amdgpu_connector) { 1171 DRM_ERROR("Couldn't find encoder's connector\n"); 1172 return; 1173 } 1174 1175 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1176 interlace = 1; 1177 1178 if (connector->latency_present[interlace]) { 1179 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1180 VIDEO_LIPSYNC, connector->video_latency[interlace]); 1181 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1182 AUDIO_LIPSYNC, connector->audio_latency[interlace]); 1183 } else { 1184 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1185 VIDEO_LIPSYNC, 0); 1186 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1187 AUDIO_LIPSYNC, 0); 1188 } 1189 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1190 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp); 1191 } 1192 1193 static void dce_v6_0_audio_write_speaker_allocation(struct drm_encoder *encoder) 1194 { 1195 struct drm_device *dev = encoder->dev; 1196 struct amdgpu_device *adev = drm_to_adev(dev); 1197 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1198 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1199 struct drm_connector *connector; 1200 struct drm_connector_list_iter iter; 1201 struct amdgpu_connector *amdgpu_connector = NULL; 1202 u8 *sadb = NULL; 1203 int sad_count; 1204 u32 tmp; 1205 1206 drm_connector_list_iter_begin(dev, &iter); 1207 drm_for_each_connector_iter(connector, &iter) { 1208 if (connector->encoder == encoder) { 1209 amdgpu_connector = to_amdgpu_connector(connector); 1210 break; 1211 } 1212 } 1213 drm_connector_list_iter_end(&iter); 1214 1215 if (!amdgpu_connector) { 1216 DRM_ERROR("Couldn't find encoder's connector\n"); 1217 return; 1218 } 1219 1220 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb); 1221 if (sad_count < 0) { 1222 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); 1223 sad_count = 0; 1224 } 1225 1226 /* program the speaker allocation */ 1227 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1228 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); 1229 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1230 HDMI_CONNECTION, 0); 1231 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1232 DP_CONNECTION, 0); 1233 1234 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) 1235 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1236 DP_CONNECTION, 1); 1237 else 1238 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1239 HDMI_CONNECTION, 1); 1240 1241 if (sad_count) 1242 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1243 SPEAKER_ALLOCATION, sadb[0]); 1244 else 1245 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1246 SPEAKER_ALLOCATION, 5); /* stereo */ 1247 1248 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1249 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); 1250 1251 kfree(sadb); 1252 } 1253 1254 static void dce_v6_0_audio_write_sad_regs(struct drm_encoder *encoder) 1255 { 1256 struct drm_device *dev = encoder->dev; 1257 struct amdgpu_device *adev = drm_to_adev(dev); 1258 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1259 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1260 struct drm_connector *connector; 1261 struct drm_connector_list_iter iter; 1262 struct amdgpu_connector *amdgpu_connector = NULL; 1263 struct cea_sad *sads; 1264 int i, sad_count; 1265 1266 static const u16 eld_reg_to_type[][2] = { 1267 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, 1268 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, 1269 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, 1270 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, 1271 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, 1272 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, 1273 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, 1274 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, 1275 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, 1276 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, 1277 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, 1278 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, 1279 }; 1280 1281 drm_connector_list_iter_begin(dev, &iter); 1282 drm_for_each_connector_iter(connector, &iter) { 1283 if (connector->encoder == encoder) { 1284 amdgpu_connector = to_amdgpu_connector(connector); 1285 break; 1286 } 1287 } 1288 drm_connector_list_iter_end(&iter); 1289 1290 if (!amdgpu_connector) { 1291 DRM_ERROR("Couldn't find encoder's connector\n"); 1292 return; 1293 } 1294 1295 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads); 1296 if (sad_count < 0) 1297 DRM_ERROR("Couldn't read SADs: %d\n", sad_count); 1298 if (sad_count <= 0) 1299 return; 1300 1301 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { 1302 u32 tmp = 0; 1303 u8 stereo_freqs = 0; 1304 int max_channels = -1; 1305 int j; 1306 1307 for (j = 0; j < sad_count; j++) { 1308 struct cea_sad *sad = &sads[j]; 1309 1310 if (sad->format == eld_reg_to_type[i][1]) { 1311 if (sad->channels > max_channels) { 1312 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1313 MAX_CHANNELS, sad->channels); 1314 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1315 DESCRIPTOR_BYTE_2, sad->byte2); 1316 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1317 SUPPORTED_FREQUENCIES, sad->freq); 1318 max_channels = sad->channels; 1319 } 1320 1321 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) 1322 stereo_freqs |= sad->freq; 1323 else 1324 break; 1325 } 1326 } 1327 1328 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1329 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs); 1330 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp); 1331 } 1332 1333 kfree(sads); 1334 1335 } 1336 1337 static void dce_v6_0_audio_enable(struct amdgpu_device *adev, 1338 struct amdgpu_audio_pin *pin, 1339 bool enable) 1340 { 1341 if (!pin) 1342 return; 1343 1344 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 1345 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0); 1346 } 1347 1348 static const u32 pin_offsets[7] = 1349 { 1350 (0x1780 - 0x1780), 1351 (0x1786 - 0x1780), 1352 (0x178c - 0x1780), 1353 (0x1792 - 0x1780), 1354 (0x1798 - 0x1780), 1355 (0x179d - 0x1780), 1356 (0x17a4 - 0x1780), 1357 }; 1358 1359 static int dce_v6_0_audio_init(struct amdgpu_device *adev) 1360 { 1361 int i; 1362 1363 if (!amdgpu_audio) 1364 return 0; 1365 1366 adev->mode_info.audio.enabled = true; 1367 1368 switch (adev->asic_type) { 1369 case CHIP_TAHITI: 1370 case CHIP_PITCAIRN: 1371 case CHIP_VERDE: 1372 default: 1373 adev->mode_info.audio.num_pins = 6; 1374 break; 1375 case CHIP_OLAND: 1376 adev->mode_info.audio.num_pins = 2; 1377 break; 1378 } 1379 1380 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1381 adev->mode_info.audio.pin[i].channels = -1; 1382 adev->mode_info.audio.pin[i].rate = -1; 1383 adev->mode_info.audio.pin[i].bits_per_sample = -1; 1384 adev->mode_info.audio.pin[i].status_bits = 0; 1385 adev->mode_info.audio.pin[i].category_code = 0; 1386 adev->mode_info.audio.pin[i].connected = false; 1387 adev->mode_info.audio.pin[i].offset = pin_offsets[i]; 1388 adev->mode_info.audio.pin[i].id = i; 1389 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1390 } 1391 1392 return 0; 1393 } 1394 1395 static void dce_v6_0_audio_fini(struct amdgpu_device *adev) 1396 { 1397 int i; 1398 1399 if (!amdgpu_audio) 1400 return; 1401 1402 if (!adev->mode_info.audio.enabled) 1403 return; 1404 1405 for (i = 0; i < adev->mode_info.audio.num_pins; i++) 1406 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1407 1408 adev->mode_info.audio.enabled = false; 1409 } 1410 1411 static void dce_v6_0_audio_set_vbi_packet(struct drm_encoder *encoder) 1412 { 1413 struct drm_device *dev = encoder->dev; 1414 struct amdgpu_device *adev = drm_to_adev(dev); 1415 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1416 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1417 u32 tmp; 1418 1419 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); 1420 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); 1421 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); 1422 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); 1423 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); 1424 } 1425 1426 static void dce_v6_0_audio_set_acr(struct drm_encoder *encoder, 1427 uint32_t clock, int bpc) 1428 { 1429 struct drm_device *dev = encoder->dev; 1430 struct amdgpu_device *adev = drm_to_adev(dev); 1431 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock); 1432 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1433 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1434 u32 tmp; 1435 1436 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); 1437 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1); 1438 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1439 bpc > 8 ? 0 : 1); 1440 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp); 1441 1442 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); 1443 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz); 1444 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp); 1445 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); 1446 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz); 1447 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp); 1448 1449 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); 1450 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz); 1451 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); 1452 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); 1453 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz); 1454 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp); 1455 1456 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); 1457 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz); 1458 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); 1459 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); 1460 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz); 1461 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); 1462 } 1463 1464 static void dce_v6_0_audio_set_avi_infoframe(struct drm_encoder *encoder, 1465 struct drm_display_mode *mode) 1466 { 1467 struct drm_device *dev = encoder->dev; 1468 struct amdgpu_device *adev = drm_to_adev(dev); 1469 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1470 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1471 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 1472 struct hdmi_avi_infoframe frame; 1473 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; 1474 uint8_t *payload = buffer + 3; 1475 uint8_t *header = buffer; 1476 ssize_t err; 1477 u32 tmp; 1478 1479 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode); 1480 if (err < 0) { 1481 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); 1482 return; 1483 } 1484 1485 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 1486 if (err < 0) { 1487 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); 1488 return; 1489 } 1490 1491 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset, 1492 payload[0x0] | (payload[0x1] << 8) | (payload[0x2] << 16) | (payload[0x3] << 24)); 1493 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset, 1494 payload[0x4] | (payload[0x5] << 8) | (payload[0x6] << 16) | (payload[0x7] << 24)); 1495 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset, 1496 payload[0x8] | (payload[0x9] << 8) | (payload[0xA] << 16) | (payload[0xB] << 24)); 1497 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset, 1498 payload[0xC] | (payload[0xD] << 8) | (header[1] << 24)); 1499 1500 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); 1501 /* anything other than 0 */ 1502 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, 1503 HDMI_AUDIO_INFO_LINE, 2); 1504 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); 1505 } 1506 1507 static void dce_v6_0_audio_set_dto(struct drm_encoder *encoder, u32 clock) 1508 { 1509 struct drm_device *dev = encoder->dev; 1510 struct amdgpu_device *adev = drm_to_adev(dev); 1511 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1512 int em = amdgpu_atombios_encoder_get_encoder_mode(encoder); 1513 u32 tmp; 1514 1515 /* 1516 * Two dtos: generally use dto0 for hdmi, dto1 for dp. 1517 * Express [24MHz / target pixel clock] as an exact rational 1518 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE 1519 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator 1520 */ 1521 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE); 1522 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, 1523 DCCG_AUDIO_DTO0_SOURCE_SEL, amdgpu_crtc->crtc_id); 1524 if (em == ATOM_ENCODER_MODE_HDMI) { 1525 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, 1526 DCCG_AUDIO_DTO_SEL, 0); 1527 } else if (ENCODER_MODE_IS_DP(em)) { 1528 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, 1529 DCCG_AUDIO_DTO_SEL, 1); 1530 } 1531 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp); 1532 if (em == ATOM_ENCODER_MODE_HDMI) { 1533 WREG32(mmDCCG_AUDIO_DTO0_PHASE, 24000); 1534 WREG32(mmDCCG_AUDIO_DTO0_MODULE, clock); 1535 } else if (ENCODER_MODE_IS_DP(em)) { 1536 WREG32(mmDCCG_AUDIO_DTO1_PHASE, 24000); 1537 WREG32(mmDCCG_AUDIO_DTO1_MODULE, clock); 1538 } 1539 } 1540 1541 static void dce_v6_0_audio_set_packet(struct drm_encoder *encoder) 1542 { 1543 struct drm_device *dev = encoder->dev; 1544 struct amdgpu_device *adev = drm_to_adev(dev); 1545 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1546 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1547 u32 tmp; 1548 1549 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); 1550 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); 1551 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1552 1553 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); 1554 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1); 1555 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp); 1556 1557 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); 1558 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); 1559 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp); 1560 1561 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); 1562 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3); 1563 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4); 1564 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5); 1565 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6); 1566 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7); 1567 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8); 1568 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp); 1569 1570 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset); 1571 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, 0xff); 1572 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, tmp); 1573 1574 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1575 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1); 1576 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3); 1577 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1578 1579 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1580 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_RESET_FIFO_WHEN_AUDIO_DIS, 1); 1581 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); 1582 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1583 } 1584 1585 static void dce_v6_0_audio_set_mute(struct drm_encoder *encoder, bool mute) 1586 { 1587 struct drm_device *dev = encoder->dev; 1588 struct amdgpu_device *adev = drm_to_adev(dev); 1589 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1590 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1591 u32 tmp; 1592 1593 tmp = RREG32(mmHDMI_GC + dig->afmt->offset); 1594 tmp = REG_SET_FIELD(tmp, HDMI_GC, HDMI_GC_AVMUTE, mute ? 1 : 0); 1595 WREG32(mmHDMI_GC + dig->afmt->offset, tmp); 1596 } 1597 1598 static void dce_v6_0_audio_hdmi_enable(struct drm_encoder *encoder, bool enable) 1599 { 1600 struct drm_device *dev = encoder->dev; 1601 struct amdgpu_device *adev = drm_to_adev(dev); 1602 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1603 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1604 u32 tmp; 1605 1606 if (enable) { 1607 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1608 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1); 1609 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1); 1610 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); 1611 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1); 1612 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1613 1614 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); 1615 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2); 1616 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); 1617 1618 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1619 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1); 1620 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1621 } else { 1622 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1623 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 0); 1624 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 0); 1625 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 0); 1626 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 0); 1627 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1628 1629 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1630 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 0); 1631 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1632 } 1633 } 1634 1635 static void dce_v6_0_audio_dp_enable(struct drm_encoder *encoder, bool enable) 1636 { 1637 struct drm_device *dev = encoder->dev; 1638 struct amdgpu_device *adev = drm_to_adev(dev); 1639 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1640 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1641 u32 tmp; 1642 1643 if (enable) { 1644 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1645 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1); 1646 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1647 1648 tmp = RREG32(mmDP_SEC_TIMESTAMP + dig->afmt->offset); 1649 tmp = REG_SET_FIELD(tmp, DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, 1); 1650 WREG32(mmDP_SEC_TIMESTAMP + dig->afmt->offset, tmp); 1651 1652 tmp = RREG32(mmDP_SEC_CNTL + dig->afmt->offset); 1653 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1); 1654 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_ATP_ENABLE, 1); 1655 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_AIP_ENABLE, 1); 1656 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 1657 WREG32(mmDP_SEC_CNTL + dig->afmt->offset, tmp); 1658 } else { 1659 WREG32(mmDP_SEC_CNTL + dig->afmt->offset, 0); 1660 } 1661 } 1662 1663 static void dce_v6_0_afmt_setmode(struct drm_encoder *encoder, 1664 struct drm_display_mode *mode) 1665 { 1666 struct drm_device *dev = encoder->dev; 1667 struct amdgpu_device *adev = drm_to_adev(dev); 1668 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1669 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1670 struct drm_connector *connector; 1671 struct drm_connector_list_iter iter; 1672 struct amdgpu_connector *amdgpu_connector = NULL; 1673 int em = amdgpu_atombios_encoder_get_encoder_mode(encoder); 1674 int bpc = 8; 1675 1676 if (!dig || !dig->afmt) 1677 return; 1678 1679 drm_connector_list_iter_begin(dev, &iter); 1680 drm_for_each_connector_iter(connector, &iter) { 1681 if (connector->encoder == encoder) { 1682 amdgpu_connector = to_amdgpu_connector(connector); 1683 break; 1684 } 1685 } 1686 drm_connector_list_iter_end(&iter); 1687 1688 if (!amdgpu_connector) { 1689 DRM_ERROR("Couldn't find encoder's connector\n"); 1690 return; 1691 } 1692 1693 if (!dig->afmt->enabled) 1694 return; 1695 1696 dig->afmt->pin = dce_v6_0_audio_get_pin(adev); 1697 if (!dig->afmt->pin) 1698 return; 1699 1700 if (encoder->crtc) { 1701 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1702 bpc = amdgpu_crtc->bpc; 1703 } 1704 1705 /* disable audio before setting up hw */ 1706 dce_v6_0_audio_enable(adev, dig->afmt->pin, false); 1707 1708 dce_v6_0_audio_set_mute(encoder, true); 1709 dce_v6_0_audio_write_speaker_allocation(encoder); 1710 dce_v6_0_audio_write_sad_regs(encoder); 1711 dce_v6_0_audio_write_latency_fields(encoder, mode); 1712 if (em == ATOM_ENCODER_MODE_HDMI) { 1713 dce_v6_0_audio_set_dto(encoder, mode->clock); 1714 dce_v6_0_audio_set_vbi_packet(encoder); 1715 dce_v6_0_audio_set_acr(encoder, mode->clock, bpc); 1716 } else if (ENCODER_MODE_IS_DP(em)) { 1717 dce_v6_0_audio_set_dto(encoder, adev->clock.default_dispclk * 10); 1718 } 1719 dce_v6_0_audio_set_packet(encoder); 1720 dce_v6_0_audio_select_pin(encoder); 1721 dce_v6_0_audio_set_avi_infoframe(encoder, mode); 1722 dce_v6_0_audio_set_mute(encoder, false); 1723 if (em == ATOM_ENCODER_MODE_HDMI) { 1724 dce_v6_0_audio_hdmi_enable(encoder, 1); 1725 } else if (ENCODER_MODE_IS_DP(em)) { 1726 dce_v6_0_audio_dp_enable(encoder, 1); 1727 } 1728 1729 /* enable audio after setting up hw */ 1730 dce_v6_0_audio_enable(adev, dig->afmt->pin, true); 1731 } 1732 1733 static void dce_v6_0_afmt_enable(struct drm_encoder *encoder, bool enable) 1734 { 1735 struct drm_device *dev = encoder->dev; 1736 struct amdgpu_device *adev = drm_to_adev(dev); 1737 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1738 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1739 1740 if (!dig || !dig->afmt) 1741 return; 1742 1743 /* Silent, r600_hdmi_enable will raise WARN for us */ 1744 if (enable && dig->afmt->enabled) 1745 return; 1746 1747 if (!enable && !dig->afmt->enabled) 1748 return; 1749 1750 if (!enable && dig->afmt->pin) { 1751 dce_v6_0_audio_enable(adev, dig->afmt->pin, false); 1752 dig->afmt->pin = NULL; 1753 } 1754 1755 dig->afmt->enabled = enable; 1756 1757 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n", 1758 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id); 1759 } 1760 1761 static int dce_v6_0_afmt_init(struct amdgpu_device *adev) 1762 { 1763 int i, j; 1764 1765 for (i = 0; i < adev->mode_info.num_dig; i++) 1766 adev->mode_info.afmt[i] = NULL; 1767 1768 /* DCE6 has audio blocks tied to DIG encoders */ 1769 for (i = 0; i < adev->mode_info.num_dig; i++) { 1770 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL); 1771 if (adev->mode_info.afmt[i]) { 1772 adev->mode_info.afmt[i]->offset = dig_offsets[i]; 1773 adev->mode_info.afmt[i]->id = i; 1774 } else { 1775 for (j = 0; j < i; j++) { 1776 kfree(adev->mode_info.afmt[j]); 1777 adev->mode_info.afmt[j] = NULL; 1778 } 1779 DRM_ERROR("Out of memory allocating afmt table\n"); 1780 return -ENOMEM; 1781 } 1782 } 1783 return 0; 1784 } 1785 1786 static void dce_v6_0_afmt_fini(struct amdgpu_device *adev) 1787 { 1788 int i; 1789 1790 for (i = 0; i < adev->mode_info.num_dig; i++) { 1791 kfree(adev->mode_info.afmt[i]); 1792 adev->mode_info.afmt[i] = NULL; 1793 } 1794 } 1795 1796 static const u32 vga_control_regs[6] = 1797 { 1798 mmD1VGA_CONTROL, 1799 mmD2VGA_CONTROL, 1800 mmD3VGA_CONTROL, 1801 mmD4VGA_CONTROL, 1802 mmD5VGA_CONTROL, 1803 mmD6VGA_CONTROL, 1804 }; 1805 1806 static void dce_v6_0_vga_enable(struct drm_crtc *crtc, bool enable) 1807 { 1808 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1809 struct drm_device *dev = crtc->dev; 1810 struct amdgpu_device *adev = drm_to_adev(dev); 1811 u32 vga_control; 1812 1813 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; 1814 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | (enable ? 1 : 0)); 1815 } 1816 1817 static void dce_v6_0_grph_enable(struct drm_crtc *crtc, bool enable) 1818 { 1819 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1820 struct drm_device *dev = crtc->dev; 1821 struct amdgpu_device *adev = drm_to_adev(dev); 1822 1823 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, enable ? 1 : 0); 1824 } 1825 1826 static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc, 1827 struct drm_framebuffer *fb, 1828 int x, int y, int atomic) 1829 { 1830 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1831 struct drm_device *dev = crtc->dev; 1832 struct amdgpu_device *adev = drm_to_adev(dev); 1833 struct drm_framebuffer *target_fb; 1834 struct drm_gem_object *obj; 1835 struct amdgpu_bo *abo; 1836 uint64_t fb_location, tiling_flags; 1837 uint32_t fb_format, fb_pitch_pixels, pipe_config; 1838 u32 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_NONE); 1839 u32 viewport_w, viewport_h; 1840 int r; 1841 bool bypass_lut = false; 1842 1843 /* no fb bound */ 1844 if (!atomic && !crtc->primary->fb) { 1845 DRM_DEBUG_KMS("No FB bound\n"); 1846 return 0; 1847 } 1848 1849 if (atomic) 1850 target_fb = fb; 1851 else 1852 target_fb = crtc->primary->fb; 1853 1854 /* If atomic, assume fb object is pinned & idle & fenced and 1855 * just update base pointers 1856 */ 1857 obj = target_fb->obj[0]; 1858 abo = gem_to_amdgpu_bo(obj); 1859 r = amdgpu_bo_reserve(abo, false); 1860 if (unlikely(r != 0)) 1861 return r; 1862 1863 if (!atomic) { 1864 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM); 1865 if (unlikely(r != 0)) { 1866 amdgpu_bo_unreserve(abo); 1867 return -EINVAL; 1868 } 1869 } 1870 fb_location = amdgpu_bo_gpu_offset(abo); 1871 1872 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); 1873 amdgpu_bo_unreserve(abo); 1874 1875 switch (target_fb->format->format) { 1876 case DRM_FORMAT_C8: 1877 fb_format = (GRPH_DEPTH(GRPH_DEPTH_8BPP) | 1878 GRPH_FORMAT(GRPH_FORMAT_INDEXED)); 1879 break; 1880 case DRM_FORMAT_XRGB4444: 1881 case DRM_FORMAT_ARGB4444: 1882 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) | 1883 GRPH_FORMAT(GRPH_FORMAT_ARGB4444)); 1884 #ifdef __BIG_ENDIAN 1885 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16); 1886 #endif 1887 break; 1888 case DRM_FORMAT_XRGB1555: 1889 case DRM_FORMAT_ARGB1555: 1890 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) | 1891 GRPH_FORMAT(GRPH_FORMAT_ARGB1555)); 1892 #ifdef __BIG_ENDIAN 1893 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16); 1894 #endif 1895 break; 1896 case DRM_FORMAT_BGRX5551: 1897 case DRM_FORMAT_BGRA5551: 1898 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) | 1899 GRPH_FORMAT(GRPH_FORMAT_BGRA5551)); 1900 #ifdef __BIG_ENDIAN 1901 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16); 1902 #endif 1903 break; 1904 case DRM_FORMAT_RGB565: 1905 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) | 1906 GRPH_FORMAT(GRPH_FORMAT_ARGB565)); 1907 #ifdef __BIG_ENDIAN 1908 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16); 1909 #endif 1910 break; 1911 case DRM_FORMAT_XRGB8888: 1912 case DRM_FORMAT_ARGB8888: 1913 fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) | 1914 GRPH_FORMAT(GRPH_FORMAT_ARGB8888)); 1915 #ifdef __BIG_ENDIAN 1916 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32); 1917 #endif 1918 break; 1919 case DRM_FORMAT_XRGB2101010: 1920 case DRM_FORMAT_ARGB2101010: 1921 fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) | 1922 GRPH_FORMAT(GRPH_FORMAT_ARGB2101010)); 1923 #ifdef __BIG_ENDIAN 1924 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32); 1925 #endif 1926 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 1927 bypass_lut = true; 1928 break; 1929 case DRM_FORMAT_BGRX1010102: 1930 case DRM_FORMAT_BGRA1010102: 1931 fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) | 1932 GRPH_FORMAT(GRPH_FORMAT_BGRA1010102)); 1933 #ifdef __BIG_ENDIAN 1934 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32); 1935 #endif 1936 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 1937 bypass_lut = true; 1938 break; 1939 case DRM_FORMAT_XBGR8888: 1940 case DRM_FORMAT_ABGR8888: 1941 fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) | 1942 GRPH_FORMAT(GRPH_FORMAT_ARGB8888)); 1943 fb_swap = (GRPH_RED_CROSSBAR(GRPH_RED_SEL_B) | 1944 GRPH_BLUE_CROSSBAR(GRPH_BLUE_SEL_R)); 1945 #ifdef __BIG_ENDIAN 1946 fb_swap |= GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32); 1947 #endif 1948 break; 1949 default: 1950 DRM_ERROR("Unsupported screen format %p4cc\n", 1951 &target_fb->format->format); 1952 return -EINVAL; 1953 } 1954 1955 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { 1956 unsigned bankw, bankh, mtaspect, tile_split, num_banks; 1957 1958 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 1959 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 1960 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 1961 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 1962 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 1963 1964 fb_format |= GRPH_NUM_BANKS(num_banks); 1965 fb_format |= GRPH_ARRAY_MODE(GRPH_ARRAY_2D_TILED_THIN1); 1966 fb_format |= GRPH_TILE_SPLIT(tile_split); 1967 fb_format |= GRPH_BANK_WIDTH(bankw); 1968 fb_format |= GRPH_BANK_HEIGHT(bankh); 1969 fb_format |= GRPH_MACRO_TILE_ASPECT(mtaspect); 1970 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { 1971 fb_format |= GRPH_ARRAY_MODE(GRPH_ARRAY_1D_TILED_THIN1); 1972 } 1973 1974 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 1975 fb_format |= GRPH_PIPE_CONFIG(pipe_config); 1976 1977 dce_v6_0_vga_enable(crtc, false); 1978 1979 /* Make sure surface address is updated at vertical blank rather than 1980 * horizontal blank 1981 */ 1982 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0); 1983 1984 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 1985 upper_32_bits(fb_location)); 1986 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 1987 upper_32_bits(fb_location)); 1988 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 1989 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK); 1990 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 1991 (u32) fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK); 1992 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); 1993 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); 1994 1995 /* 1996 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT 1997 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to 1998 * retain the full precision throughout the pipeline. 1999 */ 2000 WREG32_P(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, 2001 (bypass_lut ? GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK : 0), 2002 ~GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK); 2003 2004 if (bypass_lut) 2005 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); 2006 2007 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); 2008 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); 2009 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); 2010 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); 2011 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); 2012 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); 2013 2014 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; 2015 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); 2016 2017 dce_v6_0_grph_enable(crtc, true); 2018 2019 WREG32(mmDESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, 2020 target_fb->height); 2021 x &= ~3; 2022 y &= ~1; 2023 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, 2024 (x << 16) | y); 2025 viewport_w = crtc->mode.hdisplay; 2026 viewport_h = (crtc->mode.vdisplay + 1) & ~1; 2027 2028 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, 2029 (viewport_w << 16) | viewport_h); 2030 2031 /* set pageflip to happen anywhere in vblank interval */ 2032 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); 2033 2034 if (!atomic && fb && fb != crtc->primary->fb) { 2035 abo = gem_to_amdgpu_bo(fb->obj[0]); 2036 r = amdgpu_bo_reserve(abo, true); 2037 if (unlikely(r != 0)) 2038 return r; 2039 amdgpu_bo_unpin(abo); 2040 amdgpu_bo_unreserve(abo); 2041 } 2042 2043 /* Bytes per pixel may have changed */ 2044 dce_v6_0_bandwidth_update(adev); 2045 2046 return 0; 2047 2048 } 2049 2050 static void dce_v6_0_set_interleave(struct drm_crtc *crtc, 2051 struct drm_display_mode *mode) 2052 { 2053 struct drm_device *dev = crtc->dev; 2054 struct amdgpu_device *adev = drm_to_adev(dev); 2055 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2056 2057 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2058 WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, 2059 INTERLEAVE_EN); 2060 else 2061 WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, 0); 2062 } 2063 2064 static void dce_v6_0_crtc_load_lut(struct drm_crtc *crtc) 2065 { 2066 2067 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2068 struct drm_device *dev = crtc->dev; 2069 struct amdgpu_device *adev = drm_to_adev(dev); 2070 u16 *r, *g, *b; 2071 int i; 2072 2073 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); 2074 2075 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, 2076 ((0 << INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT) | 2077 (0 << INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT))); 2078 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, 2079 PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK); 2080 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, 2081 PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK); 2082 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, 2083 ((0 << INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT) | 2084 (0 << INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT))); 2085 2086 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); 2087 2088 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); 2089 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); 2090 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); 2091 2092 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); 2093 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); 2094 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); 2095 2096 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); 2097 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); 2098 2099 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); 2100 r = crtc->gamma_store; 2101 g = r + crtc->gamma_size; 2102 b = g + crtc->gamma_size; 2103 for (i = 0; i < 256; i++) { 2104 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, 2105 ((*r++ & 0xffc0) << 14) | 2106 ((*g++ & 0xffc0) << 4) | 2107 (*b++ >> 6)); 2108 } 2109 2110 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, 2111 ((0 << DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT) | 2112 (0 << DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT) | 2113 ICON_DEGAMMA_MODE(0) | 2114 (0 << DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT))); 2115 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, 2116 ((0 << GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT) | 2117 (0 << GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT))); 2118 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, 2119 ((0 << REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT) | 2120 (0 << REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT))); 2121 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, 2122 ((0 << OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT) | 2123 (0 << OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT))); 2124 /* XXX match this to the depth of the crtc fmt block, move to modeset? */ 2125 WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0); 2126 2127 2128 } 2129 2130 static int dce_v6_0_pick_dig_encoder(struct drm_encoder *encoder) 2131 { 2132 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 2133 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 2134 2135 switch (amdgpu_encoder->encoder_id) { 2136 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2137 return dig->linkb ? 1 : 0; 2138 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2139 return dig->linkb ? 3 : 2; 2140 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2141 return dig->linkb ? 5 : 4; 2142 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2143 return 6; 2144 default: 2145 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); 2146 return 0; 2147 } 2148 } 2149 2150 /** 2151 * dce_v6_0_pick_pll - Allocate a PPLL for use by the crtc. 2152 * 2153 * @crtc: drm crtc 2154 * 2155 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors 2156 * a single PPLL can be used for all DP crtcs/encoders. For non-DP 2157 * monitors a dedicated PPLL must be used. If a particular board has 2158 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming 2159 * as there is no need to program the PLL itself. If we are not able to 2160 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to 2161 * avoid messing up an existing monitor. 2162 * 2163 * 2164 */ 2165 static u32 dce_v6_0_pick_pll(struct drm_crtc *crtc) 2166 { 2167 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2168 struct drm_device *dev = crtc->dev; 2169 struct amdgpu_device *adev = drm_to_adev(dev); 2170 u32 pll_in_use; 2171 int pll; 2172 2173 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) { 2174 if (adev->clock.dp_extclk) 2175 /* skip PPLL programming if using ext clock */ 2176 return ATOM_PPLL_INVALID; 2177 else 2178 return ATOM_PPLL0; 2179 } else { 2180 /* use the same PPLL for all monitors with the same clock */ 2181 pll = amdgpu_pll_get_shared_nondp_ppll(crtc); 2182 if (pll != ATOM_PPLL_INVALID) 2183 return pll; 2184 } 2185 2186 /* PPLL1, and PPLL2 */ 2187 pll_in_use = amdgpu_pll_get_use_mask(crtc); 2188 if (!(pll_in_use & (1 << ATOM_PPLL2))) 2189 return ATOM_PPLL2; 2190 if (!(pll_in_use & (1 << ATOM_PPLL1))) 2191 return ATOM_PPLL1; 2192 DRM_ERROR("unable to allocate a PPLL\n"); 2193 return ATOM_PPLL_INVALID; 2194 } 2195 2196 static void dce_v6_0_lock_cursor(struct drm_crtc *crtc, bool lock) 2197 { 2198 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 2199 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2200 uint32_t cur_lock; 2201 2202 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); 2203 if (lock) 2204 cur_lock |= CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK; 2205 else 2206 cur_lock &= ~CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK; 2207 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); 2208 } 2209 2210 static void dce_v6_0_hide_cursor(struct drm_crtc *crtc) 2211 { 2212 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2213 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 2214 2215 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, 2216 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) | 2217 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT)); 2218 2219 2220 } 2221 2222 static void dce_v6_0_show_cursor(struct drm_crtc *crtc) 2223 { 2224 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2225 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 2226 2227 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2228 upper_32_bits(amdgpu_crtc->cursor_addr)); 2229 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2230 lower_32_bits(amdgpu_crtc->cursor_addr)); 2231 2232 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, 2233 CUR_CONTROL__CURSOR_EN_MASK | 2234 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) | 2235 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT)); 2236 2237 } 2238 2239 static int dce_v6_0_cursor_move_locked(struct drm_crtc *crtc, 2240 int x, int y) 2241 { 2242 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2243 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 2244 int xorigin = 0, yorigin = 0; 2245 2246 int w = amdgpu_crtc->cursor_width; 2247 2248 amdgpu_crtc->cursor_x = x; 2249 amdgpu_crtc->cursor_y = y; 2250 2251 /* avivo cursor are offset into the total surface */ 2252 x += crtc->x; 2253 y += crtc->y; 2254 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); 2255 2256 if (x < 0) { 2257 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); 2258 x = 0; 2259 } 2260 if (y < 0) { 2261 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); 2262 y = 0; 2263 } 2264 2265 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); 2266 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); 2267 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, 2268 ((w - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); 2269 2270 return 0; 2271 } 2272 2273 static int dce_v6_0_crtc_cursor_move(struct drm_crtc *crtc, 2274 int x, int y) 2275 { 2276 int ret; 2277 2278 dce_v6_0_lock_cursor(crtc, true); 2279 ret = dce_v6_0_cursor_move_locked(crtc, x, y); 2280 dce_v6_0_lock_cursor(crtc, false); 2281 2282 return ret; 2283 } 2284 2285 static int dce_v6_0_crtc_cursor_set2(struct drm_crtc *crtc, 2286 struct drm_file *file_priv, 2287 uint32_t handle, 2288 uint32_t width, 2289 uint32_t height, 2290 int32_t hot_x, 2291 int32_t hot_y) 2292 { 2293 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2294 struct drm_gem_object *obj; 2295 struct amdgpu_bo *aobj; 2296 int ret; 2297 2298 if (!handle) { 2299 /* turn off cursor */ 2300 dce_v6_0_hide_cursor(crtc); 2301 obj = NULL; 2302 goto unpin; 2303 } 2304 2305 if ((width > amdgpu_crtc->max_cursor_width) || 2306 (height > amdgpu_crtc->max_cursor_height)) { 2307 DRM_ERROR("bad cursor width or height %d x %d\n", width, height); 2308 return -EINVAL; 2309 } 2310 2311 obj = drm_gem_object_lookup(file_priv, handle); 2312 if (!obj) { 2313 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); 2314 return -ENOENT; 2315 } 2316 2317 aobj = gem_to_amdgpu_bo(obj); 2318 ret = amdgpu_bo_reserve(aobj, false); 2319 if (ret != 0) { 2320 drm_gem_object_put(obj); 2321 return ret; 2322 } 2323 2324 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM); 2325 amdgpu_bo_unreserve(aobj); 2326 if (ret) { 2327 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret); 2328 drm_gem_object_put(obj); 2329 return ret; 2330 } 2331 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj); 2332 2333 dce_v6_0_lock_cursor(crtc, true); 2334 2335 if (width != amdgpu_crtc->cursor_width || 2336 height != amdgpu_crtc->cursor_height || 2337 hot_x != amdgpu_crtc->cursor_hot_x || 2338 hot_y != amdgpu_crtc->cursor_hot_y) { 2339 int x, y; 2340 2341 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x; 2342 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y; 2343 2344 dce_v6_0_cursor_move_locked(crtc, x, y); 2345 2346 amdgpu_crtc->cursor_width = width; 2347 amdgpu_crtc->cursor_height = height; 2348 amdgpu_crtc->cursor_hot_x = hot_x; 2349 amdgpu_crtc->cursor_hot_y = hot_y; 2350 } 2351 2352 dce_v6_0_show_cursor(crtc); 2353 dce_v6_0_lock_cursor(crtc, false); 2354 2355 unpin: 2356 if (amdgpu_crtc->cursor_bo) { 2357 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); 2358 ret = amdgpu_bo_reserve(aobj, true); 2359 if (likely(ret == 0)) { 2360 amdgpu_bo_unpin(aobj); 2361 amdgpu_bo_unreserve(aobj); 2362 } 2363 drm_gem_object_put(amdgpu_crtc->cursor_bo); 2364 } 2365 2366 amdgpu_crtc->cursor_bo = obj; 2367 return 0; 2368 } 2369 2370 static void dce_v6_0_cursor_reset(struct drm_crtc *crtc) 2371 { 2372 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2373 2374 if (amdgpu_crtc->cursor_bo) { 2375 dce_v6_0_lock_cursor(crtc, true); 2376 2377 dce_v6_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, 2378 amdgpu_crtc->cursor_y); 2379 2380 dce_v6_0_show_cursor(crtc); 2381 dce_v6_0_lock_cursor(crtc, false); 2382 } 2383 } 2384 2385 static int dce_v6_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 2386 u16 *blue, uint32_t size, 2387 struct drm_modeset_acquire_ctx *ctx) 2388 { 2389 dce_v6_0_crtc_load_lut(crtc); 2390 2391 return 0; 2392 } 2393 2394 static void dce_v6_0_crtc_destroy(struct drm_crtc *crtc) 2395 { 2396 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2397 2398 drm_crtc_cleanup(crtc); 2399 kfree(amdgpu_crtc); 2400 } 2401 2402 static const struct drm_crtc_funcs dce_v6_0_crtc_funcs = { 2403 .cursor_set2 = dce_v6_0_crtc_cursor_set2, 2404 .cursor_move = dce_v6_0_crtc_cursor_move, 2405 .gamma_set = dce_v6_0_crtc_gamma_set, 2406 .set_config = amdgpu_display_crtc_set_config, 2407 .destroy = dce_v6_0_crtc_destroy, 2408 .page_flip_target = amdgpu_display_crtc_page_flip_target, 2409 .get_vblank_counter = amdgpu_get_vblank_counter_kms, 2410 .enable_vblank = amdgpu_enable_vblank_kms, 2411 .disable_vblank = amdgpu_disable_vblank_kms, 2412 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, 2413 }; 2414 2415 static void dce_v6_0_crtc_dpms(struct drm_crtc *crtc, int mode) 2416 { 2417 struct drm_device *dev = crtc->dev; 2418 struct amdgpu_device *adev = drm_to_adev(dev); 2419 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2420 unsigned type; 2421 2422 switch (mode) { 2423 case DRM_MODE_DPMS_ON: 2424 amdgpu_crtc->enabled = true; 2425 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE); 2426 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE); 2427 /* Make sure VBLANK and PFLIP interrupts are still enabled */ 2428 type = amdgpu_display_crtc_idx_to_irq_type(adev, 2429 amdgpu_crtc->crtc_id); 2430 amdgpu_irq_update(adev, &adev->crtc_irq, type); 2431 amdgpu_irq_update(adev, &adev->pageflip_irq, type); 2432 drm_crtc_vblank_on(crtc); 2433 dce_v6_0_crtc_load_lut(crtc); 2434 break; 2435 case DRM_MODE_DPMS_STANDBY: 2436 case DRM_MODE_DPMS_SUSPEND: 2437 case DRM_MODE_DPMS_OFF: 2438 drm_crtc_vblank_off(crtc); 2439 if (amdgpu_crtc->enabled) 2440 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE); 2441 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE); 2442 amdgpu_crtc->enabled = false; 2443 break; 2444 } 2445 /* adjust pm to dpms */ 2446 amdgpu_dpm_compute_clocks(adev); 2447 } 2448 2449 static void dce_v6_0_crtc_prepare(struct drm_crtc *crtc) 2450 { 2451 /* disable crtc pair power gating before programming */ 2452 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE); 2453 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE); 2454 dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2455 } 2456 2457 static void dce_v6_0_crtc_commit(struct drm_crtc *crtc) 2458 { 2459 dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 2460 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE); 2461 } 2462 2463 static void dce_v6_0_crtc_disable(struct drm_crtc *crtc) 2464 { 2465 2466 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2467 struct drm_device *dev = crtc->dev; 2468 struct amdgpu_device *adev = drm_to_adev(dev); 2469 struct amdgpu_atom_ss ss; 2470 int i; 2471 2472 dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2473 if (crtc->primary->fb) { 2474 int r; 2475 struct amdgpu_bo *abo; 2476 2477 abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]); 2478 r = amdgpu_bo_reserve(abo, true); 2479 if (unlikely(r)) 2480 DRM_ERROR("failed to reserve abo before unpin\n"); 2481 else { 2482 amdgpu_bo_unpin(abo); 2483 amdgpu_bo_unreserve(abo); 2484 } 2485 } 2486 /* disable the GRPH */ 2487 dce_v6_0_grph_enable(crtc, false); 2488 2489 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE); 2490 2491 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2492 if (adev->mode_info.crtcs[i] && 2493 adev->mode_info.crtcs[i]->enabled && 2494 i != amdgpu_crtc->crtc_id && 2495 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { 2496 /* one other crtc is using this pll don't turn 2497 * off the pll 2498 */ 2499 goto done; 2500 } 2501 } 2502 2503 switch (amdgpu_crtc->pll_id) { 2504 case ATOM_PPLL1: 2505 case ATOM_PPLL2: 2506 /* disable the ppll */ 2507 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, 2508 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 2509 break; 2510 default: 2511 break; 2512 } 2513 done: 2514 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2515 amdgpu_crtc->adjusted_clock = 0; 2516 amdgpu_crtc->encoder = NULL; 2517 amdgpu_crtc->connector = NULL; 2518 } 2519 2520 static int dce_v6_0_crtc_mode_set(struct drm_crtc *crtc, 2521 struct drm_display_mode *mode, 2522 struct drm_display_mode *adjusted_mode, 2523 int x, int y, struct drm_framebuffer *old_fb) 2524 { 2525 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2526 2527 if (!amdgpu_crtc->adjusted_clock) 2528 return -EINVAL; 2529 2530 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode); 2531 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode); 2532 dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2533 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode); 2534 amdgpu_atombios_crtc_scaler_setup(crtc); 2535 dce_v6_0_cursor_reset(crtc); 2536 /* update the hw version fpr dpm */ 2537 amdgpu_crtc->hw_mode = *adjusted_mode; 2538 2539 return 0; 2540 } 2541 2542 static bool dce_v6_0_crtc_mode_fixup(struct drm_crtc *crtc, 2543 const struct drm_display_mode *mode, 2544 struct drm_display_mode *adjusted_mode) 2545 { 2546 2547 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2548 struct drm_device *dev = crtc->dev; 2549 struct drm_encoder *encoder; 2550 2551 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */ 2552 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2553 if (encoder->crtc == crtc) { 2554 amdgpu_crtc->encoder = encoder; 2555 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder); 2556 break; 2557 } 2558 } 2559 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) { 2560 amdgpu_crtc->encoder = NULL; 2561 amdgpu_crtc->connector = NULL; 2562 return false; 2563 } 2564 if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 2565 return false; 2566 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode)) 2567 return false; 2568 /* pick pll */ 2569 amdgpu_crtc->pll_id = dce_v6_0_pick_pll(crtc); 2570 /* if we can't get a PPLL for a non-DP encoder, fail */ 2571 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) && 2572 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) 2573 return false; 2574 2575 return true; 2576 } 2577 2578 static int dce_v6_0_crtc_set_base(struct drm_crtc *crtc, int x, int y, 2579 struct drm_framebuffer *old_fb) 2580 { 2581 return dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2582 } 2583 2584 static int dce_v6_0_crtc_set_base_atomic(struct drm_crtc *crtc, 2585 struct drm_framebuffer *fb, 2586 int x, int y, enum mode_set_atomic state) 2587 { 2588 return dce_v6_0_crtc_do_set_base(crtc, fb, x, y, 1); 2589 } 2590 2591 static const struct drm_crtc_helper_funcs dce_v6_0_crtc_helper_funcs = { 2592 .dpms = dce_v6_0_crtc_dpms, 2593 .mode_fixup = dce_v6_0_crtc_mode_fixup, 2594 .mode_set = dce_v6_0_crtc_mode_set, 2595 .mode_set_base = dce_v6_0_crtc_set_base, 2596 .mode_set_base_atomic = dce_v6_0_crtc_set_base_atomic, 2597 .prepare = dce_v6_0_crtc_prepare, 2598 .commit = dce_v6_0_crtc_commit, 2599 .disable = dce_v6_0_crtc_disable, 2600 .get_scanout_position = amdgpu_crtc_get_scanout_position, 2601 }; 2602 2603 static int dce_v6_0_crtc_init(struct amdgpu_device *adev, int index) 2604 { 2605 struct amdgpu_crtc *amdgpu_crtc; 2606 2607 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) + 2608 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); 2609 if (amdgpu_crtc == NULL) 2610 return -ENOMEM; 2611 2612 drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_v6_0_crtc_funcs); 2613 2614 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); 2615 amdgpu_crtc->crtc_id = index; 2616 adev->mode_info.crtcs[index] = amdgpu_crtc; 2617 2618 amdgpu_crtc->max_cursor_width = CURSOR_WIDTH; 2619 amdgpu_crtc->max_cursor_height = CURSOR_HEIGHT; 2620 adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width; 2621 adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height; 2622 2623 amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id]; 2624 2625 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2626 amdgpu_crtc->adjusted_clock = 0; 2627 amdgpu_crtc->encoder = NULL; 2628 amdgpu_crtc->connector = NULL; 2629 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v6_0_crtc_helper_funcs); 2630 2631 return 0; 2632 } 2633 2634 static int dce_v6_0_early_init(void *handle) 2635 { 2636 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2637 2638 adev->audio_endpt_rreg = &dce_v6_0_audio_endpt_rreg; 2639 adev->audio_endpt_wreg = &dce_v6_0_audio_endpt_wreg; 2640 2641 dce_v6_0_set_display_funcs(adev); 2642 2643 adev->mode_info.num_crtc = dce_v6_0_get_num_crtc(adev); 2644 2645 switch (adev->asic_type) { 2646 case CHIP_TAHITI: 2647 case CHIP_PITCAIRN: 2648 case CHIP_VERDE: 2649 adev->mode_info.num_hpd = 6; 2650 adev->mode_info.num_dig = 6; 2651 break; 2652 case CHIP_OLAND: 2653 adev->mode_info.num_hpd = 2; 2654 adev->mode_info.num_dig = 2; 2655 break; 2656 default: 2657 return -EINVAL; 2658 } 2659 2660 dce_v6_0_set_irq_funcs(adev); 2661 2662 return 0; 2663 } 2664 2665 static int dce_v6_0_sw_init(void *handle) 2666 { 2667 int r, i; 2668 bool ret; 2669 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2670 2671 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2672 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq); 2673 if (r) 2674 return r; 2675 } 2676 2677 for (i = 8; i < 20; i += 2) { 2678 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq); 2679 if (r) 2680 return r; 2681 } 2682 2683 /* HPD hotplug */ 2684 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 42, &adev->hpd_irq); 2685 if (r) 2686 return r; 2687 2688 adev->mode_info.mode_config_initialized = true; 2689 2690 adev_to_drm(adev)->mode_config.funcs = &amdgpu_mode_funcs; 2691 adev_to_drm(adev)->mode_config.async_page_flip = true; 2692 adev_to_drm(adev)->mode_config.max_width = 16384; 2693 adev_to_drm(adev)->mode_config.max_height = 16384; 2694 adev_to_drm(adev)->mode_config.preferred_depth = 24; 2695 adev_to_drm(adev)->mode_config.prefer_shadow = 1; 2696 adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true; 2697 2698 r = amdgpu_display_modeset_create_props(adev); 2699 if (r) 2700 return r; 2701 2702 adev_to_drm(adev)->mode_config.max_width = 16384; 2703 adev_to_drm(adev)->mode_config.max_height = 16384; 2704 2705 /* allocate crtcs */ 2706 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2707 r = dce_v6_0_crtc_init(adev, i); 2708 if (r) 2709 return r; 2710 } 2711 2712 ret = amdgpu_atombios_get_connector_info_from_object_table(adev); 2713 if (ret) 2714 amdgpu_display_print_display_setup(adev_to_drm(adev)); 2715 else 2716 return -EINVAL; 2717 2718 /* setup afmt */ 2719 r = dce_v6_0_afmt_init(adev); 2720 if (r) 2721 return r; 2722 2723 r = dce_v6_0_audio_init(adev); 2724 if (r) 2725 return r; 2726 2727 /* Disable vblank IRQs aggressively for power-saving */ 2728 /* XXX: can this be enabled for DC? */ 2729 adev_to_drm(adev)->vblank_disable_immediate = true; 2730 2731 r = drm_vblank_init(adev_to_drm(adev), adev->mode_info.num_crtc); 2732 if (r) 2733 return r; 2734 2735 /* Pre-DCE11 */ 2736 INIT_DELAYED_WORK(&adev->hotplug_work, 2737 amdgpu_display_hotplug_work_func); 2738 2739 drm_kms_helper_poll_init(adev_to_drm(adev)); 2740 2741 return r; 2742 } 2743 2744 static int dce_v6_0_sw_fini(void *handle) 2745 { 2746 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2747 2748 kfree(adev->mode_info.bios_hardcoded_edid); 2749 2750 drm_kms_helper_poll_fini(adev_to_drm(adev)); 2751 2752 dce_v6_0_audio_fini(adev); 2753 dce_v6_0_afmt_fini(adev); 2754 2755 drm_mode_config_cleanup(adev_to_drm(adev)); 2756 adev->mode_info.mode_config_initialized = false; 2757 2758 return 0; 2759 } 2760 2761 static int dce_v6_0_hw_init(void *handle) 2762 { 2763 int i; 2764 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2765 2766 /* disable vga render */ 2767 dce_v6_0_set_vga_render_state(adev, false); 2768 /* init dig PHYs, disp eng pll */ 2769 amdgpu_atombios_encoder_init_dig(adev); 2770 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); 2771 2772 /* initialize hpd */ 2773 dce_v6_0_hpd_init(adev); 2774 2775 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 2776 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 2777 } 2778 2779 dce_v6_0_pageflip_interrupt_init(adev); 2780 2781 return 0; 2782 } 2783 2784 static int dce_v6_0_hw_fini(void *handle) 2785 { 2786 int i; 2787 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2788 2789 dce_v6_0_hpd_fini(adev); 2790 2791 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 2792 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 2793 } 2794 2795 dce_v6_0_pageflip_interrupt_fini(adev); 2796 2797 flush_delayed_work(&adev->hotplug_work); 2798 2799 return 0; 2800 } 2801 2802 static int dce_v6_0_suspend(void *handle) 2803 { 2804 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2805 int r; 2806 2807 r = amdgpu_display_suspend_helper(adev); 2808 if (r) 2809 return r; 2810 adev->mode_info.bl_level = 2811 amdgpu_atombios_encoder_get_backlight_level_from_reg(adev); 2812 2813 return dce_v6_0_hw_fini(handle); 2814 } 2815 2816 static int dce_v6_0_resume(void *handle) 2817 { 2818 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2819 int ret; 2820 2821 amdgpu_atombios_encoder_set_backlight_level_to_reg(adev, 2822 adev->mode_info.bl_level); 2823 2824 ret = dce_v6_0_hw_init(handle); 2825 2826 /* turn on the BL */ 2827 if (adev->mode_info.bl_encoder) { 2828 u8 bl_level = amdgpu_display_backlight_get_level(adev, 2829 adev->mode_info.bl_encoder); 2830 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder, 2831 bl_level); 2832 } 2833 if (ret) 2834 return ret; 2835 2836 return amdgpu_display_resume_helper(adev); 2837 } 2838 2839 static bool dce_v6_0_is_idle(void *handle) 2840 { 2841 return true; 2842 } 2843 2844 static int dce_v6_0_wait_for_idle(void *handle) 2845 { 2846 return 0; 2847 } 2848 2849 static int dce_v6_0_soft_reset(void *handle) 2850 { 2851 DRM_INFO("xxxx: dce_v6_0_soft_reset --- no impl!!\n"); 2852 return 0; 2853 } 2854 2855 static void dce_v6_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev, 2856 int crtc, 2857 enum amdgpu_interrupt_state state) 2858 { 2859 u32 reg_block, interrupt_mask; 2860 2861 if (crtc >= adev->mode_info.num_crtc) { 2862 DRM_DEBUG("invalid crtc %d\n", crtc); 2863 return; 2864 } 2865 2866 switch (crtc) { 2867 case 0: 2868 reg_block = SI_CRTC0_REGISTER_OFFSET; 2869 break; 2870 case 1: 2871 reg_block = SI_CRTC1_REGISTER_OFFSET; 2872 break; 2873 case 2: 2874 reg_block = SI_CRTC2_REGISTER_OFFSET; 2875 break; 2876 case 3: 2877 reg_block = SI_CRTC3_REGISTER_OFFSET; 2878 break; 2879 case 4: 2880 reg_block = SI_CRTC4_REGISTER_OFFSET; 2881 break; 2882 case 5: 2883 reg_block = SI_CRTC5_REGISTER_OFFSET; 2884 break; 2885 default: 2886 DRM_DEBUG("invalid crtc %d\n", crtc); 2887 return; 2888 } 2889 2890 switch (state) { 2891 case AMDGPU_IRQ_STATE_DISABLE: 2892 interrupt_mask = RREG32(mmINT_MASK + reg_block); 2893 interrupt_mask &= ~VBLANK_INT_MASK; 2894 WREG32(mmINT_MASK + reg_block, interrupt_mask); 2895 break; 2896 case AMDGPU_IRQ_STATE_ENABLE: 2897 interrupt_mask = RREG32(mmINT_MASK + reg_block); 2898 interrupt_mask |= VBLANK_INT_MASK; 2899 WREG32(mmINT_MASK + reg_block, interrupt_mask); 2900 break; 2901 default: 2902 break; 2903 } 2904 } 2905 2906 static void dce_v6_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev, 2907 int crtc, 2908 enum amdgpu_interrupt_state state) 2909 { 2910 2911 } 2912 2913 static int dce_v6_0_set_hpd_interrupt_state(struct amdgpu_device *adev, 2914 struct amdgpu_irq_src *src, 2915 unsigned type, 2916 enum amdgpu_interrupt_state state) 2917 { 2918 u32 dc_hpd_int_cntl; 2919 2920 if (type >= adev->mode_info.num_hpd) { 2921 DRM_DEBUG("invalid hdp %d\n", type); 2922 return 0; 2923 } 2924 2925 switch (state) { 2926 case AMDGPU_IRQ_STATE_DISABLE: 2927 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]); 2928 dc_hpd_int_cntl &= ~DC_HPDx_INT_EN; 2929 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl); 2930 break; 2931 case AMDGPU_IRQ_STATE_ENABLE: 2932 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]); 2933 dc_hpd_int_cntl |= DC_HPDx_INT_EN; 2934 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl); 2935 break; 2936 default: 2937 break; 2938 } 2939 2940 return 0; 2941 } 2942 2943 static int dce_v6_0_set_crtc_interrupt_state(struct amdgpu_device *adev, 2944 struct amdgpu_irq_src *src, 2945 unsigned type, 2946 enum amdgpu_interrupt_state state) 2947 { 2948 switch (type) { 2949 case AMDGPU_CRTC_IRQ_VBLANK1: 2950 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 0, state); 2951 break; 2952 case AMDGPU_CRTC_IRQ_VBLANK2: 2953 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 1, state); 2954 break; 2955 case AMDGPU_CRTC_IRQ_VBLANK3: 2956 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 2, state); 2957 break; 2958 case AMDGPU_CRTC_IRQ_VBLANK4: 2959 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 3, state); 2960 break; 2961 case AMDGPU_CRTC_IRQ_VBLANK5: 2962 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 4, state); 2963 break; 2964 case AMDGPU_CRTC_IRQ_VBLANK6: 2965 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 5, state); 2966 break; 2967 case AMDGPU_CRTC_IRQ_VLINE1: 2968 dce_v6_0_set_crtc_vline_interrupt_state(adev, 0, state); 2969 break; 2970 case AMDGPU_CRTC_IRQ_VLINE2: 2971 dce_v6_0_set_crtc_vline_interrupt_state(adev, 1, state); 2972 break; 2973 case AMDGPU_CRTC_IRQ_VLINE3: 2974 dce_v6_0_set_crtc_vline_interrupt_state(adev, 2, state); 2975 break; 2976 case AMDGPU_CRTC_IRQ_VLINE4: 2977 dce_v6_0_set_crtc_vline_interrupt_state(adev, 3, state); 2978 break; 2979 case AMDGPU_CRTC_IRQ_VLINE5: 2980 dce_v6_0_set_crtc_vline_interrupt_state(adev, 4, state); 2981 break; 2982 case AMDGPU_CRTC_IRQ_VLINE6: 2983 dce_v6_0_set_crtc_vline_interrupt_state(adev, 5, state); 2984 break; 2985 default: 2986 break; 2987 } 2988 return 0; 2989 } 2990 2991 static int dce_v6_0_crtc_irq(struct amdgpu_device *adev, 2992 struct amdgpu_irq_src *source, 2993 struct amdgpu_iv_entry *entry) 2994 { 2995 unsigned crtc = entry->src_id - 1; 2996 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); 2997 unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev, 2998 crtc); 2999 3000 switch (entry->src_data[0]) { 3001 case 0: /* vblank */ 3002 if (disp_int & interrupt_status_offsets[crtc].vblank) 3003 WREG32(mmVBLANK_STATUS + crtc_offsets[crtc], VBLANK_ACK); 3004 else 3005 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3006 3007 if (amdgpu_irq_enabled(adev, source, irq_type)) { 3008 drm_handle_vblank(adev_to_drm(adev), crtc); 3009 } 3010 DRM_DEBUG("IH: D%d vblank\n", crtc + 1); 3011 break; 3012 case 1: /* vline */ 3013 if (disp_int & interrupt_status_offsets[crtc].vline) 3014 WREG32(mmVLINE_STATUS + crtc_offsets[crtc], VLINE_ACK); 3015 else 3016 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3017 3018 DRM_DEBUG("IH: D%d vline\n", crtc + 1); 3019 break; 3020 default: 3021 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); 3022 break; 3023 } 3024 3025 return 0; 3026 } 3027 3028 static int dce_v6_0_set_pageflip_interrupt_state(struct amdgpu_device *adev, 3029 struct amdgpu_irq_src *src, 3030 unsigned type, 3031 enum amdgpu_interrupt_state state) 3032 { 3033 u32 reg; 3034 3035 if (type >= adev->mode_info.num_crtc) { 3036 DRM_ERROR("invalid pageflip crtc %d\n", type); 3037 return -EINVAL; 3038 } 3039 3040 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]); 3041 if (state == AMDGPU_IRQ_STATE_DISABLE) 3042 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 3043 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3044 else 3045 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 3046 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3047 3048 return 0; 3049 } 3050 3051 static int dce_v6_0_pageflip_irq(struct amdgpu_device *adev, 3052 struct amdgpu_irq_src *source, 3053 struct amdgpu_iv_entry *entry) 3054 { 3055 unsigned long flags; 3056 unsigned crtc_id; 3057 struct amdgpu_crtc *amdgpu_crtc; 3058 struct amdgpu_flip_work *works; 3059 3060 crtc_id = (entry->src_id - 8) >> 1; 3061 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 3062 3063 if (crtc_id >= adev->mode_info.num_crtc) { 3064 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id); 3065 return -EINVAL; 3066 } 3067 3068 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) & 3069 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK) 3070 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id], 3071 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK); 3072 3073 /* IRQ could occur when in initial stage */ 3074 if (amdgpu_crtc == NULL) 3075 return 0; 3076 3077 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 3078 works = amdgpu_crtc->pflip_works; 3079 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ 3080 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != " 3081 "AMDGPU_FLIP_SUBMITTED(%d)\n", 3082 amdgpu_crtc->pflip_status, 3083 AMDGPU_FLIP_SUBMITTED); 3084 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 3085 return 0; 3086 } 3087 3088 /* page flip completed. clean up */ 3089 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; 3090 amdgpu_crtc->pflip_works = NULL; 3091 3092 /* wakeup usersapce */ 3093 if (works->event) 3094 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event); 3095 3096 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 3097 3098 drm_crtc_vblank_put(&amdgpu_crtc->base); 3099 schedule_work(&works->unpin_work); 3100 3101 return 0; 3102 } 3103 3104 static int dce_v6_0_hpd_irq(struct amdgpu_device *adev, 3105 struct amdgpu_irq_src *source, 3106 struct amdgpu_iv_entry *entry) 3107 { 3108 uint32_t disp_int, mask; 3109 unsigned hpd; 3110 3111 if (entry->src_data[0] >= adev->mode_info.num_hpd) { 3112 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); 3113 return 0; 3114 } 3115 3116 hpd = entry->src_data[0]; 3117 disp_int = RREG32(interrupt_status_offsets[hpd].reg); 3118 mask = interrupt_status_offsets[hpd].hpd; 3119 3120 if (disp_int & mask) { 3121 dce_v6_0_hpd_int_ack(adev, hpd); 3122 schedule_delayed_work(&adev->hotplug_work, 0); 3123 DRM_DEBUG("IH: HPD%d\n", hpd + 1); 3124 } 3125 3126 return 0; 3127 3128 } 3129 3130 static int dce_v6_0_set_clockgating_state(void *handle, 3131 enum amd_clockgating_state state) 3132 { 3133 return 0; 3134 } 3135 3136 static int dce_v6_0_set_powergating_state(void *handle, 3137 enum amd_powergating_state state) 3138 { 3139 return 0; 3140 } 3141 3142 static const struct amd_ip_funcs dce_v6_0_ip_funcs = { 3143 .name = "dce_v6_0", 3144 .early_init = dce_v6_0_early_init, 3145 .late_init = NULL, 3146 .sw_init = dce_v6_0_sw_init, 3147 .sw_fini = dce_v6_0_sw_fini, 3148 .hw_init = dce_v6_0_hw_init, 3149 .hw_fini = dce_v6_0_hw_fini, 3150 .suspend = dce_v6_0_suspend, 3151 .resume = dce_v6_0_resume, 3152 .is_idle = dce_v6_0_is_idle, 3153 .wait_for_idle = dce_v6_0_wait_for_idle, 3154 .soft_reset = dce_v6_0_soft_reset, 3155 .set_clockgating_state = dce_v6_0_set_clockgating_state, 3156 .set_powergating_state = dce_v6_0_set_powergating_state, 3157 }; 3158 3159 static void 3160 dce_v6_0_encoder_mode_set(struct drm_encoder *encoder, 3161 struct drm_display_mode *mode, 3162 struct drm_display_mode *adjusted_mode) 3163 { 3164 3165 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3166 int em = amdgpu_atombios_encoder_get_encoder_mode(encoder); 3167 3168 amdgpu_encoder->pixel_clock = adjusted_mode->clock; 3169 3170 /* need to call this here rather than in prepare() since we need some crtc info */ 3171 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3172 3173 /* set scaler clears this on some chips */ 3174 dce_v6_0_set_interleave(encoder->crtc, mode); 3175 3176 if (em == ATOM_ENCODER_MODE_HDMI || ENCODER_MODE_IS_DP(em)) { 3177 dce_v6_0_afmt_enable(encoder, true); 3178 dce_v6_0_afmt_setmode(encoder, adjusted_mode); 3179 } 3180 } 3181 3182 static void dce_v6_0_encoder_prepare(struct drm_encoder *encoder) 3183 { 3184 3185 struct amdgpu_device *adev = drm_to_adev(encoder->dev); 3186 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3187 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 3188 3189 if ((amdgpu_encoder->active_device & 3190 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 3191 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != 3192 ENCODER_OBJECT_ID_NONE)) { 3193 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 3194 if (dig) { 3195 dig->dig_encoder = dce_v6_0_pick_dig_encoder(encoder); 3196 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) 3197 dig->afmt = adev->mode_info.afmt[dig->dig_encoder]; 3198 } 3199 } 3200 3201 amdgpu_atombios_scratch_regs_lock(adev, true); 3202 3203 if (connector) { 3204 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 3205 3206 /* select the clock/data port if it uses a router */ 3207 if (amdgpu_connector->router.cd_valid) 3208 amdgpu_i2c_router_select_cd_port(amdgpu_connector); 3209 3210 /* turn eDP panel on for mode set */ 3211 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 3212 amdgpu_atombios_encoder_set_edp_panel_power(connector, 3213 ATOM_TRANSMITTER_ACTION_POWER_ON); 3214 } 3215 3216 /* this is needed for the pll/ss setup to work correctly in some cases */ 3217 amdgpu_atombios_encoder_set_crtc_source(encoder); 3218 /* set up the FMT blocks */ 3219 dce_v6_0_program_fmt(encoder); 3220 } 3221 3222 static void dce_v6_0_encoder_commit(struct drm_encoder *encoder) 3223 { 3224 3225 struct drm_device *dev = encoder->dev; 3226 struct amdgpu_device *adev = drm_to_adev(dev); 3227 3228 /* need to call this here as we need the crtc set up */ 3229 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 3230 amdgpu_atombios_scratch_regs_lock(adev, false); 3231 } 3232 3233 static void dce_v6_0_encoder_disable(struct drm_encoder *encoder) 3234 { 3235 3236 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3237 struct amdgpu_encoder_atom_dig *dig; 3238 int em = amdgpu_atombios_encoder_get_encoder_mode(encoder); 3239 3240 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3241 3242 if (amdgpu_atombios_encoder_is_digital(encoder)) { 3243 if (em == ATOM_ENCODER_MODE_HDMI || ENCODER_MODE_IS_DP(em)) 3244 dce_v6_0_afmt_enable(encoder, false); 3245 dig = amdgpu_encoder->enc_priv; 3246 dig->dig_encoder = -1; 3247 } 3248 amdgpu_encoder->active_device = 0; 3249 } 3250 3251 /* these are handled by the primary encoders */ 3252 static void dce_v6_0_ext_prepare(struct drm_encoder *encoder) 3253 { 3254 3255 } 3256 3257 static void dce_v6_0_ext_commit(struct drm_encoder *encoder) 3258 { 3259 3260 } 3261 3262 static void 3263 dce_v6_0_ext_mode_set(struct drm_encoder *encoder, 3264 struct drm_display_mode *mode, 3265 struct drm_display_mode *adjusted_mode) 3266 { 3267 3268 } 3269 3270 static void dce_v6_0_ext_disable(struct drm_encoder *encoder) 3271 { 3272 3273 } 3274 3275 static void 3276 dce_v6_0_ext_dpms(struct drm_encoder *encoder, int mode) 3277 { 3278 3279 } 3280 3281 static bool dce_v6_0_ext_mode_fixup(struct drm_encoder *encoder, 3282 const struct drm_display_mode *mode, 3283 struct drm_display_mode *adjusted_mode) 3284 { 3285 return true; 3286 } 3287 3288 static const struct drm_encoder_helper_funcs dce_v6_0_ext_helper_funcs = { 3289 .dpms = dce_v6_0_ext_dpms, 3290 .mode_fixup = dce_v6_0_ext_mode_fixup, 3291 .prepare = dce_v6_0_ext_prepare, 3292 .mode_set = dce_v6_0_ext_mode_set, 3293 .commit = dce_v6_0_ext_commit, 3294 .disable = dce_v6_0_ext_disable, 3295 /* no detect for TMDS/LVDS yet */ 3296 }; 3297 3298 static const struct drm_encoder_helper_funcs dce_v6_0_dig_helper_funcs = { 3299 .dpms = amdgpu_atombios_encoder_dpms, 3300 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3301 .prepare = dce_v6_0_encoder_prepare, 3302 .mode_set = dce_v6_0_encoder_mode_set, 3303 .commit = dce_v6_0_encoder_commit, 3304 .disable = dce_v6_0_encoder_disable, 3305 .detect = amdgpu_atombios_encoder_dig_detect, 3306 }; 3307 3308 static const struct drm_encoder_helper_funcs dce_v6_0_dac_helper_funcs = { 3309 .dpms = amdgpu_atombios_encoder_dpms, 3310 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3311 .prepare = dce_v6_0_encoder_prepare, 3312 .mode_set = dce_v6_0_encoder_mode_set, 3313 .commit = dce_v6_0_encoder_commit, 3314 .detect = amdgpu_atombios_encoder_dac_detect, 3315 }; 3316 3317 static void dce_v6_0_encoder_destroy(struct drm_encoder *encoder) 3318 { 3319 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3320 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3321 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder); 3322 kfree(amdgpu_encoder->enc_priv); 3323 drm_encoder_cleanup(encoder); 3324 kfree(amdgpu_encoder); 3325 } 3326 3327 static const struct drm_encoder_funcs dce_v6_0_encoder_funcs = { 3328 .destroy = dce_v6_0_encoder_destroy, 3329 }; 3330 3331 static void dce_v6_0_encoder_add(struct amdgpu_device *adev, 3332 uint32_t encoder_enum, 3333 uint32_t supported_device, 3334 u16 caps) 3335 { 3336 struct drm_device *dev = adev_to_drm(adev); 3337 struct drm_encoder *encoder; 3338 struct amdgpu_encoder *amdgpu_encoder; 3339 3340 /* see if we already added it */ 3341 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 3342 amdgpu_encoder = to_amdgpu_encoder(encoder); 3343 if (amdgpu_encoder->encoder_enum == encoder_enum) { 3344 amdgpu_encoder->devices |= supported_device; 3345 return; 3346 } 3347 3348 } 3349 3350 /* add a new one */ 3351 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL); 3352 if (!amdgpu_encoder) 3353 return; 3354 3355 encoder = &amdgpu_encoder->base; 3356 switch (adev->mode_info.num_crtc) { 3357 case 1: 3358 encoder->possible_crtcs = 0x1; 3359 break; 3360 case 2: 3361 default: 3362 encoder->possible_crtcs = 0x3; 3363 break; 3364 case 4: 3365 encoder->possible_crtcs = 0xf; 3366 break; 3367 case 6: 3368 encoder->possible_crtcs = 0x3f; 3369 break; 3370 } 3371 3372 amdgpu_encoder->enc_priv = NULL; 3373 amdgpu_encoder->encoder_enum = encoder_enum; 3374 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 3375 amdgpu_encoder->devices = supported_device; 3376 amdgpu_encoder->rmx_type = RMX_OFF; 3377 amdgpu_encoder->underscan_type = UNDERSCAN_OFF; 3378 amdgpu_encoder->is_ext_encoder = false; 3379 amdgpu_encoder->caps = caps; 3380 3381 switch (amdgpu_encoder->encoder_id) { 3382 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 3383 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 3384 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3385 DRM_MODE_ENCODER_DAC, NULL); 3386 drm_encoder_helper_add(encoder, &dce_v6_0_dac_helper_funcs); 3387 break; 3388 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 3389 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 3390 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 3391 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 3392 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 3393 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 3394 amdgpu_encoder->rmx_type = RMX_FULL; 3395 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3396 DRM_MODE_ENCODER_LVDS, NULL); 3397 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder); 3398 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 3399 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3400 DRM_MODE_ENCODER_DAC, NULL); 3401 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3402 } else { 3403 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3404 DRM_MODE_ENCODER_TMDS, NULL); 3405 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3406 } 3407 drm_encoder_helper_add(encoder, &dce_v6_0_dig_helper_funcs); 3408 break; 3409 case ENCODER_OBJECT_ID_SI170B: 3410 case ENCODER_OBJECT_ID_CH7303: 3411 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: 3412 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: 3413 case ENCODER_OBJECT_ID_TITFP513: 3414 case ENCODER_OBJECT_ID_VT1623: 3415 case ENCODER_OBJECT_ID_HDMI_SI1930: 3416 case ENCODER_OBJECT_ID_TRAVIS: 3417 case ENCODER_OBJECT_ID_NUTMEG: 3418 /* these are handled by the primary encoders */ 3419 amdgpu_encoder->is_ext_encoder = true; 3420 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3421 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3422 DRM_MODE_ENCODER_LVDS, NULL); 3423 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) 3424 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3425 DRM_MODE_ENCODER_DAC, NULL); 3426 else 3427 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3428 DRM_MODE_ENCODER_TMDS, NULL); 3429 drm_encoder_helper_add(encoder, &dce_v6_0_ext_helper_funcs); 3430 break; 3431 } 3432 } 3433 3434 static const struct amdgpu_display_funcs dce_v6_0_display_funcs = { 3435 .bandwidth_update = &dce_v6_0_bandwidth_update, 3436 .vblank_get_counter = &dce_v6_0_vblank_get_counter, 3437 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level, 3438 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level, 3439 .hpd_sense = &dce_v6_0_hpd_sense, 3440 .hpd_set_polarity = &dce_v6_0_hpd_set_polarity, 3441 .hpd_get_gpio_reg = &dce_v6_0_hpd_get_gpio_reg, 3442 .page_flip = &dce_v6_0_page_flip, 3443 .page_flip_get_scanoutpos = &dce_v6_0_crtc_get_scanoutpos, 3444 .add_encoder = &dce_v6_0_encoder_add, 3445 .add_connector = &amdgpu_connector_add, 3446 }; 3447 3448 static void dce_v6_0_set_display_funcs(struct amdgpu_device *adev) 3449 { 3450 adev->mode_info.funcs = &dce_v6_0_display_funcs; 3451 } 3452 3453 static const struct amdgpu_irq_src_funcs dce_v6_0_crtc_irq_funcs = { 3454 .set = dce_v6_0_set_crtc_interrupt_state, 3455 .process = dce_v6_0_crtc_irq, 3456 }; 3457 3458 static const struct amdgpu_irq_src_funcs dce_v6_0_pageflip_irq_funcs = { 3459 .set = dce_v6_0_set_pageflip_interrupt_state, 3460 .process = dce_v6_0_pageflip_irq, 3461 }; 3462 3463 static const struct amdgpu_irq_src_funcs dce_v6_0_hpd_irq_funcs = { 3464 .set = dce_v6_0_set_hpd_interrupt_state, 3465 .process = dce_v6_0_hpd_irq, 3466 }; 3467 3468 static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev) 3469 { 3470 if (adev->mode_info.num_crtc > 0) 3471 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc; 3472 else 3473 adev->crtc_irq.num_types = 0; 3474 adev->crtc_irq.funcs = &dce_v6_0_crtc_irq_funcs; 3475 3476 adev->pageflip_irq.num_types = adev->mode_info.num_crtc; 3477 adev->pageflip_irq.funcs = &dce_v6_0_pageflip_irq_funcs; 3478 3479 adev->hpd_irq.num_types = adev->mode_info.num_hpd; 3480 adev->hpd_irq.funcs = &dce_v6_0_hpd_irq_funcs; 3481 } 3482 3483 const struct amdgpu_ip_block_version dce_v6_0_ip_block = 3484 { 3485 .type = AMD_IP_BLOCK_TYPE_DCE, 3486 .major = 6, 3487 .minor = 0, 3488 .rev = 0, 3489 .funcs = &dce_v6_0_ip_funcs, 3490 }; 3491 3492 const struct amdgpu_ip_block_version dce_v6_4_ip_block = 3493 { 3494 .type = AMD_IP_BLOCK_TYPE_DCE, 3495 .major = 6, 3496 .minor = 4, 3497 .rev = 0, 3498 .funcs = &dce_v6_0_ip_funcs, 3499 }; 3500