1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/kernel.h> 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 #include "amdgpu.h" 30 #include "amdgpu_gfx.h" 31 #include "amdgpu_psp.h" 32 #include "nv.h" 33 #include "nvd.h" 34 35 #include "gc/gc_10_1_0_offset.h" 36 #include "gc/gc_10_1_0_sh_mask.h" 37 #include "smuio/smuio_11_0_0_offset.h" 38 #include "smuio/smuio_11_0_0_sh_mask.h" 39 #include "navi10_enum.h" 40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h" 41 42 #include "soc15.h" 43 #include "soc15d.h" 44 #include "soc15_common.h" 45 #include "clearstate_gfx10.h" 46 #include "v10_structs.h" 47 #include "gfx_v10_0.h" 48 #include "nbio_v2_3.h" 49 50 /* 51 * Navi10 has two graphic rings to share each graphic pipe. 52 * 1. Primary ring 53 * 2. Async ring 54 */ 55 #define GFX10_NUM_GFX_RINGS_NV1X 1 56 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid 2 57 #define GFX10_MEC_HPD_SIZE 2048 58 59 #define F32_CE_PROGRAM_RAM_SIZE 65536 60 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 61 62 #define mmCGTT_GS_NGG_CLK_CTRL 0x5087 63 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1 64 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a 65 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1 66 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b 67 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1 68 69 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 70 #define GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L 71 72 #define mmCGTS_TCC_DISABLE_gc_10_3 0x5006 73 #define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX 1 74 #define mmCGTS_USER_TCC_DISABLE_gc_10_3 0x5007 75 #define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX 1 76 77 #define mmCP_MEC_CNTL_Sienna_Cichlid 0x0f55 78 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX 0 79 #define mmRLC_SAFE_MODE_Sienna_Cichlid 0x4ca0 80 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX 1 81 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid 0x4ca1 82 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX 1 83 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid 0x11ec 84 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX 0 85 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid 0x0fc1 86 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 87 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid 0x0fc2 88 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 89 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid 0x0fc3 90 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 91 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid 0x0fc4 92 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX 0 93 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid 0x0fc5 94 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX 0 95 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid 0x0fc6 96 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0 97 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT 0x1a 98 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK 0x04000000L 99 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK 0x00000FFCL 100 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT 0x2 101 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK 0x00000FFCL 102 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid 0x1580 103 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0 104 105 #define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish 0x0105 106 #define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish_BASE_IDX 1 107 #define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish 0x0106 108 #define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish_BASE_IDX 1 109 110 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh 0x0025 111 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX 1 112 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh 0x0026 113 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX 1 114 115 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6 0x002d 116 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6_BASE_IDX 1 117 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6 0x002e 118 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6_BASE_IDX 1 119 120 #define mmSPI_CONFIG_CNTL_1_Vangogh 0x2441 121 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX 1 122 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh 0x2261 123 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1 124 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh 0x224f 125 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX 1 126 #define mmVGT_TF_RING_SIZE_Vangogh 0x224e 127 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX 1 128 #define mmVGT_GSVS_RING_SIZE_Vangogh 0x2241 129 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX 1 130 #define mmVGT_TF_MEMORY_BASE_Vangogh 0x2250 131 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX 1 132 #define mmVGT_ESGS_RING_SIZE_Vangogh 0x2240 133 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX 1 134 #define mmSPI_CONFIG_CNTL_Vangogh 0x2440 135 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX 1 136 #define mmGCR_GENERAL_CNTL_Vangogh 0x1580 137 #define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX 0 138 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh 0x0000FFFFL 139 140 #define mmCP_HYP_PFP_UCODE_ADDR 0x5814 141 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1 142 #define mmCP_HYP_PFP_UCODE_DATA 0x5815 143 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX 1 144 #define mmCP_HYP_CE_UCODE_ADDR 0x5818 145 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX 1 146 #define mmCP_HYP_CE_UCODE_DATA 0x5819 147 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX 1 148 #define mmCP_HYP_ME_UCODE_ADDR 0x5816 149 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX 1 150 #define mmCP_HYP_ME_UCODE_DATA 0x5817 151 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX 1 152 153 #define mmCPG_PSP_DEBUG 0x5c10 154 #define mmCPG_PSP_DEBUG_BASE_IDX 1 155 #define mmCPC_PSP_DEBUG 0x5c11 156 #define mmCPC_PSP_DEBUG_BASE_IDX 1 157 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 158 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 159 160 //CC_GC_SA_UNIT_DISABLE 161 #define mmCC_GC_SA_UNIT_DISABLE 0x0fe9 162 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX 0 163 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 164 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 165 //GC_USER_SA_UNIT_DISABLE 166 #define mmGC_USER_SA_UNIT_DISABLE 0x0fea 167 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX 0 168 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 169 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 170 //PA_SC_ENHANCE_3 171 #define mmPA_SC_ENHANCE_3 0x1085 172 #define mmPA_SC_ENHANCE_3_BASE_IDX 0 173 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3 174 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK 0x00000008L 175 176 #define mmCGTT_SPI_CS_CLK_CTRL 0x507c 177 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX 1 178 179 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid 0x16f3 180 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 181 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid 0x15db 182 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 183 184 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid 0x2030 185 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX 0 186 187 #define mmRLC_SPARE_INT_0_Sienna_Cichlid 0x4ca5 188 #define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX 1 189 190 MODULE_FIRMWARE("amdgpu/navi10_ce.bin"); 191 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin"); 192 MODULE_FIRMWARE("amdgpu/navi10_me.bin"); 193 MODULE_FIRMWARE("amdgpu/navi10_mec.bin"); 194 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin"); 195 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin"); 196 197 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin"); 198 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin"); 199 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin"); 200 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin"); 201 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin"); 202 MODULE_FIRMWARE("amdgpu/navi14_ce.bin"); 203 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin"); 204 MODULE_FIRMWARE("amdgpu/navi14_me.bin"); 205 MODULE_FIRMWARE("amdgpu/navi14_mec.bin"); 206 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin"); 207 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin"); 208 209 MODULE_FIRMWARE("amdgpu/navi12_ce.bin"); 210 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin"); 211 MODULE_FIRMWARE("amdgpu/navi12_me.bin"); 212 MODULE_FIRMWARE("amdgpu/navi12_mec.bin"); 213 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin"); 214 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin"); 215 216 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin"); 217 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin"); 218 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin"); 219 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin"); 220 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin"); 221 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin"); 222 223 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin"); 224 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin"); 225 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin"); 226 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin"); 227 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin"); 228 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin"); 229 230 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin"); 231 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin"); 232 MODULE_FIRMWARE("amdgpu/vangogh_me.bin"); 233 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin"); 234 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin"); 235 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin"); 236 237 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin"); 238 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin"); 239 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin"); 240 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin"); 241 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin"); 242 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin"); 243 244 MODULE_FIRMWARE("amdgpu/beige_goby_ce.bin"); 245 MODULE_FIRMWARE("amdgpu/beige_goby_pfp.bin"); 246 MODULE_FIRMWARE("amdgpu/beige_goby_me.bin"); 247 MODULE_FIRMWARE("amdgpu/beige_goby_mec.bin"); 248 MODULE_FIRMWARE("amdgpu/beige_goby_mec2.bin"); 249 MODULE_FIRMWARE("amdgpu/beige_goby_rlc.bin"); 250 251 MODULE_FIRMWARE("amdgpu/yellow_carp_ce.bin"); 252 MODULE_FIRMWARE("amdgpu/yellow_carp_pfp.bin"); 253 MODULE_FIRMWARE("amdgpu/yellow_carp_me.bin"); 254 MODULE_FIRMWARE("amdgpu/yellow_carp_mec.bin"); 255 MODULE_FIRMWARE("amdgpu/yellow_carp_mec2.bin"); 256 MODULE_FIRMWARE("amdgpu/yellow_carp_rlc.bin"); 257 258 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_ce.bin"); 259 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_pfp.bin"); 260 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_me.bin"); 261 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec.bin"); 262 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec2.bin"); 263 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_rlc.bin"); 264 265 MODULE_FIRMWARE("amdgpu/gc_10_3_6_ce.bin"); 266 MODULE_FIRMWARE("amdgpu/gc_10_3_6_pfp.bin"); 267 MODULE_FIRMWARE("amdgpu/gc_10_3_6_me.bin"); 268 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec.bin"); 269 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec2.bin"); 270 MODULE_FIRMWARE("amdgpu/gc_10_3_6_rlc.bin"); 271 272 MODULE_FIRMWARE("amdgpu/gc_10_3_7_ce.bin"); 273 MODULE_FIRMWARE("amdgpu/gc_10_3_7_pfp.bin"); 274 MODULE_FIRMWARE("amdgpu/gc_10_3_7_me.bin"); 275 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin"); 276 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin"); 277 MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin"); 278 279 static const struct soc15_reg_golden golden_settings_gc_10_1[] = { 280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014), 281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), 282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100), 284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100), 285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100), 287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff), 290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000), 291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000), 294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), 304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188), 306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104), 313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), 315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100), 319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000) 320 }; 321 322 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] = { 323 /* Pending on emulation bring up */ 324 }; 325 326 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] = { 327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0), 328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 1002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 1006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 1052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 1056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19), 1366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20), 1368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5), 1370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa), 1372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14), 1374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19), 1376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33), 1378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 1379 }; 1380 1381 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = { 1382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014), 1383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 1386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100), 1387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100), 1388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 1392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 1396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), 1397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 1401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 1410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 1411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105), 1414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 1419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000), 1420 }; 1421 1422 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = { 1423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014), 1424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100), 1427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100), 1428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100), 1429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000), 1433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 1437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), 1438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044), 1441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe), 1443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 1445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 1446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02), 1452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000), 1455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820), 1456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104), 1459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010), 1464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000) 1465 }; 1466 1467 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = { 1468 /* Pending on emulation bring up */ 1469 }; 1470 1471 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] = { 1472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0), 1473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 1611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 1653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 1743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 1747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 1751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 1755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 1759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 1763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 1767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 1771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 1775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 1779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 1783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 1787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 1791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 1795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 1799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 1803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 1807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 1811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 1823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 1827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4), 1835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 1839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 1843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 1871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 1891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 1911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 2003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 2007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0), 2011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4), 2015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0), 2019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4), 2023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8), 2027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac), 2031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8), 2035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc), 2039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8), 2043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc), 2047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0), 2051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4), 2055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26), 2079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28), 2081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf), 2083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15), 2085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f), 2087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25), 2089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b), 2091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 2092 }; 2093 2094 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] = { 2095 /* Pending on emulation bring up */ 2096 }; 2097 2098 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] = { 2099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0), 2100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 2318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 2822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 2826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 2830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 2834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 2838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 2842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 2846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 2850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 2854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 2858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 2862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 2866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 2870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 2874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 2878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 2882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 2886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 2890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 2894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 2898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 2902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 2906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 2910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 2912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 2914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 2916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 2918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 2922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 2926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 2930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 2934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 2938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 2942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 2946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 2950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 2954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 2958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 2962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 2966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 2970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 2974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 2978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 2982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 2986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 2990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 2994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 2998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 3002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 3006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 3010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 3014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 3018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 3110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 3112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 3114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 3116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 3134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f), 3138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22), 3140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1), 3142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6), 3144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10), 3146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15), 3148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35), 3150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 3151 }; 3152 3153 static const struct soc15_reg_golden golden_settings_gc_10_3[] = { 3154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100), 3163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088), 3164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), 3166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), 3167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988), 3172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000) 3197 }; 3198 3199 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] = { 3200 /* Pending on emulation bring up */ 3201 }; 3202 3203 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] = { 3204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080), 3214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080), 3215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004), 3225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000), 3244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff), 3245 3246 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */ 3247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3248 }; 3249 3250 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] = { 3251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 3255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142), 3258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020), 3269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103), 3270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000), 3274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff), 3275 3276 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */ 3277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3278 }; 3279 3280 static const struct soc15_reg_golden golden_settings_gc_10_3_3[] = { 3281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 3284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242), 3287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) 3301 }; 3302 3303 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] = { 3304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100), 3306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100), 3307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280), 3309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000), 3310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500), 3311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400), 3312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008), 3315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988), 3316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007), 3317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 3319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070), 3320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000), 3338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000), 3339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020) 3340 }; 3341 3342 static const struct soc15_reg_golden golden_settings_gc_10_3_5[] = { 3343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xb0000ff0, 0x30000100), 3345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff000000, 0x7e000100), 3346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000) 3375 }; 3376 3377 static const struct soc15_reg_golden golden_settings_gc_10_0_cyan_skillfish[] = { 3378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000), 3379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_FAST_CLKS, 0x3fffffff, 0x0000493e), 3380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), 3381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x3c000100), 3382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0xa0000000, 0xa0000000), 3383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x00008000, 0x003c8014), 3384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_DRAM_BURST_CTRL, 0x00000010, 0x00000017), 3385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xd8d8d8d8), 3386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000003), 3387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 3388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 3389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 3390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000), 3391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860210), 3392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044), 3393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00009d00, 0x00008500), 3394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END, 0xffffffff, 0x000fffff), 3395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_DRAM_BURST_CTRL, 0x00000010, 0x00000017), 3396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xfcfcfcfc, 0xd8d8d8d8), 3397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77707770, 0x21302130), 3398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77707770, 0x21302130), 3399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), 3402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xfc02002f, 0x9402002f), 3403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00002188, 0x00000188), 3404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x08000009, 0x08000009), 3405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xcc3fcc03, 0x842a4c02), 3406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000000f, 0x00000000), 3407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffff3109, 0xffff3101), 3408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), 3409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 3410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x00030008, 0x01030000), 3411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000) 3412 }; 3413 3414 static const struct soc15_reg_golden golden_settings_gc_10_3_6[] = { 3415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x00000044), 3417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 3418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000042), 3421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x00000044), 3423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020), 3435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) 3437 }; 3438 3439 static const struct soc15_reg_golden golden_settings_gc_10_3_7[] = { 3440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 3443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000041), 3446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff), 3451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff), 3452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf000003f, 0x01200007), 3456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020), 3460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) 3462 }; 3463 3464 #define DEFAULT_SH_MEM_CONFIG \ 3465 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 3466 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 3467 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \ 3468 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 3469 3470 /* TODO: pending on golden setting value of gb address config */ 3471 #define CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN 0x00100044 3472 3473 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev); 3474 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev); 3475 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev); 3476 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev); 3477 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev); 3478 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 3479 struct amdgpu_cu_info *cu_info); 3480 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev); 3481 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 3482 u32 sh_num, u32 instance, int xcc_id); 3483 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 3484 3485 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev); 3486 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev); 3487 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev); 3488 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 3489 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume); 3490 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 3491 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 3492 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev); 3493 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev); 3494 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev); 3495 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 3496 uint16_t pasid, uint32_t flush_type, 3497 bool all_hub, uint8_t dst_sel); 3498 static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev, 3499 unsigned int vmid); 3500 3501 static int gfx_v10_0_set_powergating_state(void *handle, 3502 enum amd_powergating_state state); 3503 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) 3504 { 3505 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 3506 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 3507 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 3508 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 3509 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 3510 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 3511 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 3512 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 3513 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 3514 } 3515 3516 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring, 3517 struct amdgpu_ring *ring) 3518 { 3519 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 3520 uint64_t wptr_addr = ring->wptr_gpu_addr; 3521 uint32_t eng_sel = 0; 3522 3523 switch (ring->funcs->type) { 3524 case AMDGPU_RING_TYPE_COMPUTE: 3525 eng_sel = 0; 3526 break; 3527 case AMDGPU_RING_TYPE_GFX: 3528 eng_sel = 4; 3529 break; 3530 case AMDGPU_RING_TYPE_MES: 3531 eng_sel = 5; 3532 break; 3533 default: 3534 WARN_ON(1); 3535 } 3536 3537 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 3538 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 3539 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3540 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 3541 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 3542 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 3543 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 3544 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 3545 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 3546 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 3547 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 3548 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 3549 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 3550 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 3551 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 3552 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 3553 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 3554 } 3555 3556 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 3557 struct amdgpu_ring *ring, 3558 enum amdgpu_unmap_queues_action action, 3559 u64 gpu_addr, u64 seq) 3560 { 3561 struct amdgpu_device *adev = kiq_ring->adev; 3562 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3563 3564 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { 3565 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq); 3566 return; 3567 } 3568 3569 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 3570 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3571 PACKET3_UNMAP_QUEUES_ACTION(action) | 3572 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 3573 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 3574 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 3575 amdgpu_ring_write(kiq_ring, 3576 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 3577 3578 if (action == PREEMPT_QUEUES_NO_UNMAP) { 3579 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 3580 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 3581 amdgpu_ring_write(kiq_ring, seq); 3582 } else { 3583 amdgpu_ring_write(kiq_ring, 0); 3584 amdgpu_ring_write(kiq_ring, 0); 3585 amdgpu_ring_write(kiq_ring, 0); 3586 } 3587 } 3588 3589 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring, 3590 struct amdgpu_ring *ring, 3591 u64 addr, 3592 u64 seq) 3593 { 3594 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3595 3596 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 3597 amdgpu_ring_write(kiq_ring, 3598 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 3599 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 3600 PACKET3_QUERY_STATUS_COMMAND(2)); 3601 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3602 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 3603 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 3604 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 3605 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 3606 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 3607 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 3608 } 3609 3610 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 3611 uint16_t pasid, uint32_t flush_type, 3612 bool all_hub) 3613 { 3614 gfx_v10_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 3615 } 3616 3617 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = { 3618 .kiq_set_resources = gfx10_kiq_set_resources, 3619 .kiq_map_queues = gfx10_kiq_map_queues, 3620 .kiq_unmap_queues = gfx10_kiq_unmap_queues, 3621 .kiq_query_status = gfx10_kiq_query_status, 3622 .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs, 3623 .set_resources_size = 8, 3624 .map_queues_size = 7, 3625 .unmap_queues_size = 6, 3626 .query_status_size = 7, 3627 .invalidate_tlbs_size = 2, 3628 }; 3629 3630 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 3631 { 3632 adev->gfx.kiq[0].pmf = &gfx_v10_0_kiq_pm4_funcs; 3633 } 3634 3635 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev) 3636 { 3637 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3638 case IP_VERSION(10, 1, 10): 3639 soc15_program_register_sequence(adev, 3640 golden_settings_gc_rlc_spm_10_0_nv10, 3641 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10)); 3642 break; 3643 case IP_VERSION(10, 1, 1): 3644 soc15_program_register_sequence(adev, 3645 golden_settings_gc_rlc_spm_10_1_nv14, 3646 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14)); 3647 break; 3648 case IP_VERSION(10, 1, 2): 3649 soc15_program_register_sequence(adev, 3650 golden_settings_gc_rlc_spm_10_1_2_nv12, 3651 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12)); 3652 break; 3653 default: 3654 break; 3655 } 3656 } 3657 3658 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev) 3659 { 3660 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3661 case IP_VERSION(10, 1, 10): 3662 soc15_program_register_sequence(adev, 3663 golden_settings_gc_10_1, 3664 (const u32)ARRAY_SIZE(golden_settings_gc_10_1)); 3665 soc15_program_register_sequence(adev, 3666 golden_settings_gc_10_0_nv10, 3667 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10)); 3668 break; 3669 case IP_VERSION(10, 1, 1): 3670 soc15_program_register_sequence(adev, 3671 golden_settings_gc_10_1_1, 3672 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1)); 3673 soc15_program_register_sequence(adev, 3674 golden_settings_gc_10_1_nv14, 3675 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14)); 3676 break; 3677 case IP_VERSION(10, 1, 2): 3678 soc15_program_register_sequence(adev, 3679 golden_settings_gc_10_1_2, 3680 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2)); 3681 soc15_program_register_sequence(adev, 3682 golden_settings_gc_10_1_2_nv12, 3683 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12)); 3684 break; 3685 case IP_VERSION(10, 3, 0): 3686 soc15_program_register_sequence(adev, 3687 golden_settings_gc_10_3, 3688 (const u32)ARRAY_SIZE(golden_settings_gc_10_3)); 3689 soc15_program_register_sequence(adev, 3690 golden_settings_gc_10_3_sienna_cichlid, 3691 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid)); 3692 break; 3693 case IP_VERSION(10, 3, 2): 3694 soc15_program_register_sequence(adev, 3695 golden_settings_gc_10_3_2, 3696 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2)); 3697 break; 3698 case IP_VERSION(10, 3, 1): 3699 soc15_program_register_sequence(adev, 3700 golden_settings_gc_10_3_vangogh, 3701 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh)); 3702 break; 3703 case IP_VERSION(10, 3, 3): 3704 soc15_program_register_sequence(adev, 3705 golden_settings_gc_10_3_3, 3706 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_3)); 3707 break; 3708 case IP_VERSION(10, 3, 4): 3709 soc15_program_register_sequence(adev, 3710 golden_settings_gc_10_3_4, 3711 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4)); 3712 break; 3713 case IP_VERSION(10, 3, 5): 3714 soc15_program_register_sequence(adev, 3715 golden_settings_gc_10_3_5, 3716 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_5)); 3717 break; 3718 case IP_VERSION(10, 1, 3): 3719 case IP_VERSION(10, 1, 4): 3720 soc15_program_register_sequence(adev, 3721 golden_settings_gc_10_0_cyan_skillfish, 3722 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_cyan_skillfish)); 3723 break; 3724 case IP_VERSION(10, 3, 6): 3725 soc15_program_register_sequence(adev, 3726 golden_settings_gc_10_3_6, 3727 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_6)); 3728 break; 3729 case IP_VERSION(10, 3, 7): 3730 soc15_program_register_sequence(adev, 3731 golden_settings_gc_10_3_7, 3732 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_7)); 3733 break; 3734 default: 3735 break; 3736 } 3737 gfx_v10_0_init_spm_golden_registers(adev); 3738 } 3739 3740 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 3741 bool wc, uint32_t reg, uint32_t val) 3742 { 3743 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3744 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 3745 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); 3746 amdgpu_ring_write(ring, reg); 3747 amdgpu_ring_write(ring, 0); 3748 amdgpu_ring_write(ring, val); 3749 } 3750 3751 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 3752 int mem_space, int opt, uint32_t addr0, 3753 uint32_t addr1, uint32_t ref, uint32_t mask, 3754 uint32_t inv) 3755 { 3756 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 3757 amdgpu_ring_write(ring, 3758 /* memory (1) or register (0) */ 3759 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 3760 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 3761 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 3762 WAIT_REG_MEM_ENGINE(eng_sel))); 3763 3764 if (mem_space) 3765 BUG_ON(addr0 & 0x3); /* Dword align */ 3766 amdgpu_ring_write(ring, addr0); 3767 amdgpu_ring_write(ring, addr1); 3768 amdgpu_ring_write(ring, ref); 3769 amdgpu_ring_write(ring, mask); 3770 amdgpu_ring_write(ring, inv); /* poll interval */ 3771 } 3772 3773 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring) 3774 { 3775 struct amdgpu_device *adev = ring->adev; 3776 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 3777 uint32_t tmp = 0; 3778 unsigned int i; 3779 int r; 3780 3781 WREG32(scratch, 0xCAFEDEAD); 3782 r = amdgpu_ring_alloc(ring, 3); 3783 if (r) { 3784 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 3785 ring->idx, r); 3786 return r; 3787 } 3788 3789 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 3790 amdgpu_ring_write(ring, scratch - 3791 PACKET3_SET_UCONFIG_REG_START); 3792 amdgpu_ring_write(ring, 0xDEADBEEF); 3793 amdgpu_ring_commit(ring); 3794 3795 for (i = 0; i < adev->usec_timeout; i++) { 3796 tmp = RREG32(scratch); 3797 if (tmp == 0xDEADBEEF) 3798 break; 3799 if (amdgpu_emu_mode == 1) 3800 msleep(1); 3801 else 3802 udelay(1); 3803 } 3804 3805 if (i >= adev->usec_timeout) 3806 r = -ETIMEDOUT; 3807 3808 return r; 3809 } 3810 3811 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 3812 { 3813 struct amdgpu_device *adev = ring->adev; 3814 struct amdgpu_ib ib; 3815 struct dma_fence *f = NULL; 3816 unsigned int index; 3817 uint64_t gpu_addr; 3818 volatile uint32_t *cpu_ptr; 3819 long r; 3820 3821 memset(&ib, 0, sizeof(ib)); 3822 3823 if (ring->is_mes_queue) { 3824 uint32_t padding, offset; 3825 3826 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS); 3827 padding = amdgpu_mes_ctx_get_offs(ring, 3828 AMDGPU_MES_CTX_PADDING_OFFS); 3829 3830 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 3831 ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 3832 3833 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding); 3834 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding); 3835 *cpu_ptr = cpu_to_le32(0xCAFEDEAD); 3836 } else { 3837 r = amdgpu_device_wb_get(adev, &index); 3838 if (r) 3839 return r; 3840 3841 gpu_addr = adev->wb.gpu_addr + (index * 4); 3842 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 3843 cpu_ptr = &adev->wb.wb[index]; 3844 3845 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib); 3846 if (r) { 3847 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 3848 goto err1; 3849 } 3850 } 3851 3852 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 3853 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 3854 ib.ptr[2] = lower_32_bits(gpu_addr); 3855 ib.ptr[3] = upper_32_bits(gpu_addr); 3856 ib.ptr[4] = 0xDEADBEEF; 3857 ib.length_dw = 5; 3858 3859 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 3860 if (r) 3861 goto err2; 3862 3863 r = dma_fence_wait_timeout(f, false, timeout); 3864 if (r == 0) { 3865 r = -ETIMEDOUT; 3866 goto err2; 3867 } else if (r < 0) { 3868 goto err2; 3869 } 3870 3871 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 3872 r = 0; 3873 else 3874 r = -EINVAL; 3875 err2: 3876 if (!ring->is_mes_queue) 3877 amdgpu_ib_free(adev, &ib, NULL); 3878 dma_fence_put(f); 3879 err1: 3880 if (!ring->is_mes_queue) 3881 amdgpu_device_wb_free(adev, index); 3882 return r; 3883 } 3884 3885 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev) 3886 { 3887 amdgpu_ucode_release(&adev->gfx.pfp_fw); 3888 amdgpu_ucode_release(&adev->gfx.me_fw); 3889 amdgpu_ucode_release(&adev->gfx.ce_fw); 3890 amdgpu_ucode_release(&adev->gfx.rlc_fw); 3891 amdgpu_ucode_release(&adev->gfx.mec_fw); 3892 amdgpu_ucode_release(&adev->gfx.mec2_fw); 3893 3894 kfree(adev->gfx.rlc.register_list_format); 3895 } 3896 3897 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev) 3898 { 3899 adev->gfx.cp_fw_write_wait = false; 3900 3901 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3902 case IP_VERSION(10, 1, 10): 3903 case IP_VERSION(10, 1, 2): 3904 case IP_VERSION(10, 1, 1): 3905 case IP_VERSION(10, 1, 3): 3906 case IP_VERSION(10, 1, 4): 3907 if ((adev->gfx.me_fw_version >= 0x00000046) && 3908 (adev->gfx.me_feature_version >= 27) && 3909 (adev->gfx.pfp_fw_version >= 0x00000068) && 3910 (adev->gfx.pfp_feature_version >= 27) && 3911 (adev->gfx.mec_fw_version >= 0x0000005b) && 3912 (adev->gfx.mec_feature_version >= 27)) 3913 adev->gfx.cp_fw_write_wait = true; 3914 break; 3915 case IP_VERSION(10, 3, 0): 3916 case IP_VERSION(10, 3, 2): 3917 case IP_VERSION(10, 3, 1): 3918 case IP_VERSION(10, 3, 4): 3919 case IP_VERSION(10, 3, 5): 3920 case IP_VERSION(10, 3, 6): 3921 case IP_VERSION(10, 3, 3): 3922 case IP_VERSION(10, 3, 7): 3923 adev->gfx.cp_fw_write_wait = true; 3924 break; 3925 default: 3926 break; 3927 } 3928 3929 if (!adev->gfx.cp_fw_write_wait) 3930 DRM_WARN_ONCE("CP firmware version too old, please update!"); 3931 } 3932 3933 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev) 3934 { 3935 bool ret = false; 3936 3937 switch (adev->pdev->revision) { 3938 case 0xc2: 3939 case 0xc3: 3940 ret = true; 3941 break; 3942 default: 3943 ret = false; 3944 break; 3945 } 3946 3947 return ret; 3948 } 3949 3950 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev) 3951 { 3952 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3953 case IP_VERSION(10, 1, 10): 3954 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev)) 3955 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 3956 break; 3957 default: 3958 break; 3959 } 3960 } 3961 3962 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) 3963 { 3964 char fw_name[40]; 3965 char ucode_prefix[30]; 3966 const char *wks = ""; 3967 int err; 3968 const struct rlc_firmware_header_v2_0 *rlc_hdr; 3969 uint16_t version_major; 3970 uint16_t version_minor; 3971 3972 DRM_DEBUG("\n"); 3973 3974 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 1) && 3975 (!(adev->pdev->device == 0x7340 && adev->pdev->revision != 0x00))) 3976 wks = "_wks"; 3977 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 3978 3979 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", ucode_prefix, wks); 3980 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); 3981 if (err) 3982 goto out; 3983 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP); 3984 3985 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", ucode_prefix, wks); 3986 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name); 3987 if (err) 3988 goto out; 3989 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME); 3990 3991 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", ucode_prefix, wks); 3992 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name); 3993 if (err) 3994 goto out; 3995 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE); 3996 3997 if (!amdgpu_sriov_vf(adev)) { 3998 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix); 3999 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 4000 if (err) 4001 goto out; 4002 4003 /* don't validate this firmware. There are apparently firmwares 4004 * in the wild with incorrect size in the header 4005 */ 4006 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 4007 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 4008 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 4009 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 4010 if (err) 4011 goto out; 4012 } 4013 4014 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", ucode_prefix, wks); 4015 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); 4016 if (err) 4017 goto out; 4018 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 4019 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 4020 4021 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", ucode_prefix, wks); 4022 err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, fw_name); 4023 if (!err) { 4024 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2); 4025 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT); 4026 } else { 4027 err = 0; 4028 adev->gfx.mec2_fw = NULL; 4029 } 4030 4031 gfx_v10_0_check_fw_write_wait(adev); 4032 out: 4033 if (err) { 4034 amdgpu_ucode_release(&adev->gfx.pfp_fw); 4035 amdgpu_ucode_release(&adev->gfx.me_fw); 4036 amdgpu_ucode_release(&adev->gfx.ce_fw); 4037 amdgpu_ucode_release(&adev->gfx.rlc_fw); 4038 amdgpu_ucode_release(&adev->gfx.mec_fw); 4039 amdgpu_ucode_release(&adev->gfx.mec2_fw); 4040 } 4041 4042 gfx_v10_0_check_gfxoff_flag(adev); 4043 4044 return err; 4045 } 4046 4047 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev) 4048 { 4049 u32 count = 0; 4050 const struct cs_section_def *sect = NULL; 4051 const struct cs_extent_def *ext = NULL; 4052 4053 /* begin clear state */ 4054 count += 2; 4055 /* context control state */ 4056 count += 3; 4057 4058 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 4059 for (ext = sect->section; ext->extent != NULL; ++ext) { 4060 if (sect->id == SECT_CONTEXT) 4061 count += 2 + ext->reg_count; 4062 else 4063 return 0; 4064 } 4065 } 4066 4067 /* set PA_SC_TILE_STEERING_OVERRIDE */ 4068 count += 3; 4069 /* end clear state */ 4070 count += 2; 4071 /* clear state */ 4072 count += 2; 4073 4074 return count; 4075 } 4076 4077 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev, 4078 volatile u32 *buffer) 4079 { 4080 u32 count = 0, i; 4081 const struct cs_section_def *sect = NULL; 4082 const struct cs_extent_def *ext = NULL; 4083 int ctx_reg_offset; 4084 4085 if (adev->gfx.rlc.cs_data == NULL) 4086 return; 4087 if (buffer == NULL) 4088 return; 4089 4090 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4091 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 4092 4093 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4094 buffer[count++] = cpu_to_le32(0x80000000); 4095 buffer[count++] = cpu_to_le32(0x80000000); 4096 4097 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 4098 for (ext = sect->section; ext->extent != NULL; ++ext) { 4099 if (sect->id == SECT_CONTEXT) { 4100 buffer[count++] = 4101 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 4102 buffer[count++] = cpu_to_le32(ext->reg_index - 4103 PACKET3_SET_CONTEXT_REG_START); 4104 for (i = 0; i < ext->reg_count; i++) 4105 buffer[count++] = cpu_to_le32(ext->extent[i]); 4106 } else { 4107 return; 4108 } 4109 } 4110 } 4111 4112 ctx_reg_offset = 4113 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 4114 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 4115 buffer[count++] = cpu_to_le32(ctx_reg_offset); 4116 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); 4117 4118 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4119 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 4120 4121 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 4122 buffer[count++] = cpu_to_le32(0); 4123 } 4124 4125 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev) 4126 { 4127 /* clear state block */ 4128 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 4129 &adev->gfx.rlc.clear_state_gpu_addr, 4130 (void **)&adev->gfx.rlc.cs_ptr); 4131 4132 /* jump table block */ 4133 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 4134 &adev->gfx.rlc.cp_table_gpu_addr, 4135 (void **)&adev->gfx.rlc.cp_table_ptr); 4136 } 4137 4138 static void gfx_v10_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 4139 { 4140 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 4141 4142 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; 4143 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 4144 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1); 4145 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2); 4146 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3); 4147 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL); 4148 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX); 4149 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4150 case IP_VERSION(10, 3, 0): 4151 reg_access_ctrl->spare_int = 4152 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT_0_Sienna_Cichlid); 4153 break; 4154 default: 4155 reg_access_ctrl->spare_int = 4156 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT); 4157 break; 4158 } 4159 adev->gfx.rlc.rlcg_reg_access_supported = true; 4160 } 4161 4162 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev) 4163 { 4164 const struct cs_section_def *cs_data; 4165 int r; 4166 4167 adev->gfx.rlc.cs_data = gfx10_cs_data; 4168 4169 cs_data = adev->gfx.rlc.cs_data; 4170 4171 if (cs_data) { 4172 /* init clear state block */ 4173 r = amdgpu_gfx_rlc_init_csb(adev); 4174 if (r) 4175 return r; 4176 } 4177 4178 return 0; 4179 } 4180 4181 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev) 4182 { 4183 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 4184 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 4185 } 4186 4187 static void gfx_v10_0_me_init(struct amdgpu_device *adev) 4188 { 4189 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 4190 4191 amdgpu_gfx_graphics_queue_acquire(adev); 4192 } 4193 4194 static int gfx_v10_0_mec_init(struct amdgpu_device *adev) 4195 { 4196 int r; 4197 u32 *hpd; 4198 const __le32 *fw_data = NULL; 4199 unsigned int fw_size; 4200 u32 *fw = NULL; 4201 size_t mec_hpd_size; 4202 4203 const struct gfx_firmware_header_v1_0 *mec_hdr = NULL; 4204 4205 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 4206 4207 /* take ownership of the relevant compute queues */ 4208 amdgpu_gfx_compute_queue_acquire(adev); 4209 mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE; 4210 4211 if (mec_hpd_size) { 4212 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 4213 AMDGPU_GEM_DOMAIN_GTT, 4214 &adev->gfx.mec.hpd_eop_obj, 4215 &adev->gfx.mec.hpd_eop_gpu_addr, 4216 (void **)&hpd); 4217 if (r) { 4218 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 4219 gfx_v10_0_mec_fini(adev); 4220 return r; 4221 } 4222 4223 memset(hpd, 0, mec_hpd_size); 4224 4225 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 4226 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 4227 } 4228 4229 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4230 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 4231 4232 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 4233 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 4234 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 4235 4236 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 4237 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 4238 &adev->gfx.mec.mec_fw_obj, 4239 &adev->gfx.mec.mec_fw_gpu_addr, 4240 (void **)&fw); 4241 if (r) { 4242 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r); 4243 gfx_v10_0_mec_fini(adev); 4244 return r; 4245 } 4246 4247 memcpy(fw, fw_data, fw_size); 4248 4249 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 4250 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 4251 } 4252 4253 return 0; 4254 } 4255 4256 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 4257 { 4258 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4259 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4260 (address << SQ_IND_INDEX__INDEX__SHIFT)); 4261 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4262 } 4263 4264 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 4265 uint32_t thread, uint32_t regno, 4266 uint32_t num, uint32_t *out) 4267 { 4268 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4269 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4270 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 4271 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 4272 (SQ_IND_INDEX__AUTO_INCR_MASK)); 4273 while (num--) 4274 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4275 } 4276 4277 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 4278 { 4279 /* in gfx10 the SIMD_ID is specified as part of the INSTANCE 4280 * field when performing a select_se_sh so it should be 4281 * zero here 4282 */ 4283 WARN_ON(simd != 0); 4284 4285 /* type 2 wave data */ 4286 dst[(*no_fields)++] = 2; 4287 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 4288 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 4289 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 4290 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 4291 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 4292 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 4293 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 4294 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0); 4295 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 4296 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 4297 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); 4298 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 4299 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 4300 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 4301 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 4302 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); 4303 } 4304 4305 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 4306 uint32_t wave, uint32_t start, 4307 uint32_t size, uint32_t *dst) 4308 { 4309 WARN_ON(simd != 0); 4310 4311 wave_read_regs( 4312 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 4313 dst); 4314 } 4315 4316 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 4317 uint32_t wave, uint32_t thread, 4318 uint32_t start, uint32_t size, 4319 uint32_t *dst) 4320 { 4321 wave_read_regs( 4322 adev, wave, thread, 4323 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 4324 } 4325 4326 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev, 4327 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 4328 { 4329 nv_grbm_select(adev, me, pipe, q, vm); 4330 } 4331 4332 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev, 4333 bool enable) 4334 { 4335 uint32_t data, def; 4336 4337 data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL); 4338 4339 if (enable) 4340 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4341 else 4342 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4343 4344 if (data != def) 4345 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data); 4346 } 4347 4348 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = { 4349 .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter, 4350 .select_se_sh = &gfx_v10_0_select_se_sh, 4351 .read_wave_data = &gfx_v10_0_read_wave_data, 4352 .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs, 4353 .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs, 4354 .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q, 4355 .init_spm_golden = &gfx_v10_0_init_spm_golden_registers, 4356 .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg, 4357 }; 4358 4359 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev) 4360 { 4361 u32 gb_addr_config; 4362 4363 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4364 case IP_VERSION(10, 1, 10): 4365 case IP_VERSION(10, 1, 1): 4366 case IP_VERSION(10, 1, 2): 4367 adev->gfx.config.max_hw_contexts = 8; 4368 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4369 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4370 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4371 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4372 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4373 break; 4374 case IP_VERSION(10, 3, 0): 4375 case IP_VERSION(10, 3, 2): 4376 case IP_VERSION(10, 3, 1): 4377 case IP_VERSION(10, 3, 4): 4378 case IP_VERSION(10, 3, 5): 4379 case IP_VERSION(10, 3, 6): 4380 case IP_VERSION(10, 3, 3): 4381 case IP_VERSION(10, 3, 7): 4382 adev->gfx.config.max_hw_contexts = 8; 4383 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4384 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4385 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4386 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4387 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4388 adev->gfx.config.gb_addr_config_fields.num_pkrs = 4389 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 4390 break; 4391 case IP_VERSION(10, 1, 3): 4392 case IP_VERSION(10, 1, 4): 4393 adev->gfx.config.max_hw_contexts = 8; 4394 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4395 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4396 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 4397 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4398 gb_addr_config = CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN; 4399 break; 4400 default: 4401 BUG(); 4402 break; 4403 } 4404 4405 adev->gfx.config.gb_addr_config = gb_addr_config; 4406 4407 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 4408 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4409 GB_ADDR_CONFIG, NUM_PIPES); 4410 4411 adev->gfx.config.max_tile_pipes = 4412 adev->gfx.config.gb_addr_config_fields.num_pipes; 4413 4414 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 4415 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4416 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 4417 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 4418 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4419 GB_ADDR_CONFIG, NUM_RB_PER_SE); 4420 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 4421 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4422 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 4423 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 4424 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4425 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 4426 } 4427 4428 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 4429 int me, int pipe, int queue) 4430 { 4431 struct amdgpu_ring *ring; 4432 unsigned int irq_type; 4433 unsigned int hw_prio; 4434 4435 ring = &adev->gfx.gfx_ring[ring_id]; 4436 4437 ring->me = me; 4438 ring->pipe = pipe; 4439 ring->queue = queue; 4440 4441 ring->ring_obj = NULL; 4442 ring->use_doorbell = true; 4443 4444 if (!ring_id) 4445 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 4446 else 4447 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 4448 ring->vm_hub = AMDGPU_GFXHUB(0); 4449 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4450 4451 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 4452 hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ? 4453 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 4454 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 4455 hw_prio, NULL); 4456 } 4457 4458 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 4459 int mec, int pipe, int queue) 4460 { 4461 unsigned int irq_type; 4462 struct amdgpu_ring *ring; 4463 unsigned int hw_prio; 4464 4465 ring = &adev->gfx.compute_ring[ring_id]; 4466 4467 /* mec0 is me1 */ 4468 ring->me = mec + 1; 4469 ring->pipe = pipe; 4470 ring->queue = queue; 4471 4472 ring->ring_obj = NULL; 4473 ring->use_doorbell = true; 4474 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 4475 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 4476 + (ring_id * GFX10_MEC_HPD_SIZE); 4477 ring->vm_hub = AMDGPU_GFXHUB(0); 4478 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4479 4480 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 4481 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 4482 + ring->pipe; 4483 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 4484 AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT; 4485 /* type-2 packets are deprecated on MEC, use type-3 instead */ 4486 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 4487 hw_prio, NULL); 4488 } 4489 4490 static int gfx_v10_0_sw_init(void *handle) 4491 { 4492 int i, j, k, r, ring_id = 0; 4493 struct amdgpu_kiq *kiq; 4494 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4495 4496 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4497 case IP_VERSION(10, 1, 10): 4498 case IP_VERSION(10, 1, 1): 4499 case IP_VERSION(10, 1, 2): 4500 case IP_VERSION(10, 1, 3): 4501 case IP_VERSION(10, 1, 4): 4502 adev->gfx.me.num_me = 1; 4503 adev->gfx.me.num_pipe_per_me = 1; 4504 adev->gfx.me.num_queue_per_pipe = 1; 4505 adev->gfx.mec.num_mec = 2; 4506 adev->gfx.mec.num_pipe_per_mec = 4; 4507 adev->gfx.mec.num_queue_per_pipe = 8; 4508 break; 4509 case IP_VERSION(10, 3, 0): 4510 case IP_VERSION(10, 3, 2): 4511 case IP_VERSION(10, 3, 1): 4512 case IP_VERSION(10, 3, 4): 4513 case IP_VERSION(10, 3, 5): 4514 case IP_VERSION(10, 3, 6): 4515 case IP_VERSION(10, 3, 3): 4516 case IP_VERSION(10, 3, 7): 4517 adev->gfx.me.num_me = 1; 4518 adev->gfx.me.num_pipe_per_me = 1; 4519 adev->gfx.me.num_queue_per_pipe = 1; 4520 adev->gfx.mec.num_mec = 2; 4521 adev->gfx.mec.num_pipe_per_mec = 4; 4522 adev->gfx.mec.num_queue_per_pipe = 4; 4523 break; 4524 default: 4525 adev->gfx.me.num_me = 1; 4526 adev->gfx.me.num_pipe_per_me = 1; 4527 adev->gfx.me.num_queue_per_pipe = 1; 4528 adev->gfx.mec.num_mec = 1; 4529 adev->gfx.mec.num_pipe_per_mec = 4; 4530 adev->gfx.mec.num_queue_per_pipe = 8; 4531 break; 4532 } 4533 4534 /* KIQ event */ 4535 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4536 GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT, 4537 &adev->gfx.kiq[0].irq); 4538 if (r) 4539 return r; 4540 4541 /* EOP Event */ 4542 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4543 GFX_10_1__SRCID__CP_EOP_INTERRUPT, 4544 &adev->gfx.eop_irq); 4545 if (r) 4546 return r; 4547 4548 /* Privileged reg */ 4549 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT, 4550 &adev->gfx.priv_reg_irq); 4551 if (r) 4552 return r; 4553 4554 /* Privileged inst */ 4555 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT, 4556 &adev->gfx.priv_inst_irq); 4557 if (r) 4558 return r; 4559 4560 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 4561 4562 gfx_v10_0_me_init(adev); 4563 4564 if (adev->gfx.rlc.funcs) { 4565 if (adev->gfx.rlc.funcs->init) { 4566 r = adev->gfx.rlc.funcs->init(adev); 4567 if (r) { 4568 dev_err(adev->dev, "Failed to init rlc BOs!\n"); 4569 return r; 4570 } 4571 } 4572 } 4573 4574 r = gfx_v10_0_mec_init(adev); 4575 if (r) { 4576 DRM_ERROR("Failed to init MEC BOs!\n"); 4577 return r; 4578 } 4579 4580 /* set up the gfx ring */ 4581 for (i = 0; i < adev->gfx.me.num_me; i++) { 4582 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 4583 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 4584 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 4585 continue; 4586 4587 r = gfx_v10_0_gfx_ring_init(adev, ring_id, 4588 i, k, j); 4589 if (r) 4590 return r; 4591 ring_id++; 4592 } 4593 } 4594 } 4595 4596 ring_id = 0; 4597 /* set up the compute queues - allocate horizontally across pipes */ 4598 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 4599 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 4600 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 4601 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i, 4602 k, j)) 4603 continue; 4604 4605 r = gfx_v10_0_compute_ring_init(adev, ring_id, 4606 i, k, j); 4607 if (r) 4608 return r; 4609 4610 ring_id++; 4611 } 4612 } 4613 } 4614 4615 if (!adev->enable_mes_kiq) { 4616 r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE, 0); 4617 if (r) { 4618 DRM_ERROR("Failed to init KIQ BOs!\n"); 4619 return r; 4620 } 4621 4622 kiq = &adev->gfx.kiq[0]; 4623 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq, 0); 4624 if (r) 4625 return r; 4626 } 4627 4628 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd), 0); 4629 if (r) 4630 return r; 4631 4632 /* allocate visible FB for rlc auto-loading fw */ 4633 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 4634 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev); 4635 if (r) 4636 return r; 4637 } 4638 4639 adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE; 4640 4641 gfx_v10_0_gpu_early_init(adev); 4642 4643 return 0; 4644 } 4645 4646 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev) 4647 { 4648 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 4649 &adev->gfx.pfp.pfp_fw_gpu_addr, 4650 (void **)&adev->gfx.pfp.pfp_fw_ptr); 4651 } 4652 4653 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev) 4654 { 4655 amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj, 4656 &adev->gfx.ce.ce_fw_gpu_addr, 4657 (void **)&adev->gfx.ce.ce_fw_ptr); 4658 } 4659 4660 static void gfx_v10_0_me_fini(struct amdgpu_device *adev) 4661 { 4662 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 4663 &adev->gfx.me.me_fw_gpu_addr, 4664 (void **)&adev->gfx.me.me_fw_ptr); 4665 } 4666 4667 static int gfx_v10_0_sw_fini(void *handle) 4668 { 4669 int i; 4670 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4671 4672 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 4673 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 4674 for (i = 0; i < adev->gfx.num_compute_rings; i++) 4675 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 4676 4677 amdgpu_gfx_mqd_sw_fini(adev, 0); 4678 4679 if (!adev->enable_mes_kiq) { 4680 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 4681 amdgpu_gfx_kiq_fini(adev, 0); 4682 } 4683 4684 gfx_v10_0_pfp_fini(adev); 4685 gfx_v10_0_ce_fini(adev); 4686 gfx_v10_0_me_fini(adev); 4687 gfx_v10_0_rlc_fini(adev); 4688 gfx_v10_0_mec_fini(adev); 4689 4690 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 4691 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev); 4692 4693 gfx_v10_0_free_microcode(adev); 4694 4695 return 0; 4696 } 4697 4698 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 4699 u32 sh_num, u32 instance, int xcc_id) 4700 { 4701 u32 data; 4702 4703 if (instance == 0xffffffff) 4704 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 4705 INSTANCE_BROADCAST_WRITES, 1); 4706 else 4707 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 4708 instance); 4709 4710 if (se_num == 0xffffffff) 4711 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 4712 1); 4713 else 4714 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 4715 4716 if (sh_num == 0xffffffff) 4717 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 4718 1); 4719 else 4720 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 4721 4722 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); 4723 } 4724 4725 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev) 4726 { 4727 u32 data, mask; 4728 4729 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); 4730 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); 4731 4732 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 4733 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 4734 4735 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 4736 adev->gfx.config.max_sh_per_se); 4737 4738 return (~data) & mask; 4739 } 4740 4741 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev) 4742 { 4743 int i, j; 4744 u32 data; 4745 u32 active_rbs = 0; 4746 u32 bitmap; 4747 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 4748 adev->gfx.config.max_sh_per_se; 4749 4750 mutex_lock(&adev->grbm_idx_mutex); 4751 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4752 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4753 bitmap = i * adev->gfx.config.max_sh_per_se + j; 4754 if (((amdgpu_ip_version(adev, GC_HWIP, 0) == 4755 IP_VERSION(10, 3, 0)) || 4756 (amdgpu_ip_version(adev, GC_HWIP, 0) == 4757 IP_VERSION(10, 3, 3)) || 4758 (amdgpu_ip_version(adev, GC_HWIP, 0) == 4759 IP_VERSION(10, 3, 6))) && 4760 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 4761 continue; 4762 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0); 4763 data = gfx_v10_0_get_rb_active_bitmap(adev); 4764 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 4765 rb_bitmap_width_per_sh); 4766 } 4767 } 4768 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 4769 mutex_unlock(&adev->grbm_idx_mutex); 4770 4771 adev->gfx.config.backend_enable_mask = active_rbs; 4772 adev->gfx.config.num_rbs = hweight32(active_rbs); 4773 } 4774 4775 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev) 4776 { 4777 uint32_t num_sc; 4778 uint32_t enabled_rb_per_sh; 4779 uint32_t active_rb_bitmap; 4780 uint32_t num_rb_per_sc; 4781 uint32_t num_packer_per_sc; 4782 uint32_t pa_sc_tile_steering_override; 4783 4784 /* for ASICs that integrates GFX v10.3 4785 * pa_sc_tile_steering_override should be set to 0 4786 */ 4787 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0)) 4788 return 0; 4789 4790 /* init num_sc */ 4791 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se * 4792 adev->gfx.config.num_sc_per_sh; 4793 /* init num_rb_per_sc */ 4794 active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev); 4795 enabled_rb_per_sh = hweight32(active_rb_bitmap); 4796 num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh; 4797 /* init num_packer_per_sc */ 4798 num_packer_per_sc = adev->gfx.config.num_packer_per_sc; 4799 4800 pa_sc_tile_steering_override = 0; 4801 pa_sc_tile_steering_override |= 4802 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) & 4803 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK; 4804 pa_sc_tile_steering_override |= 4805 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) & 4806 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK; 4807 pa_sc_tile_steering_override |= 4808 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) & 4809 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK; 4810 4811 return pa_sc_tile_steering_override; 4812 } 4813 4814 #define DEFAULT_SH_MEM_BASES (0x6000) 4815 4816 static void gfx_v10_0_debug_trap_config_init(struct amdgpu_device *adev, 4817 uint32_t first_vmid, 4818 uint32_t last_vmid) 4819 { 4820 uint32_t data; 4821 uint32_t trap_config_vmid_mask = 0; 4822 int i; 4823 4824 /* Calculate trap config vmid mask */ 4825 for (i = first_vmid; i < last_vmid; i++) 4826 trap_config_vmid_mask |= (1 << i); 4827 4828 data = REG_SET_FIELD(0, SPI_GDBG_TRAP_CONFIG, 4829 VMID_SEL, trap_config_vmid_mask); 4830 data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG, 4831 TRAP_EN, 1); 4832 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_CONFIG), data); 4833 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0); 4834 4835 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), 0); 4836 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), 0); 4837 } 4838 4839 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev) 4840 { 4841 int i; 4842 uint32_t sh_mem_bases; 4843 4844 /* 4845 * Configure apertures: 4846 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 4847 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 4848 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 4849 */ 4850 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 4851 4852 mutex_lock(&adev->srbm_mutex); 4853 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 4854 nv_grbm_select(adev, 0, 0, 0, i); 4855 /* CP and shaders */ 4856 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 4857 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); 4858 } 4859 nv_grbm_select(adev, 0, 0, 0, 0); 4860 mutex_unlock(&adev->srbm_mutex); 4861 4862 /* 4863 * Initialize all compute VMIDs to have no GDS, GWS, or OA 4864 * access. These should be enabled by FW for target VMIDs. 4865 */ 4866 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 4867 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); 4868 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); 4869 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0); 4870 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0); 4871 } 4872 4873 gfx_v10_0_debug_trap_config_init(adev, adev->vm_manager.first_kfd_vmid, 4874 AMDGPU_NUM_VMID); 4875 } 4876 4877 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev) 4878 { 4879 int vmid; 4880 4881 /* 4882 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 4883 * access. Compute VMIDs should be enabled by FW for target VMIDs, 4884 * the driver can enable them for graphics. VMID0 should maintain 4885 * access so that HWS firmware can save/restore entries. 4886 */ 4887 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 4888 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0); 4889 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0); 4890 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0); 4891 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0); 4892 } 4893 } 4894 4895 4896 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev) 4897 { 4898 int i, j, k; 4899 int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1; 4900 u32 tmp, wgp_active_bitmap = 0; 4901 u32 gcrd_targets_disable_tcp = 0; 4902 u32 utcl_invreq_disable = 0; 4903 /* 4904 * GCRD_TARGETS_DISABLE field contains 4905 * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0] 4906 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0] 4907 */ 4908 u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask( 4909 2 * max_wgp_per_sh + /* TCP */ 4910 max_wgp_per_sh + /* SQC */ 4911 4); /* GL1C */ 4912 /* 4913 * UTCL1_UTCL0_INVREQ_DISABLE field contains 4914 * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0] 4915 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0] 4916 */ 4917 u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask( 4918 2 * max_wgp_per_sh + /* TCP */ 4919 2 * max_wgp_per_sh + /* SQC */ 4920 4 + /* RMI */ 4921 1); /* SQG */ 4922 4923 mutex_lock(&adev->grbm_idx_mutex); 4924 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4925 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4926 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0); 4927 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 4928 /* 4929 * Set corresponding TCP bits for the inactive WGPs in 4930 * GCRD_SA_TARGETS_DISABLE 4931 */ 4932 gcrd_targets_disable_tcp = 0; 4933 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */ 4934 utcl_invreq_disable = 0; 4935 4936 for (k = 0; k < max_wgp_per_sh; k++) { 4937 if (!(wgp_active_bitmap & (1 << k))) { 4938 gcrd_targets_disable_tcp |= 3 << (2 * k); 4939 gcrd_targets_disable_tcp |= 1 << (k + (max_wgp_per_sh * 2)); 4940 utcl_invreq_disable |= (3 << (2 * k)) | 4941 (3 << (2 * (max_wgp_per_sh + k))); 4942 } 4943 } 4944 4945 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE); 4946 /* only override TCP & SQC bits */ 4947 tmp &= (0xffffffffU << (4 * max_wgp_per_sh)); 4948 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask); 4949 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp); 4950 4951 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE); 4952 /* only override TCP & SQC bits */ 4953 tmp &= (0xffffffffU << (3 * max_wgp_per_sh)); 4954 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask); 4955 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp); 4956 } 4957 } 4958 4959 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 4960 mutex_unlock(&adev->grbm_idx_mutex); 4961 } 4962 4963 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev) 4964 { 4965 /* TCCs are global (not instanced). */ 4966 uint32_t tcc_disable; 4967 4968 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0)) { 4969 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) | 4970 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3); 4971 } else { 4972 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) | 4973 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE); 4974 } 4975 4976 adev->gfx.config.tcc_disabled_mask = 4977 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | 4978 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); 4979 } 4980 4981 static void gfx_v10_0_constants_init(struct amdgpu_device *adev) 4982 { 4983 u32 tmp; 4984 int i; 4985 4986 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 4987 4988 gfx_v10_0_setup_rb(adev); 4989 gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info); 4990 gfx_v10_0_get_tcc_info(adev); 4991 adev->gfx.config.pa_sc_tile_steering_override = 4992 gfx_v10_0_init_pa_sc_tile_steering_override(adev); 4993 4994 /* XXX SH_MEM regs */ 4995 /* where to put LDS, scratch, GPUVM in FSA64 space */ 4996 mutex_lock(&adev->srbm_mutex); 4997 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 4998 nv_grbm_select(adev, 0, 0, 0, i); 4999 /* CP and shaders */ 5000 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 5001 if (i != 0) { 5002 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 5003 (adev->gmc.private_aperture_start >> 48)); 5004 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 5005 (adev->gmc.shared_aperture_start >> 48)); 5006 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp); 5007 } 5008 } 5009 nv_grbm_select(adev, 0, 0, 0, 0); 5010 5011 mutex_unlock(&adev->srbm_mutex); 5012 5013 gfx_v10_0_init_compute_vmid(adev); 5014 gfx_v10_0_init_gds_vmid(adev); 5015 5016 } 5017 5018 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 5019 bool enable) 5020 { 5021 u32 tmp; 5022 5023 if (amdgpu_sriov_vf(adev)) 5024 return; 5025 5026 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); 5027 5028 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 5029 enable ? 1 : 0); 5030 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 5031 enable ? 1 : 0); 5032 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 5033 enable ? 1 : 0); 5034 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 5035 enable ? 1 : 0); 5036 5037 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); 5038 } 5039 5040 static int gfx_v10_0_init_csb(struct amdgpu_device *adev) 5041 { 5042 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 5043 5044 /* csib */ 5045 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) { 5046 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI, 5047 adev->gfx.rlc.clear_state_gpu_addr >> 32); 5048 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO, 5049 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 5050 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 5051 } else { 5052 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, 5053 adev->gfx.rlc.clear_state_gpu_addr >> 32); 5054 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, 5055 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 5056 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 5057 } 5058 return 0; 5059 } 5060 5061 static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) 5062 { 5063 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5064 5065 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 5066 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp); 5067 } 5068 5069 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev) 5070 { 5071 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 5072 udelay(50); 5073 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 5074 udelay(50); 5075 } 5076 5077 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 5078 bool enable) 5079 { 5080 uint32_t rlc_pg_cntl; 5081 5082 rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 5083 5084 if (!enable) { 5085 /* RLC_PG_CNTL[23] = 0 (default) 5086 * RLC will wait for handshake acks with SMU 5087 * GFXOFF will be enabled 5088 * RLC_PG_CNTL[23] = 1 5089 * RLC will not issue any message to SMU 5090 * hence no handshake between SMU & RLC 5091 * GFXOFF will be disabled 5092 */ 5093 rlc_pg_cntl |= 0x800000; 5094 } else 5095 rlc_pg_cntl &= ~0x800000; 5096 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl); 5097 } 5098 5099 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev) 5100 { 5101 /* 5102 * TODO: enable rlc & smu handshake until smu 5103 * and gfxoff feature works as expected 5104 */ 5105 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 5106 gfx_v10_0_rlc_smu_handshake_cntl(adev, false); 5107 5108 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 5109 udelay(50); 5110 } 5111 5112 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev) 5113 { 5114 uint32_t tmp; 5115 5116 /* enable Save Restore Machine */ 5117 tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL); 5118 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 5119 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 5120 WREG32_SOC15(GC, 0, mmRLC_SRM_CNTL, tmp); 5121 } 5122 5123 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev) 5124 { 5125 const struct rlc_firmware_header_v2_0 *hdr; 5126 const __le32 *fw_data; 5127 unsigned int i, fw_size; 5128 5129 if (!adev->gfx.rlc_fw) 5130 return -EINVAL; 5131 5132 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 5133 amdgpu_ucode_print_rlc_hdr(&hdr->header); 5134 5135 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5136 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 5137 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 5138 5139 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, 5140 RLCG_UCODE_LOADING_START_ADDRESS); 5141 5142 for (i = 0; i < fw_size; i++) 5143 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, 5144 le32_to_cpup(fw_data++)); 5145 5146 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 5147 5148 return 0; 5149 } 5150 5151 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) 5152 { 5153 int r; 5154 5155 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 5156 adev->psp.autoload_supported) { 5157 5158 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5159 if (r) 5160 return r; 5161 5162 gfx_v10_0_init_csb(adev); 5163 5164 gfx_v10_0_update_spm_vmid_internal(adev, 0xf); 5165 5166 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 5167 gfx_v10_0_rlc_enable_srm(adev); 5168 } else { 5169 if (amdgpu_sriov_vf(adev)) { 5170 gfx_v10_0_init_csb(adev); 5171 return 0; 5172 } 5173 5174 adev->gfx.rlc.funcs->stop(adev); 5175 5176 /* disable CG */ 5177 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); 5178 5179 /* disable PG */ 5180 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0); 5181 5182 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 5183 /* legacy rlc firmware loading */ 5184 r = gfx_v10_0_rlc_load_microcode(adev); 5185 if (r) 5186 return r; 5187 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5188 /* rlc backdoor autoload firmware */ 5189 r = gfx_v10_0_rlc_backdoor_autoload_enable(adev); 5190 if (r) 5191 return r; 5192 } 5193 5194 gfx_v10_0_init_csb(adev); 5195 5196 gfx_v10_0_update_spm_vmid_internal(adev, 0xf); 5197 5198 adev->gfx.rlc.funcs->start(adev); 5199 5200 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5201 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5202 if (r) 5203 return r; 5204 } 5205 } 5206 5207 return 0; 5208 } 5209 5210 static struct { 5211 FIRMWARE_ID id; 5212 unsigned int offset; 5213 unsigned int size; 5214 } rlc_autoload_info[FIRMWARE_ID_MAX]; 5215 5216 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev) 5217 { 5218 int ret; 5219 RLC_TABLE_OF_CONTENT *rlc_toc; 5220 5221 ret = amdgpu_bo_create_reserved(adev, adev->psp.toc.size_bytes, PAGE_SIZE, 5222 AMDGPU_GEM_DOMAIN_GTT, 5223 &adev->gfx.rlc.rlc_toc_bo, 5224 &adev->gfx.rlc.rlc_toc_gpu_addr, 5225 (void **)&adev->gfx.rlc.rlc_toc_buf); 5226 if (ret) { 5227 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret); 5228 return ret; 5229 } 5230 5231 /* Copy toc from psp sos fw to rlc toc buffer */ 5232 memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc.start_addr, adev->psp.toc.size_bytes); 5233 5234 rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf; 5235 while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) && 5236 (rlc_toc->id < FIRMWARE_ID_MAX)) { 5237 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) && 5238 (rlc_toc->id <= FIRMWARE_ID_CP_MES)) { 5239 /* Offset needs 4KB alignment */ 5240 rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE); 5241 } 5242 5243 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id; 5244 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4; 5245 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4; 5246 5247 rlc_toc++; 5248 } 5249 5250 return 0; 5251 } 5252 5253 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev) 5254 { 5255 uint32_t total_size = 0; 5256 FIRMWARE_ID id; 5257 int ret; 5258 5259 ret = gfx_v10_0_parse_rlc_toc(adev); 5260 if (ret) { 5261 dev_err(adev->dev, "failed to parse rlc toc\n"); 5262 return 0; 5263 } 5264 5265 for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++) 5266 total_size += rlc_autoload_info[id].size; 5267 5268 /* In case the offset in rlc toc ucode is aligned */ 5269 if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset) 5270 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset + 5271 rlc_autoload_info[FIRMWARE_ID_MAX-1].size; 5272 5273 return total_size; 5274 } 5275 5276 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev) 5277 { 5278 int r; 5279 uint32_t total_size; 5280 5281 total_size = gfx_v10_0_calc_toc_total_size(adev); 5282 5283 r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE, 5284 AMDGPU_GEM_DOMAIN_GTT, 5285 &adev->gfx.rlc.rlc_autoload_bo, 5286 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5287 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5288 if (r) { 5289 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 5290 return r; 5291 } 5292 5293 return 0; 5294 } 5295 5296 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev) 5297 { 5298 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo, 5299 &adev->gfx.rlc.rlc_toc_gpu_addr, 5300 (void **)&adev->gfx.rlc.rlc_toc_buf); 5301 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 5302 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5303 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5304 } 5305 5306 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 5307 FIRMWARE_ID id, 5308 const void *fw_data, 5309 uint32_t fw_size) 5310 { 5311 uint32_t toc_offset; 5312 uint32_t toc_fw_size; 5313 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 5314 5315 if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX) 5316 return; 5317 5318 toc_offset = rlc_autoload_info[id].offset; 5319 toc_fw_size = rlc_autoload_info[id].size; 5320 5321 if (fw_size == 0) 5322 fw_size = toc_fw_size; 5323 5324 if (fw_size > toc_fw_size) 5325 fw_size = toc_fw_size; 5326 5327 memcpy(ptr + toc_offset, fw_data, fw_size); 5328 5329 if (fw_size < toc_fw_size) 5330 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 5331 } 5332 5333 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 5334 { 5335 void *data; 5336 uint32_t size; 5337 5338 data = adev->gfx.rlc.rlc_toc_buf; 5339 size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size; 5340 5341 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5342 FIRMWARE_ID_RLC_TOC, 5343 data, size); 5344 } 5345 5346 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 5347 { 5348 const __le32 *fw_data; 5349 uint32_t fw_size; 5350 const struct gfx_firmware_header_v1_0 *cp_hdr; 5351 const struct rlc_firmware_header_v2_0 *rlc_hdr; 5352 5353 /* pfp ucode */ 5354 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5355 adev->gfx.pfp_fw->data; 5356 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 5357 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5358 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5359 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5360 FIRMWARE_ID_CP_PFP, 5361 fw_data, fw_size); 5362 5363 /* ce ucode */ 5364 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5365 adev->gfx.ce_fw->data; 5366 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 5367 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5368 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5369 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5370 FIRMWARE_ID_CP_CE, 5371 fw_data, fw_size); 5372 5373 /* me ucode */ 5374 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5375 adev->gfx.me_fw->data; 5376 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 5377 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5378 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5379 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5380 FIRMWARE_ID_CP_ME, 5381 fw_data, fw_size); 5382 5383 /* rlc ucode */ 5384 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 5385 adev->gfx.rlc_fw->data; 5386 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5387 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 5388 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 5389 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5390 FIRMWARE_ID_RLC_G_UCODE, 5391 fw_data, fw_size); 5392 5393 /* mec1 ucode */ 5394 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5395 adev->gfx.mec_fw->data; 5396 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 5397 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5398 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 5399 cp_hdr->jt_size * 4; 5400 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5401 FIRMWARE_ID_CP_MEC, 5402 fw_data, fw_size); 5403 /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */ 5404 } 5405 5406 /* Temporarily put sdma part here */ 5407 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 5408 { 5409 const __le32 *fw_data; 5410 uint32_t fw_size; 5411 const struct sdma_firmware_header_v1_0 *sdma_hdr; 5412 int i; 5413 5414 for (i = 0; i < adev->sdma.num_instances; i++) { 5415 sdma_hdr = (const struct sdma_firmware_header_v1_0 *) 5416 adev->sdma.instance[i].fw->data; 5417 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data + 5418 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); 5419 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes); 5420 5421 if (i == 0) { 5422 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5423 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size); 5424 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5425 FIRMWARE_ID_SDMA0_JT, 5426 (uint32_t *)fw_data + 5427 sdma_hdr->jt_offset, 5428 sdma_hdr->jt_size * 4); 5429 } else if (i == 1) { 5430 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5431 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size); 5432 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5433 FIRMWARE_ID_SDMA1_JT, 5434 (uint32_t *)fw_data + 5435 sdma_hdr->jt_offset, 5436 sdma_hdr->jt_size * 4); 5437 } 5438 } 5439 } 5440 5441 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 5442 { 5443 uint32_t rlc_g_offset, rlc_g_size, tmp; 5444 uint64_t gpu_addr; 5445 5446 gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev); 5447 gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev); 5448 gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev); 5449 5450 rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset; 5451 rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size; 5452 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; 5453 5454 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr)); 5455 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr)); 5456 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size); 5457 5458 tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR); 5459 if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK | 5460 RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) { 5461 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n"); 5462 return -EINVAL; 5463 } 5464 5465 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5466 if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) { 5467 DRM_ERROR("RLC ROM should halt itself\n"); 5468 return -EINVAL; 5469 } 5470 5471 return 0; 5472 } 5473 5474 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev) 5475 { 5476 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5477 uint32_t tmp; 5478 int i; 5479 uint64_t addr; 5480 5481 /* Trigger an invalidation of the L1 instruction caches */ 5482 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5483 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5484 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 5485 5486 /* Wait for invalidation complete */ 5487 for (i = 0; i < usec_timeout; i++) { 5488 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5489 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 5490 INVALIDATE_CACHE_COMPLETE)) 5491 break; 5492 udelay(1); 5493 } 5494 5495 if (i >= usec_timeout) { 5496 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5497 return -EINVAL; 5498 } 5499 5500 /* Program me ucode address into intruction cache address register */ 5501 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5502 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset; 5503 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 5504 lower_32_bits(addr) & 0xFFFFF000); 5505 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 5506 upper_32_bits(addr)); 5507 5508 return 0; 5509 } 5510 5511 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev) 5512 { 5513 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5514 uint32_t tmp; 5515 int i; 5516 uint64_t addr; 5517 5518 /* Trigger an invalidation of the L1 instruction caches */ 5519 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5520 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5521 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 5522 5523 /* Wait for invalidation complete */ 5524 for (i = 0; i < usec_timeout; i++) { 5525 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5526 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 5527 INVALIDATE_CACHE_COMPLETE)) 5528 break; 5529 udelay(1); 5530 } 5531 5532 if (i >= usec_timeout) { 5533 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5534 return -EINVAL; 5535 } 5536 5537 /* Program ce ucode address into intruction cache address register */ 5538 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5539 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset; 5540 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 5541 lower_32_bits(addr) & 0xFFFFF000); 5542 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 5543 upper_32_bits(addr)); 5544 5545 return 0; 5546 } 5547 5548 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev) 5549 { 5550 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5551 uint32_t tmp; 5552 int i; 5553 uint64_t addr; 5554 5555 /* Trigger an invalidation of the L1 instruction caches */ 5556 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5557 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5558 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 5559 5560 /* Wait for invalidation complete */ 5561 for (i = 0; i < usec_timeout; i++) { 5562 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5563 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 5564 INVALIDATE_CACHE_COMPLETE)) 5565 break; 5566 udelay(1); 5567 } 5568 5569 if (i >= usec_timeout) { 5570 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5571 return -EINVAL; 5572 } 5573 5574 /* Program pfp ucode address into intruction cache address register */ 5575 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5576 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset; 5577 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 5578 lower_32_bits(addr) & 0xFFFFF000); 5579 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 5580 upper_32_bits(addr)); 5581 5582 return 0; 5583 } 5584 5585 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev) 5586 { 5587 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5588 uint32_t tmp; 5589 int i; 5590 uint64_t addr; 5591 5592 /* Trigger an invalidation of the L1 instruction caches */ 5593 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 5594 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5595 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 5596 5597 /* Wait for invalidation complete */ 5598 for (i = 0; i < usec_timeout; i++) { 5599 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 5600 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 5601 INVALIDATE_CACHE_COMPLETE)) 5602 break; 5603 udelay(1); 5604 } 5605 5606 if (i >= usec_timeout) { 5607 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5608 return -EINVAL; 5609 } 5610 5611 /* Program mec1 ucode address into intruction cache address register */ 5612 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5613 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset; 5614 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, 5615 lower_32_bits(addr) & 0xFFFFF000); 5616 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 5617 upper_32_bits(addr)); 5618 5619 return 0; 5620 } 5621 5622 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 5623 { 5624 uint32_t cp_status; 5625 uint32_t bootload_status; 5626 int i, r; 5627 5628 for (i = 0; i < adev->usec_timeout; i++) { 5629 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT); 5630 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS); 5631 if ((cp_status == 0) && 5632 (REG_GET_FIELD(bootload_status, 5633 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 5634 break; 5635 } 5636 udelay(1); 5637 } 5638 5639 if (i >= adev->usec_timeout) { 5640 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 5641 return -ETIMEDOUT; 5642 } 5643 5644 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5645 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev); 5646 if (r) 5647 return r; 5648 5649 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev); 5650 if (r) 5651 return r; 5652 5653 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev); 5654 if (r) 5655 return r; 5656 5657 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev); 5658 if (r) 5659 return r; 5660 } 5661 5662 return 0; 5663 } 5664 5665 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 5666 { 5667 int i; 5668 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); 5669 5670 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 5671 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 5672 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); 5673 5674 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) 5675 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); 5676 else 5677 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp); 5678 5679 if (adev->job_hang && !enable) 5680 return 0; 5681 5682 for (i = 0; i < adev->usec_timeout; i++) { 5683 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0) 5684 break; 5685 udelay(1); 5686 } 5687 5688 if (i >= adev->usec_timeout) 5689 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 5690 5691 return 0; 5692 } 5693 5694 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 5695 { 5696 int r; 5697 const struct gfx_firmware_header_v1_0 *pfp_hdr; 5698 const __le32 *fw_data; 5699 unsigned int i, fw_size; 5700 uint32_t tmp; 5701 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5702 5703 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 5704 adev->gfx.pfp_fw->data; 5705 5706 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 5707 5708 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 5709 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 5710 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); 5711 5712 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes, 5713 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5714 &adev->gfx.pfp.pfp_fw_obj, 5715 &adev->gfx.pfp.pfp_fw_gpu_addr, 5716 (void **)&adev->gfx.pfp.pfp_fw_ptr); 5717 if (r) { 5718 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r); 5719 gfx_v10_0_pfp_fini(adev); 5720 return r; 5721 } 5722 5723 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); 5724 5725 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 5726 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 5727 5728 /* Trigger an invalidation of the L1 instruction caches */ 5729 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5730 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5731 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 5732 5733 /* Wait for invalidation complete */ 5734 for (i = 0; i < usec_timeout; i++) { 5735 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5736 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 5737 INVALIDATE_CACHE_COMPLETE)) 5738 break; 5739 udelay(1); 5740 } 5741 5742 if (i >= usec_timeout) { 5743 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5744 return -EINVAL; 5745 } 5746 5747 if (amdgpu_emu_mode == 1) 5748 adev->hdp.funcs->flush_hdp(adev, NULL); 5749 5750 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL); 5751 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 5752 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 5753 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 5754 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 5755 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp); 5756 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 5757 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000); 5758 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 5759 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 5760 5761 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0); 5762 5763 for (i = 0; i < pfp_hdr->jt_size; i++) 5764 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA, 5765 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i)); 5766 5767 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 5768 5769 return 0; 5770 } 5771 5772 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev) 5773 { 5774 int r; 5775 const struct gfx_firmware_header_v1_0 *ce_hdr; 5776 const __le32 *fw_data; 5777 unsigned int i, fw_size; 5778 uint32_t tmp; 5779 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5780 5781 ce_hdr = (const struct gfx_firmware_header_v1_0 *) 5782 adev->gfx.ce_fw->data; 5783 5784 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 5785 5786 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 5787 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 5788 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes); 5789 5790 r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes, 5791 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5792 &adev->gfx.ce.ce_fw_obj, 5793 &adev->gfx.ce.ce_fw_gpu_addr, 5794 (void **)&adev->gfx.ce.ce_fw_ptr); 5795 if (r) { 5796 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r); 5797 gfx_v10_0_ce_fini(adev); 5798 return r; 5799 } 5800 5801 memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size); 5802 5803 amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj); 5804 amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj); 5805 5806 /* Trigger an invalidation of the L1 instruction caches */ 5807 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5808 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5809 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 5810 5811 /* Wait for invalidation complete */ 5812 for (i = 0; i < usec_timeout; i++) { 5813 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5814 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 5815 INVALIDATE_CACHE_COMPLETE)) 5816 break; 5817 udelay(1); 5818 } 5819 5820 if (i >= usec_timeout) { 5821 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5822 return -EINVAL; 5823 } 5824 5825 if (amdgpu_emu_mode == 1) 5826 adev->hdp.funcs->flush_hdp(adev, NULL); 5827 5828 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL); 5829 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0); 5830 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0); 5831 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0); 5832 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 5833 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 5834 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000); 5835 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 5836 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr)); 5837 5838 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0); 5839 5840 for (i = 0; i < ce_hdr->jt_size; i++) 5841 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA, 5842 le32_to_cpup(fw_data + ce_hdr->jt_offset + i)); 5843 5844 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); 5845 5846 return 0; 5847 } 5848 5849 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 5850 { 5851 int r; 5852 const struct gfx_firmware_header_v1_0 *me_hdr; 5853 const __le32 *fw_data; 5854 unsigned int i, fw_size; 5855 uint32_t tmp; 5856 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5857 5858 me_hdr = (const struct gfx_firmware_header_v1_0 *) 5859 adev->gfx.me_fw->data; 5860 5861 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 5862 5863 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 5864 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 5865 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); 5866 5867 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, 5868 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5869 &adev->gfx.me.me_fw_obj, 5870 &adev->gfx.me.me_fw_gpu_addr, 5871 (void **)&adev->gfx.me.me_fw_ptr); 5872 if (r) { 5873 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r); 5874 gfx_v10_0_me_fini(adev); 5875 return r; 5876 } 5877 5878 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); 5879 5880 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 5881 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 5882 5883 /* Trigger an invalidation of the L1 instruction caches */ 5884 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5885 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5886 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 5887 5888 /* Wait for invalidation complete */ 5889 for (i = 0; i < usec_timeout; i++) { 5890 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5891 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 5892 INVALIDATE_CACHE_COMPLETE)) 5893 break; 5894 udelay(1); 5895 } 5896 5897 if (i >= usec_timeout) { 5898 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5899 return -EINVAL; 5900 } 5901 5902 if (amdgpu_emu_mode == 1) 5903 adev->hdp.funcs->flush_hdp(adev, NULL); 5904 5905 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL); 5906 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 5907 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 5908 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 5909 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 5910 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 5911 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000); 5912 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 5913 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 5914 5915 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0); 5916 5917 for (i = 0; i < me_hdr->jt_size; i++) 5918 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA, 5919 le32_to_cpup(fw_data + me_hdr->jt_offset + i)); 5920 5921 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); 5922 5923 return 0; 5924 } 5925 5926 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 5927 { 5928 int r; 5929 5930 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 5931 return -EINVAL; 5932 5933 gfx_v10_0_cp_gfx_enable(adev, false); 5934 5935 r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev); 5936 if (r) { 5937 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 5938 return r; 5939 } 5940 5941 r = gfx_v10_0_cp_gfx_load_ce_microcode(adev); 5942 if (r) { 5943 dev_err(adev->dev, "(%d) failed to load ce fw\n", r); 5944 return r; 5945 } 5946 5947 r = gfx_v10_0_cp_gfx_load_me_microcode(adev); 5948 if (r) { 5949 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 5950 return r; 5951 } 5952 5953 return 0; 5954 } 5955 5956 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev) 5957 { 5958 struct amdgpu_ring *ring; 5959 const struct cs_section_def *sect = NULL; 5960 const struct cs_extent_def *ext = NULL; 5961 int r, i; 5962 int ctx_reg_offset; 5963 5964 /* init the CP */ 5965 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, 5966 adev->gfx.config.max_hw_contexts - 1); 5967 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); 5968 5969 gfx_v10_0_cp_gfx_enable(adev, true); 5970 5971 ring = &adev->gfx.gfx_ring[0]; 5972 r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4); 5973 if (r) { 5974 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 5975 return r; 5976 } 5977 5978 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 5979 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 5980 5981 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 5982 amdgpu_ring_write(ring, 0x80000000); 5983 amdgpu_ring_write(ring, 0x80000000); 5984 5985 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 5986 for (ext = sect->section; ext->extent != NULL; ++ext) { 5987 if (sect->id == SECT_CONTEXT) { 5988 amdgpu_ring_write(ring, 5989 PACKET3(PACKET3_SET_CONTEXT_REG, 5990 ext->reg_count)); 5991 amdgpu_ring_write(ring, ext->reg_index - 5992 PACKET3_SET_CONTEXT_REG_START); 5993 for (i = 0; i < ext->reg_count; i++) 5994 amdgpu_ring_write(ring, ext->extent[i]); 5995 } 5996 } 5997 } 5998 5999 ctx_reg_offset = 6000 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 6001 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 6002 amdgpu_ring_write(ring, ctx_reg_offset); 6003 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); 6004 6005 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 6006 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 6007 6008 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 6009 amdgpu_ring_write(ring, 0); 6010 6011 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 6012 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 6013 amdgpu_ring_write(ring, 0x8000); 6014 amdgpu_ring_write(ring, 0x8000); 6015 6016 amdgpu_ring_commit(ring); 6017 6018 /* submit cs packet to copy state 0 to next available state */ 6019 if (adev->gfx.num_gfx_rings > 1) { 6020 /* maximum supported gfx ring is 2 */ 6021 ring = &adev->gfx.gfx_ring[1]; 6022 r = amdgpu_ring_alloc(ring, 2); 6023 if (r) { 6024 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 6025 return r; 6026 } 6027 6028 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 6029 amdgpu_ring_write(ring, 0); 6030 6031 amdgpu_ring_commit(ring); 6032 } 6033 return 0; 6034 } 6035 6036 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 6037 CP_PIPE_ID pipe) 6038 { 6039 u32 tmp; 6040 6041 tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL); 6042 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 6043 6044 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp); 6045 } 6046 6047 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 6048 struct amdgpu_ring *ring) 6049 { 6050 u32 tmp; 6051 6052 if (!amdgpu_async_gfx_ring) { 6053 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 6054 if (ring->use_doorbell) { 6055 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6056 DOORBELL_OFFSET, ring->doorbell_index); 6057 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6058 DOORBELL_EN, 1); 6059 } else { 6060 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6061 DOORBELL_EN, 0); 6062 } 6063 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); 6064 } 6065 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 6066 case IP_VERSION(10, 3, 0): 6067 case IP_VERSION(10, 3, 2): 6068 case IP_VERSION(10, 3, 1): 6069 case IP_VERSION(10, 3, 4): 6070 case IP_VERSION(10, 3, 5): 6071 case IP_VERSION(10, 3, 6): 6072 case IP_VERSION(10, 3, 3): 6073 case IP_VERSION(10, 3, 7): 6074 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6075 DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index); 6076 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6077 6078 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6079 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK); 6080 break; 6081 default: 6082 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6083 DOORBELL_RANGE_LOWER, ring->doorbell_index); 6084 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6085 6086 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6087 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 6088 break; 6089 } 6090 } 6091 6092 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev) 6093 { 6094 struct amdgpu_ring *ring; 6095 u32 tmp; 6096 u32 rb_bufsz; 6097 u64 rb_addr, rptr_addr, wptr_gpu_addr; 6098 6099 /* Set the write pointer delay */ 6100 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); 6101 6102 /* set the RB to use vmid 0 */ 6103 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); 6104 6105 /* Init gfx ring 0 for pipe 0 */ 6106 mutex_lock(&adev->srbm_mutex); 6107 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6108 6109 /* Set ring buffer size */ 6110 ring = &adev->gfx.gfx_ring[0]; 6111 rb_bufsz = order_base_2(ring->ring_size / 8); 6112 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 6113 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 6114 #ifdef __BIG_ENDIAN 6115 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 6116 #endif 6117 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6118 6119 /* Initialize the ring buffer's write pointers */ 6120 ring->wptr = 0; 6121 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 6122 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 6123 6124 /* set the wb address wether it's enabled or not */ 6125 rptr_addr = ring->rptr_gpu_addr; 6126 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 6127 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6128 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6129 6130 wptr_gpu_addr = ring->wptr_gpu_addr; 6131 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6132 lower_32_bits(wptr_gpu_addr)); 6133 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6134 upper_32_bits(wptr_gpu_addr)); 6135 6136 mdelay(1); 6137 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6138 6139 rb_addr = ring->gpu_addr >> 8; 6140 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); 6141 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 6142 6143 WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1); 6144 6145 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6146 mutex_unlock(&adev->srbm_mutex); 6147 6148 /* Init gfx ring 1 for pipe 1 */ 6149 if (adev->gfx.num_gfx_rings > 1) { 6150 mutex_lock(&adev->srbm_mutex); 6151 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1); 6152 /* maximum supported gfx ring is 2 */ 6153 ring = &adev->gfx.gfx_ring[1]; 6154 rb_bufsz = order_base_2(ring->ring_size / 8); 6155 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 6156 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 6157 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6158 /* Initialize the ring buffer's write pointers */ 6159 ring->wptr = 0; 6160 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); 6161 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 6162 /* Set the wb address wether it's enabled or not */ 6163 rptr_addr = ring->rptr_gpu_addr; 6164 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 6165 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6166 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6167 wptr_gpu_addr = ring->wptr_gpu_addr; 6168 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6169 lower_32_bits(wptr_gpu_addr)); 6170 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6171 upper_32_bits(wptr_gpu_addr)); 6172 6173 mdelay(1); 6174 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6175 6176 rb_addr = ring->gpu_addr >> 8; 6177 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr); 6178 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr)); 6179 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1); 6180 6181 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6182 mutex_unlock(&adev->srbm_mutex); 6183 } 6184 /* Switch to pipe 0 */ 6185 mutex_lock(&adev->srbm_mutex); 6186 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6187 mutex_unlock(&adev->srbm_mutex); 6188 6189 /* start the ring */ 6190 gfx_v10_0_cp_gfx_start(adev); 6191 6192 return 0; 6193 } 6194 6195 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 6196 { 6197 if (enable) { 6198 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 6199 case IP_VERSION(10, 3, 0): 6200 case IP_VERSION(10, 3, 2): 6201 case IP_VERSION(10, 3, 1): 6202 case IP_VERSION(10, 3, 4): 6203 case IP_VERSION(10, 3, 5): 6204 case IP_VERSION(10, 3, 6): 6205 case IP_VERSION(10, 3, 3): 6206 case IP_VERSION(10, 3, 7): 6207 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0); 6208 break; 6209 default: 6210 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0); 6211 break; 6212 } 6213 } else { 6214 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 6215 case IP_VERSION(10, 3, 0): 6216 case IP_VERSION(10, 3, 2): 6217 case IP_VERSION(10, 3, 1): 6218 case IP_VERSION(10, 3, 4): 6219 case IP_VERSION(10, 3, 5): 6220 case IP_VERSION(10, 3, 6): 6221 case IP_VERSION(10, 3, 3): 6222 case IP_VERSION(10, 3, 7): 6223 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 6224 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6225 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6226 break; 6227 default: 6228 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 6229 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6230 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6231 break; 6232 } 6233 adev->gfx.kiq[0].ring.sched.ready = false; 6234 } 6235 udelay(50); 6236 } 6237 6238 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev) 6239 { 6240 const struct gfx_firmware_header_v1_0 *mec_hdr; 6241 const __le32 *fw_data; 6242 unsigned int i; 6243 u32 tmp; 6244 u32 usec_timeout = 50000; /* Wait for 50 ms */ 6245 6246 if (!adev->gfx.mec_fw) 6247 return -EINVAL; 6248 6249 gfx_v10_0_cp_compute_enable(adev, false); 6250 6251 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 6252 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 6253 6254 fw_data = (const __le32 *) 6255 (adev->gfx.mec_fw->data + 6256 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 6257 6258 /* Trigger an invalidation of the L1 instruction caches */ 6259 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6260 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6261 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 6262 6263 /* Wait for invalidation complete */ 6264 for (i = 0; i < usec_timeout; i++) { 6265 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6266 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 6267 INVALIDATE_CACHE_COMPLETE)) 6268 break; 6269 udelay(1); 6270 } 6271 6272 if (i >= usec_timeout) { 6273 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6274 return -EINVAL; 6275 } 6276 6277 if (amdgpu_emu_mode == 1) 6278 adev->hdp.funcs->flush_hdp(adev, NULL); 6279 6280 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL); 6281 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 6282 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 6283 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6284 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); 6285 6286 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr & 6287 0xFFFFF000); 6288 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 6289 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 6290 6291 /* MEC1 */ 6292 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0); 6293 6294 for (i = 0; i < mec_hdr->jt_size; i++) 6295 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, 6296 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 6297 6298 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 6299 6300 /* 6301 * TODO: Loading MEC2 firmware is only necessary if MEC2 should run 6302 * different microcode than MEC1. 6303 */ 6304 6305 return 0; 6306 } 6307 6308 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring) 6309 { 6310 uint32_t tmp; 6311 struct amdgpu_device *adev = ring->adev; 6312 6313 /* tell RLC which is KIQ queue */ 6314 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 6315 case IP_VERSION(10, 3, 0): 6316 case IP_VERSION(10, 3, 2): 6317 case IP_VERSION(10, 3, 1): 6318 case IP_VERSION(10, 3, 4): 6319 case IP_VERSION(10, 3, 5): 6320 case IP_VERSION(10, 3, 6): 6321 case IP_VERSION(10, 3, 3): 6322 case IP_VERSION(10, 3, 7): 6323 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid); 6324 tmp &= 0xffffff00; 6325 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6326 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); 6327 tmp |= 0x80; 6328 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); 6329 break; 6330 default: 6331 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 6332 tmp &= 0xffffff00; 6333 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6334 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 6335 tmp |= 0x80; 6336 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 6337 break; 6338 } 6339 } 6340 6341 static void gfx_v10_0_gfx_mqd_set_priority(struct amdgpu_device *adev, 6342 struct v10_gfx_mqd *mqd, 6343 struct amdgpu_mqd_prop *prop) 6344 { 6345 bool priority = 0; 6346 u32 tmp; 6347 6348 /* set up default queue priority level 6349 * 0x0 = low priority, 0x1 = high priority 6350 */ 6351 if (prop->hqd_pipe_priority == AMDGPU_GFX_PIPE_PRIO_HIGH) 6352 priority = 1; 6353 6354 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY); 6355 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority); 6356 mqd->cp_gfx_hqd_queue_priority = tmp; 6357 } 6358 6359 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, 6360 struct amdgpu_mqd_prop *prop) 6361 { 6362 struct v10_gfx_mqd *mqd = m; 6363 uint64_t hqd_gpu_addr, wb_gpu_addr; 6364 uint32_t tmp; 6365 uint32_t rb_bufsz; 6366 6367 /* set up gfx hqd wptr */ 6368 mqd->cp_gfx_hqd_wptr = 0; 6369 mqd->cp_gfx_hqd_wptr_hi = 0; 6370 6371 /* set the pointer to the MQD */ 6372 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; 6373 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 6374 6375 /* set up mqd control */ 6376 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL); 6377 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 6378 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 6379 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 6380 mqd->cp_gfx_mqd_control = tmp; 6381 6382 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 6383 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID); 6384 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 6385 mqd->cp_gfx_hqd_vmid = 0; 6386 6387 /* set up gfx queue priority */ 6388 gfx_v10_0_gfx_mqd_set_priority(adev, mqd, prop); 6389 6390 /* set up time quantum */ 6391 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM); 6392 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 6393 mqd->cp_gfx_hqd_quantum = tmp; 6394 6395 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 6396 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 6397 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 6398 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 6399 6400 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 6401 wb_gpu_addr = prop->rptr_gpu_addr; 6402 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 6403 mqd->cp_gfx_hqd_rptr_addr_hi = 6404 upper_32_bits(wb_gpu_addr) & 0xffff; 6405 6406 /* set up rb_wptr_poll addr */ 6407 wb_gpu_addr = prop->wptr_gpu_addr; 6408 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 6409 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 6410 6411 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 6412 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 6413 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL); 6414 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 6415 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 6416 #ifdef __BIG_ENDIAN 6417 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 6418 #endif 6419 mqd->cp_gfx_hqd_cntl = tmp; 6420 6421 /* set up cp_doorbell_control */ 6422 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 6423 if (prop->use_doorbell) { 6424 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6425 DOORBELL_OFFSET, prop->doorbell_index); 6426 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6427 DOORBELL_EN, 1); 6428 } else 6429 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6430 DOORBELL_EN, 0); 6431 mqd->cp_rb_doorbell_control = tmp; 6432 6433 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6434 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR); 6435 6436 /* active the queue */ 6437 mqd->cp_gfx_hqd_active = 1; 6438 6439 return 0; 6440 } 6441 6442 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring) 6443 { 6444 struct amdgpu_device *adev = ring->adev; 6445 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 6446 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 6447 6448 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 6449 memset((void *)mqd, 0, sizeof(*mqd)); 6450 mutex_lock(&adev->srbm_mutex); 6451 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6452 amdgpu_ring_init_mqd(ring); 6453 6454 /* 6455 * if there are 2 gfx rings, set the lower doorbell 6456 * range of the first ring, otherwise the range of 6457 * the second ring will override the first ring 6458 */ 6459 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1) 6460 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6461 6462 nv_grbm_select(adev, 0, 0, 0, 0); 6463 mutex_unlock(&adev->srbm_mutex); 6464 if (adev->gfx.me.mqd_backup[mqd_idx]) 6465 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6466 } else { 6467 mutex_lock(&adev->srbm_mutex); 6468 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6469 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1) 6470 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6471 6472 nv_grbm_select(adev, 0, 0, 0, 0); 6473 mutex_unlock(&adev->srbm_mutex); 6474 /* restore mqd with the backup copy */ 6475 if (adev->gfx.me.mqd_backup[mqd_idx]) 6476 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 6477 /* reset the ring */ 6478 ring->wptr = 0; 6479 *ring->wptr_cpu_addr = 0; 6480 amdgpu_ring_clear_ring(ring); 6481 } 6482 6483 return 0; 6484 } 6485 6486 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 6487 { 6488 int r, i; 6489 struct amdgpu_ring *ring; 6490 6491 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6492 ring = &adev->gfx.gfx_ring[i]; 6493 6494 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6495 if (unlikely(r != 0)) 6496 return r; 6497 6498 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6499 if (!r) { 6500 r = gfx_v10_0_gfx_init_queue(ring); 6501 amdgpu_bo_kunmap(ring->mqd_obj); 6502 ring->mqd_ptr = NULL; 6503 } 6504 amdgpu_bo_unreserve(ring->mqd_obj); 6505 if (r) 6506 return r; 6507 } 6508 6509 r = amdgpu_gfx_enable_kgq(adev, 0); 6510 if (r) 6511 return r; 6512 6513 return gfx_v10_0_cp_gfx_start(adev); 6514 } 6515 6516 static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 6517 struct amdgpu_mqd_prop *prop) 6518 { 6519 struct v10_compute_mqd *mqd = m; 6520 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 6521 uint32_t tmp; 6522 6523 mqd->header = 0xC0310800; 6524 mqd->compute_pipelinestat_enable = 0x00000001; 6525 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 6526 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 6527 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 6528 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 6529 mqd->compute_misc_reserved = 0x00000003; 6530 6531 eop_base_addr = prop->eop_gpu_addr >> 8; 6532 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 6533 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 6534 6535 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 6536 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); 6537 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 6538 (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1)); 6539 6540 mqd->cp_hqd_eop_control = tmp; 6541 6542 /* enable doorbell? */ 6543 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 6544 6545 if (prop->use_doorbell) { 6546 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6547 DOORBELL_OFFSET, prop->doorbell_index); 6548 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6549 DOORBELL_EN, 1); 6550 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6551 DOORBELL_SOURCE, 0); 6552 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6553 DOORBELL_HIT, 0); 6554 } else { 6555 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6556 DOORBELL_EN, 0); 6557 } 6558 6559 mqd->cp_hqd_pq_doorbell_control = tmp; 6560 6561 /* disable the queue if it's active */ 6562 mqd->cp_hqd_dequeue_request = 0; 6563 mqd->cp_hqd_pq_rptr = 0; 6564 mqd->cp_hqd_pq_wptr_lo = 0; 6565 mqd->cp_hqd_pq_wptr_hi = 0; 6566 6567 /* set the pointer to the MQD */ 6568 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 6569 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 6570 6571 /* set MQD vmid to 0 */ 6572 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); 6573 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 6574 mqd->cp_mqd_control = tmp; 6575 6576 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 6577 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 6578 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 6579 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 6580 6581 /* set up the HQD, this is similar to CP_RB0_CNTL */ 6582 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); 6583 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 6584 (order_base_2(prop->queue_size / 4) - 1)); 6585 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 6586 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 6587 #ifdef __BIG_ENDIAN 6588 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 6589 #endif 6590 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 6591 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 6592 prop->allow_tunneling); 6593 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 6594 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 6595 mqd->cp_hqd_pq_control = tmp; 6596 6597 /* set the wb address whether it's enabled or not */ 6598 wb_gpu_addr = prop->rptr_gpu_addr; 6599 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 6600 mqd->cp_hqd_pq_rptr_report_addr_hi = 6601 upper_32_bits(wb_gpu_addr) & 0xffff; 6602 6603 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 6604 wb_gpu_addr = prop->wptr_gpu_addr; 6605 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 6606 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 6607 6608 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6609 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); 6610 6611 /* set the vmid for the queue */ 6612 mqd->cp_hqd_vmid = 0; 6613 6614 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); 6615 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 6616 mqd->cp_hqd_persistent_state = tmp; 6617 6618 /* set MIN_IB_AVAIL_SIZE */ 6619 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); 6620 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 6621 mqd->cp_hqd_ib_control = tmp; 6622 6623 /* set static priority for a compute queue/ring */ 6624 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 6625 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 6626 6627 mqd->cp_hqd_active = prop->hqd_active; 6628 6629 return 0; 6630 } 6631 6632 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring) 6633 { 6634 struct amdgpu_device *adev = ring->adev; 6635 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6636 int j; 6637 6638 /* inactivate the queue */ 6639 if (amdgpu_sriov_vf(adev)) 6640 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0); 6641 6642 /* disable wptr polling */ 6643 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 6644 6645 /* disable the queue if it's active */ 6646 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 6647 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 6648 for (j = 0; j < adev->usec_timeout; j++) { 6649 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 6650 break; 6651 udelay(1); 6652 } 6653 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 6654 mqd->cp_hqd_dequeue_request); 6655 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 6656 mqd->cp_hqd_pq_rptr); 6657 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 6658 mqd->cp_hqd_pq_wptr_lo); 6659 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 6660 mqd->cp_hqd_pq_wptr_hi); 6661 } 6662 6663 /* disable doorbells */ 6664 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0); 6665 6666 /* write the EOP addr */ 6667 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, 6668 mqd->cp_hqd_eop_base_addr_lo); 6669 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, 6670 mqd->cp_hqd_eop_base_addr_hi); 6671 6672 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 6673 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, 6674 mqd->cp_hqd_eop_control); 6675 6676 /* set the pointer to the MQD */ 6677 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, 6678 mqd->cp_mqd_base_addr_lo); 6679 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, 6680 mqd->cp_mqd_base_addr_hi); 6681 6682 /* set MQD vmid to 0 */ 6683 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, 6684 mqd->cp_mqd_control); 6685 6686 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 6687 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, 6688 mqd->cp_hqd_pq_base_lo); 6689 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, 6690 mqd->cp_hqd_pq_base_hi); 6691 6692 /* set up the HQD, this is similar to CP_RB0_CNTL */ 6693 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, 6694 mqd->cp_hqd_pq_control); 6695 6696 /* set the wb address whether it's enabled or not */ 6697 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, 6698 mqd->cp_hqd_pq_rptr_report_addr_lo); 6699 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 6700 mqd->cp_hqd_pq_rptr_report_addr_hi); 6701 6702 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 6703 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, 6704 mqd->cp_hqd_pq_wptr_poll_addr_lo); 6705 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 6706 mqd->cp_hqd_pq_wptr_poll_addr_hi); 6707 6708 /* enable the doorbell if requested */ 6709 if (ring->use_doorbell) { 6710 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, 6711 (adev->doorbell_index.kiq * 2) << 2); 6712 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 6713 (adev->doorbell_index.userqueue_end * 2) << 2); 6714 } 6715 6716 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 6717 mqd->cp_hqd_pq_doorbell_control); 6718 6719 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6720 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 6721 mqd->cp_hqd_pq_wptr_lo); 6722 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 6723 mqd->cp_hqd_pq_wptr_hi); 6724 6725 /* set the vmid for the queue */ 6726 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); 6727 6728 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 6729 mqd->cp_hqd_persistent_state); 6730 6731 /* activate the queue */ 6732 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 6733 mqd->cp_hqd_active); 6734 6735 if (ring->use_doorbell) 6736 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 6737 6738 return 0; 6739 } 6740 6741 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring) 6742 { 6743 struct amdgpu_device *adev = ring->adev; 6744 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6745 6746 gfx_v10_0_kiq_setting(ring); 6747 6748 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 6749 /* reset MQD to a clean status */ 6750 if (adev->gfx.kiq[0].mqd_backup) 6751 memcpy_toio(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd)); 6752 6753 /* reset ring buffer */ 6754 ring->wptr = 0; 6755 amdgpu_ring_clear_ring(ring); 6756 6757 mutex_lock(&adev->srbm_mutex); 6758 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6759 gfx_v10_0_kiq_init_register(ring); 6760 nv_grbm_select(adev, 0, 0, 0, 0); 6761 mutex_unlock(&adev->srbm_mutex); 6762 } else { 6763 memset((void *)mqd, 0, sizeof(*mqd)); 6764 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 6765 amdgpu_ring_clear_ring(ring); 6766 mutex_lock(&adev->srbm_mutex); 6767 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6768 amdgpu_ring_init_mqd(ring); 6769 gfx_v10_0_kiq_init_register(ring); 6770 nv_grbm_select(adev, 0, 0, 0, 0); 6771 mutex_unlock(&adev->srbm_mutex); 6772 6773 if (adev->gfx.kiq[0].mqd_backup) 6774 memcpy_fromio(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd)); 6775 } 6776 6777 return 0; 6778 } 6779 6780 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring) 6781 { 6782 struct amdgpu_device *adev = ring->adev; 6783 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6784 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 6785 6786 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 6787 memset((void *)mqd, 0, sizeof(*mqd)); 6788 mutex_lock(&adev->srbm_mutex); 6789 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6790 amdgpu_ring_init_mqd(ring); 6791 nv_grbm_select(adev, 0, 0, 0, 0); 6792 mutex_unlock(&adev->srbm_mutex); 6793 6794 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6795 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6796 } else { 6797 /* restore MQD to a clean status */ 6798 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6799 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 6800 /* reset ring buffer */ 6801 ring->wptr = 0; 6802 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 6803 amdgpu_ring_clear_ring(ring); 6804 } 6805 6806 return 0; 6807 } 6808 6809 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev) 6810 { 6811 struct amdgpu_ring *ring; 6812 int r; 6813 6814 ring = &adev->gfx.kiq[0].ring; 6815 6816 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6817 if (unlikely(r != 0)) 6818 return r; 6819 6820 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6821 if (unlikely(r != 0)) { 6822 amdgpu_bo_unreserve(ring->mqd_obj); 6823 return r; 6824 } 6825 6826 gfx_v10_0_kiq_init_queue(ring); 6827 amdgpu_bo_kunmap(ring->mqd_obj); 6828 ring->mqd_ptr = NULL; 6829 amdgpu_bo_unreserve(ring->mqd_obj); 6830 return 0; 6831 } 6832 6833 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev) 6834 { 6835 struct amdgpu_ring *ring = NULL; 6836 int r = 0, i; 6837 6838 gfx_v10_0_cp_compute_enable(adev, true); 6839 6840 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6841 ring = &adev->gfx.compute_ring[i]; 6842 6843 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6844 if (unlikely(r != 0)) 6845 goto done; 6846 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6847 if (!r) { 6848 r = gfx_v10_0_kcq_init_queue(ring); 6849 amdgpu_bo_kunmap(ring->mqd_obj); 6850 ring->mqd_ptr = NULL; 6851 } 6852 amdgpu_bo_unreserve(ring->mqd_obj); 6853 if (r) 6854 goto done; 6855 } 6856 6857 r = amdgpu_gfx_enable_kcq(adev, 0); 6858 done: 6859 return r; 6860 } 6861 6862 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev) 6863 { 6864 int r, i; 6865 struct amdgpu_ring *ring; 6866 6867 if (!(adev->flags & AMD_IS_APU)) 6868 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 6869 6870 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 6871 /* legacy firmware loading */ 6872 r = gfx_v10_0_cp_gfx_load_microcode(adev); 6873 if (r) 6874 return r; 6875 6876 r = gfx_v10_0_cp_compute_load_microcode(adev); 6877 if (r) 6878 return r; 6879 } 6880 6881 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) 6882 r = amdgpu_mes_kiq_hw_init(adev); 6883 else 6884 r = gfx_v10_0_kiq_resume(adev); 6885 if (r) 6886 return r; 6887 6888 r = gfx_v10_0_kcq_resume(adev); 6889 if (r) 6890 return r; 6891 6892 if (!amdgpu_async_gfx_ring) { 6893 r = gfx_v10_0_cp_gfx_resume(adev); 6894 if (r) 6895 return r; 6896 } else { 6897 r = gfx_v10_0_cp_async_gfx_ring_resume(adev); 6898 if (r) 6899 return r; 6900 } 6901 6902 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6903 ring = &adev->gfx.gfx_ring[i]; 6904 r = amdgpu_ring_test_helper(ring); 6905 if (r) 6906 return r; 6907 } 6908 6909 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6910 ring = &adev->gfx.compute_ring[i]; 6911 r = amdgpu_ring_test_helper(ring); 6912 if (r) 6913 return r; 6914 } 6915 6916 return 0; 6917 } 6918 6919 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable) 6920 { 6921 gfx_v10_0_cp_gfx_enable(adev, enable); 6922 gfx_v10_0_cp_compute_enable(adev, enable); 6923 } 6924 6925 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev) 6926 { 6927 uint32_t data, pattern = 0xDEADBEEF; 6928 6929 /* 6930 * check if mmVGT_ESGS_RING_SIZE_UMD 6931 * has been remapped to mmVGT_ESGS_RING_SIZE 6932 */ 6933 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 6934 case IP_VERSION(10, 3, 0): 6935 case IP_VERSION(10, 3, 2): 6936 case IP_VERSION(10, 3, 4): 6937 case IP_VERSION(10, 3, 5): 6938 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid); 6939 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0); 6940 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 6941 6942 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) { 6943 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data); 6944 return true; 6945 } 6946 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data); 6947 break; 6948 case IP_VERSION(10, 3, 1): 6949 case IP_VERSION(10, 3, 3): 6950 case IP_VERSION(10, 3, 6): 6951 case IP_VERSION(10, 3, 7): 6952 return true; 6953 default: 6954 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE); 6955 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0); 6956 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 6957 6958 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) { 6959 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data); 6960 return true; 6961 } 6962 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data); 6963 break; 6964 } 6965 6966 return false; 6967 } 6968 6969 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev) 6970 { 6971 uint32_t data; 6972 6973 if (amdgpu_sriov_vf(adev)) 6974 return; 6975 6976 /* 6977 * Initialize cam_index to 0 6978 * index will auto-inc after each data writing 6979 */ 6980 WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0); 6981 6982 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 6983 case IP_VERSION(10, 3, 0): 6984 case IP_VERSION(10, 3, 2): 6985 case IP_VERSION(10, 3, 1): 6986 case IP_VERSION(10, 3, 4): 6987 case IP_VERSION(10, 3, 5): 6988 case IP_VERSION(10, 3, 6): 6989 case IP_VERSION(10, 3, 3): 6990 case IP_VERSION(10, 3, 7): 6991 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 6992 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 6993 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 6994 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) << 6995 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 6996 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 6997 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 6998 6999 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 7000 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 7001 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7002 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) << 7003 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7004 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7005 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7006 7007 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 7008 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 7009 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7010 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) << 7011 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7012 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7013 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7014 7015 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 7016 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 7017 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7018 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) << 7019 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7020 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7021 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7022 7023 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7024 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7025 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7026 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) << 7027 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7028 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7029 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7030 7031 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7032 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7033 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7034 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) << 7035 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7036 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7037 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7038 7039 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7040 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7041 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7042 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) << 7043 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7044 break; 7045 default: 7046 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 7047 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 7048 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7049 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) << 7050 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7051 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7052 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7053 7054 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 7055 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 7056 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7057 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) << 7058 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7059 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7060 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7061 7062 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 7063 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 7064 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7065 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) << 7066 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7067 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7068 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7069 7070 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 7071 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 7072 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7073 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) << 7074 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7075 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7076 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7077 7078 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7079 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7080 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7081 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) << 7082 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7083 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7084 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7085 7086 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7087 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7088 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7089 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) << 7090 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7091 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7092 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7093 7094 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7095 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7096 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7097 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) << 7098 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7099 break; 7100 } 7101 7102 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7103 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7104 } 7105 7106 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev) 7107 { 7108 uint32_t data; 7109 7110 data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG); 7111 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 7112 WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data); 7113 7114 data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG); 7115 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 7116 WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data); 7117 } 7118 7119 static int gfx_v10_0_hw_init(void *handle) 7120 { 7121 int r; 7122 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7123 7124 if (!amdgpu_emu_mode) 7125 gfx_v10_0_init_golden_registers(adev); 7126 7127 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 7128 /** 7129 * For gfx 10, rlc firmware loading relies on smu firmware is 7130 * loaded firstly, so in direct type, it has to load smc ucode 7131 * here before rlc. 7132 */ 7133 if (!(adev->flags & AMD_IS_APU)) { 7134 r = amdgpu_pm_load_smu_firmware(adev, NULL); 7135 if (r) 7136 return r; 7137 } 7138 gfx_v10_0_disable_gpa_mode(adev); 7139 } 7140 7141 /* if GRBM CAM not remapped, set up the remapping */ 7142 if (!gfx_v10_0_check_grbm_cam_remapping(adev)) 7143 gfx_v10_0_setup_grbm_cam_remapping(adev); 7144 7145 gfx_v10_0_constants_init(adev); 7146 7147 r = gfx_v10_0_rlc_resume(adev); 7148 if (r) 7149 return r; 7150 7151 /* 7152 * init golden registers and rlc resume may override some registers, 7153 * reconfig them here 7154 */ 7155 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 10) || 7156 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 1) || 7157 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) 7158 gfx_v10_0_tcp_harvest(adev); 7159 7160 r = gfx_v10_0_cp_resume(adev); 7161 if (r) 7162 return r; 7163 7164 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 0)) 7165 gfx_v10_3_program_pbb_mode(adev); 7166 7167 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0)) 7168 gfx_v10_3_set_power_brake_sequence(adev); 7169 7170 return r; 7171 } 7172 7173 static int gfx_v10_0_hw_fini(void *handle) 7174 { 7175 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7176 7177 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 7178 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 7179 7180 /* WA added for Vangogh asic fixing the SMU suspend failure 7181 * It needs to set power gating again during gfxoff control 7182 * otherwise the gfxoff disallowing will be failed to set. 7183 */ 7184 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 1)) 7185 gfx_v10_0_set_powergating_state(handle, AMD_PG_STATE_UNGATE); 7186 7187 if (!adev->no_hw_access) { 7188 if (amdgpu_async_gfx_ring) { 7189 if (amdgpu_gfx_disable_kgq(adev, 0)) 7190 DRM_ERROR("KGQ disable failed\n"); 7191 } 7192 7193 if (amdgpu_gfx_disable_kcq(adev, 0)) 7194 DRM_ERROR("KCQ disable failed\n"); 7195 } 7196 7197 if (amdgpu_sriov_vf(adev)) { 7198 gfx_v10_0_cp_gfx_enable(adev, false); 7199 /* Remove the steps of clearing KIQ position. 7200 * It causes GFX hang when another Win guest is rendering. 7201 */ 7202 return 0; 7203 } 7204 gfx_v10_0_cp_enable(adev, false); 7205 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 7206 7207 return 0; 7208 } 7209 7210 static int gfx_v10_0_suspend(void *handle) 7211 { 7212 return gfx_v10_0_hw_fini(handle); 7213 } 7214 7215 static int gfx_v10_0_resume(void *handle) 7216 { 7217 return gfx_v10_0_hw_init(handle); 7218 } 7219 7220 static bool gfx_v10_0_is_idle(void *handle) 7221 { 7222 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7223 7224 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), 7225 GRBM_STATUS, GUI_ACTIVE)) 7226 return false; 7227 else 7228 return true; 7229 } 7230 7231 static int gfx_v10_0_wait_for_idle(void *handle) 7232 { 7233 unsigned int i; 7234 u32 tmp; 7235 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7236 7237 for (i = 0; i < adev->usec_timeout; i++) { 7238 /* read MC_STATUS */ 7239 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) & 7240 GRBM_STATUS__GUI_ACTIVE_MASK; 7241 7242 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 7243 return 0; 7244 udelay(1); 7245 } 7246 return -ETIMEDOUT; 7247 } 7248 7249 static int gfx_v10_0_soft_reset(void *handle) 7250 { 7251 u32 grbm_soft_reset = 0; 7252 u32 tmp; 7253 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7254 7255 /* GRBM_STATUS */ 7256 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); 7257 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 7258 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 7259 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK | 7260 GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK | 7261 GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) { 7262 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7263 GRBM_SOFT_RESET, SOFT_RESET_CP, 7264 1); 7265 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7266 GRBM_SOFT_RESET, SOFT_RESET_GFX, 7267 1); 7268 } 7269 7270 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 7271 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7272 GRBM_SOFT_RESET, SOFT_RESET_CP, 7273 1); 7274 } 7275 7276 /* GRBM_STATUS2 */ 7277 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); 7278 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7279 case IP_VERSION(10, 3, 0): 7280 case IP_VERSION(10, 3, 2): 7281 case IP_VERSION(10, 3, 1): 7282 case IP_VERSION(10, 3, 4): 7283 case IP_VERSION(10, 3, 5): 7284 case IP_VERSION(10, 3, 6): 7285 case IP_VERSION(10, 3, 3): 7286 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid)) 7287 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7288 GRBM_SOFT_RESET, 7289 SOFT_RESET_RLC, 7290 1); 7291 break; 7292 default: 7293 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 7294 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7295 GRBM_SOFT_RESET, 7296 SOFT_RESET_RLC, 7297 1); 7298 break; 7299 } 7300 7301 if (grbm_soft_reset) { 7302 /* stop the rlc */ 7303 gfx_v10_0_rlc_stop(adev); 7304 7305 /* Disable GFX parsing/prefetching */ 7306 gfx_v10_0_cp_gfx_enable(adev, false); 7307 7308 /* Disable MEC parsing/prefetching */ 7309 gfx_v10_0_cp_compute_enable(adev, false); 7310 7311 if (grbm_soft_reset) { 7312 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7313 tmp |= grbm_soft_reset; 7314 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 7315 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7316 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7317 7318 udelay(50); 7319 7320 tmp &= ~grbm_soft_reset; 7321 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7322 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7323 } 7324 7325 /* Wait a little for things to settle down */ 7326 udelay(50); 7327 } 7328 return 0; 7329 } 7330 7331 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev) 7332 { 7333 uint64_t clock, clock_lo, clock_hi, hi_check; 7334 7335 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7336 case IP_VERSION(10, 1, 3): 7337 case IP_VERSION(10, 1, 4): 7338 preempt_disable(); 7339 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish); 7340 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish); 7341 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish); 7342 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7343 * roughly every 42 seconds. 7344 */ 7345 if (hi_check != clock_hi) { 7346 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish); 7347 clock_hi = hi_check; 7348 } 7349 preempt_enable(); 7350 clock = clock_lo | (clock_hi << 32ULL); 7351 break; 7352 case IP_VERSION(10, 3, 1): 7353 case IP_VERSION(10, 3, 3): 7354 case IP_VERSION(10, 3, 7): 7355 preempt_disable(); 7356 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh); 7357 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh); 7358 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh); 7359 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7360 * roughly every 42 seconds. 7361 */ 7362 if (hi_check != clock_hi) { 7363 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh); 7364 clock_hi = hi_check; 7365 } 7366 preempt_enable(); 7367 clock = clock_lo | (clock_hi << 32ULL); 7368 break; 7369 case IP_VERSION(10, 3, 6): 7370 preempt_disable(); 7371 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6); 7372 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6); 7373 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6); 7374 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7375 * roughly every 42 seconds. 7376 */ 7377 if (hi_check != clock_hi) { 7378 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6); 7379 clock_hi = hi_check; 7380 } 7381 preempt_enable(); 7382 clock = clock_lo | (clock_hi << 32ULL); 7383 break; 7384 default: 7385 preempt_disable(); 7386 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER); 7387 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER); 7388 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER); 7389 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7390 * roughly every 42 seconds. 7391 */ 7392 if (hi_check != clock_hi) { 7393 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER); 7394 clock_hi = hi_check; 7395 } 7396 preempt_enable(); 7397 clock = clock_lo | (clock_hi << 32ULL); 7398 break; 7399 } 7400 return clock; 7401 } 7402 7403 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 7404 uint32_t vmid, 7405 uint32_t gds_base, uint32_t gds_size, 7406 uint32_t gws_base, uint32_t gws_size, 7407 uint32_t oa_base, uint32_t oa_size) 7408 { 7409 struct amdgpu_device *adev = ring->adev; 7410 7411 /* GDS Base */ 7412 gfx_v10_0_write_data_to_reg(ring, 0, false, 7413 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, 7414 gds_base); 7415 7416 /* GDS Size */ 7417 gfx_v10_0_write_data_to_reg(ring, 0, false, 7418 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, 7419 gds_size); 7420 7421 /* GWS */ 7422 gfx_v10_0_write_data_to_reg(ring, 0, false, 7423 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid, 7424 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 7425 7426 /* OA */ 7427 gfx_v10_0_write_data_to_reg(ring, 0, false, 7428 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid, 7429 (1 << (oa_size + oa_base)) - (1 << oa_base)); 7430 } 7431 7432 static int gfx_v10_0_early_init(void *handle) 7433 { 7434 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7435 7436 adev->gfx.funcs = &gfx_v10_0_gfx_funcs; 7437 7438 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7439 case IP_VERSION(10, 1, 10): 7440 case IP_VERSION(10, 1, 1): 7441 case IP_VERSION(10, 1, 2): 7442 case IP_VERSION(10, 1, 3): 7443 case IP_VERSION(10, 1, 4): 7444 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X; 7445 break; 7446 case IP_VERSION(10, 3, 0): 7447 case IP_VERSION(10, 3, 2): 7448 case IP_VERSION(10, 3, 1): 7449 case IP_VERSION(10, 3, 4): 7450 case IP_VERSION(10, 3, 5): 7451 case IP_VERSION(10, 3, 6): 7452 case IP_VERSION(10, 3, 3): 7453 case IP_VERSION(10, 3, 7): 7454 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid; 7455 break; 7456 default: 7457 break; 7458 } 7459 7460 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 7461 AMDGPU_MAX_COMPUTE_RINGS); 7462 7463 gfx_v10_0_set_kiq_pm4_funcs(adev); 7464 gfx_v10_0_set_ring_funcs(adev); 7465 gfx_v10_0_set_irq_funcs(adev); 7466 gfx_v10_0_set_gds_init(adev); 7467 gfx_v10_0_set_rlc_funcs(adev); 7468 gfx_v10_0_set_mqd_funcs(adev); 7469 7470 /* init rlcg reg access ctrl */ 7471 gfx_v10_0_init_rlcg_reg_access_ctrl(adev); 7472 7473 return gfx_v10_0_init_microcode(adev); 7474 } 7475 7476 static int gfx_v10_0_late_init(void *handle) 7477 { 7478 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7479 int r; 7480 7481 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 7482 if (r) 7483 return r; 7484 7485 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 7486 if (r) 7487 return r; 7488 7489 return 0; 7490 } 7491 7492 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev) 7493 { 7494 uint32_t rlc_cntl; 7495 7496 /* if RLC is not enabled, do nothing */ 7497 rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL); 7498 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 7499 } 7500 7501 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 7502 { 7503 uint32_t data; 7504 unsigned int i; 7505 7506 data = RLC_SAFE_MODE__CMD_MASK; 7507 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 7508 7509 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7510 case IP_VERSION(10, 3, 0): 7511 case IP_VERSION(10, 3, 2): 7512 case IP_VERSION(10, 3, 1): 7513 case IP_VERSION(10, 3, 4): 7514 case IP_VERSION(10, 3, 5): 7515 case IP_VERSION(10, 3, 6): 7516 case IP_VERSION(10, 3, 3): 7517 case IP_VERSION(10, 3, 7): 7518 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7519 7520 /* wait for RLC_SAFE_MODE */ 7521 for (i = 0; i < adev->usec_timeout; i++) { 7522 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid), 7523 RLC_SAFE_MODE, CMD)) 7524 break; 7525 udelay(1); 7526 } 7527 break; 7528 default: 7529 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7530 7531 /* wait for RLC_SAFE_MODE */ 7532 for (i = 0; i < adev->usec_timeout; i++) { 7533 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), 7534 RLC_SAFE_MODE, CMD)) 7535 break; 7536 udelay(1); 7537 } 7538 break; 7539 } 7540 } 7541 7542 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id) 7543 { 7544 uint32_t data; 7545 7546 data = RLC_SAFE_MODE__CMD_MASK; 7547 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7548 case IP_VERSION(10, 3, 0): 7549 case IP_VERSION(10, 3, 2): 7550 case IP_VERSION(10, 3, 1): 7551 case IP_VERSION(10, 3, 4): 7552 case IP_VERSION(10, 3, 5): 7553 case IP_VERSION(10, 3, 6): 7554 case IP_VERSION(10, 3, 3): 7555 case IP_VERSION(10, 3, 7): 7556 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7557 break; 7558 default: 7559 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7560 break; 7561 } 7562 } 7563 7564 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 7565 bool enable) 7566 { 7567 uint32_t data, def; 7568 7569 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 7570 return; 7571 7572 /* It is disabled by HW by default */ 7573 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 7574 /* 0 - Disable some blocks' MGCG */ 7575 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000); 7576 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000); 7577 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000); 7578 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000); 7579 7580 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 7581 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7582 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7583 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 7584 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7585 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK | 7586 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK | 7587 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK); 7588 7589 if (def != data) 7590 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7591 7592 /* MGLS is a global flag to control all MGLS in GFX */ 7593 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 7594 /* 2 - RLC memory Light sleep */ 7595 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 7596 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 7597 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 7598 if (def != data) 7599 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 7600 } 7601 /* 3 - CP memory Light sleep */ 7602 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 7603 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 7604 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 7605 if (def != data) 7606 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 7607 } 7608 } 7609 } else if (!enable || !(adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 7610 /* 1 - MGCG_OVERRIDE */ 7611 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7612 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 7613 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7614 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7615 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK | 7616 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK | 7617 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK); 7618 if (def != data) 7619 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7620 7621 /* 2 - disable MGLS in CP */ 7622 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 7623 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 7624 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 7625 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 7626 } 7627 7628 /* 3 - disable MGLS in RLC */ 7629 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 7630 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 7631 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 7632 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 7633 } 7634 7635 } 7636 } 7637 7638 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev, 7639 bool enable) 7640 { 7641 uint32_t data, def; 7642 7643 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS))) 7644 return; 7645 7646 /* Enable 3D CGCG/CGLS */ 7647 if (enable) { 7648 /* write cmd to clear cgcg/cgls ov */ 7649 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7650 7651 /* unset CGCG override */ 7652 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 7653 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 7654 7655 /* update CGCG and CGLS override bits */ 7656 if (def != data) 7657 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7658 7659 /* enable 3Dcgcg FSM(0x0000363f) */ 7660 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 7661 data = 0; 7662 7663 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 7664 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 7665 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 7666 7667 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 7668 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 7669 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 7670 7671 if (def != data) 7672 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 7673 7674 /* set IDLE_POLL_COUNT(0x00900100) */ 7675 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 7676 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 7677 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 7678 if (def != data) 7679 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 7680 } else { 7681 /* Disable CGCG/CGLS */ 7682 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 7683 7684 /* disable cgcg, cgls should be disabled */ 7685 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 7686 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 7687 7688 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 7689 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 7690 7691 /* disable cgcg and cgls in FSM */ 7692 if (def != data) 7693 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 7694 } 7695 } 7696 7697 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 7698 bool enable) 7699 { 7700 uint32_t def, data; 7701 7702 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS))) 7703 return; 7704 7705 if (enable) { 7706 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7707 7708 /* unset CGCG override */ 7709 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 7710 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 7711 7712 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 7713 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 7714 7715 /* update CGCG and CGLS override bits */ 7716 if (def != data) 7717 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7718 7719 /* enable cgcg FSM(0x0000363F) */ 7720 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 7721 data = 0; 7722 7723 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 7724 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 7725 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 7726 7727 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 7728 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 7729 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 7730 7731 if (def != data) 7732 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 7733 7734 /* set IDLE_POLL_COUNT(0x00900100) */ 7735 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 7736 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 7737 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 7738 if (def != data) 7739 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 7740 } else { 7741 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 7742 7743 /* reset CGCG/CGLS bits */ 7744 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 7745 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 7746 7747 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 7748 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 7749 7750 /* disable cgcg and cgls in FSM */ 7751 if (def != data) 7752 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 7753 } 7754 } 7755 7756 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev, 7757 bool enable) 7758 { 7759 uint32_t def, data; 7760 7761 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 7762 return; 7763 7764 if (enable) { 7765 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7766 /* unset FGCG override */ 7767 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 7768 /* update FGCG override bits */ 7769 if (def != data) 7770 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7771 7772 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); 7773 /* unset RLC SRAM CLK GATER override */ 7774 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 7775 /* update RLC SRAM CLK GATER override bits */ 7776 if (def != data) 7777 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); 7778 } else { 7779 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7780 /* reset FGCG bits */ 7781 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 7782 /* disable FGCG*/ 7783 if (def != data) 7784 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7785 7786 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); 7787 /* reset RLC SRAM CLK GATER bits */ 7788 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 7789 /* disable RLC SRAM CLK*/ 7790 if (def != data) 7791 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); 7792 } 7793 } 7794 7795 static void gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_device *adev) 7796 { 7797 uint32_t reg_data = 0; 7798 uint32_t reg_idx = 0; 7799 uint32_t i; 7800 7801 const uint32_t tcp_ctrl_regs[] = { 7802 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG, 7803 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG, 7804 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG, 7805 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG, 7806 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG, 7807 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG, 7808 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG, 7809 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG, 7810 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG, 7811 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG, 7812 mmCGTS_SA0_WGP12_CU0_TCP_CTRL_REG, 7813 mmCGTS_SA0_WGP12_CU1_TCP_CTRL_REG, 7814 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG, 7815 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG, 7816 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG, 7817 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG, 7818 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG, 7819 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG, 7820 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG, 7821 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG, 7822 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG, 7823 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG, 7824 mmCGTS_SA1_WGP12_CU0_TCP_CTRL_REG, 7825 mmCGTS_SA1_WGP12_CU1_TCP_CTRL_REG 7826 }; 7827 7828 const uint32_t tcp_ctrl_regs_nv12[] = { 7829 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG, 7830 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG, 7831 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG, 7832 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG, 7833 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG, 7834 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG, 7835 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG, 7836 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG, 7837 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG, 7838 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG, 7839 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG, 7840 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG, 7841 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG, 7842 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG, 7843 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG, 7844 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG, 7845 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG, 7846 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG, 7847 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG, 7848 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG, 7849 }; 7850 7851 const uint32_t sm_ctlr_regs[] = { 7852 mmCGTS_SA0_QUAD0_SM_CTRL_REG, 7853 mmCGTS_SA0_QUAD1_SM_CTRL_REG, 7854 mmCGTS_SA1_QUAD0_SM_CTRL_REG, 7855 mmCGTS_SA1_QUAD1_SM_CTRL_REG 7856 }; 7857 7858 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) { 7859 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs_nv12); i++) { 7860 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] + 7861 tcp_ctrl_regs_nv12[i]; 7862 reg_data = RREG32(reg_idx); 7863 reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK; 7864 WREG32(reg_idx, reg_data); 7865 } 7866 } else { 7867 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs); i++) { 7868 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] + 7869 tcp_ctrl_regs[i]; 7870 reg_data = RREG32(reg_idx); 7871 reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK; 7872 WREG32(reg_idx, reg_data); 7873 } 7874 } 7875 7876 for (i = 0; i < ARRAY_SIZE(sm_ctlr_regs); i++) { 7877 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_QUAD0_SM_CTRL_REG_BASE_IDX] + 7878 sm_ctlr_regs[i]; 7879 reg_data = RREG32(reg_idx); 7880 reg_data &= ~CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE_MASK; 7881 reg_data |= 2 << CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE__SHIFT; 7882 WREG32(reg_idx, reg_data); 7883 } 7884 } 7885 7886 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev, 7887 bool enable) 7888 { 7889 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 7890 7891 if (enable) { 7892 /* enable FGCG firstly*/ 7893 gfx_v10_0_update_fine_grain_clock_gating(adev, enable); 7894 /* CGCG/CGLS should be enabled after MGCG/MGLS 7895 * === MGCG + MGLS === 7896 */ 7897 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 7898 /* === CGCG /CGLS for GFX 3D Only === */ 7899 gfx_v10_0_update_3d_clock_gating(adev, enable); 7900 /* === CGCG + CGLS === */ 7901 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 7902 7903 if ((amdgpu_ip_version(adev, GC_HWIP, 0) == 7904 IP_VERSION(10, 1, 10)) || 7905 (amdgpu_ip_version(adev, GC_HWIP, 0) == 7906 IP_VERSION(10, 1, 1)) || 7907 (amdgpu_ip_version(adev, GC_HWIP, 0) == 7908 IP_VERSION(10, 1, 2))) 7909 gfx_v10_0_apply_medium_grain_clock_gating_workaround(adev); 7910 } else { 7911 /* CGCG/CGLS should be disabled before MGCG/MGLS 7912 * === CGCG + CGLS === 7913 */ 7914 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 7915 /* === CGCG /CGLS for GFX 3D Only === */ 7916 gfx_v10_0_update_3d_clock_gating(adev, enable); 7917 /* === MGCG + MGLS === */ 7918 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 7919 /* disable fgcg at last*/ 7920 gfx_v10_0_update_fine_grain_clock_gating(adev, enable); 7921 } 7922 7923 if (adev->cg_flags & 7924 (AMD_CG_SUPPORT_GFX_MGCG | 7925 AMD_CG_SUPPORT_GFX_CGLS | 7926 AMD_CG_SUPPORT_GFX_CGCG | 7927 AMD_CG_SUPPORT_GFX_3D_CGCG | 7928 AMD_CG_SUPPORT_GFX_3D_CGLS)) 7929 gfx_v10_0_enable_gui_idle_interrupt(adev, enable); 7930 7931 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 7932 7933 return 0; 7934 } 7935 7936 static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev, 7937 unsigned int vmid) 7938 { 7939 u32 data; 7940 7941 /* not for *_SOC15 */ 7942 data = RREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL); 7943 7944 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 7945 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 7946 7947 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data); 7948 } 7949 7950 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned int vmid) 7951 { 7952 amdgpu_gfx_off_ctrl(adev, false); 7953 7954 gfx_v10_0_update_spm_vmid_internal(adev, vmid); 7955 7956 amdgpu_gfx_off_ctrl(adev, true); 7957 } 7958 7959 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev, 7960 uint32_t offset, 7961 struct soc15_reg_rlcg *entries, int arr_size) 7962 { 7963 int i; 7964 uint32_t reg; 7965 7966 if (!entries) 7967 return false; 7968 7969 for (i = 0; i < arr_size; i++) { 7970 const struct soc15_reg_rlcg *entry; 7971 7972 entry = &entries[i]; 7973 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 7974 if (offset == reg) 7975 return true; 7976 } 7977 7978 return false; 7979 } 7980 7981 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 7982 { 7983 return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0); 7984 } 7985 7986 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable) 7987 { 7988 u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 7989 7990 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) 7991 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 7992 else 7993 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 7994 7995 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data); 7996 7997 /* 7998 * CGPG enablement required and the register to program the hysteresis value 7999 * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value 8000 * in refclk count. Note that RLC FW is modified to take 16 bits from 8001 * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits. 8002 * 8003 * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us as part) 8004 * of CGPG enablement starting point. 8005 * Power/performance team will optimize it and might give a new value later. 8006 */ 8007 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 8008 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 8009 case IP_VERSION(10, 3, 1): 8010 case IP_VERSION(10, 3, 3): 8011 case IP_VERSION(10, 3, 6): 8012 case IP_VERSION(10, 3, 7): 8013 data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh; 8014 WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data); 8015 break; 8016 default: 8017 break; 8018 } 8019 } 8020 } 8021 8022 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable) 8023 { 8024 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 8025 8026 gfx_v10_cntl_power_gating(adev, enable); 8027 8028 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 8029 } 8030 8031 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = { 8032 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 8033 .set_safe_mode = gfx_v10_0_set_safe_mode, 8034 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 8035 .init = gfx_v10_0_rlc_init, 8036 .get_csb_size = gfx_v10_0_get_csb_size, 8037 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 8038 .resume = gfx_v10_0_rlc_resume, 8039 .stop = gfx_v10_0_rlc_stop, 8040 .reset = gfx_v10_0_rlc_reset, 8041 .start = gfx_v10_0_rlc_start, 8042 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 8043 }; 8044 8045 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = { 8046 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 8047 .set_safe_mode = gfx_v10_0_set_safe_mode, 8048 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 8049 .init = gfx_v10_0_rlc_init, 8050 .get_csb_size = gfx_v10_0_get_csb_size, 8051 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 8052 .resume = gfx_v10_0_rlc_resume, 8053 .stop = gfx_v10_0_rlc_stop, 8054 .reset = gfx_v10_0_rlc_reset, 8055 .start = gfx_v10_0_rlc_start, 8056 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 8057 .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range, 8058 }; 8059 8060 static int gfx_v10_0_set_powergating_state(void *handle, 8061 enum amd_powergating_state state) 8062 { 8063 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8064 bool enable = (state == AMD_PG_STATE_GATE); 8065 8066 if (amdgpu_sriov_vf(adev)) 8067 return 0; 8068 8069 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 8070 case IP_VERSION(10, 1, 10): 8071 case IP_VERSION(10, 1, 1): 8072 case IP_VERSION(10, 1, 2): 8073 case IP_VERSION(10, 3, 0): 8074 case IP_VERSION(10, 3, 2): 8075 case IP_VERSION(10, 3, 4): 8076 case IP_VERSION(10, 3, 5): 8077 amdgpu_gfx_off_ctrl(adev, enable); 8078 break; 8079 case IP_VERSION(10, 3, 1): 8080 case IP_VERSION(10, 3, 3): 8081 case IP_VERSION(10, 3, 6): 8082 case IP_VERSION(10, 3, 7): 8083 if (!enable) 8084 amdgpu_gfx_off_ctrl(adev, false); 8085 8086 gfx_v10_cntl_pg(adev, enable); 8087 8088 if (enable) 8089 amdgpu_gfx_off_ctrl(adev, true); 8090 8091 break; 8092 default: 8093 break; 8094 } 8095 return 0; 8096 } 8097 8098 static int gfx_v10_0_set_clockgating_state(void *handle, 8099 enum amd_clockgating_state state) 8100 { 8101 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8102 8103 if (amdgpu_sriov_vf(adev)) 8104 return 0; 8105 8106 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 8107 case IP_VERSION(10, 1, 10): 8108 case IP_VERSION(10, 1, 1): 8109 case IP_VERSION(10, 1, 2): 8110 case IP_VERSION(10, 3, 0): 8111 case IP_VERSION(10, 3, 2): 8112 case IP_VERSION(10, 3, 1): 8113 case IP_VERSION(10, 3, 4): 8114 case IP_VERSION(10, 3, 5): 8115 case IP_VERSION(10, 3, 6): 8116 case IP_VERSION(10, 3, 3): 8117 case IP_VERSION(10, 3, 7): 8118 gfx_v10_0_update_gfx_clock_gating(adev, 8119 state == AMD_CG_STATE_GATE); 8120 break; 8121 default: 8122 break; 8123 } 8124 return 0; 8125 } 8126 8127 static void gfx_v10_0_get_clockgating_state(void *handle, u64 *flags) 8128 { 8129 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8130 int data; 8131 8132 /* AMD_CG_SUPPORT_GFX_FGCG */ 8133 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 8134 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 8135 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 8136 8137 /* AMD_CG_SUPPORT_GFX_MGCG */ 8138 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 8139 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 8140 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 8141 8142 /* AMD_CG_SUPPORT_GFX_CGCG */ 8143 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)); 8144 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 8145 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 8146 8147 /* AMD_CG_SUPPORT_GFX_CGLS */ 8148 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 8149 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 8150 8151 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 8152 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL)); 8153 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 8154 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 8155 8156 /* AMD_CG_SUPPORT_GFX_CP_LS */ 8157 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); 8158 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 8159 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 8160 8161 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 8162 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)); 8163 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 8164 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 8165 8166 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 8167 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 8168 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 8169 } 8170 8171 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 8172 { 8173 /* gfx10 is 32bit rptr*/ 8174 return *(uint32_t *)ring->rptr_cpu_addr; 8175 } 8176 8177 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 8178 { 8179 struct amdgpu_device *adev = ring->adev; 8180 u64 wptr; 8181 8182 /* XXX check if swapping is necessary on BE */ 8183 if (ring->use_doorbell) { 8184 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 8185 } else { 8186 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); 8187 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; 8188 } 8189 8190 return wptr; 8191 } 8192 8193 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 8194 { 8195 struct amdgpu_device *adev = ring->adev; 8196 uint32_t *wptr_saved; 8197 uint32_t *is_queue_unmap; 8198 uint64_t aggregated_db_index; 8199 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_GFX].mqd_size; 8200 uint64_t wptr_tmp; 8201 8202 if (ring->is_mes_queue) { 8203 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 8204 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 8205 sizeof(uint32_t)); 8206 aggregated_db_index = 8207 amdgpu_mes_get_aggregated_doorbell_index(adev, 8208 AMDGPU_MES_PRIORITY_LEVEL_NORMAL); 8209 8210 wptr_tmp = ring->wptr & ring->buf_mask; 8211 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp); 8212 *wptr_saved = wptr_tmp; 8213 /* assume doorbell always being used by mes mapped queue */ 8214 if (*is_queue_unmap) { 8215 WDOORBELL64(aggregated_db_index, wptr_tmp); 8216 WDOORBELL64(ring->doorbell_index, wptr_tmp); 8217 } else { 8218 WDOORBELL64(ring->doorbell_index, wptr_tmp); 8219 8220 if (*is_queue_unmap) 8221 WDOORBELL64(aggregated_db_index, wptr_tmp); 8222 } 8223 } else { 8224 if (ring->use_doorbell) { 8225 /* XXX check if swapping is necessary on BE */ 8226 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 8227 ring->wptr); 8228 WDOORBELL64(ring->doorbell_index, ring->wptr); 8229 } else { 8230 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, 8231 lower_32_bits(ring->wptr)); 8232 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, 8233 upper_32_bits(ring->wptr)); 8234 } 8235 } 8236 } 8237 8238 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 8239 { 8240 /* gfx10 hardware is 32bit rptr */ 8241 return *(uint32_t *)ring->rptr_cpu_addr; 8242 } 8243 8244 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 8245 { 8246 u64 wptr; 8247 8248 /* XXX check if swapping is necessary on BE */ 8249 if (ring->use_doorbell) 8250 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 8251 else 8252 BUG(); 8253 return wptr; 8254 } 8255 8256 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 8257 { 8258 struct amdgpu_device *adev = ring->adev; 8259 uint32_t *wptr_saved; 8260 uint32_t *is_queue_unmap; 8261 uint64_t aggregated_db_index; 8262 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size; 8263 uint64_t wptr_tmp; 8264 8265 if (ring->is_mes_queue) { 8266 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 8267 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 8268 sizeof(uint32_t)); 8269 aggregated_db_index = 8270 amdgpu_mes_get_aggregated_doorbell_index(adev, 8271 AMDGPU_MES_PRIORITY_LEVEL_NORMAL); 8272 8273 wptr_tmp = ring->wptr & ring->buf_mask; 8274 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp); 8275 *wptr_saved = wptr_tmp; 8276 /* assume doorbell always used by mes mapped queue */ 8277 if (*is_queue_unmap) { 8278 WDOORBELL64(aggregated_db_index, wptr_tmp); 8279 WDOORBELL64(ring->doorbell_index, wptr_tmp); 8280 } else { 8281 WDOORBELL64(ring->doorbell_index, wptr_tmp); 8282 8283 if (*is_queue_unmap) 8284 WDOORBELL64(aggregated_db_index, wptr_tmp); 8285 } 8286 } else { 8287 /* XXX check if swapping is necessary on BE */ 8288 if (ring->use_doorbell) { 8289 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 8290 ring->wptr); 8291 WDOORBELL64(ring->doorbell_index, ring->wptr); 8292 } else { 8293 BUG(); /* only DOORBELL method supported on gfx10 now */ 8294 } 8295 } 8296 } 8297 8298 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 8299 { 8300 struct amdgpu_device *adev = ring->adev; 8301 u32 ref_and_mask, reg_mem_engine; 8302 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 8303 8304 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 8305 switch (ring->me) { 8306 case 1: 8307 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 8308 break; 8309 case 2: 8310 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 8311 break; 8312 default: 8313 return; 8314 } 8315 reg_mem_engine = 0; 8316 } else { 8317 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 8318 reg_mem_engine = 1; /* pfp */ 8319 } 8320 8321 gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 8322 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 8323 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 8324 ref_and_mask, ref_and_mask, 0x20); 8325 } 8326 8327 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 8328 struct amdgpu_job *job, 8329 struct amdgpu_ib *ib, 8330 uint32_t flags) 8331 { 8332 unsigned int vmid = AMDGPU_JOB_GET_VMID(job); 8333 u32 header, control = 0; 8334 8335 if (ib->flags & AMDGPU_IB_FLAG_CE) 8336 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2); 8337 else 8338 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 8339 8340 control |= ib->length_dw | (vmid << 24); 8341 8342 if (ring->adev->gfx.mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 8343 control |= INDIRECT_BUFFER_PRE_ENB(1); 8344 8345 if (flags & AMDGPU_IB_PREEMPTED) 8346 control |= INDIRECT_BUFFER_PRE_RESUME(1); 8347 8348 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid) 8349 gfx_v10_0_ring_emit_de_meta(ring, 8350 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8351 } 8352 8353 if (ring->is_mes_queue) 8354 /* inherit vmid from mqd */ 8355 control |= 0x400000; 8356 8357 amdgpu_ring_write(ring, header); 8358 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 8359 amdgpu_ring_write(ring, 8360 #ifdef __BIG_ENDIAN 8361 (2 << 0) | 8362 #endif 8363 lower_32_bits(ib->gpu_addr)); 8364 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8365 amdgpu_ring_write(ring, control); 8366 } 8367 8368 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 8369 struct amdgpu_job *job, 8370 struct amdgpu_ib *ib, 8371 uint32_t flags) 8372 { 8373 unsigned int vmid = AMDGPU_JOB_GET_VMID(job); 8374 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 8375 8376 if (ring->is_mes_queue) 8377 /* inherit vmid from mqd */ 8378 control |= 0x40000000; 8379 8380 /* Currently, there is a high possibility to get wave ID mismatch 8381 * between ME and GDS, leading to a hw deadlock, because ME generates 8382 * different wave IDs than the GDS expects. This situation happens 8383 * randomly when at least 5 compute pipes use GDS ordered append. 8384 * The wave IDs generated by ME are also wrong after suspend/resume. 8385 * Those are probably bugs somewhere else in the kernel driver. 8386 * 8387 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 8388 * GDS to 0 for this ring (me/pipe). 8389 */ 8390 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 8391 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 8392 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID); 8393 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 8394 } 8395 8396 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 8397 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 8398 amdgpu_ring_write(ring, 8399 #ifdef __BIG_ENDIAN 8400 (2 << 0) | 8401 #endif 8402 lower_32_bits(ib->gpu_addr)); 8403 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8404 amdgpu_ring_write(ring, control); 8405 } 8406 8407 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 8408 u64 seq, unsigned int flags) 8409 { 8410 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 8411 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 8412 8413 /* RELEASE_MEM - flush caches, send int */ 8414 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 8415 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 8416 PACKET3_RELEASE_MEM_GCR_GL2_WB | 8417 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */ 8418 PACKET3_RELEASE_MEM_GCR_GLM_WB | 8419 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 8420 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 8421 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 8422 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 8423 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 8424 8425 /* 8426 * the address should be Qword aligned if 64bit write, Dword 8427 * aligned if only send 32bit data low (discard data high) 8428 */ 8429 if (write64bit) 8430 BUG_ON(addr & 0x7); 8431 else 8432 BUG_ON(addr & 0x3); 8433 amdgpu_ring_write(ring, lower_32_bits(addr)); 8434 amdgpu_ring_write(ring, upper_32_bits(addr)); 8435 amdgpu_ring_write(ring, lower_32_bits(seq)); 8436 amdgpu_ring_write(ring, upper_32_bits(seq)); 8437 amdgpu_ring_write(ring, ring->is_mes_queue ? 8438 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0); 8439 } 8440 8441 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 8442 { 8443 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 8444 uint32_t seq = ring->fence_drv.sync_seq; 8445 uint64_t addr = ring->fence_drv.gpu_addr; 8446 8447 gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 8448 upper_32_bits(addr), seq, 0xffffffff, 4); 8449 } 8450 8451 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 8452 uint16_t pasid, uint32_t flush_type, 8453 bool all_hub, uint8_t dst_sel) 8454 { 8455 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 8456 amdgpu_ring_write(ring, 8457 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 8458 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 8459 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 8460 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 8461 } 8462 8463 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 8464 unsigned int vmid, uint64_t pd_addr) 8465 { 8466 if (ring->is_mes_queue) 8467 gfx_v10_0_ring_invalidate_tlbs(ring, 0, 0, false, 0); 8468 else 8469 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 8470 8471 /* compute doesn't have PFP */ 8472 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 8473 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 8474 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 8475 amdgpu_ring_write(ring, 0x0); 8476 } 8477 } 8478 8479 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 8480 u64 seq, unsigned int flags) 8481 { 8482 struct amdgpu_device *adev = ring->adev; 8483 8484 /* we only allocate 32bit for each seq wb address */ 8485 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 8486 8487 /* write fence seq to the "addr" */ 8488 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8489 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8490 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 8491 amdgpu_ring_write(ring, lower_32_bits(addr)); 8492 amdgpu_ring_write(ring, upper_32_bits(addr)); 8493 amdgpu_ring_write(ring, lower_32_bits(seq)); 8494 8495 if (flags & AMDGPU_FENCE_FLAG_INT) { 8496 /* set register to trigger INT */ 8497 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8498 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8499 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 8500 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); 8501 amdgpu_ring_write(ring, 0); 8502 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 8503 } 8504 } 8505 8506 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring) 8507 { 8508 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 8509 amdgpu_ring_write(ring, 0); 8510 } 8511 8512 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 8513 uint32_t flags) 8514 { 8515 uint32_t dw2 = 0; 8516 8517 if (ring->adev->gfx.mcbp) 8518 gfx_v10_0_ring_emit_ce_meta(ring, 8519 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8520 8521 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 8522 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 8523 /* set load_global_config & load_global_uconfig */ 8524 dw2 |= 0x8001; 8525 /* set load_cs_sh_regs */ 8526 dw2 |= 0x01000000; 8527 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 8528 dw2 |= 0x10002; 8529 8530 /* set load_ce_ram if preamble presented */ 8531 if (AMDGPU_PREAMBLE_IB_PRESENT & flags) 8532 dw2 |= 0x10000000; 8533 } else { 8534 /* still load_ce_ram if this is the first time preamble presented 8535 * although there is no context switch happens. 8536 */ 8537 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) 8538 dw2 |= 0x10000000; 8539 } 8540 8541 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 8542 amdgpu_ring_write(ring, dw2); 8543 amdgpu_ring_write(ring, 0); 8544 } 8545 8546 static unsigned int gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) 8547 { 8548 unsigned int ret; 8549 8550 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 8551 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 8552 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 8553 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ 8554 ret = ring->wptr & ring->buf_mask; 8555 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ 8556 8557 return ret; 8558 } 8559 8560 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned int offset) 8561 { 8562 unsigned int cur; 8563 8564 BUG_ON(offset > ring->buf_mask); 8565 BUG_ON(ring->ring[offset] != 0x55aa55aa); 8566 8567 cur = (ring->wptr - 1) & ring->buf_mask; 8568 if (likely(cur > offset)) 8569 ring->ring[offset] = cur - offset; 8570 else 8571 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 8572 } 8573 8574 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring) 8575 { 8576 int i, r = 0; 8577 struct amdgpu_device *adev = ring->adev; 8578 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 8579 struct amdgpu_ring *kiq_ring = &kiq->ring; 8580 unsigned long flags; 8581 8582 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 8583 return -EINVAL; 8584 8585 spin_lock_irqsave(&kiq->ring_lock, flags); 8586 8587 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 8588 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8589 return -ENOMEM; 8590 } 8591 8592 /* assert preemption condition */ 8593 amdgpu_ring_set_preempt_cond_exec(ring, false); 8594 8595 /* assert IB preemption, emit the trailing fence */ 8596 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 8597 ring->trail_fence_gpu_addr, 8598 ++ring->trail_seq); 8599 amdgpu_ring_commit(kiq_ring); 8600 8601 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8602 8603 /* poll the trailing fence */ 8604 for (i = 0; i < adev->usec_timeout; i++) { 8605 if (ring->trail_seq == 8606 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 8607 break; 8608 udelay(1); 8609 } 8610 8611 if (i >= adev->usec_timeout) { 8612 r = -EINVAL; 8613 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 8614 } 8615 8616 /* deassert preemption condition */ 8617 amdgpu_ring_set_preempt_cond_exec(ring, true); 8618 return r; 8619 } 8620 8621 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume) 8622 { 8623 struct amdgpu_device *adev = ring->adev; 8624 struct v10_ce_ib_state ce_payload = {0}; 8625 uint64_t offset, ce_payload_gpu_addr; 8626 void *ce_payload_cpu_addr; 8627 int cnt; 8628 8629 cnt = (sizeof(ce_payload) >> 2) + 4 - 2; 8630 8631 if (ring->is_mes_queue) { 8632 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 8633 gfx[0].gfx_meta_data) + 8634 offsetof(struct v10_gfx_meta_data, ce_payload); 8635 ce_payload_gpu_addr = 8636 amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 8637 ce_payload_cpu_addr = 8638 amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 8639 } else { 8640 offset = offsetof(struct v10_gfx_meta_data, ce_payload); 8641 ce_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 8642 ce_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 8643 } 8644 8645 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8646 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | 8647 WRITE_DATA_DST_SEL(8) | 8648 WR_CONFIRM) | 8649 WRITE_DATA_CACHE_POLICY(0)); 8650 amdgpu_ring_write(ring, lower_32_bits(ce_payload_gpu_addr)); 8651 amdgpu_ring_write(ring, upper_32_bits(ce_payload_gpu_addr)); 8652 8653 if (resume) 8654 amdgpu_ring_write_multiple(ring, ce_payload_cpu_addr, 8655 sizeof(ce_payload) >> 2); 8656 else 8657 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, 8658 sizeof(ce_payload) >> 2); 8659 } 8660 8661 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 8662 { 8663 struct amdgpu_device *adev = ring->adev; 8664 struct v10_de_ib_state de_payload = {0}; 8665 uint64_t offset, gds_addr, de_payload_gpu_addr; 8666 void *de_payload_cpu_addr; 8667 int cnt; 8668 8669 if (ring->is_mes_queue) { 8670 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 8671 gfx[0].gfx_meta_data) + 8672 offsetof(struct v10_gfx_meta_data, de_payload); 8673 de_payload_gpu_addr = 8674 amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 8675 de_payload_cpu_addr = 8676 amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 8677 8678 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 8679 gfx[0].gds_backup) + 8680 offsetof(struct v10_gfx_meta_data, de_payload); 8681 gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 8682 } else { 8683 offset = offsetof(struct v10_gfx_meta_data, de_payload); 8684 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 8685 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 8686 8687 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) + 8688 AMDGPU_CSA_SIZE - adev->gds.gds_size, 8689 PAGE_SIZE); 8690 } 8691 8692 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 8693 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 8694 8695 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 8696 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8697 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 8698 WRITE_DATA_DST_SEL(8) | 8699 WR_CONFIRM) | 8700 WRITE_DATA_CACHE_POLICY(0)); 8701 amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr)); 8702 amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr)); 8703 8704 if (resume) 8705 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr, 8706 sizeof(de_payload) >> 2); 8707 else 8708 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 8709 sizeof(de_payload) >> 2); 8710 } 8711 8712 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 8713 bool secure) 8714 { 8715 uint32_t v = secure ? FRAME_TMZ : 0; 8716 8717 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 8718 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 8719 } 8720 8721 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 8722 uint32_t reg_val_offs) 8723 { 8724 struct amdgpu_device *adev = ring->adev; 8725 8726 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 8727 amdgpu_ring_write(ring, 0 | /* src: register*/ 8728 (5 << 8) | /* dst: memory */ 8729 (1 << 20)); /* write confirm */ 8730 amdgpu_ring_write(ring, reg); 8731 amdgpu_ring_write(ring, 0); 8732 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 8733 reg_val_offs * 4)); 8734 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 8735 reg_val_offs * 4)); 8736 } 8737 8738 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 8739 uint32_t val) 8740 { 8741 uint32_t cmd = 0; 8742 8743 switch (ring->funcs->type) { 8744 case AMDGPU_RING_TYPE_GFX: 8745 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 8746 break; 8747 case AMDGPU_RING_TYPE_KIQ: 8748 cmd = (1 << 16); /* no inc addr */ 8749 break; 8750 default: 8751 cmd = WR_CONFIRM; 8752 break; 8753 } 8754 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8755 amdgpu_ring_write(ring, cmd); 8756 amdgpu_ring_write(ring, reg); 8757 amdgpu_ring_write(ring, 0); 8758 amdgpu_ring_write(ring, val); 8759 } 8760 8761 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 8762 uint32_t val, uint32_t mask) 8763 { 8764 gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 8765 } 8766 8767 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 8768 uint32_t reg0, uint32_t reg1, 8769 uint32_t ref, uint32_t mask) 8770 { 8771 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 8772 struct amdgpu_device *adev = ring->adev; 8773 bool fw_version_ok = false; 8774 8775 fw_version_ok = adev->gfx.cp_fw_write_wait; 8776 8777 if (fw_version_ok) 8778 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 8779 ref, mask, 0x20); 8780 else 8781 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 8782 ref, mask); 8783 } 8784 8785 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring, 8786 unsigned int vmid) 8787 { 8788 struct amdgpu_device *adev = ring->adev; 8789 uint32_t value = 0; 8790 8791 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 8792 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 8793 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 8794 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 8795 WREG32_SOC15(GC, 0, mmSQ_CMD, value); 8796 } 8797 8798 static void 8799 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 8800 uint32_t me, uint32_t pipe, 8801 enum amdgpu_interrupt_state state) 8802 { 8803 uint32_t cp_int_cntl, cp_int_cntl_reg; 8804 8805 if (!me) { 8806 switch (pipe) { 8807 case 0: 8808 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0); 8809 break; 8810 case 1: 8811 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1); 8812 break; 8813 default: 8814 DRM_DEBUG("invalid pipe %d\n", pipe); 8815 return; 8816 } 8817 } else { 8818 DRM_DEBUG("invalid me %d\n", me); 8819 return; 8820 } 8821 8822 switch (state) { 8823 case AMDGPU_IRQ_STATE_DISABLE: 8824 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 8825 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 8826 TIME_STAMP_INT_ENABLE, 0); 8827 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 8828 break; 8829 case AMDGPU_IRQ_STATE_ENABLE: 8830 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 8831 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 8832 TIME_STAMP_INT_ENABLE, 1); 8833 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 8834 break; 8835 default: 8836 break; 8837 } 8838 } 8839 8840 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 8841 int me, int pipe, 8842 enum amdgpu_interrupt_state state) 8843 { 8844 u32 mec_int_cntl, mec_int_cntl_reg; 8845 8846 /* 8847 * amdgpu controls only the first MEC. That's why this function only 8848 * handles the setting of interrupts for this specific MEC. All other 8849 * pipes' interrupts are set by amdkfd. 8850 */ 8851 8852 if (me == 1) { 8853 switch (pipe) { 8854 case 0: 8855 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 8856 break; 8857 case 1: 8858 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 8859 break; 8860 case 2: 8861 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 8862 break; 8863 case 3: 8864 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 8865 break; 8866 default: 8867 DRM_DEBUG("invalid pipe %d\n", pipe); 8868 return; 8869 } 8870 } else { 8871 DRM_DEBUG("invalid me %d\n", me); 8872 return; 8873 } 8874 8875 switch (state) { 8876 case AMDGPU_IRQ_STATE_DISABLE: 8877 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 8878 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 8879 TIME_STAMP_INT_ENABLE, 0); 8880 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 8881 break; 8882 case AMDGPU_IRQ_STATE_ENABLE: 8883 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 8884 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 8885 TIME_STAMP_INT_ENABLE, 1); 8886 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 8887 break; 8888 default: 8889 break; 8890 } 8891 } 8892 8893 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev, 8894 struct amdgpu_irq_src *src, 8895 unsigned int type, 8896 enum amdgpu_interrupt_state state) 8897 { 8898 switch (type) { 8899 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 8900 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 8901 break; 8902 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 8903 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 8904 break; 8905 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 8906 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 8907 break; 8908 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 8909 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 8910 break; 8911 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 8912 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 8913 break; 8914 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 8915 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 8916 break; 8917 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 8918 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 8919 break; 8920 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 8921 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 8922 break; 8923 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 8924 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 8925 break; 8926 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 8927 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 8928 break; 8929 default: 8930 break; 8931 } 8932 return 0; 8933 } 8934 8935 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev, 8936 struct amdgpu_irq_src *source, 8937 struct amdgpu_iv_entry *entry) 8938 { 8939 int i; 8940 u8 me_id, pipe_id, queue_id; 8941 struct amdgpu_ring *ring; 8942 uint32_t mes_queue_id = entry->src_data[0]; 8943 8944 DRM_DEBUG("IH: CP EOP\n"); 8945 8946 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 8947 struct amdgpu_mes_queue *queue; 8948 8949 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 8950 8951 spin_lock(&adev->mes.queue_id_lock); 8952 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 8953 if (queue) { 8954 DRM_DEBUG("process mes queue id = %d\n", mes_queue_id); 8955 amdgpu_fence_process(queue->ring); 8956 } 8957 spin_unlock(&adev->mes.queue_id_lock); 8958 } else { 8959 me_id = (entry->ring_id & 0x0c) >> 2; 8960 pipe_id = (entry->ring_id & 0x03) >> 0; 8961 queue_id = (entry->ring_id & 0x70) >> 4; 8962 8963 switch (me_id) { 8964 case 0: 8965 if (pipe_id == 0) 8966 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 8967 else 8968 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 8969 break; 8970 case 1: 8971 case 2: 8972 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 8973 ring = &adev->gfx.compute_ring[i]; 8974 /* Per-queue interrupt is supported for MEC starting from VI. 8975 * The interrupt can only be enabled/disabled per pipe instead 8976 * of per queue. 8977 */ 8978 if ((ring->me == me_id) && 8979 (ring->pipe == pipe_id) && 8980 (ring->queue == queue_id)) 8981 amdgpu_fence_process(ring); 8982 } 8983 break; 8984 } 8985 } 8986 8987 return 0; 8988 } 8989 8990 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 8991 struct amdgpu_irq_src *source, 8992 unsigned int type, 8993 enum amdgpu_interrupt_state state) 8994 { 8995 switch (state) { 8996 case AMDGPU_IRQ_STATE_DISABLE: 8997 case AMDGPU_IRQ_STATE_ENABLE: 8998 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 8999 PRIV_REG_INT_ENABLE, 9000 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 9001 break; 9002 default: 9003 break; 9004 } 9005 9006 return 0; 9007 } 9008 9009 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 9010 struct amdgpu_irq_src *source, 9011 unsigned int type, 9012 enum amdgpu_interrupt_state state) 9013 { 9014 switch (state) { 9015 case AMDGPU_IRQ_STATE_DISABLE: 9016 case AMDGPU_IRQ_STATE_ENABLE: 9017 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 9018 PRIV_INSTR_INT_ENABLE, 9019 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 9020 break; 9021 default: 9022 break; 9023 } 9024 9025 return 0; 9026 } 9027 9028 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev, 9029 struct amdgpu_iv_entry *entry) 9030 { 9031 u8 me_id, pipe_id, queue_id; 9032 struct amdgpu_ring *ring; 9033 int i; 9034 9035 me_id = (entry->ring_id & 0x0c) >> 2; 9036 pipe_id = (entry->ring_id & 0x03) >> 0; 9037 queue_id = (entry->ring_id & 0x70) >> 4; 9038 9039 switch (me_id) { 9040 case 0: 9041 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 9042 ring = &adev->gfx.gfx_ring[i]; 9043 /* we only enabled 1 gfx queue per pipe for now */ 9044 if (ring->me == me_id && ring->pipe == pipe_id) 9045 drm_sched_fault(&ring->sched); 9046 } 9047 break; 9048 case 1: 9049 case 2: 9050 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 9051 ring = &adev->gfx.compute_ring[i]; 9052 if (ring->me == me_id && ring->pipe == pipe_id && 9053 ring->queue == queue_id) 9054 drm_sched_fault(&ring->sched); 9055 } 9056 break; 9057 default: 9058 BUG(); 9059 } 9060 } 9061 9062 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev, 9063 struct amdgpu_irq_src *source, 9064 struct amdgpu_iv_entry *entry) 9065 { 9066 DRM_ERROR("Illegal register access in command stream\n"); 9067 gfx_v10_0_handle_priv_fault(adev, entry); 9068 return 0; 9069 } 9070 9071 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev, 9072 struct amdgpu_irq_src *source, 9073 struct amdgpu_iv_entry *entry) 9074 { 9075 DRM_ERROR("Illegal instruction in command stream\n"); 9076 gfx_v10_0_handle_priv_fault(adev, entry); 9077 return 0; 9078 } 9079 9080 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 9081 struct amdgpu_irq_src *src, 9082 unsigned int type, 9083 enum amdgpu_interrupt_state state) 9084 { 9085 uint32_t tmp, target; 9086 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring); 9087 9088 if (ring->me == 1) 9089 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 9090 else 9091 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL); 9092 target += ring->pipe; 9093 9094 switch (type) { 9095 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 9096 if (state == AMDGPU_IRQ_STATE_DISABLE) { 9097 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 9098 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 9099 GENERIC2_INT_ENABLE, 0); 9100 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 9101 9102 tmp = RREG32_SOC15_IP(GC, target); 9103 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 9104 GENERIC2_INT_ENABLE, 0); 9105 WREG32_SOC15_IP(GC, target, tmp); 9106 } else { 9107 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 9108 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 9109 GENERIC2_INT_ENABLE, 1); 9110 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 9111 9112 tmp = RREG32_SOC15_IP(GC, target); 9113 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 9114 GENERIC2_INT_ENABLE, 1); 9115 WREG32_SOC15_IP(GC, target, tmp); 9116 } 9117 break; 9118 default: 9119 BUG(); /* kiq only support GENERIC2_INT now */ 9120 break; 9121 } 9122 return 0; 9123 } 9124 9125 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev, 9126 struct amdgpu_irq_src *source, 9127 struct amdgpu_iv_entry *entry) 9128 { 9129 u8 me_id, pipe_id, queue_id; 9130 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring); 9131 9132 me_id = (entry->ring_id & 0x0c) >> 2; 9133 pipe_id = (entry->ring_id & 0x03) >> 0; 9134 queue_id = (entry->ring_id & 0x70) >> 4; 9135 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n", 9136 me_id, pipe_id, queue_id); 9137 9138 amdgpu_fence_process(ring); 9139 return 0; 9140 } 9141 9142 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring) 9143 { 9144 const unsigned int gcr_cntl = 9145 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 9146 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 9147 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 9148 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 9149 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 9150 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 9151 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 9152 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 9153 9154 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 9155 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 9156 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 9157 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 9158 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 9159 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 9160 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 9161 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 9162 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 9163 } 9164 9165 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = { 9166 .name = "gfx_v10_0", 9167 .early_init = gfx_v10_0_early_init, 9168 .late_init = gfx_v10_0_late_init, 9169 .sw_init = gfx_v10_0_sw_init, 9170 .sw_fini = gfx_v10_0_sw_fini, 9171 .hw_init = gfx_v10_0_hw_init, 9172 .hw_fini = gfx_v10_0_hw_fini, 9173 .suspend = gfx_v10_0_suspend, 9174 .resume = gfx_v10_0_resume, 9175 .is_idle = gfx_v10_0_is_idle, 9176 .wait_for_idle = gfx_v10_0_wait_for_idle, 9177 .soft_reset = gfx_v10_0_soft_reset, 9178 .set_clockgating_state = gfx_v10_0_set_clockgating_state, 9179 .set_powergating_state = gfx_v10_0_set_powergating_state, 9180 .get_clockgating_state = gfx_v10_0_get_clockgating_state, 9181 }; 9182 9183 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = { 9184 .type = AMDGPU_RING_TYPE_GFX, 9185 .align_mask = 0xff, 9186 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9187 .support_64bit_ptrs = true, 9188 .secure_submission_supported = true, 9189 .get_rptr = gfx_v10_0_ring_get_rptr_gfx, 9190 .get_wptr = gfx_v10_0_ring_get_wptr_gfx, 9191 .set_wptr = gfx_v10_0_ring_set_wptr_gfx, 9192 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 9193 5 + /* COND_EXEC */ 9194 7 + /* PIPELINE_SYNC */ 9195 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9196 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9197 2 + /* VM_FLUSH */ 9198 8 + /* FENCE for VM_FLUSH */ 9199 20 + /* GDS switch */ 9200 4 + /* double SWITCH_BUFFER, 9201 * the first COND_EXEC jump to the place 9202 * just prior to this double SWITCH_BUFFER 9203 */ 9204 5 + /* COND_EXEC */ 9205 7 + /* HDP_flush */ 9206 4 + /* VGT_flush */ 9207 14 + /* CE_META */ 9208 31 + /* DE_META */ 9209 3 + /* CNTX_CTRL */ 9210 5 + /* HDP_INVL */ 9211 8 + 8 + /* FENCE x2 */ 9212 2 + /* SWITCH_BUFFER */ 9213 8, /* gfx_v10_0_emit_mem_sync */ 9214 .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */ 9215 .emit_ib = gfx_v10_0_ring_emit_ib_gfx, 9216 .emit_fence = gfx_v10_0_ring_emit_fence, 9217 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 9218 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 9219 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 9220 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 9221 .test_ring = gfx_v10_0_ring_test_ring, 9222 .test_ib = gfx_v10_0_ring_test_ib, 9223 .insert_nop = amdgpu_ring_insert_nop, 9224 .pad_ib = amdgpu_ring_generic_pad_ib, 9225 .emit_switch_buffer = gfx_v10_0_ring_emit_sb, 9226 .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl, 9227 .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec, 9228 .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec, 9229 .preempt_ib = gfx_v10_0_ring_preempt_ib, 9230 .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl, 9231 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9232 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9233 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9234 .soft_recovery = gfx_v10_0_ring_soft_recovery, 9235 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 9236 }; 9237 9238 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = { 9239 .type = AMDGPU_RING_TYPE_COMPUTE, 9240 .align_mask = 0xff, 9241 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9242 .support_64bit_ptrs = true, 9243 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 9244 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 9245 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 9246 .emit_frame_size = 9247 20 + /* gfx_v10_0_ring_emit_gds_switch */ 9248 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 9249 5 + /* hdp invalidate */ 9250 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 9251 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9252 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9253 2 + /* gfx_v10_0_ring_emit_vm_flush */ 9254 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */ 9255 8, /* gfx_v10_0_emit_mem_sync */ 9256 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 9257 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 9258 .emit_fence = gfx_v10_0_ring_emit_fence, 9259 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 9260 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 9261 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 9262 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 9263 .test_ring = gfx_v10_0_ring_test_ring, 9264 .test_ib = gfx_v10_0_ring_test_ib, 9265 .insert_nop = amdgpu_ring_insert_nop, 9266 .pad_ib = amdgpu_ring_generic_pad_ib, 9267 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9268 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9269 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9270 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 9271 }; 9272 9273 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = { 9274 .type = AMDGPU_RING_TYPE_KIQ, 9275 .align_mask = 0xff, 9276 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9277 .support_64bit_ptrs = true, 9278 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 9279 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 9280 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 9281 .emit_frame_size = 9282 20 + /* gfx_v10_0_ring_emit_gds_switch */ 9283 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 9284 5 + /*hdp invalidate */ 9285 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 9286 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9287 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9288 2 + /* gfx_v10_0_ring_emit_vm_flush */ 9289 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 9290 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 9291 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 9292 .emit_fence = gfx_v10_0_ring_emit_fence_kiq, 9293 .test_ring = gfx_v10_0_ring_test_ring, 9294 .test_ib = gfx_v10_0_ring_test_ib, 9295 .insert_nop = amdgpu_ring_insert_nop, 9296 .pad_ib = amdgpu_ring_generic_pad_ib, 9297 .emit_rreg = gfx_v10_0_ring_emit_rreg, 9298 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9299 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9300 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9301 }; 9302 9303 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev) 9304 { 9305 int i; 9306 9307 adev->gfx.kiq[0].ring.funcs = &gfx_v10_0_ring_funcs_kiq; 9308 9309 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 9310 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx; 9311 9312 for (i = 0; i < adev->gfx.num_compute_rings; i++) 9313 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute; 9314 } 9315 9316 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = { 9317 .set = gfx_v10_0_set_eop_interrupt_state, 9318 .process = gfx_v10_0_eop_irq, 9319 }; 9320 9321 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = { 9322 .set = gfx_v10_0_set_priv_reg_fault_state, 9323 .process = gfx_v10_0_priv_reg_irq, 9324 }; 9325 9326 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = { 9327 .set = gfx_v10_0_set_priv_inst_fault_state, 9328 .process = gfx_v10_0_priv_inst_irq, 9329 }; 9330 9331 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = { 9332 .set = gfx_v10_0_kiq_set_interrupt_state, 9333 .process = gfx_v10_0_kiq_irq, 9334 }; 9335 9336 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev) 9337 { 9338 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 9339 adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs; 9340 9341 adev->gfx.kiq[0].irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; 9342 adev->gfx.kiq[0].irq.funcs = &gfx_v10_0_kiq_irq_funcs; 9343 9344 adev->gfx.priv_reg_irq.num_types = 1; 9345 adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs; 9346 9347 adev->gfx.priv_inst_irq.num_types = 1; 9348 adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs; 9349 } 9350 9351 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev) 9352 { 9353 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 9354 case IP_VERSION(10, 1, 10): 9355 case IP_VERSION(10, 1, 1): 9356 case IP_VERSION(10, 1, 3): 9357 case IP_VERSION(10, 1, 4): 9358 case IP_VERSION(10, 3, 2): 9359 case IP_VERSION(10, 3, 1): 9360 case IP_VERSION(10, 3, 4): 9361 case IP_VERSION(10, 3, 5): 9362 case IP_VERSION(10, 3, 6): 9363 case IP_VERSION(10, 3, 3): 9364 case IP_VERSION(10, 3, 7): 9365 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs; 9366 break; 9367 case IP_VERSION(10, 1, 2): 9368 case IP_VERSION(10, 3, 0): 9369 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov; 9370 break; 9371 default: 9372 break; 9373 } 9374 } 9375 9376 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev) 9377 { 9378 unsigned int total_cu = adev->gfx.config.max_cu_per_sh * 9379 adev->gfx.config.max_sh_per_se * 9380 adev->gfx.config.max_shader_engines; 9381 9382 adev->gds.gds_size = 0x10000; 9383 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1; 9384 adev->gds.gws_size = 64; 9385 adev->gds.oa_size = 16; 9386 } 9387 9388 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev) 9389 { 9390 /* set gfx eng mqd */ 9391 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = 9392 sizeof(struct v10_gfx_mqd); 9393 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = 9394 gfx_v10_0_gfx_mqd_init; 9395 /* set compute eng mqd */ 9396 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 9397 sizeof(struct v10_compute_mqd); 9398 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 9399 gfx_v10_0_compute_mqd_init; 9400 } 9401 9402 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 9403 u32 bitmap) 9404 { 9405 u32 data; 9406 9407 if (!bitmap) 9408 return; 9409 9410 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9411 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9412 9413 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); 9414 } 9415 9416 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 9417 { 9418 u32 disabled_mask = 9419 ~amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 9420 u32 efuse_setting = 0; 9421 u32 vbios_setting = 0; 9422 9423 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); 9424 efuse_setting &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9425 efuse_setting >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9426 9427 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); 9428 vbios_setting &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9429 vbios_setting >>= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9430 9431 disabled_mask |= efuse_setting | vbios_setting; 9432 9433 return (~disabled_mask); 9434 } 9435 9436 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 9437 { 9438 u32 wgp_idx, wgp_active_bitmap; 9439 u32 cu_bitmap_per_wgp, cu_active_bitmap; 9440 9441 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 9442 cu_active_bitmap = 0; 9443 9444 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 9445 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 9446 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 9447 if (wgp_active_bitmap & (1 << wgp_idx)) 9448 cu_active_bitmap |= cu_bitmap_per_wgp; 9449 } 9450 9451 return cu_active_bitmap; 9452 } 9453 9454 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 9455 struct amdgpu_cu_info *cu_info) 9456 { 9457 int i, j, k, counter, active_cu_number = 0; 9458 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 9459 unsigned int disable_masks[4 * 2]; 9460 9461 if (!adev || !cu_info) 9462 return -EINVAL; 9463 9464 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 9465 9466 mutex_lock(&adev->grbm_idx_mutex); 9467 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 9468 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 9469 bitmap = i * adev->gfx.config.max_sh_per_se + j; 9470 if (((amdgpu_ip_version(adev, GC_HWIP, 0) == 9471 IP_VERSION(10, 3, 0)) || 9472 (amdgpu_ip_version(adev, GC_HWIP, 0) == 9473 IP_VERSION(10, 3, 3)) || 9474 (amdgpu_ip_version(adev, GC_HWIP, 0) == 9475 IP_VERSION(10, 3, 6)) || 9476 (amdgpu_ip_version(adev, GC_HWIP, 0) == 9477 IP_VERSION(10, 3, 7))) && 9478 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 9479 continue; 9480 mask = 1; 9481 ao_bitmap = 0; 9482 counter = 0; 9483 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0); 9484 if (i < 4 && j < 2) 9485 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh( 9486 adev, disable_masks[i * 2 + j]); 9487 bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev); 9488 cu_info->bitmap[0][i][j] = bitmap; 9489 9490 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 9491 if (bitmap & mask) { 9492 if (counter < adev->gfx.config.max_cu_per_sh) 9493 ao_bitmap |= mask; 9494 counter++; 9495 } 9496 mask <<= 1; 9497 } 9498 active_cu_number += counter; 9499 if (i < 2 && j < 2) 9500 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 9501 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 9502 } 9503 } 9504 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 9505 mutex_unlock(&adev->grbm_idx_mutex); 9506 9507 cu_info->number = active_cu_number; 9508 cu_info->ao_cu_mask = ao_cu_mask; 9509 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 9510 9511 return 0; 9512 } 9513 9514 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev) 9515 { 9516 uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask; 9517 9518 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE); 9519 efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK; 9520 efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 9521 9522 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE); 9523 vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK; 9524 vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 9525 9526 max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 9527 adev->gfx.config.max_shader_engines); 9528 disabled_sa = efuse_setting | vbios_setting; 9529 disabled_sa &= max_sa_mask; 9530 9531 return disabled_sa; 9532 } 9533 9534 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev) 9535 { 9536 uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines; 9537 uint32_t disabled_sa_mask, se_index, disabled_sa_per_se; 9538 9539 disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev); 9540 9541 max_sa_per_se = adev->gfx.config.max_sh_per_se; 9542 max_sa_per_se_mask = (1 << max_sa_per_se) - 1; 9543 max_shader_engines = adev->gfx.config.max_shader_engines; 9544 9545 for (se_index = 0; max_shader_engines > se_index; se_index++) { 9546 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se); 9547 disabled_sa_per_se &= max_sa_per_se_mask; 9548 if (disabled_sa_per_se == max_sa_per_se_mask) { 9549 WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1); 9550 break; 9551 } 9552 } 9553 } 9554 9555 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev) 9556 { 9557 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 9558 (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) | 9559 (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) | 9560 (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT)); 9561 9562 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL); 9563 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, 9564 (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) | 9565 (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) | 9566 (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) | 9567 (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT)); 9568 9569 WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid, 9570 (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) | 9571 (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) | 9572 (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT)); 9573 9574 WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL); 9575 9576 WREG32_SOC15(GC, 0, mmDIDT_IND_DATA, 9577 (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT)); 9578 } 9579 9580 const struct amdgpu_ip_block_version gfx_v10_0_ip_block = { 9581 .type = AMD_IP_BLOCK_TYPE_GFX, 9582 .major = 10, 9583 .minor = 0, 9584 .rev = 0, 9585 .funcs = &gfx_v10_0_ip_funcs, 9586 }; 9587