1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "gfxhub_v3_0_3.h" 26 27 #include "gc/gc_11_0_3_offset.h" 28 #include "gc/gc_11_0_3_sh_mask.h" 29 #include "navi10_enum.h" 30 #include "soc15_common.h" 31 32 #define regGCVM_L2_CNTL3_DEFAULT 0x80100007 33 #define regGCVM_L2_CNTL4_DEFAULT 0x000000c1 34 #define regGCVM_L2_CNTL5_DEFAULT 0x00003fe0 35 36 static const char *gfxhub_client_ids[] = { 37 "CB/DB", 38 "Reserved", 39 "GE1", 40 "GE2", 41 "CPF", 42 "CPC", 43 "CPG", 44 "RLC", 45 "TCP", 46 "SQC (inst)", 47 "SQC (data)", 48 "SQG", 49 "Reserved", 50 "SDMA0", 51 "SDMA1", 52 "GCR", 53 "SDMA2", 54 "SDMA3", 55 }; 56 57 static uint32_t gfxhub_v3_0_3_get_invalidate_req(unsigned int vmid, 58 uint32_t flush_type) 59 { 60 u32 req = 0; 61 62 /* invalidate using legacy mode on vmid*/ 63 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, 64 PER_VMID_INVALIDATE_REQ, 1 << vmid); 65 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 66 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 67 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 68 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 69 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 70 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 71 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, 72 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 73 74 return req; 75 } 76 77 static void 78 gfxhub_v3_0_3_print_l2_protection_fault_status(struct amdgpu_device *adev, 79 uint32_t status) 80 { 81 u32 cid = REG_GET_FIELD(status, 82 GCVM_L2_PROTECTION_FAULT_STATUS, CID); 83 84 dev_err(adev->dev, 85 "GCVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 86 status); 87 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 88 cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" : gfxhub_client_ids[cid], 89 cid); 90 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 91 REG_GET_FIELD(status, 92 GCVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 93 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 94 REG_GET_FIELD(status, 95 GCVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 96 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 97 REG_GET_FIELD(status, 98 GCVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 99 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 100 REG_GET_FIELD(status, 101 GCVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 102 dev_err(adev->dev, "\t RW: 0x%lx\n", 103 REG_GET_FIELD(status, 104 GCVM_L2_PROTECTION_FAULT_STATUS, RW)); 105 } 106 107 static u64 gfxhub_v3_0_3_get_fb_location(struct amdgpu_device *adev) 108 { 109 u64 base = RREG32_SOC15(GC, 0, regGCMC_VM_FB_LOCATION_BASE); 110 111 base &= GCMC_VM_FB_LOCATION_BASE__FB_BASE_MASK; 112 base <<= 24; 113 114 return base; 115 } 116 117 static u64 gfxhub_v3_0_3_get_mc_fb_offset(struct amdgpu_device *adev) 118 { 119 return (u64)RREG32_SOC15(GC, 0, regGCMC_VM_FB_OFFSET) << 24; 120 } 121 122 static void gfxhub_v3_0_3_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid, 123 uint64_t page_table_base) 124 { 125 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 126 127 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 128 hub->ctx_addr_distance * vmid, 129 lower_32_bits(page_table_base)); 130 131 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 132 hub->ctx_addr_distance * vmid, 133 upper_32_bits(page_table_base)); 134 } 135 136 static void gfxhub_v3_0_3_init_gart_aperture_regs(struct amdgpu_device *adev) 137 { 138 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 139 140 gfxhub_v3_0_3_setup_vm_pt_regs(adev, 0, pt_base); 141 142 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 143 (u32)(adev->gmc.gart_start >> 12)); 144 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 145 (u32)(adev->gmc.gart_start >> 44)); 146 147 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 148 (u32)(adev->gmc.gart_end >> 12)); 149 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 150 (u32)(adev->gmc.gart_end >> 44)); 151 } 152 153 static void gfxhub_v3_0_3_init_system_aperture_regs(struct amdgpu_device *adev) 154 { 155 uint64_t value; 156 157 /* Disable AGP. */ 158 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BASE, 0); 159 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_TOP, 0); 160 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, 0x00FFFFFF); 161 162 /* Program the system aperture low logical page number. */ 163 WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR, 164 adev->gmc.vram_start >> 18); 165 WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 166 adev->gmc.vram_end >> 18); 167 168 /* Set default page address. */ 169 value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start 170 + adev->vm_manager.vram_base_offset; 171 WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 172 (u32)(value >> 12)); 173 WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 174 (u32)(value >> 44)); 175 176 /* Program "protection fault". */ 177 WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 178 (u32)(adev->dummy_page_addr >> 12)); 179 WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 180 (u32)((u64)adev->dummy_page_addr >> 44)); 181 182 WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2, 183 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 184 } 185 186 187 static void gfxhub_v3_0_3_init_tlb_regs(struct amdgpu_device *adev) 188 { 189 uint32_t tmp; 190 191 /* Setup TLB control */ 192 tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL); 193 194 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 195 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 196 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 197 ENABLE_ADVANCED_DRIVER_MODEL, 1); 198 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 199 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 200 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); 201 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 202 MTYPE, MTYPE_UC); /* UC, uncached */ 203 204 WREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, tmp); 205 } 206 207 static void gfxhub_v3_0_3_init_cache_regs(struct amdgpu_device *adev) 208 { 209 uint32_t tmp; 210 211 /* These registers are not accessible to VF-SRIOV. 212 * The PF will program them instead. 213 */ 214 if (amdgpu_sriov_vf(adev)) 215 return; 216 217 /* Setup L2 cache */ 218 tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL); 219 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1); 220 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); 221 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, 222 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 223 /* XXX for emulation, Refer to closed source code.*/ 224 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, 225 L2_PDE0_CACHE_TAG_GENERATION_MODE, 0); 226 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); 227 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 228 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); 229 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL, tmp); 230 231 tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL2); 232 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 233 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 234 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL2, tmp); 235 236 tmp = regGCVM_L2_CNTL3_DEFAULT; 237 if (adev->gmc.translate_further) { 238 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12); 239 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, 240 L2_CACHE_BIGK_FRAGMENT_SIZE, 9); 241 } else { 242 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9); 243 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, 244 L2_CACHE_BIGK_FRAGMENT_SIZE, 6); 245 } 246 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, tmp); 247 248 tmp = regGCVM_L2_CNTL4_DEFAULT; 249 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); 250 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); 251 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL4, tmp); 252 253 tmp = regGCVM_L2_CNTL5_DEFAULT; 254 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0); 255 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL5, tmp); 256 } 257 258 static void gfxhub_v3_0_3_enable_system_domain(struct amdgpu_device *adev) 259 { 260 uint32_t tmp; 261 262 tmp = RREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL); 263 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 264 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 265 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, 266 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); 267 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL, tmp); 268 } 269 270 static void gfxhub_v3_0_3_disable_identity_aperture(struct amdgpu_device *adev) 271 { 272 /* These registers are not accessible to VF-SRIOV. 273 * The PF will program them instead. 274 */ 275 if (amdgpu_sriov_vf(adev)) 276 return; 277 278 WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 279 0xFFFFFFFF); 280 WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 281 0x0000000F); 282 283 WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 284 0); 285 WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 286 0); 287 288 WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0); 289 WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0); 290 291 } 292 293 static void gfxhub_v3_0_3_setup_vmid_config(struct amdgpu_device *adev) 294 { 295 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 296 int i; 297 uint32_t tmp; 298 299 for (i = 0; i <= 14; i++) { 300 tmp = RREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL, i); 301 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 302 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 303 adev->vm_manager.num_level); 304 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 305 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 306 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 307 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 308 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 309 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 310 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 311 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 312 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 313 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 314 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 315 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 316 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 317 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 318 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 319 PAGE_TABLE_BLOCK_SIZE, 320 adev->vm_manager.block_size - 9); 321 /* Send no-retry XNACK on fault to suppress VM fault storm. */ 322 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 323 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 324 !amdgpu_noretry); 325 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL, 326 i * hub->ctx_distance, tmp); 327 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, 328 i * hub->ctx_addr_distance, 0); 329 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, 330 i * hub->ctx_addr_distance, 0); 331 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, 332 i * hub->ctx_addr_distance, 333 lower_32_bits(adev->vm_manager.max_pfn - 1)); 334 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, 335 i * hub->ctx_addr_distance, 336 upper_32_bits(adev->vm_manager.max_pfn - 1)); 337 } 338 339 hub->vm_cntx_cntl = tmp; 340 } 341 342 static void gfxhub_v3_0_3_program_invalidation(struct amdgpu_device *adev) 343 { 344 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 345 unsigned i; 346 347 for (i = 0 ; i < 18; ++i) { 348 WREG32_SOC15_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 349 i * hub->eng_addr_distance, 0xffffffff); 350 WREG32_SOC15_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 351 i * hub->eng_addr_distance, 0x1f); 352 } 353 } 354 355 static int gfxhub_v3_0_3_gart_enable(struct amdgpu_device *adev) 356 { 357 if (amdgpu_sriov_vf(adev)) { 358 /* 359 * GCMC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are 360 * VF copy registers so vbios post doesn't program them, for 361 * SRIOV driver need to program them 362 */ 363 WREG32_SOC15(GC, 0, regGCMC_VM_FB_LOCATION_BASE, 364 adev->gmc.vram_start >> 24); 365 WREG32_SOC15(GC, 0, regGCMC_VM_FB_LOCATION_TOP, 366 adev->gmc.vram_end >> 24); 367 } 368 369 /* GART Enable. */ 370 gfxhub_v3_0_3_init_gart_aperture_regs(adev); 371 gfxhub_v3_0_3_init_system_aperture_regs(adev); 372 gfxhub_v3_0_3_init_tlb_regs(adev); 373 gfxhub_v3_0_3_init_cache_regs(adev); 374 375 gfxhub_v3_0_3_enable_system_domain(adev); 376 gfxhub_v3_0_3_disable_identity_aperture(adev); 377 gfxhub_v3_0_3_setup_vmid_config(adev); 378 gfxhub_v3_0_3_program_invalidation(adev); 379 380 return 0; 381 } 382 383 static void gfxhub_v3_0_3_gart_disable(struct amdgpu_device *adev) 384 { 385 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 386 u32 tmp; 387 u32 i; 388 389 /* Disable all tables */ 390 for (i = 0; i < 16; i++) 391 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_CNTL, 392 i * hub->ctx_distance, 0); 393 394 /* Setup TLB control */ 395 tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL); 396 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 397 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 398 ENABLE_ADVANCED_DRIVER_MODEL, 0); 399 WREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, tmp); 400 401 /* Setup L2 cache */ 402 WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); 403 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, 0); 404 } 405 406 /** 407 * gfxhub_v3_0_3_set_fault_enable_default - update GART/VM fault handling 408 * 409 * @adev: amdgpu_device pointer 410 * @value: true redirects VM faults to the default page 411 */ 412 static void gfxhub_v3_0_3_set_fault_enable_default(struct amdgpu_device *adev, 413 bool value) 414 { 415 u32 tmp; 416 417 /* These registers are not accessible to VF-SRIOV. 418 * The PF will program them instead. 419 */ 420 if (amdgpu_sriov_vf(adev)) 421 return; 422 423 tmp = RREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL); 424 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 425 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 426 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 427 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 428 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 429 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); 430 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 431 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); 432 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 433 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 434 value); 435 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 436 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); 437 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 438 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 439 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 440 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 441 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 442 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 443 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 444 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 445 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 446 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 447 if (!value) { 448 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 449 CRASH_ON_NO_RETRY_FAULT, 1); 450 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 451 CRASH_ON_RETRY_FAULT, 1); 452 } 453 WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL, tmp); 454 } 455 456 static const struct amdgpu_vmhub_funcs gfxhub_v3_0_3_vmhub_funcs = { 457 .print_l2_protection_fault_status = gfxhub_v3_0_3_print_l2_protection_fault_status, 458 .get_invalidate_req = gfxhub_v3_0_3_get_invalidate_req, 459 }; 460 461 static void gfxhub_v3_0_3_init(struct amdgpu_device *adev) 462 { 463 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 464 465 hub->ctx0_ptb_addr_lo32 = 466 SOC15_REG_OFFSET(GC, 0, 467 regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); 468 hub->ctx0_ptb_addr_hi32 = 469 SOC15_REG_OFFSET(GC, 0, 470 regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); 471 hub->vm_inv_eng0_sem = 472 SOC15_REG_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_SEM); 473 hub->vm_inv_eng0_req = 474 SOC15_REG_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_REQ); 475 hub->vm_inv_eng0_ack = 476 SOC15_REG_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_ACK); 477 hub->vm_context0_cntl = 478 SOC15_REG_OFFSET(GC, 0, regGCVM_CONTEXT0_CNTL); 479 hub->vm_l2_pro_fault_status = 480 SOC15_REG_OFFSET(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS); 481 hub->vm_l2_pro_fault_cntl = 482 SOC15_REG_OFFSET(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL); 483 484 hub->ctx_distance = regGCVM_CONTEXT1_CNTL - regGCVM_CONTEXT0_CNTL; 485 hub->ctx_addr_distance = regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 - 486 regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 487 hub->eng_distance = regGCVM_INVALIDATE_ENG1_REQ - 488 regGCVM_INVALIDATE_ENG0_REQ; 489 hub->eng_addr_distance = regGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 - 490 regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32; 491 492 hub->vm_cntx_cntl_vm_fault = GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 493 GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 494 GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 495 GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 496 GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 497 GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 498 GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 499 500 hub->vmhub_funcs = &gfxhub_v3_0_3_vmhub_funcs; 501 } 502 503 const struct amdgpu_gfxhub_funcs gfxhub_v3_0_3_funcs = { 504 .get_fb_location = gfxhub_v3_0_3_get_fb_location, 505 .get_mc_fb_offset = gfxhub_v3_0_3_get_mc_fb_offset, 506 .setup_vm_pt_regs = gfxhub_v3_0_3_setup_vm_pt_regs, 507 .gart_enable = gfxhub_v3_0_3_gart_enable, 508 .gart_disable = gfxhub_v3_0_3_gart_disable, 509 .set_fault_enable_default = gfxhub_v3_0_3_set_fault_enable_default, 510 .init = gfxhub_v3_0_3_init, 511 }; 512