1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/pci.h> 26 27 #include <drm/drm_cache.h> 28 29 #include "amdgpu.h" 30 #include "gmc_v9_0.h" 31 #include "amdgpu_atomfirmware.h" 32 #include "amdgpu_gem.h" 33 34 #include "hdp/hdp_4_0_offset.h" 35 #include "hdp/hdp_4_0_sh_mask.h" 36 #include "gc/gc_9_0_sh_mask.h" 37 #include "dce/dce_12_0_offset.h" 38 #include "dce/dce_12_0_sh_mask.h" 39 #include "vega10_enum.h" 40 #include "mmhub/mmhub_1_0_offset.h" 41 #include "athub/athub_1_0_offset.h" 42 #include "oss/osssys_4_0_offset.h" 43 44 #include "soc15.h" 45 #include "soc15_common.h" 46 #include "umc/umc_6_0_sh_mask.h" 47 48 #include "gfxhub_v1_0.h" 49 #include "mmhub_v1_0.h" 50 #include "athub_v1_0.h" 51 #include "gfxhub_v1_1.h" 52 #include "mmhub_v9_4.h" 53 #include "umc_v6_1.h" 54 55 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 56 57 #include "amdgpu_ras.h" 58 59 /* add these here since we already include dce12 headers and these are for DCN */ 60 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d 61 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 62 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 63 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 64 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL 65 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L 66 67 /* XXX Move this macro to VEGA10 header file, which is like vid.h for VI.*/ 68 #define AMDGPU_NUM_OF_VMIDS 8 69 70 static const u32 golden_settings_vega10_hdp[] = 71 { 72 0xf64, 0x0fffffff, 0x00000000, 73 0xf65, 0x0fffffff, 0x00000000, 74 0xf66, 0x0fffffff, 0x00000000, 75 0xf67, 0x0fffffff, 0x00000000, 76 0xf68, 0x0fffffff, 0x00000000, 77 0xf6a, 0x0fffffff, 0x00000000, 78 0xf6b, 0x0fffffff, 0x00000000, 79 0xf6c, 0x0fffffff, 0x00000000, 80 0xf6d, 0x0fffffff, 0x00000000, 81 0xf6e, 0x0fffffff, 0x00000000, 82 }; 83 84 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] = 85 { 86 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa), 87 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565) 88 }; 89 90 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] = 91 { 92 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800), 93 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008) 94 }; 95 96 static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = { 97 (0x000143c0 + 0x00000000), 98 (0x000143c0 + 0x00000800), 99 (0x000143c0 + 0x00001000), 100 (0x000143c0 + 0x00001800), 101 (0x000543c0 + 0x00000000), 102 (0x000543c0 + 0x00000800), 103 (0x000543c0 + 0x00001000), 104 (0x000543c0 + 0x00001800), 105 (0x000943c0 + 0x00000000), 106 (0x000943c0 + 0x00000800), 107 (0x000943c0 + 0x00001000), 108 (0x000943c0 + 0x00001800), 109 (0x000d43c0 + 0x00000000), 110 (0x000d43c0 + 0x00000800), 111 (0x000d43c0 + 0x00001000), 112 (0x000d43c0 + 0x00001800), 113 (0x001143c0 + 0x00000000), 114 (0x001143c0 + 0x00000800), 115 (0x001143c0 + 0x00001000), 116 (0x001143c0 + 0x00001800), 117 (0x001543c0 + 0x00000000), 118 (0x001543c0 + 0x00000800), 119 (0x001543c0 + 0x00001000), 120 (0x001543c0 + 0x00001800), 121 (0x001943c0 + 0x00000000), 122 (0x001943c0 + 0x00000800), 123 (0x001943c0 + 0x00001000), 124 (0x001943c0 + 0x00001800), 125 (0x001d43c0 + 0x00000000), 126 (0x001d43c0 + 0x00000800), 127 (0x001d43c0 + 0x00001000), 128 (0x001d43c0 + 0x00001800), 129 }; 130 131 static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = { 132 (0x000143e0 + 0x00000000), 133 (0x000143e0 + 0x00000800), 134 (0x000143e0 + 0x00001000), 135 (0x000143e0 + 0x00001800), 136 (0x000543e0 + 0x00000000), 137 (0x000543e0 + 0x00000800), 138 (0x000543e0 + 0x00001000), 139 (0x000543e0 + 0x00001800), 140 (0x000943e0 + 0x00000000), 141 (0x000943e0 + 0x00000800), 142 (0x000943e0 + 0x00001000), 143 (0x000943e0 + 0x00001800), 144 (0x000d43e0 + 0x00000000), 145 (0x000d43e0 + 0x00000800), 146 (0x000d43e0 + 0x00001000), 147 (0x000d43e0 + 0x00001800), 148 (0x001143e0 + 0x00000000), 149 (0x001143e0 + 0x00000800), 150 (0x001143e0 + 0x00001000), 151 (0x001143e0 + 0x00001800), 152 (0x001543e0 + 0x00000000), 153 (0x001543e0 + 0x00000800), 154 (0x001543e0 + 0x00001000), 155 (0x001543e0 + 0x00001800), 156 (0x001943e0 + 0x00000000), 157 (0x001943e0 + 0x00000800), 158 (0x001943e0 + 0x00001000), 159 (0x001943e0 + 0x00001800), 160 (0x001d43e0 + 0x00000000), 161 (0x001d43e0 + 0x00000800), 162 (0x001d43e0 + 0x00001000), 163 (0x001d43e0 + 0x00001800), 164 }; 165 166 static const uint32_t ecc_umc_mcumc_status_addrs[] = { 167 (0x000143c2 + 0x00000000), 168 (0x000143c2 + 0x00000800), 169 (0x000143c2 + 0x00001000), 170 (0x000143c2 + 0x00001800), 171 (0x000543c2 + 0x00000000), 172 (0x000543c2 + 0x00000800), 173 (0x000543c2 + 0x00001000), 174 (0x000543c2 + 0x00001800), 175 (0x000943c2 + 0x00000000), 176 (0x000943c2 + 0x00000800), 177 (0x000943c2 + 0x00001000), 178 (0x000943c2 + 0x00001800), 179 (0x000d43c2 + 0x00000000), 180 (0x000d43c2 + 0x00000800), 181 (0x000d43c2 + 0x00001000), 182 (0x000d43c2 + 0x00001800), 183 (0x001143c2 + 0x00000000), 184 (0x001143c2 + 0x00000800), 185 (0x001143c2 + 0x00001000), 186 (0x001143c2 + 0x00001800), 187 (0x001543c2 + 0x00000000), 188 (0x001543c2 + 0x00000800), 189 (0x001543c2 + 0x00001000), 190 (0x001543c2 + 0x00001800), 191 (0x001943c2 + 0x00000000), 192 (0x001943c2 + 0x00000800), 193 (0x001943c2 + 0x00001000), 194 (0x001943c2 + 0x00001800), 195 (0x001d43c2 + 0x00000000), 196 (0x001d43c2 + 0x00000800), 197 (0x001d43c2 + 0x00001000), 198 (0x001d43c2 + 0x00001800), 199 }; 200 201 static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev, 202 struct amdgpu_irq_src *src, 203 unsigned type, 204 enum amdgpu_interrupt_state state) 205 { 206 u32 bits, i, tmp, reg; 207 208 bits = 0x7f; 209 210 switch (state) { 211 case AMDGPU_IRQ_STATE_DISABLE: 212 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 213 reg = ecc_umc_mcumc_ctrl_addrs[i]; 214 tmp = RREG32(reg); 215 tmp &= ~bits; 216 WREG32(reg, tmp); 217 } 218 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 219 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 220 tmp = RREG32(reg); 221 tmp &= ~bits; 222 WREG32(reg, tmp); 223 } 224 break; 225 case AMDGPU_IRQ_STATE_ENABLE: 226 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 227 reg = ecc_umc_mcumc_ctrl_addrs[i]; 228 tmp = RREG32(reg); 229 tmp |= bits; 230 WREG32(reg, tmp); 231 } 232 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 233 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 234 tmp = RREG32(reg); 235 tmp |= bits; 236 WREG32(reg, tmp); 237 } 238 break; 239 default: 240 break; 241 } 242 243 return 0; 244 } 245 246 static int gmc_v9_0_process_ras_data_cb(struct amdgpu_device *adev, 247 struct ras_err_data *err_data, 248 struct amdgpu_iv_entry *entry) 249 { 250 kgd2kfd_set_sram_ecc_flag(adev->kfd.dev); 251 if (adev->umc.funcs->query_ras_error_count) 252 adev->umc.funcs->query_ras_error_count(adev, err_data); 253 /* umc query_ras_error_address is also responsible for clearing 254 * error status 255 */ 256 if (adev->umc.funcs->query_ras_error_address) 257 adev->umc.funcs->query_ras_error_address(adev, err_data); 258 259 /* only uncorrectable error needs gpu reset */ 260 if (err_data->ue_count) 261 amdgpu_ras_reset_gpu(adev, 0); 262 263 return AMDGPU_RAS_SUCCESS; 264 } 265 266 static int gmc_v9_0_process_ecc_irq(struct amdgpu_device *adev, 267 struct amdgpu_irq_src *source, 268 struct amdgpu_iv_entry *entry) 269 { 270 struct ras_common_if *ras_if = adev->gmc.umc_ras_if; 271 struct ras_dispatch_if ih_data = { 272 .entry = entry, 273 }; 274 275 if (!ras_if) 276 return 0; 277 278 ih_data.head = *ras_if; 279 280 amdgpu_ras_interrupt_dispatch(adev, &ih_data); 281 return 0; 282 } 283 284 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 285 struct amdgpu_irq_src *src, 286 unsigned type, 287 enum amdgpu_interrupt_state state) 288 { 289 struct amdgpu_vmhub *hub; 290 u32 tmp, reg, bits, i, j; 291 292 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 293 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 294 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 295 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 296 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 297 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 298 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 299 300 switch (state) { 301 case AMDGPU_IRQ_STATE_DISABLE: 302 for (j = 0; j < adev->num_vmhubs; j++) { 303 hub = &adev->vmhub[j]; 304 for (i = 0; i < 16; i++) { 305 reg = hub->vm_context0_cntl + i; 306 tmp = RREG32(reg); 307 tmp &= ~bits; 308 WREG32(reg, tmp); 309 } 310 } 311 break; 312 case AMDGPU_IRQ_STATE_ENABLE: 313 for (j = 0; j < adev->num_vmhubs; j++) { 314 hub = &adev->vmhub[j]; 315 for (i = 0; i < 16; i++) { 316 reg = hub->vm_context0_cntl + i; 317 tmp = RREG32(reg); 318 tmp |= bits; 319 WREG32(reg, tmp); 320 } 321 } 322 default: 323 break; 324 } 325 326 return 0; 327 } 328 329 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, 330 struct amdgpu_irq_src *source, 331 struct amdgpu_iv_entry *entry) 332 { 333 struct amdgpu_vmhub *hub; 334 bool retry_fault = !!(entry->src_data[1] & 0x80); 335 uint32_t status = 0; 336 u64 addr; 337 char hub_name[10]; 338 339 addr = (u64)entry->src_data[0] << 12; 340 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 341 342 if (retry_fault && amdgpu_gmc_filter_faults(adev, addr, entry->pasid, 343 entry->timestamp)) 344 return 1; /* This also prevents sending it to KFD */ 345 346 if (entry->client_id == SOC15_IH_CLIENTID_VMC) { 347 snprintf(hub_name, sizeof(hub_name), "mmhub0"); 348 hub = &adev->vmhub[AMDGPU_MMHUB_0]; 349 } else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) { 350 snprintf(hub_name, sizeof(hub_name), "mmhub1"); 351 hub = &adev->vmhub[AMDGPU_MMHUB_1]; 352 } else { 353 snprintf(hub_name, sizeof(hub_name), "gfxhub0"); 354 hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 355 } 356 357 /* If it's the first fault for this address, process it normally */ 358 if (!amdgpu_sriov_vf(adev)) { 359 /* 360 * Issue a dummy read to wait for the status register to 361 * be updated to avoid reading an incorrect value due to 362 * the new fast GRBM interface. 363 */ 364 if (entry->vmid_src == AMDGPU_GFXHUB_0) 365 RREG32(hub->vm_l2_pro_fault_status); 366 367 status = RREG32(hub->vm_l2_pro_fault_status); 368 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 369 } 370 371 if (printk_ratelimit()) { 372 struct amdgpu_task_info task_info; 373 374 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 375 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 376 377 dev_err(adev->dev, 378 "[%s] %s page fault (src_id:%u ring:%u vmid:%u " 379 "pasid:%u, for process %s pid %d thread %s pid %d)\n", 380 hub_name, retry_fault ? "retry" : "no-retry", 381 entry->src_id, entry->ring_id, entry->vmid, 382 entry->pasid, task_info.process_name, task_info.tgid, 383 task_info.task_name, task_info.pid); 384 dev_err(adev->dev, " in page starting at address 0x%016llx from client %d\n", 385 addr, entry->client_id); 386 if (!amdgpu_sriov_vf(adev)) { 387 dev_err(adev->dev, 388 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 389 status); 390 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 391 REG_GET_FIELD(status, 392 VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 393 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 394 REG_GET_FIELD(status, 395 VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 396 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 397 REG_GET_FIELD(status, 398 VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 399 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 400 REG_GET_FIELD(status, 401 VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 402 dev_err(adev->dev, "\t RW: 0x%lx\n", 403 REG_GET_FIELD(status, 404 VM_L2_PROTECTION_FAULT_STATUS, RW)); 405 406 } 407 } 408 409 return 0; 410 } 411 412 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = { 413 .set = gmc_v9_0_vm_fault_interrupt_state, 414 .process = gmc_v9_0_process_interrupt, 415 }; 416 417 418 static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = { 419 .set = gmc_v9_0_ecc_interrupt_state, 420 .process = gmc_v9_0_process_ecc_irq, 421 }; 422 423 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev) 424 { 425 adev->gmc.vm_fault.num_types = 1; 426 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs; 427 428 adev->gmc.ecc_irq.num_types = 1; 429 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs; 430 } 431 432 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid, 433 uint32_t flush_type) 434 { 435 u32 req = 0; 436 437 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 438 PER_VMID_INVALIDATE_REQ, 1 << vmid); 439 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 440 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 441 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 442 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 443 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 444 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 445 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 446 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 447 448 return req; 449 } 450 451 /* 452 * GART 453 * VMID 0 is the physical GPU addresses as used by the kernel. 454 * VMIDs 1-15 are used for userspace clients and are handled 455 * by the amdgpu vm/hsa code. 456 */ 457 458 /** 459 * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type 460 * 461 * @adev: amdgpu_device pointer 462 * @vmid: vm instance to flush 463 * @flush_type: the flush type 464 * 465 * Flush the TLB for the requested page table using certain type. 466 */ 467 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 468 uint32_t vmhub, uint32_t flush_type) 469 { 470 const unsigned eng = 17; 471 u32 j, tmp; 472 struct amdgpu_vmhub *hub; 473 474 BUG_ON(vmhub >= adev->num_vmhubs); 475 476 hub = &adev->vmhub[vmhub]; 477 tmp = gmc_v9_0_get_invalidate_req(vmid, flush_type); 478 479 /* This is necessary for a HW workaround under SRIOV as well 480 * as GFXOFF under bare metal 481 */ 482 if (adev->gfx.kiq.ring.sched.ready && 483 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) && 484 !adev->in_gpu_reset) { 485 uint32_t req = hub->vm_inv_eng0_req + eng; 486 uint32_t ack = hub->vm_inv_eng0_ack + eng; 487 488 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, tmp, 489 1 << vmid); 490 return; 491 } 492 493 spin_lock(&adev->gmc.invalidate_lock); 494 WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp); 495 496 /* 497 * Issue a dummy read to wait for the ACK register to be cleared 498 * to avoid a false ACK due to the new fast GRBM interface. 499 */ 500 if (vmhub == AMDGPU_GFXHUB_0) 501 RREG32_NO_KIQ(hub->vm_inv_eng0_req + eng); 502 503 for (j = 0; j < adev->usec_timeout; j++) { 504 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng); 505 if (tmp & (1 << vmid)) 506 break; 507 udelay(1); 508 } 509 spin_unlock(&adev->gmc.invalidate_lock); 510 if (j < adev->usec_timeout) 511 return; 512 513 DRM_ERROR("Timeout waiting for VM flush ACK!\n"); 514 } 515 516 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 517 unsigned vmid, uint64_t pd_addr) 518 { 519 struct amdgpu_device *adev = ring->adev; 520 struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub]; 521 uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0); 522 unsigned eng = ring->vm_inv_eng; 523 524 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid), 525 lower_32_bits(pd_addr)); 526 527 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid), 528 upper_32_bits(pd_addr)); 529 530 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + eng, 531 hub->vm_inv_eng0_ack + eng, 532 req, 1 << vmid); 533 534 return pd_addr; 535 } 536 537 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 538 unsigned pasid) 539 { 540 struct amdgpu_device *adev = ring->adev; 541 uint32_t reg; 542 543 /* Do nothing because there's no lut register for mmhub1. */ 544 if (ring->funcs->vmhub == AMDGPU_MMHUB_1) 545 return; 546 547 if (ring->funcs->vmhub == AMDGPU_GFXHUB_0) 548 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; 549 else 550 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; 551 552 amdgpu_ring_emit_wreg(ring, reg, pasid); 553 } 554 555 /* 556 * PTE format on VEGA 10: 557 * 63:59 reserved 558 * 58:57 mtype 559 * 56 F 560 * 55 L 561 * 54 P 562 * 53 SW 563 * 52 T 564 * 50:48 reserved 565 * 47:12 4k physical page base address 566 * 11:7 fragment 567 * 6 write 568 * 5 read 569 * 4 exe 570 * 3 Z 571 * 2 snooped 572 * 1 system 573 * 0 valid 574 * 575 * PDE format on VEGA 10: 576 * 63:59 block fragment size 577 * 58:55 reserved 578 * 54 P 579 * 53:48 reserved 580 * 47:6 physical base address of PD or PTE 581 * 5:3 reserved 582 * 2 C 583 * 1 system 584 * 0 valid 585 */ 586 587 static uint64_t gmc_v9_0_get_vm_pte_flags(struct amdgpu_device *adev, 588 uint32_t flags) 589 590 { 591 uint64_t pte_flag = 0; 592 593 if (flags & AMDGPU_VM_PAGE_EXECUTABLE) 594 pte_flag |= AMDGPU_PTE_EXECUTABLE; 595 if (flags & AMDGPU_VM_PAGE_READABLE) 596 pte_flag |= AMDGPU_PTE_READABLE; 597 if (flags & AMDGPU_VM_PAGE_WRITEABLE) 598 pte_flag |= AMDGPU_PTE_WRITEABLE; 599 600 switch (flags & AMDGPU_VM_MTYPE_MASK) { 601 case AMDGPU_VM_MTYPE_DEFAULT: 602 pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 603 break; 604 case AMDGPU_VM_MTYPE_NC: 605 pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 606 break; 607 case AMDGPU_VM_MTYPE_WC: 608 pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_WC); 609 break; 610 case AMDGPU_VM_MTYPE_CC: 611 pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_CC); 612 break; 613 case AMDGPU_VM_MTYPE_UC: 614 pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_UC); 615 break; 616 default: 617 pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 618 break; 619 } 620 621 if (flags & AMDGPU_VM_PAGE_PRT) 622 pte_flag |= AMDGPU_PTE_PRT; 623 624 return pte_flag; 625 } 626 627 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level, 628 uint64_t *addr, uint64_t *flags) 629 { 630 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 631 *addr = adev->vm_manager.vram_base_offset + *addr - 632 adev->gmc.vram_start; 633 BUG_ON(*addr & 0xFFFF00000000003FULL); 634 635 if (!adev->gmc.translate_further) 636 return; 637 638 if (level == AMDGPU_VM_PDB1) { 639 /* Set the block fragment size */ 640 if (!(*flags & AMDGPU_PDE_PTE)) 641 *flags |= AMDGPU_PDE_BFS(0x9); 642 643 } else if (level == AMDGPU_VM_PDB0) { 644 if (*flags & AMDGPU_PDE_PTE) 645 *flags &= ~AMDGPU_PDE_PTE; 646 else 647 *flags |= AMDGPU_PTE_TF; 648 } 649 } 650 651 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = { 652 .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb, 653 .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb, 654 .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping, 655 .get_vm_pte_flags = gmc_v9_0_get_vm_pte_flags, 656 .get_vm_pde = gmc_v9_0_get_vm_pde 657 }; 658 659 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev) 660 { 661 adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs; 662 } 663 664 static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev) 665 { 666 switch (adev->asic_type) { 667 case CHIP_VEGA20: 668 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; 669 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; 670 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; 671 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET; 672 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; 673 adev->umc.funcs = &umc_v6_1_funcs; 674 break; 675 default: 676 break; 677 } 678 } 679 680 static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev) 681 { 682 switch (adev->asic_type) { 683 case CHIP_VEGA20: 684 adev->mmhub_funcs = &mmhub_v1_0_funcs; 685 break; 686 default: 687 break; 688 } 689 } 690 691 static int gmc_v9_0_early_init(void *handle) 692 { 693 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 694 695 gmc_v9_0_set_gmc_funcs(adev); 696 gmc_v9_0_set_irq_funcs(adev); 697 gmc_v9_0_set_umc_funcs(adev); 698 gmc_v9_0_set_mmhub_funcs(adev); 699 700 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 701 adev->gmc.shared_aperture_end = 702 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 703 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 704 adev->gmc.private_aperture_end = 705 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 706 707 return 0; 708 } 709 710 static bool gmc_v9_0_keep_stolen_memory(struct amdgpu_device *adev) 711 { 712 713 /* 714 * TODO: 715 * Currently there is a bug where some memory client outside 716 * of the driver writes to first 8M of VRAM on S3 resume, 717 * this overrides GART which by default gets placed in first 8M and 718 * causes VM_FAULTS once GTT is accessed. 719 * Keep the stolen memory reservation until the while this is not solved. 720 * Also check code in gmc_v9_0_get_vbios_fb_size and gmc_v9_0_late_init 721 */ 722 switch (adev->asic_type) { 723 case CHIP_VEGA10: 724 case CHIP_RAVEN: 725 case CHIP_ARCTURUS: 726 case CHIP_RENOIR: 727 return true; 728 case CHIP_VEGA12: 729 case CHIP_VEGA20: 730 default: 731 return false; 732 } 733 } 734 735 static int gmc_v9_0_allocate_vm_inv_eng(struct amdgpu_device *adev) 736 { 737 struct amdgpu_ring *ring; 738 unsigned vm_inv_engs[AMDGPU_MAX_VMHUBS] = 739 {GFXHUB_FREE_VM_INV_ENGS_BITMAP, MMHUB_FREE_VM_INV_ENGS_BITMAP, 740 GFXHUB_FREE_VM_INV_ENGS_BITMAP}; 741 unsigned i; 742 unsigned vmhub, inv_eng; 743 744 for (i = 0; i < adev->num_rings; ++i) { 745 ring = adev->rings[i]; 746 vmhub = ring->funcs->vmhub; 747 748 inv_eng = ffs(vm_inv_engs[vmhub]); 749 if (!inv_eng) { 750 dev_err(adev->dev, "no VM inv eng for ring %s\n", 751 ring->name); 752 return -EINVAL; 753 } 754 755 ring->vm_inv_eng = inv_eng - 1; 756 vm_inv_engs[vmhub] &= ~(1 << ring->vm_inv_eng); 757 758 dev_info(adev->dev, "ring %s uses VM inv eng %u on hub %u\n", 759 ring->name, ring->vm_inv_eng, ring->funcs->vmhub); 760 } 761 762 return 0; 763 } 764 765 static int gmc_v9_0_ecc_ras_block_late_init(void *handle, 766 struct ras_fs_if *fs_info, struct ras_common_if *ras_block) 767 { 768 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 769 struct ras_common_if **ras_if = NULL; 770 struct ras_ih_if ih_info = { 771 .cb = gmc_v9_0_process_ras_data_cb, 772 }; 773 int r; 774 775 if (ras_block->block == AMDGPU_RAS_BLOCK__UMC) 776 ras_if = &adev->gmc.umc_ras_if; 777 else if (ras_block->block == AMDGPU_RAS_BLOCK__MMHUB) 778 ras_if = &adev->gmc.mmhub_ras_if; 779 else 780 BUG(); 781 782 if (!amdgpu_ras_is_supported(adev, ras_block->block)) { 783 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0); 784 return 0; 785 } 786 787 /* handle resume path. */ 788 if (*ras_if) { 789 /* resend ras TA enable cmd during resume. 790 * prepare to handle failure. 791 */ 792 ih_info.head = **ras_if; 793 r = amdgpu_ras_feature_enable_on_boot(adev, *ras_if, 1); 794 if (r) { 795 if (r == -EAGAIN) { 796 /* request a gpu reset. will run again. */ 797 amdgpu_ras_request_reset_on_boot(adev, 798 ras_block->block); 799 return 0; 800 } 801 /* fail to enable ras, cleanup all. */ 802 goto irq; 803 } 804 /* enable successfully. continue. */ 805 goto resume; 806 } 807 808 *ras_if = kmalloc(sizeof(**ras_if), GFP_KERNEL); 809 if (!*ras_if) 810 return -ENOMEM; 811 812 **ras_if = *ras_block; 813 814 r = amdgpu_ras_feature_enable_on_boot(adev, *ras_if, 1); 815 if (r) { 816 if (r == -EAGAIN) { 817 amdgpu_ras_request_reset_on_boot(adev, 818 ras_block->block); 819 r = 0; 820 } 821 goto feature; 822 } 823 824 ih_info.head = **ras_if; 825 fs_info->head = **ras_if; 826 827 if (ras_block->block == AMDGPU_RAS_BLOCK__UMC) { 828 r = amdgpu_ras_interrupt_add_handler(adev, &ih_info); 829 if (r) 830 goto interrupt; 831 } 832 833 amdgpu_ras_debugfs_create(adev, fs_info); 834 835 r = amdgpu_ras_sysfs_create(adev, fs_info); 836 if (r) 837 goto sysfs; 838 resume: 839 if (ras_block->block == AMDGPU_RAS_BLOCK__UMC) { 840 r = amdgpu_irq_get(adev, &adev->gmc.ecc_irq, 0); 841 if (r) 842 goto irq; 843 } 844 845 return 0; 846 irq: 847 amdgpu_ras_sysfs_remove(adev, *ras_if); 848 sysfs: 849 amdgpu_ras_debugfs_remove(adev, *ras_if); 850 if (ras_block->block == AMDGPU_RAS_BLOCK__UMC) 851 amdgpu_ras_interrupt_remove_handler(adev, &ih_info); 852 interrupt: 853 amdgpu_ras_feature_enable(adev, *ras_if, 0); 854 feature: 855 kfree(*ras_if); 856 *ras_if = NULL; 857 return r; 858 } 859 860 static int gmc_v9_0_ecc_late_init(void *handle) 861 { 862 int r; 863 864 struct ras_fs_if umc_fs_info = { 865 .sysfs_name = "umc_err_count", 866 .debugfs_name = "umc_err_inject", 867 }; 868 struct ras_common_if umc_ras_block = { 869 .block = AMDGPU_RAS_BLOCK__UMC, 870 .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 871 .sub_block_index = 0, 872 .name = "umc", 873 }; 874 struct ras_fs_if mmhub_fs_info = { 875 .sysfs_name = "mmhub_err_count", 876 .debugfs_name = "mmhub_err_inject", 877 }; 878 struct ras_common_if mmhub_ras_block = { 879 .block = AMDGPU_RAS_BLOCK__MMHUB, 880 .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 881 .sub_block_index = 0, 882 .name = "mmhub", 883 }; 884 885 r = gmc_v9_0_ecc_ras_block_late_init(handle, 886 &umc_fs_info, &umc_ras_block); 887 if (r) 888 return r; 889 890 r = gmc_v9_0_ecc_ras_block_late_init(handle, 891 &mmhub_fs_info, &mmhub_ras_block); 892 return r; 893 } 894 895 static int gmc_v9_0_late_init(void *handle) 896 { 897 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 898 bool r; 899 900 if (!gmc_v9_0_keep_stolen_memory(adev)) 901 amdgpu_bo_late_init(adev); 902 903 r = gmc_v9_0_allocate_vm_inv_eng(adev); 904 if (r) 905 return r; 906 /* Check if ecc is available */ 907 if (!amdgpu_sriov_vf(adev)) { 908 switch (adev->asic_type) { 909 case CHIP_VEGA10: 910 case CHIP_VEGA20: 911 r = amdgpu_atomfirmware_mem_ecc_supported(adev); 912 if (!r) { 913 DRM_INFO("ECC is not present.\n"); 914 if (adev->df_funcs->enable_ecc_force_par_wr_rmw) 915 adev->df_funcs->enable_ecc_force_par_wr_rmw(adev, false); 916 } else { 917 DRM_INFO("ECC is active.\n"); 918 } 919 920 r = amdgpu_atomfirmware_sram_ecc_supported(adev); 921 if (!r) { 922 DRM_INFO("SRAM ECC is not present.\n"); 923 } else { 924 DRM_INFO("SRAM ECC is active.\n"); 925 } 926 break; 927 default: 928 break; 929 } 930 } 931 932 r = gmc_v9_0_ecc_late_init(handle); 933 if (r) 934 return r; 935 936 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 937 } 938 939 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, 940 struct amdgpu_gmc *mc) 941 { 942 u64 base = 0; 943 944 if (adev->asic_type == CHIP_ARCTURUS) 945 base = mmhub_v9_4_get_fb_location(adev); 946 else if (!amdgpu_sriov_vf(adev)) 947 base = mmhub_v1_0_get_fb_location(adev); 948 949 /* add the xgmi offset of the physical node */ 950 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 951 amdgpu_gmc_vram_location(adev, mc, base); 952 amdgpu_gmc_gart_location(adev, mc); 953 amdgpu_gmc_agp_location(adev, mc); 954 /* base offset of vram pages */ 955 adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev); 956 957 /* XXX: add the xgmi offset of the physical node? */ 958 adev->vm_manager.vram_base_offset += 959 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 960 } 961 962 /** 963 * gmc_v9_0_mc_init - initialize the memory controller driver params 964 * 965 * @adev: amdgpu_device pointer 966 * 967 * Look up the amount of vram, vram width, and decide how to place 968 * vram and gart within the GPU's physical address space. 969 * Returns 0 for success. 970 */ 971 static int gmc_v9_0_mc_init(struct amdgpu_device *adev) 972 { 973 int chansize, numchan; 974 int r; 975 976 if (amdgpu_sriov_vf(adev)) { 977 /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN, 978 * and DF related registers is not readable, seems hardcord is the 979 * only way to set the correct vram_width 980 */ 981 adev->gmc.vram_width = 2048; 982 } else if (amdgpu_emu_mode != 1) { 983 adev->gmc.vram_width = amdgpu_atomfirmware_get_vram_width(adev); 984 } 985 986 if (!adev->gmc.vram_width) { 987 /* hbm memory channel size */ 988 if (adev->flags & AMD_IS_APU) 989 chansize = 64; 990 else 991 chansize = 128; 992 993 numchan = adev->df_funcs->get_hbm_channel_number(adev); 994 adev->gmc.vram_width = numchan * chansize; 995 } 996 997 /* size in MB on si */ 998 adev->gmc.mc_vram_size = 999 adev->nbio_funcs->get_memsize(adev) * 1024ULL * 1024ULL; 1000 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 1001 1002 if (!(adev->flags & AMD_IS_APU)) { 1003 r = amdgpu_device_resize_fb_bar(adev); 1004 if (r) 1005 return r; 1006 } 1007 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 1008 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 1009 1010 #ifdef CONFIG_X86_64 1011 if (adev->flags & AMD_IS_APU) { 1012 adev->gmc.aper_base = gfxhub_v1_0_get_mc_fb_offset(adev); 1013 adev->gmc.aper_size = adev->gmc.real_vram_size; 1014 } 1015 #endif 1016 /* In case the PCI BAR is larger than the actual amount of vram */ 1017 adev->gmc.visible_vram_size = adev->gmc.aper_size; 1018 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 1019 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 1020 1021 /* set the gart size */ 1022 if (amdgpu_gart_size == -1) { 1023 switch (adev->asic_type) { 1024 case CHIP_VEGA10: /* all engines support GPUVM */ 1025 case CHIP_VEGA12: /* all engines support GPUVM */ 1026 case CHIP_VEGA20: 1027 case CHIP_ARCTURUS: 1028 default: 1029 adev->gmc.gart_size = 512ULL << 20; 1030 break; 1031 case CHIP_RAVEN: /* DCE SG support */ 1032 case CHIP_RENOIR: 1033 adev->gmc.gart_size = 1024ULL << 20; 1034 break; 1035 } 1036 } else { 1037 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 1038 } 1039 1040 gmc_v9_0_vram_gtt_location(adev, &adev->gmc); 1041 1042 return 0; 1043 } 1044 1045 static int gmc_v9_0_gart_init(struct amdgpu_device *adev) 1046 { 1047 int r; 1048 1049 if (adev->gart.bo) { 1050 WARN(1, "VEGA10 PCIE GART already initialized\n"); 1051 return 0; 1052 } 1053 /* Initialize common gart structure */ 1054 r = amdgpu_gart_init(adev); 1055 if (r) 1056 return r; 1057 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 1058 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(MTYPE_UC) | 1059 AMDGPU_PTE_EXECUTABLE; 1060 return amdgpu_gart_table_vram_alloc(adev); 1061 } 1062 1063 static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev) 1064 { 1065 u32 d1vga_control; 1066 unsigned size; 1067 1068 /* 1069 * TODO Remove once GART corruption is resolved 1070 * Check related code in gmc_v9_0_sw_fini 1071 * */ 1072 if (gmc_v9_0_keep_stolen_memory(adev)) 1073 return 9 * 1024 * 1024; 1074 1075 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); 1076 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 1077 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */ 1078 } else { 1079 u32 viewport; 1080 1081 switch (adev->asic_type) { 1082 case CHIP_RAVEN: 1083 case CHIP_RENOIR: 1084 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 1085 size = (REG_GET_FIELD(viewport, 1086 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 1087 REG_GET_FIELD(viewport, 1088 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * 1089 4); 1090 break; 1091 case CHIP_VEGA10: 1092 case CHIP_VEGA12: 1093 case CHIP_VEGA20: 1094 default: 1095 viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE); 1096 size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 1097 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) * 1098 4); 1099 break; 1100 } 1101 } 1102 /* return 0 if the pre-OS buffer uses up most of vram */ 1103 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024)) 1104 return 0; 1105 1106 return size; 1107 } 1108 1109 static int gmc_v9_0_sw_init(void *handle) 1110 { 1111 int r; 1112 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1113 1114 gfxhub_v1_0_init(adev); 1115 if (adev->asic_type == CHIP_ARCTURUS) 1116 mmhub_v9_4_init(adev); 1117 else 1118 mmhub_v1_0_init(adev); 1119 1120 spin_lock_init(&adev->gmc.invalidate_lock); 1121 1122 adev->gmc.vram_type = amdgpu_atomfirmware_get_vram_type(adev); 1123 switch (adev->asic_type) { 1124 case CHIP_RAVEN: 1125 adev->num_vmhubs = 2; 1126 1127 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) { 1128 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1129 } else { 1130 /* vm_size is 128TB + 512GB for legacy 3-level page support */ 1131 amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48); 1132 adev->gmc.translate_further = 1133 adev->vm_manager.num_level > 1; 1134 } 1135 break; 1136 case CHIP_VEGA10: 1137 case CHIP_VEGA12: 1138 case CHIP_VEGA20: 1139 case CHIP_RENOIR: 1140 adev->num_vmhubs = 2; 1141 1142 1143 /* 1144 * To fulfill 4-level page support, 1145 * vm size is 256TB (48bit), maximum size of Vega10, 1146 * block size 512 (9bit) 1147 */ 1148 /* sriov restrict max_pfn below AMDGPU_GMC_HOLE */ 1149 if (amdgpu_sriov_vf(adev)) 1150 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 47); 1151 else 1152 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1153 break; 1154 case CHIP_ARCTURUS: 1155 adev->num_vmhubs = 3; 1156 1157 /* Keep the vm size same with Vega20 */ 1158 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1159 break; 1160 default: 1161 break; 1162 } 1163 1164 /* This interrupt is VMC page fault.*/ 1165 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT, 1166 &adev->gmc.vm_fault); 1167 if (r) 1168 return r; 1169 1170 if (adev->asic_type == CHIP_ARCTURUS) { 1171 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC1, VMC_1_0__SRCID__VM_FAULT, 1172 &adev->gmc.vm_fault); 1173 if (r) 1174 return r; 1175 } 1176 1177 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT, 1178 &adev->gmc.vm_fault); 1179 1180 if (r) 1181 return r; 1182 1183 /* interrupt sent to DF. */ 1184 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0, 1185 &adev->gmc.ecc_irq); 1186 if (r) 1187 return r; 1188 1189 /* Set the internal MC address mask 1190 * This is the max address of the GPU's 1191 * internal address space. 1192 */ 1193 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 1194 1195 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); 1196 if (r) { 1197 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); 1198 return r; 1199 } 1200 adev->need_swiotlb = drm_need_swiotlb(44); 1201 1202 if (adev->gmc.xgmi.supported) { 1203 r = gfxhub_v1_1_get_xgmi_info(adev); 1204 if (r) 1205 return r; 1206 } 1207 1208 r = gmc_v9_0_mc_init(adev); 1209 if (r) 1210 return r; 1211 1212 adev->gmc.stolen_size = gmc_v9_0_get_vbios_fb_size(adev); 1213 1214 /* Memory manager */ 1215 r = amdgpu_bo_init(adev); 1216 if (r) 1217 return r; 1218 1219 r = gmc_v9_0_gart_init(adev); 1220 if (r) 1221 return r; 1222 1223 /* 1224 * number of VMs 1225 * VMID 0 is reserved for System 1226 * amdgpu graphics/compute will use VMIDs 1-7 1227 * amdkfd will use VMIDs 8-15 1228 */ 1229 adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS; 1230 adev->vm_manager.id_mgr[AMDGPU_MMHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS; 1231 adev->vm_manager.id_mgr[AMDGPU_MMHUB_1].num_ids = AMDGPU_NUM_OF_VMIDS; 1232 1233 amdgpu_vm_manager_init(adev); 1234 1235 return 0; 1236 } 1237 1238 static int gmc_v9_0_sw_fini(void *handle) 1239 { 1240 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1241 void *stolen_vga_buf; 1242 1243 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC) && 1244 adev->gmc.umc_ras_if) { 1245 struct ras_common_if *ras_if = adev->gmc.umc_ras_if; 1246 struct ras_ih_if ih_info = { 1247 .head = *ras_if, 1248 }; 1249 1250 /* remove fs first */ 1251 amdgpu_ras_debugfs_remove(adev, ras_if); 1252 amdgpu_ras_sysfs_remove(adev, ras_if); 1253 /* remove the IH */ 1254 amdgpu_ras_interrupt_remove_handler(adev, &ih_info); 1255 amdgpu_ras_feature_enable(adev, ras_if, 0); 1256 kfree(ras_if); 1257 } 1258 1259 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB) && 1260 adev->gmc.mmhub_ras_if) { 1261 struct ras_common_if *ras_if = adev->gmc.mmhub_ras_if; 1262 1263 /* remove fs and disable ras feature */ 1264 amdgpu_ras_debugfs_remove(adev, ras_if); 1265 amdgpu_ras_sysfs_remove(adev, ras_if); 1266 amdgpu_ras_feature_enable(adev, ras_if, 0); 1267 kfree(ras_if); 1268 } 1269 1270 amdgpu_gem_force_release(adev); 1271 amdgpu_vm_manager_fini(adev); 1272 1273 if (gmc_v9_0_keep_stolen_memory(adev)) 1274 amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, &stolen_vga_buf); 1275 1276 amdgpu_gart_table_vram_free(adev); 1277 amdgpu_bo_fini(adev); 1278 amdgpu_gart_fini(adev); 1279 1280 return 0; 1281 } 1282 1283 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) 1284 { 1285 1286 switch (adev->asic_type) { 1287 case CHIP_VEGA10: 1288 if (amdgpu_sriov_vf(adev)) 1289 break; 1290 /* fall through */ 1291 case CHIP_VEGA20: 1292 soc15_program_register_sequence(adev, 1293 golden_settings_mmhub_1_0_0, 1294 ARRAY_SIZE(golden_settings_mmhub_1_0_0)); 1295 soc15_program_register_sequence(adev, 1296 golden_settings_athub_1_0_0, 1297 ARRAY_SIZE(golden_settings_athub_1_0_0)); 1298 break; 1299 case CHIP_VEGA12: 1300 break; 1301 case CHIP_RAVEN: 1302 /* TODO for renoir */ 1303 soc15_program_register_sequence(adev, 1304 golden_settings_athub_1_0_0, 1305 ARRAY_SIZE(golden_settings_athub_1_0_0)); 1306 break; 1307 default: 1308 break; 1309 } 1310 } 1311 1312 /** 1313 * gmc_v9_0_gart_enable - gart enable 1314 * 1315 * @adev: amdgpu_device pointer 1316 */ 1317 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) 1318 { 1319 int r, i; 1320 bool value; 1321 u32 tmp; 1322 1323 amdgpu_device_program_register_sequence(adev, 1324 golden_settings_vega10_hdp, 1325 ARRAY_SIZE(golden_settings_vega10_hdp)); 1326 1327 if (adev->gart.bo == NULL) { 1328 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 1329 return -EINVAL; 1330 } 1331 r = amdgpu_gart_table_vram_pin(adev); 1332 if (r) 1333 return r; 1334 1335 switch (adev->asic_type) { 1336 case CHIP_RAVEN: 1337 /* TODO for renoir */ 1338 mmhub_v1_0_update_power_gating(adev, true); 1339 break; 1340 default: 1341 break; 1342 } 1343 1344 r = gfxhub_v1_0_gart_enable(adev); 1345 if (r) 1346 return r; 1347 1348 if (adev->asic_type == CHIP_ARCTURUS) 1349 r = mmhub_v9_4_gart_enable(adev); 1350 else 1351 r = mmhub_v1_0_gart_enable(adev); 1352 if (r) 1353 return r; 1354 1355 WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1); 1356 1357 tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL); 1358 WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp); 1359 1360 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8)); 1361 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40)); 1362 1363 /* After HDP is initialized, flush HDP.*/ 1364 adev->nbio_funcs->hdp_flush(adev, NULL); 1365 1366 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 1367 value = false; 1368 else 1369 value = true; 1370 1371 gfxhub_v1_0_set_fault_enable_default(adev, value); 1372 if (adev->asic_type == CHIP_ARCTURUS) 1373 mmhub_v9_4_set_fault_enable_default(adev, value); 1374 else 1375 mmhub_v1_0_set_fault_enable_default(adev, value); 1376 1377 for (i = 0; i < adev->num_vmhubs; ++i) 1378 gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0); 1379 1380 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 1381 (unsigned)(adev->gmc.gart_size >> 20), 1382 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 1383 adev->gart.ready = true; 1384 return 0; 1385 } 1386 1387 static int gmc_v9_0_hw_init(void *handle) 1388 { 1389 int r; 1390 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1391 1392 /* The sequence of these two function calls matters.*/ 1393 gmc_v9_0_init_golden_registers(adev); 1394 1395 if (adev->mode_info.num_crtc) { 1396 /* Lockout access through VGA aperture*/ 1397 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 1398 1399 /* disable VGA render */ 1400 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 1401 } 1402 1403 r = gmc_v9_0_gart_enable(adev); 1404 1405 return r; 1406 } 1407 1408 /** 1409 * gmc_v9_0_gart_disable - gart disable 1410 * 1411 * @adev: amdgpu_device pointer 1412 * 1413 * This disables all VM page table. 1414 */ 1415 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev) 1416 { 1417 gfxhub_v1_0_gart_disable(adev); 1418 if (adev->asic_type == CHIP_ARCTURUS) 1419 mmhub_v9_4_gart_disable(adev); 1420 else 1421 mmhub_v1_0_gart_disable(adev); 1422 amdgpu_gart_table_vram_unpin(adev); 1423 } 1424 1425 static int gmc_v9_0_hw_fini(void *handle) 1426 { 1427 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1428 1429 if (amdgpu_sriov_vf(adev)) { 1430 /* full access mode, so don't touch any GMC register */ 1431 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 1432 return 0; 1433 } 1434 1435 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 1436 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1437 gmc_v9_0_gart_disable(adev); 1438 1439 return 0; 1440 } 1441 1442 static int gmc_v9_0_suspend(void *handle) 1443 { 1444 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1445 1446 return gmc_v9_0_hw_fini(adev); 1447 } 1448 1449 static int gmc_v9_0_resume(void *handle) 1450 { 1451 int r; 1452 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1453 1454 r = gmc_v9_0_hw_init(adev); 1455 if (r) 1456 return r; 1457 1458 amdgpu_vmid_reset_all(adev); 1459 1460 return 0; 1461 } 1462 1463 static bool gmc_v9_0_is_idle(void *handle) 1464 { 1465 /* MC is always ready in GMC v9.*/ 1466 return true; 1467 } 1468 1469 static int gmc_v9_0_wait_for_idle(void *handle) 1470 { 1471 /* There is no need to wait for MC idle in GMC v9.*/ 1472 return 0; 1473 } 1474 1475 static int gmc_v9_0_soft_reset(void *handle) 1476 { 1477 /* XXX for emulation.*/ 1478 return 0; 1479 } 1480 1481 static int gmc_v9_0_set_clockgating_state(void *handle, 1482 enum amd_clockgating_state state) 1483 { 1484 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1485 1486 if (adev->asic_type == CHIP_ARCTURUS) 1487 mmhub_v9_4_set_clockgating(adev, state); 1488 else 1489 mmhub_v1_0_set_clockgating(adev, state); 1490 1491 athub_v1_0_set_clockgating(adev, state); 1492 1493 return 0; 1494 } 1495 1496 static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags) 1497 { 1498 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1499 1500 if (adev->asic_type == CHIP_ARCTURUS) 1501 mmhub_v9_4_get_clockgating(adev, flags); 1502 else 1503 mmhub_v1_0_get_clockgating(adev, flags); 1504 1505 athub_v1_0_get_clockgating(adev, flags); 1506 } 1507 1508 static int gmc_v9_0_set_powergating_state(void *handle, 1509 enum amd_powergating_state state) 1510 { 1511 return 0; 1512 } 1513 1514 const struct amd_ip_funcs gmc_v9_0_ip_funcs = { 1515 .name = "gmc_v9_0", 1516 .early_init = gmc_v9_0_early_init, 1517 .late_init = gmc_v9_0_late_init, 1518 .sw_init = gmc_v9_0_sw_init, 1519 .sw_fini = gmc_v9_0_sw_fini, 1520 .hw_init = gmc_v9_0_hw_init, 1521 .hw_fini = gmc_v9_0_hw_fini, 1522 .suspend = gmc_v9_0_suspend, 1523 .resume = gmc_v9_0_resume, 1524 .is_idle = gmc_v9_0_is_idle, 1525 .wait_for_idle = gmc_v9_0_wait_for_idle, 1526 .soft_reset = gmc_v9_0_soft_reset, 1527 .set_clockgating_state = gmc_v9_0_set_clockgating_state, 1528 .set_powergating_state = gmc_v9_0_set_powergating_state, 1529 .get_clockgating_state = gmc_v9_0_get_clockgating_state, 1530 }; 1531 1532 const struct amdgpu_ip_block_version gmc_v9_0_ip_block = 1533 { 1534 .type = AMD_IP_BLOCK_TYPE_GMC, 1535 .major = 9, 1536 .minor = 0, 1537 .rev = 0, 1538 .funcs = &gmc_v9_0_ip_funcs, 1539 }; 1540