1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 33 #include "sdma0/sdma0_4_2_offset.h" 34 #include "sdma0/sdma0_4_2_sh_mask.h" 35 #include "sdma1/sdma1_4_2_offset.h" 36 #include "sdma1/sdma1_4_2_sh_mask.h" 37 #include "sdma2/sdma2_4_2_2_offset.h" 38 #include "sdma2/sdma2_4_2_2_sh_mask.h" 39 #include "sdma3/sdma3_4_2_2_offset.h" 40 #include "sdma3/sdma3_4_2_2_sh_mask.h" 41 #include "sdma4/sdma4_4_2_2_offset.h" 42 #include "sdma4/sdma4_4_2_2_sh_mask.h" 43 #include "sdma5/sdma5_4_2_2_offset.h" 44 #include "sdma5/sdma5_4_2_2_sh_mask.h" 45 #include "sdma6/sdma6_4_2_2_offset.h" 46 #include "sdma6/sdma6_4_2_2_sh_mask.h" 47 #include "sdma7/sdma7_4_2_2_offset.h" 48 #include "sdma7/sdma7_4_2_2_sh_mask.h" 49 #include "hdp/hdp_4_0_offset.h" 50 #include "sdma0/sdma0_4_1_default.h" 51 52 #include "soc15_common.h" 53 #include "soc15.h" 54 #include "vega10_sdma_pkt_open.h" 55 56 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h" 57 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h" 58 59 #include "amdgpu_ras.h" 60 61 MODULE_FIRMWARE("amdgpu/vega10_sdma.bin"); 62 MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin"); 63 MODULE_FIRMWARE("amdgpu/vega12_sdma.bin"); 64 MODULE_FIRMWARE("amdgpu/vega12_sdma1.bin"); 65 MODULE_FIRMWARE("amdgpu/vega20_sdma.bin"); 66 MODULE_FIRMWARE("amdgpu/vega20_sdma1.bin"); 67 MODULE_FIRMWARE("amdgpu/raven_sdma.bin"); 68 MODULE_FIRMWARE("amdgpu/picasso_sdma.bin"); 69 MODULE_FIRMWARE("amdgpu/raven2_sdma.bin"); 70 MODULE_FIRMWARE("amdgpu/arcturus_sdma.bin"); 71 MODULE_FIRMWARE("amdgpu/renoir_sdma.bin"); 72 73 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L 74 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L 75 76 #define WREG32_SDMA(instance, offset, value) \ 77 WREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)), value) 78 #define RREG32_SDMA(instance, offset) \ 79 RREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset))) 80 81 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev); 82 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev); 83 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev); 84 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev); 85 86 static const struct soc15_reg_golden golden_settings_sdma_4[] = { 87 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 88 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100), 89 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100), 90 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 91 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100), 92 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 93 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000), 94 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100), 95 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 96 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0100, 0x00000100), 97 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 98 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 99 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000), 100 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100), 101 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100), 102 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 103 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL, 0x800f0100, 0x00000100), 104 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 105 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_POWER_CNTL, 0x003ff000, 0x0003c000), 106 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL, 0x800f0100, 0x00000100), 107 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 108 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL, 0x800f0100, 0x00000100), 109 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 110 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0), 111 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xfc000000, 0x00000000) 112 }; 113 114 static const struct soc15_reg_golden golden_settings_sdma_vg10[] = { 115 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 116 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 117 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 118 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 119 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002) 120 }; 121 122 static const struct soc15_reg_golden golden_settings_sdma_vg12[] = { 123 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104001), 124 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001), 125 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 126 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104001), 127 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001) 128 }; 129 130 static const struct soc15_reg_golden golden_settings_sdma_4_1[] = { 131 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 132 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 133 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100), 134 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 135 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0xfc3fffff, 0x40000051), 136 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100), 137 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 138 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100), 139 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 140 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 141 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000) 142 }; 143 144 static const struct soc15_reg_golden golden_settings_sdma0_4_2_init[] = { 145 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 146 }; 147 148 static const struct soc15_reg_golden golden_settings_sdma0_4_2[] = 149 { 150 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 151 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 152 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 153 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 154 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 155 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 156 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 157 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 158 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RD_BURST_CNTL, 0x0000000f, 0x00000003), 159 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 160 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 161 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 162 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 163 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 164 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 165 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 166 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 167 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 168 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 169 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 170 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 171 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 172 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 173 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 174 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 175 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 176 }; 177 178 static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = { 179 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 180 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100), 181 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 182 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 183 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 184 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 185 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 186 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 187 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RD_BURST_CNTL, 0x0000000f, 0x00000003), 188 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 189 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 190 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 191 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 192 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 193 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 194 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 195 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 196 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 197 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 198 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 199 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 200 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 201 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 202 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 203 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 204 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0), 205 }; 206 207 static const struct soc15_reg_golden golden_settings_sdma_rv1[] = 208 { 209 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002), 210 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002) 211 }; 212 213 static const struct soc15_reg_golden golden_settings_sdma_rv2[] = 214 { 215 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00003001), 216 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00003001) 217 }; 218 219 static const struct soc15_reg_golden golden_settings_sdma_arct[] = 220 { 221 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 222 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 223 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 224 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 225 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 226 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 227 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 228 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 229 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 230 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 231 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 232 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 233 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 234 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 235 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 236 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 237 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 238 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 239 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 240 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 241 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 242 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 243 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 244 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002) 245 }; 246 247 static const struct soc15_reg_golden golden_settings_sdma_4_3[] = { 248 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 249 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 250 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002), 251 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002), 252 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 253 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003fff07, 0x40000051), 254 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 255 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 256 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 257 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000) 258 }; 259 260 static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev, 261 u32 instance, u32 offset) 262 { 263 switch (instance) { 264 case 0: 265 return (adev->reg_offset[SDMA0_HWIP][0][0] + offset); 266 case 1: 267 return (adev->reg_offset[SDMA1_HWIP][0][0] + offset); 268 case 2: 269 return (adev->reg_offset[SDMA2_HWIP][0][1] + offset); 270 case 3: 271 return (adev->reg_offset[SDMA3_HWIP][0][1] + offset); 272 case 4: 273 return (adev->reg_offset[SDMA4_HWIP][0][1] + offset); 274 case 5: 275 return (adev->reg_offset[SDMA5_HWIP][0][1] + offset); 276 case 6: 277 return (adev->reg_offset[SDMA6_HWIP][0][1] + offset); 278 case 7: 279 return (adev->reg_offset[SDMA7_HWIP][0][1] + offset); 280 default: 281 break; 282 } 283 return 0; 284 } 285 286 static unsigned sdma_v4_0_seq_to_irq_id(int seq_num) 287 { 288 switch (seq_num) { 289 case 0: 290 return SOC15_IH_CLIENTID_SDMA0; 291 case 1: 292 return SOC15_IH_CLIENTID_SDMA1; 293 case 2: 294 return SOC15_IH_CLIENTID_SDMA2; 295 case 3: 296 return SOC15_IH_CLIENTID_SDMA3; 297 case 4: 298 return SOC15_IH_CLIENTID_SDMA4; 299 case 5: 300 return SOC15_IH_CLIENTID_SDMA5; 301 case 6: 302 return SOC15_IH_CLIENTID_SDMA6; 303 case 7: 304 return SOC15_IH_CLIENTID_SDMA7; 305 default: 306 break; 307 } 308 return -EINVAL; 309 } 310 311 static int sdma_v4_0_irq_id_to_seq(unsigned client_id) 312 { 313 switch (client_id) { 314 case SOC15_IH_CLIENTID_SDMA0: 315 return 0; 316 case SOC15_IH_CLIENTID_SDMA1: 317 return 1; 318 case SOC15_IH_CLIENTID_SDMA2: 319 return 2; 320 case SOC15_IH_CLIENTID_SDMA3: 321 return 3; 322 case SOC15_IH_CLIENTID_SDMA4: 323 return 4; 324 case SOC15_IH_CLIENTID_SDMA5: 325 return 5; 326 case SOC15_IH_CLIENTID_SDMA6: 327 return 6; 328 case SOC15_IH_CLIENTID_SDMA7: 329 return 7; 330 default: 331 break; 332 } 333 return -EINVAL; 334 } 335 336 static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev) 337 { 338 switch (adev->asic_type) { 339 case CHIP_VEGA10: 340 soc15_program_register_sequence(adev, 341 golden_settings_sdma_4, 342 ARRAY_SIZE(golden_settings_sdma_4)); 343 soc15_program_register_sequence(adev, 344 golden_settings_sdma_vg10, 345 ARRAY_SIZE(golden_settings_sdma_vg10)); 346 break; 347 case CHIP_VEGA12: 348 soc15_program_register_sequence(adev, 349 golden_settings_sdma_4, 350 ARRAY_SIZE(golden_settings_sdma_4)); 351 soc15_program_register_sequence(adev, 352 golden_settings_sdma_vg12, 353 ARRAY_SIZE(golden_settings_sdma_vg12)); 354 break; 355 case CHIP_VEGA20: 356 soc15_program_register_sequence(adev, 357 golden_settings_sdma0_4_2_init, 358 ARRAY_SIZE(golden_settings_sdma0_4_2_init)); 359 soc15_program_register_sequence(adev, 360 golden_settings_sdma0_4_2, 361 ARRAY_SIZE(golden_settings_sdma0_4_2)); 362 soc15_program_register_sequence(adev, 363 golden_settings_sdma1_4_2, 364 ARRAY_SIZE(golden_settings_sdma1_4_2)); 365 break; 366 case CHIP_ARCTURUS: 367 soc15_program_register_sequence(adev, 368 golden_settings_sdma_arct, 369 ARRAY_SIZE(golden_settings_sdma_arct)); 370 break; 371 case CHIP_RAVEN: 372 soc15_program_register_sequence(adev, 373 golden_settings_sdma_4_1, 374 ARRAY_SIZE(golden_settings_sdma_4_1)); 375 if (adev->rev_id >= 8) 376 soc15_program_register_sequence(adev, 377 golden_settings_sdma_rv2, 378 ARRAY_SIZE(golden_settings_sdma_rv2)); 379 else 380 soc15_program_register_sequence(adev, 381 golden_settings_sdma_rv1, 382 ARRAY_SIZE(golden_settings_sdma_rv1)); 383 break; 384 case CHIP_RENOIR: 385 soc15_program_register_sequence(adev, 386 golden_settings_sdma_4_3, 387 ARRAY_SIZE(golden_settings_sdma_4_3)); 388 break; 389 default: 390 break; 391 } 392 } 393 394 static int sdma_v4_0_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst) 395 { 396 int err = 0; 397 const struct sdma_firmware_header_v1_0 *hdr; 398 399 err = amdgpu_ucode_validate(sdma_inst->fw); 400 if (err) 401 return err; 402 403 hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data; 404 sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version); 405 sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version); 406 407 if (sdma_inst->feature_version >= 20) 408 sdma_inst->burst_nop = true; 409 410 return 0; 411 } 412 413 static void sdma_v4_0_destroy_inst_ctx(struct amdgpu_device *adev) 414 { 415 int i; 416 417 for (i = 0; i < adev->sdma.num_instances; i++) { 418 if (adev->sdma.instance[i].fw != NULL) 419 release_firmware(adev->sdma.instance[i].fw); 420 421 /* arcturus shares the same FW memory across 422 all SDMA isntances */ 423 if (adev->asic_type == CHIP_ARCTURUS) 424 break; 425 } 426 427 memset((void*)adev->sdma.instance, 0, 428 sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES); 429 } 430 431 /** 432 * sdma_v4_0_init_microcode - load ucode images from disk 433 * 434 * @adev: amdgpu_device pointer 435 * 436 * Use the firmware interface to load the ucode images into 437 * the driver (not loaded into hw). 438 * Returns 0 on success, error on failure. 439 */ 440 441 // emulation only, won't work on real chip 442 // vega10 real chip need to use PSP to load firmware 443 static int sdma_v4_0_init_microcode(struct amdgpu_device *adev) 444 { 445 const char *chip_name; 446 char fw_name[30]; 447 int err = 0, i; 448 struct amdgpu_firmware_info *info = NULL; 449 const struct common_firmware_header *header = NULL; 450 451 DRM_DEBUG("\n"); 452 453 switch (adev->asic_type) { 454 case CHIP_VEGA10: 455 chip_name = "vega10"; 456 break; 457 case CHIP_VEGA12: 458 chip_name = "vega12"; 459 break; 460 case CHIP_VEGA20: 461 chip_name = "vega20"; 462 break; 463 case CHIP_RAVEN: 464 if (adev->rev_id >= 8) 465 chip_name = "raven2"; 466 else if (adev->pdev->device == 0x15d8) 467 chip_name = "picasso"; 468 else 469 chip_name = "raven"; 470 break; 471 case CHIP_ARCTURUS: 472 chip_name = "arcturus"; 473 break; 474 case CHIP_RENOIR: 475 chip_name = "renoir"; 476 break; 477 default: 478 BUG(); 479 } 480 481 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 482 483 err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev); 484 if (err) 485 goto out; 486 487 err = sdma_v4_0_init_inst_ctx(&adev->sdma.instance[0]); 488 if (err) 489 goto out; 490 491 for (i = 1; i < adev->sdma.num_instances; i++) { 492 if (adev->asic_type == CHIP_ARCTURUS) { 493 /* Acturus will leverage the same FW memory 494 for every SDMA instance */ 495 memcpy((void*)&adev->sdma.instance[i], 496 (void*)&adev->sdma.instance[0], 497 sizeof(struct amdgpu_sdma_instance)); 498 } 499 else { 500 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma%d.bin", chip_name, i); 501 502 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); 503 if (err) 504 goto out; 505 506 err = sdma_v4_0_init_inst_ctx(&adev->sdma.instance[i]); 507 if (err) 508 goto out; 509 } 510 } 511 512 DRM_DEBUG("psp_load == '%s'\n", 513 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false"); 514 515 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 516 for (i = 0; i < adev->sdma.num_instances; i++) { 517 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 518 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 519 info->fw = adev->sdma.instance[i].fw; 520 header = (const struct common_firmware_header *)info->fw->data; 521 adev->firmware.fw_size += 522 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 523 } 524 } 525 526 out: 527 if (err) { 528 DRM_ERROR("sdma_v4_0: Failed to load firmware \"%s\"\n", fw_name); 529 sdma_v4_0_destroy_inst_ctx(adev); 530 } 531 return err; 532 } 533 534 /** 535 * sdma_v4_0_ring_get_rptr - get the current read pointer 536 * 537 * @ring: amdgpu ring pointer 538 * 539 * Get the current rptr from the hardware (VEGA10+). 540 */ 541 static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring) 542 { 543 u64 *rptr; 544 545 /* XXX check if swapping is necessary on BE */ 546 rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]); 547 548 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 549 return ((*rptr) >> 2); 550 } 551 552 /** 553 * sdma_v4_0_ring_get_wptr - get the current write pointer 554 * 555 * @ring: amdgpu ring pointer 556 * 557 * Get the current wptr from the hardware (VEGA10+). 558 */ 559 static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring) 560 { 561 struct amdgpu_device *adev = ring->adev; 562 u64 wptr; 563 564 if (ring->use_doorbell) { 565 /* XXX check if swapping is necessary on BE */ 566 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 567 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 568 } else { 569 wptr = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI); 570 wptr = wptr << 32; 571 wptr |= RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR); 572 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", 573 ring->me, wptr); 574 } 575 576 return wptr >> 2; 577 } 578 579 /** 580 * sdma_v4_0_ring_set_wptr - commit the write pointer 581 * 582 * @ring: amdgpu ring pointer 583 * 584 * Write the wptr back to the hardware (VEGA10+). 585 */ 586 static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring) 587 { 588 struct amdgpu_device *adev = ring->adev; 589 590 DRM_DEBUG("Setting write pointer\n"); 591 if (ring->use_doorbell) { 592 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 593 594 DRM_DEBUG("Using doorbell -- " 595 "wptr_offs == 0x%08x " 596 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 597 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 598 ring->wptr_offs, 599 lower_32_bits(ring->wptr << 2), 600 upper_32_bits(ring->wptr << 2)); 601 /* XXX check if swapping is necessary on BE */ 602 WRITE_ONCE(*wb, (ring->wptr << 2)); 603 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 604 ring->doorbell_index, ring->wptr << 2); 605 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 606 } else { 607 DRM_DEBUG("Not using doorbell -- " 608 "mmSDMA%i_GFX_RB_WPTR == 0x%08x " 609 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 610 ring->me, 611 lower_32_bits(ring->wptr << 2), 612 ring->me, 613 upper_32_bits(ring->wptr << 2)); 614 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR, 615 lower_32_bits(ring->wptr << 2)); 616 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI, 617 upper_32_bits(ring->wptr << 2)); 618 } 619 } 620 621 /** 622 * sdma_v4_0_page_ring_get_wptr - get the current write pointer 623 * 624 * @ring: amdgpu ring pointer 625 * 626 * Get the current wptr from the hardware (VEGA10+). 627 */ 628 static uint64_t sdma_v4_0_page_ring_get_wptr(struct amdgpu_ring *ring) 629 { 630 struct amdgpu_device *adev = ring->adev; 631 u64 wptr; 632 633 if (ring->use_doorbell) { 634 /* XXX check if swapping is necessary on BE */ 635 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 636 } else { 637 wptr = RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI); 638 wptr = wptr << 32; 639 wptr |= RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR); 640 } 641 642 return wptr >> 2; 643 } 644 645 /** 646 * sdma_v4_0_ring_set_wptr - commit the write pointer 647 * 648 * @ring: amdgpu ring pointer 649 * 650 * Write the wptr back to the hardware (VEGA10+). 651 */ 652 static void sdma_v4_0_page_ring_set_wptr(struct amdgpu_ring *ring) 653 { 654 struct amdgpu_device *adev = ring->adev; 655 656 if (ring->use_doorbell) { 657 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 658 659 /* XXX check if swapping is necessary on BE */ 660 WRITE_ONCE(*wb, (ring->wptr << 2)); 661 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 662 } else { 663 uint64_t wptr = ring->wptr << 2; 664 665 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR, 666 lower_32_bits(wptr)); 667 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI, 668 upper_32_bits(wptr)); 669 } 670 } 671 672 static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 673 { 674 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 675 int i; 676 677 for (i = 0; i < count; i++) 678 if (sdma && sdma->burst_nop && (i == 0)) 679 amdgpu_ring_write(ring, ring->funcs->nop | 680 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 681 else 682 amdgpu_ring_write(ring, ring->funcs->nop); 683 } 684 685 /** 686 * sdma_v4_0_ring_emit_ib - Schedule an IB on the DMA engine 687 * 688 * @ring: amdgpu ring pointer 689 * @ib: IB object to schedule 690 * 691 * Schedule an IB in the DMA ring (VEGA10). 692 */ 693 static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring, 694 struct amdgpu_job *job, 695 struct amdgpu_ib *ib, 696 uint32_t flags) 697 { 698 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 699 700 /* IB packet must end on a 8 DW boundary */ 701 sdma_v4_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8); 702 703 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 704 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 705 /* base must be 32 byte aligned */ 706 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 707 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 708 amdgpu_ring_write(ring, ib->length_dw); 709 amdgpu_ring_write(ring, 0); 710 amdgpu_ring_write(ring, 0); 711 712 } 713 714 static void sdma_v4_0_wait_reg_mem(struct amdgpu_ring *ring, 715 int mem_space, int hdp, 716 uint32_t addr0, uint32_t addr1, 717 uint32_t ref, uint32_t mask, 718 uint32_t inv) 719 { 720 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 721 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) | 722 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) | 723 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 724 if (mem_space) { 725 /* memory */ 726 amdgpu_ring_write(ring, addr0); 727 amdgpu_ring_write(ring, addr1); 728 } else { 729 /* registers */ 730 amdgpu_ring_write(ring, addr0 << 2); 731 amdgpu_ring_write(ring, addr1 << 2); 732 } 733 amdgpu_ring_write(ring, ref); /* reference */ 734 amdgpu_ring_write(ring, mask); /* mask */ 735 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 736 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */ 737 } 738 739 /** 740 * sdma_v4_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 741 * 742 * @ring: amdgpu ring pointer 743 * 744 * Emit an hdp flush packet on the requested DMA ring. 745 */ 746 static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 747 { 748 struct amdgpu_device *adev = ring->adev; 749 u32 ref_and_mask = 0; 750 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg; 751 752 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; 753 754 sdma_v4_0_wait_reg_mem(ring, 0, 1, 755 adev->nbio_funcs->get_hdp_flush_done_offset(adev), 756 adev->nbio_funcs->get_hdp_flush_req_offset(adev), 757 ref_and_mask, ref_and_mask, 10); 758 } 759 760 /** 761 * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring 762 * 763 * @ring: amdgpu ring pointer 764 * @fence: amdgpu fence object 765 * 766 * Add a DMA fence packet to the ring to write 767 * the fence seq number and DMA trap packet to generate 768 * an interrupt if needed (VEGA10). 769 */ 770 static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 771 unsigned flags) 772 { 773 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 774 /* write the fence */ 775 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 776 /* zero in first two bits */ 777 BUG_ON(addr & 0x3); 778 amdgpu_ring_write(ring, lower_32_bits(addr)); 779 amdgpu_ring_write(ring, upper_32_bits(addr)); 780 amdgpu_ring_write(ring, lower_32_bits(seq)); 781 782 /* optionally write high bits as well */ 783 if (write64bit) { 784 addr += 4; 785 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 786 /* zero in first two bits */ 787 BUG_ON(addr & 0x3); 788 amdgpu_ring_write(ring, lower_32_bits(addr)); 789 amdgpu_ring_write(ring, upper_32_bits(addr)); 790 amdgpu_ring_write(ring, upper_32_bits(seq)); 791 } 792 793 /* generate an interrupt */ 794 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 795 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 796 } 797 798 799 /** 800 * sdma_v4_0_gfx_stop - stop the gfx async dma engines 801 * 802 * @adev: amdgpu_device pointer 803 * 804 * Stop the gfx async dma ring buffers (VEGA10). 805 */ 806 static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev) 807 { 808 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES]; 809 u32 rb_cntl, ib_cntl; 810 int i, unset = 0; 811 812 for (i = 0; i < adev->sdma.num_instances; i++) { 813 sdma[i] = &adev->sdma.instance[i].ring; 814 815 if ((adev->mman.buffer_funcs_ring == sdma[i]) && unset != 1) { 816 amdgpu_ttm_set_buffer_funcs_status(adev, false); 817 unset = 1; 818 } 819 820 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL); 821 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 822 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); 823 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL); 824 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 825 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl); 826 827 sdma[i]->sched.ready = false; 828 } 829 } 830 831 /** 832 * sdma_v4_0_rlc_stop - stop the compute async dma engines 833 * 834 * @adev: amdgpu_device pointer 835 * 836 * Stop the compute async dma queues (VEGA10). 837 */ 838 static void sdma_v4_0_rlc_stop(struct amdgpu_device *adev) 839 { 840 /* XXX todo */ 841 } 842 843 /** 844 * sdma_v4_0_page_stop - stop the page async dma engines 845 * 846 * @adev: amdgpu_device pointer 847 * 848 * Stop the page async dma ring buffers (VEGA10). 849 */ 850 static void sdma_v4_0_page_stop(struct amdgpu_device *adev) 851 { 852 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES]; 853 u32 rb_cntl, ib_cntl; 854 int i; 855 bool unset = false; 856 857 for (i = 0; i < adev->sdma.num_instances; i++) { 858 sdma[i] = &adev->sdma.instance[i].page; 859 860 if ((adev->mman.buffer_funcs_ring == sdma[i]) && 861 (unset == false)) { 862 amdgpu_ttm_set_buffer_funcs_status(adev, false); 863 unset = true; 864 } 865 866 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL); 867 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, 868 RB_ENABLE, 0); 869 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); 870 ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL); 871 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, 872 IB_ENABLE, 0); 873 WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl); 874 875 sdma[i]->sched.ready = false; 876 } 877 } 878 879 /** 880 * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch 881 * 882 * @adev: amdgpu_device pointer 883 * @enable: enable/disable the DMA MEs context switch. 884 * 885 * Halt or unhalt the async dma engines context switch (VEGA10). 886 */ 887 static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 888 { 889 u32 f32_cntl, phase_quantum = 0; 890 int i; 891 892 if (amdgpu_sdma_phase_quantum) { 893 unsigned value = amdgpu_sdma_phase_quantum; 894 unsigned unit = 0; 895 896 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 897 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 898 value = (value + 1) >> 1; 899 unit++; 900 } 901 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 902 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 903 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 904 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 905 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 906 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 907 WARN_ONCE(1, 908 "clamping sdma_phase_quantum to %uK clock cycles\n", 909 value << unit); 910 } 911 phase_quantum = 912 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 913 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 914 } 915 916 for (i = 0; i < adev->sdma.num_instances; i++) { 917 f32_cntl = RREG32_SDMA(i, mmSDMA0_CNTL); 918 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 919 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 920 if (enable && amdgpu_sdma_phase_quantum) { 921 WREG32_SDMA(i, mmSDMA0_PHASE0_QUANTUM, phase_quantum); 922 WREG32_SDMA(i, mmSDMA0_PHASE1_QUANTUM, phase_quantum); 923 WREG32_SDMA(i, mmSDMA0_PHASE2_QUANTUM, phase_quantum); 924 } 925 WREG32_SDMA(i, mmSDMA0_CNTL, f32_cntl); 926 } 927 928 } 929 930 /** 931 * sdma_v4_0_enable - stop the async dma engines 932 * 933 * @adev: amdgpu_device pointer 934 * @enable: enable/disable the DMA MEs. 935 * 936 * Halt or unhalt the async dma engines (VEGA10). 937 */ 938 static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable) 939 { 940 u32 f32_cntl; 941 int i; 942 943 if (enable == false) { 944 sdma_v4_0_gfx_stop(adev); 945 sdma_v4_0_rlc_stop(adev); 946 if (adev->sdma.has_page_queue) 947 sdma_v4_0_page_stop(adev); 948 } 949 950 for (i = 0; i < adev->sdma.num_instances; i++) { 951 f32_cntl = RREG32_SDMA(i, mmSDMA0_F32_CNTL); 952 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 953 WREG32_SDMA(i, mmSDMA0_F32_CNTL, f32_cntl); 954 } 955 } 956 957 /** 958 * sdma_v4_0_rb_cntl - get parameters for rb_cntl 959 */ 960 static uint32_t sdma_v4_0_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl) 961 { 962 /* Set ring buffer size in dwords */ 963 uint32_t rb_bufsz = order_base_2(ring->ring_size / 4); 964 965 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 966 #ifdef __BIG_ENDIAN 967 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 968 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 969 RPTR_WRITEBACK_SWAP_ENABLE, 1); 970 #endif 971 return rb_cntl; 972 } 973 974 /** 975 * sdma_v4_0_gfx_resume - setup and start the async dma engines 976 * 977 * @adev: amdgpu_device pointer 978 * @i: instance to resume 979 * 980 * Set up the gfx DMA ring buffers and enable them (VEGA10). 981 * Returns 0 for success, error for failure. 982 */ 983 static void sdma_v4_0_gfx_resume(struct amdgpu_device *adev, unsigned int i) 984 { 985 struct amdgpu_ring *ring = &adev->sdma.instance[i].ring; 986 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 987 u32 wb_offset; 988 u32 doorbell; 989 u32 doorbell_offset; 990 u64 wptr_gpu_addr; 991 992 wb_offset = (ring->rptr_offs * 4); 993 994 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL); 995 rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl); 996 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); 997 998 /* Initialize the ring buffer's read and write pointers */ 999 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR, 0); 1000 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_HI, 0); 1001 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR, 0); 1002 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_HI, 0); 1003 1004 /* set the wb address whether it's enabled or not */ 1005 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_HI, 1006 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 1007 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_LO, 1008 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 1009 1010 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 1011 RPTR_WRITEBACK_ENABLE, 1); 1012 1013 WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE, ring->gpu_addr >> 8); 1014 WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE_HI, ring->gpu_addr >> 40); 1015 1016 ring->wptr = 0; 1017 1018 /* before programing wptr to a less value, need set minor_ptr_update first */ 1019 WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 1); 1020 1021 doorbell = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL); 1022 doorbell_offset = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET); 1023 1024 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1025 ring->use_doorbell); 1026 doorbell_offset = REG_SET_FIELD(doorbell_offset, 1027 SDMA0_GFX_DOORBELL_OFFSET, 1028 OFFSET, ring->doorbell_index); 1029 WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL, doorbell); 1030 WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET, doorbell_offset); 1031 1032 sdma_v4_0_ring_set_wptr(ring); 1033 1034 /* set minor_ptr_update to 0 after wptr programed */ 1035 WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 0); 1036 1037 /* setup the wptr shadow polling */ 1038 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 1039 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO, 1040 lower_32_bits(wptr_gpu_addr)); 1041 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI, 1042 upper_32_bits(wptr_gpu_addr)); 1043 wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL); 1044 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 1045 SDMA0_GFX_RB_WPTR_POLL_CNTL, 1046 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 1047 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 1048 1049 /* enable DMA RB */ 1050 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 1051 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); 1052 1053 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL); 1054 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 1055 #ifdef __BIG_ENDIAN 1056 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 1057 #endif 1058 /* enable DMA IBs */ 1059 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl); 1060 1061 ring->sched.ready = true; 1062 } 1063 1064 /** 1065 * sdma_v4_0_page_resume - setup and start the async dma engines 1066 * 1067 * @adev: amdgpu_device pointer 1068 * @i: instance to resume 1069 * 1070 * Set up the page DMA ring buffers and enable them (VEGA10). 1071 * Returns 0 for success, error for failure. 1072 */ 1073 static void sdma_v4_0_page_resume(struct amdgpu_device *adev, unsigned int i) 1074 { 1075 struct amdgpu_ring *ring = &adev->sdma.instance[i].page; 1076 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 1077 u32 wb_offset; 1078 u32 doorbell; 1079 u32 doorbell_offset; 1080 u64 wptr_gpu_addr; 1081 1082 wb_offset = (ring->rptr_offs * 4); 1083 1084 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL); 1085 rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl); 1086 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); 1087 1088 /* Initialize the ring buffer's read and write pointers */ 1089 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR, 0); 1090 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_HI, 0); 1091 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR, 0); 1092 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_HI, 0); 1093 1094 /* set the wb address whether it's enabled or not */ 1095 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_HI, 1096 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 1097 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_LO, 1098 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 1099 1100 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, 1101 RPTR_WRITEBACK_ENABLE, 1); 1102 1103 WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE, ring->gpu_addr >> 8); 1104 WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE_HI, ring->gpu_addr >> 40); 1105 1106 ring->wptr = 0; 1107 1108 /* before programing wptr to a less value, need set minor_ptr_update first */ 1109 WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 1); 1110 1111 doorbell = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL); 1112 doorbell_offset = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET); 1113 1114 doorbell = REG_SET_FIELD(doorbell, SDMA0_PAGE_DOORBELL, ENABLE, 1115 ring->use_doorbell); 1116 doorbell_offset = REG_SET_FIELD(doorbell_offset, 1117 SDMA0_PAGE_DOORBELL_OFFSET, 1118 OFFSET, ring->doorbell_index); 1119 WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL, doorbell); 1120 WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET, doorbell_offset); 1121 1122 /* paging queue doorbell range is setup at sdma_v4_0_gfx_resume */ 1123 sdma_v4_0_page_ring_set_wptr(ring); 1124 1125 /* set minor_ptr_update to 0 after wptr programed */ 1126 WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 0); 1127 1128 /* setup the wptr shadow polling */ 1129 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 1130 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO, 1131 lower_32_bits(wptr_gpu_addr)); 1132 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI, 1133 upper_32_bits(wptr_gpu_addr)); 1134 wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL); 1135 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 1136 SDMA0_PAGE_RB_WPTR_POLL_CNTL, 1137 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 1138 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 1139 1140 /* enable DMA RB */ 1141 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, RB_ENABLE, 1); 1142 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); 1143 1144 ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL); 1145 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_ENABLE, 1); 1146 #ifdef __BIG_ENDIAN 1147 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1); 1148 #endif 1149 /* enable DMA IBs */ 1150 WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl); 1151 1152 ring->sched.ready = true; 1153 } 1154 1155 static void 1156 sdma_v4_1_update_power_gating(struct amdgpu_device *adev, bool enable) 1157 { 1158 uint32_t def, data; 1159 1160 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_SDMA)) { 1161 /* enable idle interrupt */ 1162 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 1163 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 1164 1165 if (data != def) 1166 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 1167 } else { 1168 /* disable idle interrupt */ 1169 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 1170 data &= ~SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 1171 if (data != def) 1172 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 1173 } 1174 } 1175 1176 static void sdma_v4_1_init_power_gating(struct amdgpu_device *adev) 1177 { 1178 uint32_t def, data; 1179 1180 /* Enable HW based PG. */ 1181 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1182 data |= SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK; 1183 if (data != def) 1184 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1185 1186 /* enable interrupt */ 1187 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 1188 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 1189 if (data != def) 1190 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 1191 1192 /* Configure hold time to filter in-valid power on/off request. Use default right now */ 1193 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1194 data &= ~SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK; 1195 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK); 1196 /* Configure switch time for hysteresis purpose. Use default right now */ 1197 data &= ~SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK; 1198 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK); 1199 if(data != def) 1200 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1201 } 1202 1203 static void sdma_v4_0_init_pg(struct amdgpu_device *adev) 1204 { 1205 if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA)) 1206 return; 1207 1208 switch (adev->asic_type) { 1209 case CHIP_RAVEN: 1210 case CHIP_RENOIR: 1211 sdma_v4_1_init_power_gating(adev); 1212 sdma_v4_1_update_power_gating(adev, true); 1213 break; 1214 default: 1215 break; 1216 } 1217 } 1218 1219 /** 1220 * sdma_v4_0_rlc_resume - setup and start the async dma engines 1221 * 1222 * @adev: amdgpu_device pointer 1223 * 1224 * Set up the compute DMA queues and enable them (VEGA10). 1225 * Returns 0 for success, error for failure. 1226 */ 1227 static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev) 1228 { 1229 sdma_v4_0_init_pg(adev); 1230 1231 return 0; 1232 } 1233 1234 /** 1235 * sdma_v4_0_load_microcode - load the sDMA ME ucode 1236 * 1237 * @adev: amdgpu_device pointer 1238 * 1239 * Loads the sDMA0/1 ucode. 1240 * Returns 0 for success, -EINVAL if the ucode is not available. 1241 */ 1242 static int sdma_v4_0_load_microcode(struct amdgpu_device *adev) 1243 { 1244 const struct sdma_firmware_header_v1_0 *hdr; 1245 const __le32 *fw_data; 1246 u32 fw_size; 1247 int i, j; 1248 1249 /* halt the MEs */ 1250 sdma_v4_0_enable(adev, false); 1251 1252 for (i = 0; i < adev->sdma.num_instances; i++) { 1253 if (!adev->sdma.instance[i].fw) 1254 return -EINVAL; 1255 1256 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 1257 amdgpu_ucode_print_sdma_hdr(&hdr->header); 1258 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1259 1260 fw_data = (const __le32 *) 1261 (adev->sdma.instance[i].fw->data + 1262 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1263 1264 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR, 0); 1265 1266 for (j = 0; j < fw_size; j++) 1267 WREG32_SDMA(i, mmSDMA0_UCODE_DATA, 1268 le32_to_cpup(fw_data++)); 1269 1270 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR, 1271 adev->sdma.instance[i].fw_version); 1272 } 1273 1274 return 0; 1275 } 1276 1277 /** 1278 * sdma_v4_0_start - setup and start the async dma engines 1279 * 1280 * @adev: amdgpu_device pointer 1281 * 1282 * Set up the DMA engines and enable them (VEGA10). 1283 * Returns 0 for success, error for failure. 1284 */ 1285 static int sdma_v4_0_start(struct amdgpu_device *adev) 1286 { 1287 struct amdgpu_ring *ring; 1288 int i, r = 0; 1289 1290 if (amdgpu_sriov_vf(adev)) { 1291 sdma_v4_0_ctx_switch_enable(adev, false); 1292 sdma_v4_0_enable(adev, false); 1293 } else { 1294 1295 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1296 r = sdma_v4_0_load_microcode(adev); 1297 if (r) 1298 return r; 1299 } 1300 1301 /* unhalt the MEs */ 1302 sdma_v4_0_enable(adev, true); 1303 /* enable sdma ring preemption */ 1304 sdma_v4_0_ctx_switch_enable(adev, true); 1305 } 1306 1307 /* start the gfx rings and rlc compute queues */ 1308 for (i = 0; i < adev->sdma.num_instances; i++) { 1309 uint32_t temp; 1310 1311 WREG32_SDMA(i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL, 0); 1312 sdma_v4_0_gfx_resume(adev, i); 1313 if (adev->sdma.has_page_queue) 1314 sdma_v4_0_page_resume(adev, i); 1315 1316 /* set utc l1 enable flag always to 1 */ 1317 temp = RREG32_SDMA(i, mmSDMA0_CNTL); 1318 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); 1319 WREG32_SDMA(i, mmSDMA0_CNTL, temp); 1320 1321 if (!amdgpu_sriov_vf(adev)) { 1322 /* unhalt engine */ 1323 temp = RREG32_SDMA(i, mmSDMA0_F32_CNTL); 1324 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 1325 WREG32_SDMA(i, mmSDMA0_F32_CNTL, temp); 1326 } 1327 } 1328 1329 if (amdgpu_sriov_vf(adev)) { 1330 sdma_v4_0_ctx_switch_enable(adev, true); 1331 sdma_v4_0_enable(adev, true); 1332 } else { 1333 r = sdma_v4_0_rlc_resume(adev); 1334 if (r) 1335 return r; 1336 } 1337 1338 for (i = 0; i < adev->sdma.num_instances; i++) { 1339 ring = &adev->sdma.instance[i].ring; 1340 1341 r = amdgpu_ring_test_helper(ring); 1342 if (r) 1343 return r; 1344 1345 if (adev->sdma.has_page_queue) { 1346 struct amdgpu_ring *page = &adev->sdma.instance[i].page; 1347 1348 r = amdgpu_ring_test_helper(page); 1349 if (r) 1350 return r; 1351 1352 if (adev->mman.buffer_funcs_ring == page) 1353 amdgpu_ttm_set_buffer_funcs_status(adev, true); 1354 } 1355 1356 if (adev->mman.buffer_funcs_ring == ring) 1357 amdgpu_ttm_set_buffer_funcs_status(adev, true); 1358 } 1359 1360 return r; 1361 } 1362 1363 /** 1364 * sdma_v4_0_ring_test_ring - simple async dma engine test 1365 * 1366 * @ring: amdgpu_ring structure holding ring information 1367 * 1368 * Test the DMA engine by writing using it to write an 1369 * value to memory. (VEGA10). 1370 * Returns 0 for success, error for failure. 1371 */ 1372 static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring) 1373 { 1374 struct amdgpu_device *adev = ring->adev; 1375 unsigned i; 1376 unsigned index; 1377 int r; 1378 u32 tmp; 1379 u64 gpu_addr; 1380 1381 r = amdgpu_device_wb_get(adev, &index); 1382 if (r) 1383 return r; 1384 1385 gpu_addr = adev->wb.gpu_addr + (index * 4); 1386 tmp = 0xCAFEDEAD; 1387 adev->wb.wb[index] = cpu_to_le32(tmp); 1388 1389 r = amdgpu_ring_alloc(ring, 5); 1390 if (r) 1391 goto error_free_wb; 1392 1393 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1394 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 1395 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 1396 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 1397 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 1398 amdgpu_ring_write(ring, 0xDEADBEEF); 1399 amdgpu_ring_commit(ring); 1400 1401 for (i = 0; i < adev->usec_timeout; i++) { 1402 tmp = le32_to_cpu(adev->wb.wb[index]); 1403 if (tmp == 0xDEADBEEF) 1404 break; 1405 udelay(1); 1406 } 1407 1408 if (i >= adev->usec_timeout) 1409 r = -ETIMEDOUT; 1410 1411 error_free_wb: 1412 amdgpu_device_wb_free(adev, index); 1413 return r; 1414 } 1415 1416 /** 1417 * sdma_v4_0_ring_test_ib - test an IB on the DMA engine 1418 * 1419 * @ring: amdgpu_ring structure holding ring information 1420 * 1421 * Test a simple IB in the DMA ring (VEGA10). 1422 * Returns 0 on success, error on failure. 1423 */ 1424 static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1425 { 1426 struct amdgpu_device *adev = ring->adev; 1427 struct amdgpu_ib ib; 1428 struct dma_fence *f = NULL; 1429 unsigned index; 1430 long r; 1431 u32 tmp = 0; 1432 u64 gpu_addr; 1433 1434 r = amdgpu_device_wb_get(adev, &index); 1435 if (r) 1436 return r; 1437 1438 gpu_addr = adev->wb.gpu_addr + (index * 4); 1439 tmp = 0xCAFEDEAD; 1440 adev->wb.wb[index] = cpu_to_le32(tmp); 1441 memset(&ib, 0, sizeof(ib)); 1442 r = amdgpu_ib_get(adev, NULL, 256, &ib); 1443 if (r) 1444 goto err0; 1445 1446 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1447 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1448 ib.ptr[1] = lower_32_bits(gpu_addr); 1449 ib.ptr[2] = upper_32_bits(gpu_addr); 1450 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 1451 ib.ptr[4] = 0xDEADBEEF; 1452 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1453 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1454 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1455 ib.length_dw = 8; 1456 1457 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1458 if (r) 1459 goto err1; 1460 1461 r = dma_fence_wait_timeout(f, false, timeout); 1462 if (r == 0) { 1463 r = -ETIMEDOUT; 1464 goto err1; 1465 } else if (r < 0) { 1466 goto err1; 1467 } 1468 tmp = le32_to_cpu(adev->wb.wb[index]); 1469 if (tmp == 0xDEADBEEF) 1470 r = 0; 1471 else 1472 r = -EINVAL; 1473 1474 err1: 1475 amdgpu_ib_free(adev, &ib, NULL); 1476 dma_fence_put(f); 1477 err0: 1478 amdgpu_device_wb_free(adev, index); 1479 return r; 1480 } 1481 1482 1483 /** 1484 * sdma_v4_0_vm_copy_pte - update PTEs by copying them from the GART 1485 * 1486 * @ib: indirect buffer to fill with commands 1487 * @pe: addr of the page entry 1488 * @src: src addr to copy from 1489 * @count: number of page entries to update 1490 * 1491 * Update PTEs by copying them from the GART using sDMA (VEGA10). 1492 */ 1493 static void sdma_v4_0_vm_copy_pte(struct amdgpu_ib *ib, 1494 uint64_t pe, uint64_t src, 1495 unsigned count) 1496 { 1497 unsigned bytes = count * 8; 1498 1499 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1500 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1501 ib->ptr[ib->length_dw++] = bytes - 1; 1502 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1503 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1504 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1505 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1506 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1507 1508 } 1509 1510 /** 1511 * sdma_v4_0_vm_write_pte - update PTEs by writing them manually 1512 * 1513 * @ib: indirect buffer to fill with commands 1514 * @pe: addr of the page entry 1515 * @addr: dst addr to write into pe 1516 * @count: number of page entries to update 1517 * @incr: increase next addr by incr bytes 1518 * @flags: access flags 1519 * 1520 * Update PTEs by writing them manually using sDMA (VEGA10). 1521 */ 1522 static void sdma_v4_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1523 uint64_t value, unsigned count, 1524 uint32_t incr) 1525 { 1526 unsigned ndw = count * 2; 1527 1528 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1529 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1530 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1531 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1532 ib->ptr[ib->length_dw++] = ndw - 1; 1533 for (; ndw > 0; ndw -= 2) { 1534 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1535 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1536 value += incr; 1537 } 1538 } 1539 1540 /** 1541 * sdma_v4_0_vm_set_pte_pde - update the page tables using sDMA 1542 * 1543 * @ib: indirect buffer to fill with commands 1544 * @pe: addr of the page entry 1545 * @addr: dst addr to write into pe 1546 * @count: number of page entries to update 1547 * @incr: increase next addr by incr bytes 1548 * @flags: access flags 1549 * 1550 * Update the page tables using sDMA (VEGA10). 1551 */ 1552 static void sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib *ib, 1553 uint64_t pe, 1554 uint64_t addr, unsigned count, 1555 uint32_t incr, uint64_t flags) 1556 { 1557 /* for physically contiguous pages (vram) */ 1558 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1559 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1560 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1561 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1562 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1563 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1564 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1565 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1566 ib->ptr[ib->length_dw++] = 0; 1567 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1568 } 1569 1570 /** 1571 * sdma_v4_0_ring_pad_ib - pad the IB to the required number of dw 1572 * 1573 * @ib: indirect buffer to fill with padding 1574 * 1575 */ 1576 static void sdma_v4_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1577 { 1578 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1579 u32 pad_count; 1580 int i; 1581 1582 pad_count = (8 - (ib->length_dw & 0x7)) % 8; 1583 for (i = 0; i < pad_count; i++) 1584 if (sdma && sdma->burst_nop && (i == 0)) 1585 ib->ptr[ib->length_dw++] = 1586 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1587 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1588 else 1589 ib->ptr[ib->length_dw++] = 1590 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1591 } 1592 1593 1594 /** 1595 * sdma_v4_0_ring_emit_pipeline_sync - sync the pipeline 1596 * 1597 * @ring: amdgpu_ring pointer 1598 * 1599 * Make sure all previous operations are completed (CIK). 1600 */ 1601 static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1602 { 1603 uint32_t seq = ring->fence_drv.sync_seq; 1604 uint64_t addr = ring->fence_drv.gpu_addr; 1605 1606 /* wait for idle */ 1607 sdma_v4_0_wait_reg_mem(ring, 1, 0, 1608 addr & 0xfffffffc, 1609 upper_32_bits(addr) & 0xffffffff, 1610 seq, 0xffffffff, 4); 1611 } 1612 1613 1614 /** 1615 * sdma_v4_0_ring_emit_vm_flush - vm flush using sDMA 1616 * 1617 * @ring: amdgpu_ring pointer 1618 * @vm: amdgpu_vm pointer 1619 * 1620 * Update the page table base and flush the VM TLB 1621 * using sDMA (VEGA10). 1622 */ 1623 static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1624 unsigned vmid, uint64_t pd_addr) 1625 { 1626 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1627 } 1628 1629 static void sdma_v4_0_ring_emit_wreg(struct amdgpu_ring *ring, 1630 uint32_t reg, uint32_t val) 1631 { 1632 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1633 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1634 amdgpu_ring_write(ring, reg); 1635 amdgpu_ring_write(ring, val); 1636 } 1637 1638 static void sdma_v4_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1639 uint32_t val, uint32_t mask) 1640 { 1641 sdma_v4_0_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10); 1642 } 1643 1644 static bool sdma_v4_0_fw_support_paging_queue(struct amdgpu_device *adev) 1645 { 1646 uint fw_version = adev->sdma.instance[0].fw_version; 1647 1648 switch (adev->asic_type) { 1649 case CHIP_VEGA10: 1650 return fw_version >= 430; 1651 case CHIP_VEGA12: 1652 /*return fw_version >= 31;*/ 1653 return false; 1654 case CHIP_VEGA20: 1655 return fw_version >= 123; 1656 default: 1657 return false; 1658 } 1659 } 1660 1661 static int sdma_v4_0_early_init(void *handle) 1662 { 1663 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1664 int r; 1665 1666 if (adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_RENOIR) 1667 adev->sdma.num_instances = 1; 1668 else if (adev->asic_type == CHIP_ARCTURUS) 1669 adev->sdma.num_instances = 8; 1670 else 1671 adev->sdma.num_instances = 2; 1672 1673 r = sdma_v4_0_init_microcode(adev); 1674 if (r) { 1675 DRM_ERROR("Failed to load sdma firmware!\n"); 1676 return r; 1677 } 1678 1679 /* TODO: Page queue breaks driver reload under SRIOV */ 1680 if ((adev->asic_type == CHIP_VEGA10) && amdgpu_sriov_vf((adev))) 1681 adev->sdma.has_page_queue = false; 1682 else if (sdma_v4_0_fw_support_paging_queue(adev)) 1683 adev->sdma.has_page_queue = true; 1684 1685 sdma_v4_0_set_ring_funcs(adev); 1686 sdma_v4_0_set_buffer_funcs(adev); 1687 sdma_v4_0_set_vm_pte_funcs(adev); 1688 sdma_v4_0_set_irq_funcs(adev); 1689 1690 return 0; 1691 } 1692 1693 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev, 1694 struct ras_err_data *err_data, 1695 struct amdgpu_iv_entry *entry); 1696 1697 static int sdma_v4_0_late_init(void *handle) 1698 { 1699 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1700 struct ras_common_if **ras_if = &adev->sdma.ras_if; 1701 struct ras_ih_if ih_info = { 1702 .cb = sdma_v4_0_process_ras_data_cb, 1703 }; 1704 struct ras_fs_if fs_info = { 1705 .sysfs_name = "sdma_err_count", 1706 .debugfs_name = "sdma_err_inject", 1707 }; 1708 struct ras_common_if ras_block = { 1709 .block = AMDGPU_RAS_BLOCK__SDMA, 1710 .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 1711 .sub_block_index = 0, 1712 .name = "sdma", 1713 }; 1714 int r, i; 1715 1716 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 1717 amdgpu_ras_feature_enable_on_boot(adev, &ras_block, 0); 1718 return 0; 1719 } 1720 1721 /* handle resume path. */ 1722 if (*ras_if) { 1723 /* resend ras TA enable cmd during resume. 1724 * prepare to handle failure. 1725 */ 1726 ih_info.head = **ras_if; 1727 r = amdgpu_ras_feature_enable_on_boot(adev, *ras_if, 1); 1728 if (r) { 1729 if (r == -EAGAIN) { 1730 /* request a gpu reset. will run again. */ 1731 amdgpu_ras_request_reset_on_boot(adev, 1732 AMDGPU_RAS_BLOCK__SDMA); 1733 return 0; 1734 } 1735 /* fail to enable ras, cleanup all. */ 1736 goto irq; 1737 } 1738 /* enable successfully. continue. */ 1739 goto resume; 1740 } 1741 1742 *ras_if = kmalloc(sizeof(**ras_if), GFP_KERNEL); 1743 if (!*ras_if) 1744 return -ENOMEM; 1745 1746 **ras_if = ras_block; 1747 1748 r = amdgpu_ras_feature_enable_on_boot(adev, *ras_if, 1); 1749 if (r) { 1750 if (r == -EAGAIN) { 1751 amdgpu_ras_request_reset_on_boot(adev, 1752 AMDGPU_RAS_BLOCK__SDMA); 1753 r = 0; 1754 } 1755 goto feature; 1756 } 1757 1758 ih_info.head = **ras_if; 1759 fs_info.head = **ras_if; 1760 1761 r = amdgpu_ras_interrupt_add_handler(adev, &ih_info); 1762 if (r) 1763 goto interrupt; 1764 1765 amdgpu_ras_debugfs_create(adev, &fs_info); 1766 1767 r = amdgpu_ras_sysfs_create(adev, &fs_info); 1768 if (r) 1769 goto sysfs; 1770 resume: 1771 for (i = 0; i < adev->sdma.num_instances; i++) { 1772 r = amdgpu_irq_get(adev, &adev->sdma.ecc_irq, 1773 AMDGPU_SDMA_IRQ_INSTANCE0 + i); 1774 if (r) 1775 goto irq; 1776 } 1777 1778 return 0; 1779 irq: 1780 amdgpu_ras_sysfs_remove(adev, *ras_if); 1781 sysfs: 1782 amdgpu_ras_debugfs_remove(adev, *ras_if); 1783 amdgpu_ras_interrupt_remove_handler(adev, &ih_info); 1784 interrupt: 1785 amdgpu_ras_feature_enable(adev, *ras_if, 0); 1786 feature: 1787 kfree(*ras_if); 1788 *ras_if = NULL; 1789 return r; 1790 } 1791 1792 static int sdma_v4_0_sw_init(void *handle) 1793 { 1794 struct amdgpu_ring *ring; 1795 int r, i; 1796 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1797 1798 /* SDMA trap event */ 1799 for (i = 0; i < adev->sdma.num_instances; i++) { 1800 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1801 SDMA0_4_0__SRCID__SDMA_TRAP, 1802 &adev->sdma.trap_irq); 1803 if (r) 1804 return r; 1805 } 1806 1807 /* SDMA SRAM ECC event */ 1808 for (i = 0; i < adev->sdma.num_instances; i++) { 1809 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1810 SDMA0_4_0__SRCID__SDMA_SRAM_ECC, 1811 &adev->sdma.ecc_irq); 1812 if (r) 1813 return r; 1814 } 1815 1816 for (i = 0; i < adev->sdma.num_instances; i++) { 1817 ring = &adev->sdma.instance[i].ring; 1818 ring->ring_obj = NULL; 1819 ring->use_doorbell = true; 1820 1821 DRM_INFO("use_doorbell being set to: [%s]\n", 1822 ring->use_doorbell?"true":"false"); 1823 1824 /* doorbell size is 2 dwords, get DWORD offset */ 1825 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1; 1826 1827 sprintf(ring->name, "sdma%d", i); 1828 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, 1829 AMDGPU_SDMA_IRQ_INSTANCE0 + i); 1830 if (r) 1831 return r; 1832 1833 if (adev->sdma.has_page_queue) { 1834 ring = &adev->sdma.instance[i].page; 1835 ring->ring_obj = NULL; 1836 ring->use_doorbell = true; 1837 1838 /* paging queue use same doorbell index/routing as gfx queue 1839 * with 0x400 (4096 dwords) offset on second doorbell page 1840 */ 1841 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1; 1842 ring->doorbell_index += 0x400; 1843 1844 sprintf(ring->name, "page%d", i); 1845 r = amdgpu_ring_init(adev, ring, 1024, 1846 &adev->sdma.trap_irq, 1847 AMDGPU_SDMA_IRQ_INSTANCE0 + i); 1848 if (r) 1849 return r; 1850 } 1851 } 1852 1853 return r; 1854 } 1855 1856 static int sdma_v4_0_sw_fini(void *handle) 1857 { 1858 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1859 int i; 1860 1861 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA) && 1862 adev->sdma.ras_if) { 1863 struct ras_common_if *ras_if = adev->sdma.ras_if; 1864 struct ras_ih_if ih_info = { 1865 .head = *ras_if, 1866 }; 1867 1868 /*remove fs first*/ 1869 amdgpu_ras_debugfs_remove(adev, ras_if); 1870 amdgpu_ras_sysfs_remove(adev, ras_if); 1871 /*remove the IH*/ 1872 amdgpu_ras_interrupt_remove_handler(adev, &ih_info); 1873 amdgpu_ras_feature_enable(adev, ras_if, 0); 1874 kfree(ras_if); 1875 } 1876 1877 for (i = 0; i < adev->sdma.num_instances; i++) { 1878 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1879 if (adev->sdma.has_page_queue) 1880 amdgpu_ring_fini(&adev->sdma.instance[i].page); 1881 } 1882 1883 sdma_v4_0_destroy_inst_ctx(adev); 1884 1885 return 0; 1886 } 1887 1888 static int sdma_v4_0_hw_init(void *handle) 1889 { 1890 int r; 1891 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1892 1893 if ((adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs && 1894 adev->powerplay.pp_funcs->set_powergating_by_smu) || 1895 adev->asic_type == CHIP_RENOIR) 1896 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false); 1897 1898 if (!amdgpu_sriov_vf(adev)) 1899 sdma_v4_0_init_golden_registers(adev); 1900 1901 r = sdma_v4_0_start(adev); 1902 1903 return r; 1904 } 1905 1906 static int sdma_v4_0_hw_fini(void *handle) 1907 { 1908 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1909 int i; 1910 1911 if (amdgpu_sriov_vf(adev)) 1912 return 0; 1913 1914 for (i = 0; i < adev->sdma.num_instances; i++) { 1915 amdgpu_irq_put(adev, &adev->sdma.ecc_irq, 1916 AMDGPU_SDMA_IRQ_INSTANCE0 + i); 1917 } 1918 1919 sdma_v4_0_ctx_switch_enable(adev, false); 1920 sdma_v4_0_enable(adev, false); 1921 1922 if ((adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs 1923 && adev->powerplay.pp_funcs->set_powergating_by_smu) || 1924 adev->asic_type == CHIP_RENOIR) 1925 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, true); 1926 1927 return 0; 1928 } 1929 1930 static int sdma_v4_0_suspend(void *handle) 1931 { 1932 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1933 1934 return sdma_v4_0_hw_fini(adev); 1935 } 1936 1937 static int sdma_v4_0_resume(void *handle) 1938 { 1939 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1940 1941 return sdma_v4_0_hw_init(adev); 1942 } 1943 1944 static bool sdma_v4_0_is_idle(void *handle) 1945 { 1946 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1947 u32 i; 1948 1949 for (i = 0; i < adev->sdma.num_instances; i++) { 1950 u32 tmp = RREG32_SDMA(i, mmSDMA0_STATUS_REG); 1951 1952 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1953 return false; 1954 } 1955 1956 return true; 1957 } 1958 1959 static int sdma_v4_0_wait_for_idle(void *handle) 1960 { 1961 unsigned i, j; 1962 u32 sdma[AMDGPU_MAX_SDMA_INSTANCES]; 1963 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1964 1965 for (i = 0; i < adev->usec_timeout; i++) { 1966 for (j = 0; j < adev->sdma.num_instances; j++) { 1967 sdma[j] = RREG32_SDMA(j, mmSDMA0_STATUS_REG); 1968 if (!(sdma[j] & SDMA0_STATUS_REG__IDLE_MASK)) 1969 break; 1970 } 1971 if (j == adev->sdma.num_instances) 1972 return 0; 1973 udelay(1); 1974 } 1975 return -ETIMEDOUT; 1976 } 1977 1978 static int sdma_v4_0_soft_reset(void *handle) 1979 { 1980 /* todo */ 1981 1982 return 0; 1983 } 1984 1985 static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev, 1986 struct amdgpu_irq_src *source, 1987 unsigned type, 1988 enum amdgpu_interrupt_state state) 1989 { 1990 u32 sdma_cntl; 1991 1992 sdma_cntl = RREG32_SDMA(type, mmSDMA0_CNTL); 1993 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1994 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1995 WREG32_SDMA(type, mmSDMA0_CNTL, sdma_cntl); 1996 1997 return 0; 1998 } 1999 2000 static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev, 2001 struct amdgpu_irq_src *source, 2002 struct amdgpu_iv_entry *entry) 2003 { 2004 uint32_t instance; 2005 2006 DRM_DEBUG("IH: SDMA trap\n"); 2007 instance = sdma_v4_0_irq_id_to_seq(entry->client_id); 2008 switch (entry->ring_id) { 2009 case 0: 2010 amdgpu_fence_process(&adev->sdma.instance[instance].ring); 2011 break; 2012 case 1: 2013 if (adev->asic_type == CHIP_VEGA20) 2014 amdgpu_fence_process(&adev->sdma.instance[instance].page); 2015 break; 2016 case 2: 2017 /* XXX compute */ 2018 break; 2019 case 3: 2020 if (adev->asic_type != CHIP_VEGA20) 2021 amdgpu_fence_process(&adev->sdma.instance[instance].page); 2022 break; 2023 } 2024 return 0; 2025 } 2026 2027 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev, 2028 struct ras_err_data *err_data, 2029 struct amdgpu_iv_entry *entry) 2030 { 2031 uint32_t err_source; 2032 int instance; 2033 2034 instance = sdma_v4_0_irq_id_to_seq(entry->client_id); 2035 if (instance < 0) 2036 return 0; 2037 2038 switch (entry->src_id) { 2039 case SDMA0_4_0__SRCID__SDMA_SRAM_ECC: 2040 err_source = 0; 2041 break; 2042 case SDMA0_4_0__SRCID__SDMA_ECC: 2043 err_source = 1; 2044 break; 2045 default: 2046 return 0; 2047 } 2048 2049 kgd2kfd_set_sram_ecc_flag(adev->kfd.dev); 2050 2051 amdgpu_ras_reset_gpu(adev, 0); 2052 2053 return AMDGPU_RAS_SUCCESS; 2054 } 2055 2056 static int sdma_v4_0_process_ecc_irq(struct amdgpu_device *adev, 2057 struct amdgpu_irq_src *source, 2058 struct amdgpu_iv_entry *entry) 2059 { 2060 struct ras_common_if *ras_if = adev->sdma.ras_if; 2061 struct ras_dispatch_if ih_data = { 2062 .entry = entry, 2063 }; 2064 2065 if (!ras_if) 2066 return 0; 2067 2068 ih_data.head = *ras_if; 2069 2070 amdgpu_ras_interrupt_dispatch(adev, &ih_data); 2071 return 0; 2072 } 2073 2074 static int sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device *adev, 2075 struct amdgpu_irq_src *source, 2076 struct amdgpu_iv_entry *entry) 2077 { 2078 int instance; 2079 2080 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 2081 2082 instance = sdma_v4_0_irq_id_to_seq(entry->client_id); 2083 if (instance < 0) 2084 return 0; 2085 2086 switch (entry->ring_id) { 2087 case 0: 2088 drm_sched_fault(&adev->sdma.instance[instance].ring.sched); 2089 break; 2090 } 2091 return 0; 2092 } 2093 2094 static int sdma_v4_0_set_ecc_irq_state(struct amdgpu_device *adev, 2095 struct amdgpu_irq_src *source, 2096 unsigned type, 2097 enum amdgpu_interrupt_state state) 2098 { 2099 u32 sdma_edc_config; 2100 2101 sdma_edc_config = RREG32_SDMA(type, mmSDMA0_EDC_CONFIG); 2102 sdma_edc_config = REG_SET_FIELD(sdma_edc_config, SDMA0_EDC_CONFIG, ECC_INT_ENABLE, 2103 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 2104 WREG32_SDMA(type, mmSDMA0_EDC_CONFIG, sdma_edc_config); 2105 2106 return 0; 2107 } 2108 2109 static void sdma_v4_0_update_medium_grain_clock_gating( 2110 struct amdgpu_device *adev, 2111 bool enable) 2112 { 2113 uint32_t data, def; 2114 int i; 2115 2116 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 2117 for (i = 0; i < adev->sdma.num_instances; i++) { 2118 def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL); 2119 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 2120 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 2121 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 2122 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 2123 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 2124 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 2125 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 2126 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 2127 if (def != data) 2128 WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data); 2129 } 2130 } else { 2131 for (i = 0; i < adev->sdma.num_instances; i++) { 2132 def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL); 2133 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 2134 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 2135 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 2136 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 2137 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 2138 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 2139 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 2140 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 2141 if (def != data) 2142 WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data); 2143 } 2144 } 2145 } 2146 2147 2148 static void sdma_v4_0_update_medium_grain_light_sleep( 2149 struct amdgpu_device *adev, 2150 bool enable) 2151 { 2152 uint32_t data, def; 2153 int i; 2154 2155 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 2156 for (i = 0; i < adev->sdma.num_instances; i++) { 2157 /* 1-not override: enable sdma mem light sleep */ 2158 def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL); 2159 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 2160 if (def != data) 2161 WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data); 2162 } 2163 } else { 2164 for (i = 0; i < adev->sdma.num_instances; i++) { 2165 /* 0-override:disable sdma mem light sleep */ 2166 def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL); 2167 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 2168 if (def != data) 2169 WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data); 2170 } 2171 } 2172 } 2173 2174 static int sdma_v4_0_set_clockgating_state(void *handle, 2175 enum amd_clockgating_state state) 2176 { 2177 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2178 2179 if (amdgpu_sriov_vf(adev)) 2180 return 0; 2181 2182 switch (adev->asic_type) { 2183 case CHIP_VEGA10: 2184 case CHIP_VEGA12: 2185 case CHIP_VEGA20: 2186 case CHIP_RAVEN: 2187 case CHIP_ARCTURUS: 2188 case CHIP_RENOIR: 2189 sdma_v4_0_update_medium_grain_clock_gating(adev, 2190 state == AMD_CG_STATE_GATE ? true : false); 2191 sdma_v4_0_update_medium_grain_light_sleep(adev, 2192 state == AMD_CG_STATE_GATE ? true : false); 2193 break; 2194 default: 2195 break; 2196 } 2197 return 0; 2198 } 2199 2200 static int sdma_v4_0_set_powergating_state(void *handle, 2201 enum amd_powergating_state state) 2202 { 2203 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2204 2205 switch (adev->asic_type) { 2206 case CHIP_RAVEN: 2207 sdma_v4_1_update_power_gating(adev, 2208 state == AMD_PG_STATE_GATE ? true : false); 2209 break; 2210 default: 2211 break; 2212 } 2213 2214 return 0; 2215 } 2216 2217 static void sdma_v4_0_get_clockgating_state(void *handle, u32 *flags) 2218 { 2219 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2220 int data; 2221 2222 if (amdgpu_sriov_vf(adev)) 2223 *flags = 0; 2224 2225 /* AMD_CG_SUPPORT_SDMA_MGCG */ 2226 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); 2227 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK)) 2228 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 2229 2230 /* AMD_CG_SUPPORT_SDMA_LS */ 2231 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 2232 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 2233 *flags |= AMD_CG_SUPPORT_SDMA_LS; 2234 } 2235 2236 const struct amd_ip_funcs sdma_v4_0_ip_funcs = { 2237 .name = "sdma_v4_0", 2238 .early_init = sdma_v4_0_early_init, 2239 .late_init = sdma_v4_0_late_init, 2240 .sw_init = sdma_v4_0_sw_init, 2241 .sw_fini = sdma_v4_0_sw_fini, 2242 .hw_init = sdma_v4_0_hw_init, 2243 .hw_fini = sdma_v4_0_hw_fini, 2244 .suspend = sdma_v4_0_suspend, 2245 .resume = sdma_v4_0_resume, 2246 .is_idle = sdma_v4_0_is_idle, 2247 .wait_for_idle = sdma_v4_0_wait_for_idle, 2248 .soft_reset = sdma_v4_0_soft_reset, 2249 .set_clockgating_state = sdma_v4_0_set_clockgating_state, 2250 .set_powergating_state = sdma_v4_0_set_powergating_state, 2251 .get_clockgating_state = sdma_v4_0_get_clockgating_state, 2252 }; 2253 2254 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = { 2255 .type = AMDGPU_RING_TYPE_SDMA, 2256 .align_mask = 0xf, 2257 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2258 .support_64bit_ptrs = true, 2259 .vmhub = AMDGPU_MMHUB_0, 2260 .get_rptr = sdma_v4_0_ring_get_rptr, 2261 .get_wptr = sdma_v4_0_ring_get_wptr, 2262 .set_wptr = sdma_v4_0_ring_set_wptr, 2263 .emit_frame_size = 2264 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 2265 3 + /* hdp invalidate */ 2266 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 2267 /* sdma_v4_0_ring_emit_vm_flush */ 2268 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2269 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2270 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 2271 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 2272 .emit_ib = sdma_v4_0_ring_emit_ib, 2273 .emit_fence = sdma_v4_0_ring_emit_fence, 2274 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 2275 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 2276 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 2277 .test_ring = sdma_v4_0_ring_test_ring, 2278 .test_ib = sdma_v4_0_ring_test_ib, 2279 .insert_nop = sdma_v4_0_ring_insert_nop, 2280 .pad_ib = sdma_v4_0_ring_pad_ib, 2281 .emit_wreg = sdma_v4_0_ring_emit_wreg, 2282 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 2283 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2284 }; 2285 2286 /* 2287 * On Arcturus, SDMA instance 5~7 has a different vmhub type(AMDGPU_MMHUB_1). 2288 * So create a individual constant ring_funcs for those instances. 2289 */ 2290 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs_2nd_mmhub = { 2291 .type = AMDGPU_RING_TYPE_SDMA, 2292 .align_mask = 0xf, 2293 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2294 .support_64bit_ptrs = true, 2295 .vmhub = AMDGPU_MMHUB_1, 2296 .get_rptr = sdma_v4_0_ring_get_rptr, 2297 .get_wptr = sdma_v4_0_ring_get_wptr, 2298 .set_wptr = sdma_v4_0_ring_set_wptr, 2299 .emit_frame_size = 2300 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 2301 3 + /* hdp invalidate */ 2302 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 2303 /* sdma_v4_0_ring_emit_vm_flush */ 2304 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2305 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2306 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 2307 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 2308 .emit_ib = sdma_v4_0_ring_emit_ib, 2309 .emit_fence = sdma_v4_0_ring_emit_fence, 2310 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 2311 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 2312 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 2313 .test_ring = sdma_v4_0_ring_test_ring, 2314 .test_ib = sdma_v4_0_ring_test_ib, 2315 .insert_nop = sdma_v4_0_ring_insert_nop, 2316 .pad_ib = sdma_v4_0_ring_pad_ib, 2317 .emit_wreg = sdma_v4_0_ring_emit_wreg, 2318 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 2319 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2320 }; 2321 2322 static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs = { 2323 .type = AMDGPU_RING_TYPE_SDMA, 2324 .align_mask = 0xf, 2325 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2326 .support_64bit_ptrs = true, 2327 .vmhub = AMDGPU_MMHUB_0, 2328 .get_rptr = sdma_v4_0_ring_get_rptr, 2329 .get_wptr = sdma_v4_0_page_ring_get_wptr, 2330 .set_wptr = sdma_v4_0_page_ring_set_wptr, 2331 .emit_frame_size = 2332 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 2333 3 + /* hdp invalidate */ 2334 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 2335 /* sdma_v4_0_ring_emit_vm_flush */ 2336 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2337 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2338 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 2339 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 2340 .emit_ib = sdma_v4_0_ring_emit_ib, 2341 .emit_fence = sdma_v4_0_ring_emit_fence, 2342 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 2343 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 2344 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 2345 .test_ring = sdma_v4_0_ring_test_ring, 2346 .test_ib = sdma_v4_0_ring_test_ib, 2347 .insert_nop = sdma_v4_0_ring_insert_nop, 2348 .pad_ib = sdma_v4_0_ring_pad_ib, 2349 .emit_wreg = sdma_v4_0_ring_emit_wreg, 2350 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 2351 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2352 }; 2353 2354 static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs_2nd_mmhub = { 2355 .type = AMDGPU_RING_TYPE_SDMA, 2356 .align_mask = 0xf, 2357 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2358 .support_64bit_ptrs = true, 2359 .vmhub = AMDGPU_MMHUB_1, 2360 .get_rptr = sdma_v4_0_ring_get_rptr, 2361 .get_wptr = sdma_v4_0_page_ring_get_wptr, 2362 .set_wptr = sdma_v4_0_page_ring_set_wptr, 2363 .emit_frame_size = 2364 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 2365 3 + /* hdp invalidate */ 2366 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 2367 /* sdma_v4_0_ring_emit_vm_flush */ 2368 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2369 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2370 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 2371 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 2372 .emit_ib = sdma_v4_0_ring_emit_ib, 2373 .emit_fence = sdma_v4_0_ring_emit_fence, 2374 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 2375 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 2376 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 2377 .test_ring = sdma_v4_0_ring_test_ring, 2378 .test_ib = sdma_v4_0_ring_test_ib, 2379 .insert_nop = sdma_v4_0_ring_insert_nop, 2380 .pad_ib = sdma_v4_0_ring_pad_ib, 2381 .emit_wreg = sdma_v4_0_ring_emit_wreg, 2382 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 2383 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2384 }; 2385 2386 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev) 2387 { 2388 int i; 2389 2390 for (i = 0; i < adev->sdma.num_instances; i++) { 2391 if (adev->asic_type == CHIP_ARCTURUS && i >= 5) 2392 adev->sdma.instance[i].ring.funcs = 2393 &sdma_v4_0_ring_funcs_2nd_mmhub; 2394 else 2395 adev->sdma.instance[i].ring.funcs = 2396 &sdma_v4_0_ring_funcs; 2397 adev->sdma.instance[i].ring.me = i; 2398 if (adev->sdma.has_page_queue) { 2399 if (adev->asic_type == CHIP_ARCTURUS && i >= 5) 2400 adev->sdma.instance[i].page.funcs = 2401 &sdma_v4_0_page_ring_funcs_2nd_mmhub; 2402 else 2403 adev->sdma.instance[i].page.funcs = 2404 &sdma_v4_0_page_ring_funcs; 2405 adev->sdma.instance[i].page.me = i; 2406 } 2407 } 2408 } 2409 2410 static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = { 2411 .set = sdma_v4_0_set_trap_irq_state, 2412 .process = sdma_v4_0_process_trap_irq, 2413 }; 2414 2415 static const struct amdgpu_irq_src_funcs sdma_v4_0_illegal_inst_irq_funcs = { 2416 .process = sdma_v4_0_process_illegal_inst_irq, 2417 }; 2418 2419 static const struct amdgpu_irq_src_funcs sdma_v4_0_ecc_irq_funcs = { 2420 .set = sdma_v4_0_set_ecc_irq_state, 2421 .process = sdma_v4_0_process_ecc_irq, 2422 }; 2423 2424 2425 2426 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev) 2427 { 2428 switch (adev->sdma.num_instances) { 2429 case 1: 2430 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE1; 2431 adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE1; 2432 break; 2433 case 8: 2434 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 2435 adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 2436 break; 2437 case 2: 2438 default: 2439 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE2; 2440 adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE2; 2441 break; 2442 } 2443 adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs; 2444 adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs; 2445 adev->sdma.ecc_irq.funcs = &sdma_v4_0_ecc_irq_funcs; 2446 } 2447 2448 /** 2449 * sdma_v4_0_emit_copy_buffer - copy buffer using the sDMA engine 2450 * 2451 * @ring: amdgpu_ring structure holding ring information 2452 * @src_offset: src GPU address 2453 * @dst_offset: dst GPU address 2454 * @byte_count: number of bytes to xfer 2455 * 2456 * Copy GPU buffers using the DMA engine (VEGA10/12). 2457 * Used by the amdgpu ttm implementation to move pages if 2458 * registered as the asic copy callback. 2459 */ 2460 static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib, 2461 uint64_t src_offset, 2462 uint64_t dst_offset, 2463 uint32_t byte_count) 2464 { 2465 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 2466 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 2467 ib->ptr[ib->length_dw++] = byte_count - 1; 2468 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 2469 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 2470 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 2471 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2472 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2473 } 2474 2475 /** 2476 * sdma_v4_0_emit_fill_buffer - fill buffer using the sDMA engine 2477 * 2478 * @ring: amdgpu_ring structure holding ring information 2479 * @src_data: value to write to buffer 2480 * @dst_offset: dst GPU address 2481 * @byte_count: number of bytes to xfer 2482 * 2483 * Fill GPU buffers using the DMA engine (VEGA10/12). 2484 */ 2485 static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib, 2486 uint32_t src_data, 2487 uint64_t dst_offset, 2488 uint32_t byte_count) 2489 { 2490 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 2491 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2492 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2493 ib->ptr[ib->length_dw++] = src_data; 2494 ib->ptr[ib->length_dw++] = byte_count - 1; 2495 } 2496 2497 static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = { 2498 .copy_max_bytes = 0x400000, 2499 .copy_num_dw = 7, 2500 .emit_copy_buffer = sdma_v4_0_emit_copy_buffer, 2501 2502 .fill_max_bytes = 0x400000, 2503 .fill_num_dw = 5, 2504 .emit_fill_buffer = sdma_v4_0_emit_fill_buffer, 2505 }; 2506 2507 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev) 2508 { 2509 adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs; 2510 if (adev->sdma.has_page_queue) 2511 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page; 2512 else 2513 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 2514 } 2515 2516 static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = { 2517 .copy_pte_num_dw = 7, 2518 .copy_pte = sdma_v4_0_vm_copy_pte, 2519 2520 .write_pte = sdma_v4_0_vm_write_pte, 2521 .set_pte_pde = sdma_v4_0_vm_set_pte_pde, 2522 }; 2523 2524 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev) 2525 { 2526 struct drm_gpu_scheduler *sched; 2527 unsigned i; 2528 2529 adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs; 2530 for (i = 0; i < adev->sdma.num_instances; i++) { 2531 if (adev->sdma.has_page_queue) 2532 sched = &adev->sdma.instance[i].page.sched; 2533 else 2534 sched = &adev->sdma.instance[i].ring.sched; 2535 adev->vm_manager.vm_pte_rqs[i] = 2536 &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL]; 2537 } 2538 adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances; 2539 } 2540 2541 const struct amdgpu_ip_block_version sdma_v4_0_ip_block = { 2542 .type = AMD_IP_BLOCK_TYPE_SDMA, 2543 .major = 4, 2544 .minor = 0, 2545 .rev = 0, 2546 .funcs = &sdma_v4_0_ip_funcs, 2547 }; 2548