1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 33 #include "gc/gc_11_0_0_offset.h" 34 #include "gc/gc_11_0_0_sh_mask.h" 35 #include "gc/gc_11_0_0_default.h" 36 #include "hdp/hdp_6_0_0_offset.h" 37 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h" 38 39 #include "soc15_common.h" 40 #include "soc15.h" 41 #include "sdma_v6_0_0_pkt_open.h" 42 #include "nbio_v4_3.h" 43 #include "sdma_common.h" 44 #include "sdma_v6_0.h" 45 #include "v11_structs.h" 46 47 MODULE_FIRMWARE("amdgpu/sdma_6_0_0.bin"); 48 MODULE_FIRMWARE("amdgpu/sdma_6_0_1.bin"); 49 MODULE_FIRMWARE("amdgpu/sdma_6_0_2.bin"); 50 MODULE_FIRMWARE("amdgpu/sdma_6_0_3.bin"); 51 MODULE_FIRMWARE("amdgpu/sdma_6_1_0.bin"); 52 MODULE_FIRMWARE("amdgpu/sdma_6_1_1.bin"); 53 54 #define SDMA1_REG_OFFSET 0x600 55 #define SDMA0_HYP_DEC_REG_START 0x5880 56 #define SDMA0_HYP_DEC_REG_END 0x589a 57 #define SDMA1_HYP_DEC_REG_OFFSET 0x20 58 59 static void sdma_v6_0_set_ring_funcs(struct amdgpu_device *adev); 60 static void sdma_v6_0_set_buffer_funcs(struct amdgpu_device *adev); 61 static void sdma_v6_0_set_vm_pte_funcs(struct amdgpu_device *adev); 62 static void sdma_v6_0_set_irq_funcs(struct amdgpu_device *adev); 63 static int sdma_v6_0_start(struct amdgpu_device *adev); 64 65 static u32 sdma_v6_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset) 66 { 67 u32 base; 68 69 if (internal_offset >= SDMA0_HYP_DEC_REG_START && 70 internal_offset <= SDMA0_HYP_DEC_REG_END) { 71 base = adev->reg_offset[GC_HWIP][0][1]; 72 if (instance != 0) 73 internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance; 74 } else { 75 base = adev->reg_offset[GC_HWIP][0][0]; 76 if (instance == 1) 77 internal_offset += SDMA1_REG_OFFSET; 78 } 79 80 return base + internal_offset; 81 } 82 83 static unsigned sdma_v6_0_ring_init_cond_exec(struct amdgpu_ring *ring, 84 uint64_t addr) 85 { 86 unsigned ret; 87 88 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COND_EXE)); 89 amdgpu_ring_write(ring, lower_32_bits(addr)); 90 amdgpu_ring_write(ring, upper_32_bits(addr)); 91 amdgpu_ring_write(ring, 1); 92 /* this is the offset we need patch later */ 93 ret = ring->wptr & ring->buf_mask; 94 /* insert dummy here and patch it later */ 95 amdgpu_ring_write(ring, 0); 96 97 return ret; 98 } 99 100 /** 101 * sdma_v6_0_ring_get_rptr - get the current read pointer 102 * 103 * @ring: amdgpu ring pointer 104 * 105 * Get the current rptr from the hardware. 106 */ 107 static uint64_t sdma_v6_0_ring_get_rptr(struct amdgpu_ring *ring) 108 { 109 u64 *rptr; 110 111 /* XXX check if swapping is necessary on BE */ 112 rptr = (u64 *)ring->rptr_cpu_addr; 113 114 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 115 return ((*rptr) >> 2); 116 } 117 118 /** 119 * sdma_v6_0_ring_get_wptr - get the current write pointer 120 * 121 * @ring: amdgpu ring pointer 122 * 123 * Get the current wptr from the hardware. 124 */ 125 static uint64_t sdma_v6_0_ring_get_wptr(struct amdgpu_ring *ring) 126 { 127 u64 wptr = 0; 128 129 if (ring->use_doorbell) { 130 /* XXX check if swapping is necessary on BE */ 131 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr)); 132 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 133 } 134 135 return wptr >> 2; 136 } 137 138 /** 139 * sdma_v6_0_ring_set_wptr - commit the write pointer 140 * 141 * @ring: amdgpu ring pointer 142 * 143 * Write the wptr back to the hardware. 144 */ 145 static void sdma_v6_0_ring_set_wptr(struct amdgpu_ring *ring) 146 { 147 struct amdgpu_device *adev = ring->adev; 148 149 if (ring->use_doorbell) { 150 DRM_DEBUG("Using doorbell -- " 151 "wptr_offs == 0x%08x " 152 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 153 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 154 ring->wptr_offs, 155 lower_32_bits(ring->wptr << 2), 156 upper_32_bits(ring->wptr << 2)); 157 /* XXX check if swapping is necessary on BE */ 158 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 159 ring->wptr << 2); 160 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 161 ring->doorbell_index, ring->wptr << 2); 162 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 163 } else { 164 DRM_DEBUG("Not using doorbell -- " 165 "regSDMA%i_GFX_RB_WPTR == 0x%08x " 166 "regSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 167 ring->me, 168 lower_32_bits(ring->wptr << 2), 169 ring->me, 170 upper_32_bits(ring->wptr << 2)); 171 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, 172 ring->me, regSDMA0_QUEUE0_RB_WPTR), 173 lower_32_bits(ring->wptr << 2)); 174 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, 175 ring->me, regSDMA0_QUEUE0_RB_WPTR_HI), 176 upper_32_bits(ring->wptr << 2)); 177 } 178 } 179 180 static void sdma_v6_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 181 { 182 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 183 int i; 184 185 for (i = 0; i < count; i++) 186 if (sdma && sdma->burst_nop && (i == 0)) 187 amdgpu_ring_write(ring, ring->funcs->nop | 188 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 189 else 190 amdgpu_ring_write(ring, ring->funcs->nop); 191 } 192 193 /* 194 * sdma_v6_0_ring_emit_ib - Schedule an IB on the DMA engine 195 * 196 * @ring: amdgpu ring pointer 197 * @ib: IB object to schedule 198 * @flags: unused 199 * @job: job to retrieve vmid from 200 * 201 * Schedule an IB in the DMA ring. 202 */ 203 static void sdma_v6_0_ring_emit_ib(struct amdgpu_ring *ring, 204 struct amdgpu_job *job, 205 struct amdgpu_ib *ib, 206 uint32_t flags) 207 { 208 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 209 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid); 210 211 /* An IB packet must end on a 8 DW boundary--the next dword 212 * must be on a 8-dword boundary. Our IB packet below is 6 213 * dwords long, thus add x number of NOPs, such that, in 214 * modular arithmetic, 215 * wptr + 6 + x = 8k, k >= 0, which in C is, 216 * (wptr + 6 + x) % 8 = 0. 217 * The expression below, is a solution of x. 218 */ 219 sdma_v6_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 220 221 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_INDIRECT) | 222 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 223 /* base must be 32 byte aligned */ 224 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 225 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 226 amdgpu_ring_write(ring, ib->length_dw); 227 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); 228 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); 229 } 230 231 /** 232 * sdma_v6_0_ring_emit_mem_sync - flush the IB by graphics cache rinse 233 * 234 * @ring: amdgpu ring pointer 235 * 236 * flush the IB by graphics cache rinse. 237 */ 238 static void sdma_v6_0_ring_emit_mem_sync(struct amdgpu_ring *ring) 239 { 240 uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV | 241 SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV | 242 SDMA_GCR_GLI_INV(1); 243 244 /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */ 245 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_GCR_REQ)); 246 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0)); 247 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) | 248 SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0)); 249 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) | 250 SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16)); 251 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) | 252 SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0)); 253 } 254 255 256 /** 257 * sdma_v6_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 258 * 259 * @ring: amdgpu ring pointer 260 * 261 * Emit an hdp flush packet on the requested DMA ring. 262 */ 263 static void sdma_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 264 { 265 struct amdgpu_device *adev = ring->adev; 266 u32 ref_and_mask = 0; 267 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 268 269 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; 270 271 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) | 272 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 273 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 274 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2); 275 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2); 276 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 277 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 278 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 279 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 280 } 281 282 /** 283 * sdma_v6_0_ring_emit_fence - emit a fence on the DMA ring 284 * 285 * @ring: amdgpu ring pointer 286 * @addr: address 287 * @seq: fence seq number 288 * @flags: fence flags 289 * 290 * Add a DMA fence packet to the ring to write 291 * the fence seq number and DMA trap packet to generate 292 * an interrupt if needed. 293 */ 294 static void sdma_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 295 unsigned flags) 296 { 297 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 298 /* write the fence */ 299 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) | 300 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */ 301 /* zero in first two bits */ 302 BUG_ON(addr & 0x3); 303 amdgpu_ring_write(ring, lower_32_bits(addr)); 304 amdgpu_ring_write(ring, upper_32_bits(addr)); 305 amdgpu_ring_write(ring, lower_32_bits(seq)); 306 307 /* optionally write high bits as well */ 308 if (write64bit) { 309 addr += 4; 310 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) | 311 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); 312 /* zero in first two bits */ 313 BUG_ON(addr & 0x3); 314 amdgpu_ring_write(ring, lower_32_bits(addr)); 315 amdgpu_ring_write(ring, upper_32_bits(addr)); 316 amdgpu_ring_write(ring, upper_32_bits(seq)); 317 } 318 319 if (flags & AMDGPU_FENCE_FLAG_INT) { 320 uint32_t ctx = ring->is_mes_queue ? 321 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0; 322 /* generate an interrupt */ 323 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_TRAP)); 324 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(ctx)); 325 } 326 } 327 328 /** 329 * sdma_v6_0_gfx_stop - stop the gfx async dma engines 330 * 331 * @adev: amdgpu_device pointer 332 * 333 * Stop the gfx async dma ring buffers. 334 */ 335 static void sdma_v6_0_gfx_stop(struct amdgpu_device *adev) 336 { 337 u32 rb_cntl, ib_cntl; 338 int i; 339 340 for (i = 0; i < adev->sdma.num_instances; i++) { 341 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL)); 342 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 0); 343 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); 344 ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL)); 345 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 0); 346 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl); 347 } 348 } 349 350 /** 351 * sdma_v6_0_rlc_stop - stop the compute async dma engines 352 * 353 * @adev: amdgpu_device pointer 354 * 355 * Stop the compute async dma queues. 356 */ 357 static void sdma_v6_0_rlc_stop(struct amdgpu_device *adev) 358 { 359 /* XXX todo */ 360 } 361 362 /** 363 * sdma_v6_0_ctxempty_int_enable - enable or disable context empty interrupts 364 * 365 * @adev: amdgpu_device pointer 366 * @enable: enable/disable context switching due to queue empty conditions 367 * 368 * Enable or disable the async dma engines queue empty context switch. 369 */ 370 static void sdma_v6_0_ctxempty_int_enable(struct amdgpu_device *adev, bool enable) 371 { 372 u32 f32_cntl; 373 int i; 374 375 if (!amdgpu_sriov_vf(adev)) { 376 for (i = 0; i < adev->sdma.num_instances; i++) { 377 f32_cntl = RREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_CNTL)); 378 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 379 CTXEMPTY_INT_ENABLE, enable ? 1 : 0); 380 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_CNTL), f32_cntl); 381 } 382 } 383 } 384 385 /** 386 * sdma_v6_0_enable - stop the async dma engines 387 * 388 * @adev: amdgpu_device pointer 389 * @enable: enable/disable the DMA MEs. 390 * 391 * Halt or unhalt the async dma engines. 392 */ 393 static void sdma_v6_0_enable(struct amdgpu_device *adev, bool enable) 394 { 395 u32 f32_cntl; 396 int i; 397 398 if (!enable) { 399 sdma_v6_0_gfx_stop(adev); 400 sdma_v6_0_rlc_stop(adev); 401 } 402 403 if (amdgpu_sriov_vf(adev)) 404 return; 405 406 for (i = 0; i < adev->sdma.num_instances; i++) { 407 f32_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL)); 408 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 409 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), f32_cntl); 410 } 411 } 412 413 /** 414 * sdma_v6_0_gfx_resume - setup and start the async dma engines 415 * 416 * @adev: amdgpu_device pointer 417 * 418 * Set up the gfx DMA ring buffers and enable them. 419 * Returns 0 for success, error for failure. 420 */ 421 static int sdma_v6_0_gfx_resume(struct amdgpu_device *adev) 422 { 423 struct amdgpu_ring *ring; 424 u32 rb_cntl, ib_cntl; 425 u32 rb_bufsz; 426 u32 doorbell; 427 u32 doorbell_offset; 428 u32 temp; 429 u64 wptr_gpu_addr; 430 int i, r; 431 432 for (i = 0; i < adev->sdma.num_instances; i++) { 433 ring = &adev->sdma.instance[i].ring; 434 435 if (!amdgpu_sriov_vf(adev)) 436 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); 437 438 /* Set ring buffer size in dwords */ 439 rb_bufsz = order_base_2(ring->ring_size / 4); 440 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL)); 441 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz); 442 #ifdef __BIG_ENDIAN 443 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SWAP_ENABLE, 1); 444 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, 445 RPTR_WRITEBACK_SWAP_ENABLE, 1); 446 #endif 447 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_PRIV, 1); 448 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); 449 450 /* Initialize the ring buffer's read and write pointers */ 451 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0); 452 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), 0); 453 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0); 454 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), 0); 455 456 /* setup the wptr shadow polling */ 457 wptr_gpu_addr = ring->wptr_gpu_addr; 458 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO), 459 lower_32_bits(wptr_gpu_addr)); 460 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI), 461 upper_32_bits(wptr_gpu_addr)); 462 463 /* set the wb address whether it's enabled or not */ 464 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_HI), 465 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); 466 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_LO), 467 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); 468 469 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 470 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 0); 471 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, F32_WPTR_POLL_ENABLE, 1); 472 473 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE), ring->gpu_addr >> 8); 474 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40); 475 476 ring->wptr = 0; 477 478 /* before programing wptr to a less value, need set minor_ptr_update first */ 479 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 1); 480 481 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ 482 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2); 483 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2); 484 } 485 486 doorbell = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL)); 487 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET)); 488 489 if (ring->use_doorbell) { 490 doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 1); 491 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_QUEUE0_DOORBELL_OFFSET, 492 OFFSET, ring->doorbell_index); 493 } else { 494 doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 0); 495 } 496 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL), doorbell); 497 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET), doorbell_offset); 498 499 if (i == 0) 500 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, 501 ring->doorbell_index, 502 adev->doorbell_index.sdma_doorbell_range * adev->sdma.num_instances); 503 504 if (amdgpu_sriov_vf(adev)) 505 sdma_v6_0_ring_set_wptr(ring); 506 507 /* set minor_ptr_update to 0 after wptr programed */ 508 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 0); 509 510 /* Set up RESP_MODE to non-copy addresses */ 511 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL)); 512 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3); 513 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9); 514 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL), temp); 515 516 /* program default cache read and write policy */ 517 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE)); 518 /* clean read policy and write policy bits */ 519 temp &= 0xFF0FFF; 520 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | 521 (CACHE_WRITE_POLICY_L2__DEFAULT << 14) | 522 SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK); 523 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE), temp); 524 525 if (!amdgpu_sriov_vf(adev)) { 526 /* unhalt engine */ 527 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL)); 528 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 529 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, TH1_RESET, 0); 530 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), temp); 531 } 532 533 /* enable DMA RB */ 534 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 1); 535 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); 536 537 ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL)); 538 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 1); 539 #ifdef __BIG_ENDIAN 540 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_SWAP_ENABLE, 1); 541 #endif 542 /* enable DMA IBs */ 543 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl); 544 545 if (amdgpu_sriov_vf(adev)) 546 sdma_v6_0_enable(adev, true); 547 548 r = amdgpu_ring_test_helper(ring); 549 if (r) 550 return r; 551 } 552 553 return 0; 554 } 555 556 /** 557 * sdma_v6_0_rlc_resume - setup and start the async dma engines 558 * 559 * @adev: amdgpu_device pointer 560 * 561 * Set up the compute DMA queues and enable them. 562 * Returns 0 for success, error for failure. 563 */ 564 static int sdma_v6_0_rlc_resume(struct amdgpu_device *adev) 565 { 566 return 0; 567 } 568 569 /** 570 * sdma_v6_0_load_microcode - load the sDMA ME ucode 571 * 572 * @adev: amdgpu_device pointer 573 * 574 * Loads the sDMA0/1 ucode. 575 * Returns 0 for success, -EINVAL if the ucode is not available. 576 */ 577 static int sdma_v6_0_load_microcode(struct amdgpu_device *adev) 578 { 579 const struct sdma_firmware_header_v2_0 *hdr; 580 const __le32 *fw_data; 581 u32 fw_size; 582 int i, j; 583 bool use_broadcast; 584 585 /* halt the MEs */ 586 sdma_v6_0_enable(adev, false); 587 588 if (!adev->sdma.instance[0].fw) 589 return -EINVAL; 590 591 /* use broadcast mode to load SDMA microcode by default */ 592 use_broadcast = true; 593 594 if (use_broadcast) { 595 dev_info(adev->dev, "Use broadcast method to load SDMA firmware\n"); 596 /* load Control Thread microcode */ 597 hdr = (const struct sdma_firmware_header_v2_0 *)adev->sdma.instance[0].fw->data; 598 amdgpu_ucode_print_sdma_hdr(&hdr->header); 599 fw_size = le32_to_cpu(hdr->ctx_jt_offset + hdr->ctx_jt_size) / 4; 600 601 fw_data = (const __le32 *) 602 (adev->sdma.instance[0].fw->data + 603 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 604 605 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_ADDR), 0); 606 607 for (j = 0; j < fw_size; j++) { 608 if (amdgpu_emu_mode == 1 && j % 500 == 0) 609 msleep(1); 610 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_DATA), le32_to_cpup(fw_data++)); 611 } 612 613 /* load Context Switch microcode */ 614 fw_size = le32_to_cpu(hdr->ctl_jt_offset + hdr->ctl_jt_size) / 4; 615 616 fw_data = (const __le32 *) 617 (adev->sdma.instance[0].fw->data + 618 le32_to_cpu(hdr->ctl_ucode_offset)); 619 620 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_ADDR), 0x8000); 621 622 for (j = 0; j < fw_size; j++) { 623 if (amdgpu_emu_mode == 1 && j % 500 == 0) 624 msleep(1); 625 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_DATA), le32_to_cpup(fw_data++)); 626 } 627 } else { 628 dev_info(adev->dev, "Use legacy method to load SDMA firmware\n"); 629 for (i = 0; i < adev->sdma.num_instances; i++) { 630 /* load Control Thread microcode */ 631 hdr = (const struct sdma_firmware_header_v2_0 *)adev->sdma.instance[0].fw->data; 632 amdgpu_ucode_print_sdma_hdr(&hdr->header); 633 fw_size = le32_to_cpu(hdr->ctx_jt_offset + hdr->ctx_jt_size) / 4; 634 635 fw_data = (const __le32 *) 636 (adev->sdma.instance[0].fw->data + 637 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 638 639 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), 0); 640 641 for (j = 0; j < fw_size; j++) { 642 if (amdgpu_emu_mode == 1 && j % 500 == 0) 643 msleep(1); 644 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); 645 } 646 647 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), adev->sdma.instance[0].fw_version); 648 649 /* load Context Switch microcode */ 650 fw_size = le32_to_cpu(hdr->ctl_jt_offset + hdr->ctl_jt_size) / 4; 651 652 fw_data = (const __le32 *) 653 (adev->sdma.instance[0].fw->data + 654 le32_to_cpu(hdr->ctl_ucode_offset)); 655 656 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), 0x8000); 657 658 for (j = 0; j < fw_size; j++) { 659 if (amdgpu_emu_mode == 1 && j % 500 == 0) 660 msleep(1); 661 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); 662 } 663 664 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), adev->sdma.instance[0].fw_version); 665 } 666 } 667 668 return 0; 669 } 670 671 static int sdma_v6_0_soft_reset(void *handle) 672 { 673 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 674 u32 tmp; 675 int i; 676 677 sdma_v6_0_gfx_stop(adev); 678 679 for (i = 0; i < adev->sdma.num_instances; i++) { 680 tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE)); 681 tmp |= SDMA0_FREEZE__FREEZE_MASK; 682 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE), tmp); 683 tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL)); 684 tmp |= SDMA0_F32_CNTL__HALT_MASK; 685 tmp |= SDMA0_F32_CNTL__TH1_RESET_MASK; 686 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), tmp); 687 688 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_PREEMPT), 0); 689 690 udelay(100); 691 692 tmp = GRBM_SOFT_RESET__SOFT_RESET_SDMA0_MASK << i; 693 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp); 694 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 695 696 udelay(100); 697 698 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, 0); 699 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 700 701 udelay(100); 702 } 703 704 return sdma_v6_0_start(adev); 705 } 706 707 static bool sdma_v6_0_check_soft_reset(void *handle) 708 { 709 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 710 struct amdgpu_ring *ring; 711 int i, r; 712 long tmo = msecs_to_jiffies(1000); 713 714 for (i = 0; i < adev->sdma.num_instances; i++) { 715 ring = &adev->sdma.instance[i].ring; 716 r = amdgpu_ring_test_ib(ring, tmo); 717 if (r) 718 return true; 719 } 720 721 return false; 722 } 723 724 /** 725 * sdma_v6_0_start - setup and start the async dma engines 726 * 727 * @adev: amdgpu_device pointer 728 * 729 * Set up the DMA engines and enable them. 730 * Returns 0 for success, error for failure. 731 */ 732 static int sdma_v6_0_start(struct amdgpu_device *adev) 733 { 734 int r = 0; 735 736 if (amdgpu_sriov_vf(adev)) { 737 sdma_v6_0_enable(adev, false); 738 739 /* set RB registers */ 740 r = sdma_v6_0_gfx_resume(adev); 741 return r; 742 } 743 744 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 745 r = sdma_v6_0_load_microcode(adev); 746 if (r) 747 return r; 748 749 /* The value of regSDMA_F32_CNTL is invalid the moment after loading fw */ 750 if (amdgpu_emu_mode == 1) 751 msleep(1000); 752 } 753 754 /* unhalt the MEs */ 755 sdma_v6_0_enable(adev, true); 756 /* enable sdma ring preemption */ 757 sdma_v6_0_ctxempty_int_enable(adev, true); 758 759 /* start the gfx rings and rlc compute queues */ 760 r = sdma_v6_0_gfx_resume(adev); 761 if (r) 762 return r; 763 r = sdma_v6_0_rlc_resume(adev); 764 765 return r; 766 } 767 768 static int sdma_v6_0_mqd_init(struct amdgpu_device *adev, void *mqd, 769 struct amdgpu_mqd_prop *prop) 770 { 771 struct v11_sdma_mqd *m = mqd; 772 uint64_t wb_gpu_addr; 773 774 m->sdmax_rlcx_rb_cntl = 775 order_base_2(prop->queue_size / 4) << SDMA0_QUEUE0_RB_CNTL__RB_SIZE__SHIFT | 776 1 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 777 4 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT | 778 1 << SDMA0_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT; 779 780 m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8); 781 m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8); 782 783 wb_gpu_addr = prop->wptr_gpu_addr; 784 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr); 785 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr); 786 787 wb_gpu_addr = prop->rptr_gpu_addr; 788 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr); 789 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr); 790 791 m->sdmax_rlcx_ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, 0, 792 regSDMA0_QUEUE0_IB_CNTL)); 793 794 m->sdmax_rlcx_doorbell_offset = 795 prop->doorbell_index << SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT; 796 797 m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_QUEUE0_DOORBELL, ENABLE, 1); 798 799 m->sdmax_rlcx_skip_cntl = 0; 800 m->sdmax_rlcx_context_status = 0; 801 m->sdmax_rlcx_doorbell_log = 0; 802 803 m->sdmax_rlcx_rb_aql_cntl = regSDMA0_QUEUE0_RB_AQL_CNTL_DEFAULT; 804 m->sdmax_rlcx_dummy_reg = regSDMA0_QUEUE0_DUMMY_REG_DEFAULT; 805 806 return 0; 807 } 808 809 static void sdma_v6_0_set_mqd_funcs(struct amdgpu_device *adev) 810 { 811 adev->mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v11_sdma_mqd); 812 adev->mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v6_0_mqd_init; 813 } 814 815 /** 816 * sdma_v6_0_ring_test_ring - simple async dma engine test 817 * 818 * @ring: amdgpu_ring structure holding ring information 819 * 820 * Test the DMA engine by writing using it to write an 821 * value to memory. 822 * Returns 0 for success, error for failure. 823 */ 824 static int sdma_v6_0_ring_test_ring(struct amdgpu_ring *ring) 825 { 826 struct amdgpu_device *adev = ring->adev; 827 unsigned i; 828 unsigned index; 829 int r; 830 u32 tmp; 831 u64 gpu_addr; 832 volatile uint32_t *cpu_ptr = NULL; 833 834 tmp = 0xCAFEDEAD; 835 836 if (ring->is_mes_queue) { 837 uint32_t offset = 0; 838 offset = amdgpu_mes_ctx_get_offs(ring, 839 AMDGPU_MES_CTX_PADDING_OFFS); 840 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 841 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 842 *cpu_ptr = tmp; 843 } else { 844 r = amdgpu_device_wb_get(adev, &index); 845 if (r) { 846 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 847 return r; 848 } 849 850 gpu_addr = adev->wb.gpu_addr + (index * 4); 851 adev->wb.wb[index] = cpu_to_le32(tmp); 852 } 853 854 r = amdgpu_ring_alloc(ring, 5); 855 if (r) { 856 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 857 amdgpu_device_wb_free(adev, index); 858 return r; 859 } 860 861 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) | 862 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 863 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 864 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 865 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 866 amdgpu_ring_write(ring, 0xDEADBEEF); 867 amdgpu_ring_commit(ring); 868 869 for (i = 0; i < adev->usec_timeout; i++) { 870 if (ring->is_mes_queue) 871 tmp = le32_to_cpu(*cpu_ptr); 872 else 873 tmp = le32_to_cpu(adev->wb.wb[index]); 874 if (tmp == 0xDEADBEEF) 875 break; 876 if (amdgpu_emu_mode == 1) 877 msleep(1); 878 else 879 udelay(1); 880 } 881 882 if (i >= adev->usec_timeout) 883 r = -ETIMEDOUT; 884 885 if (!ring->is_mes_queue) 886 amdgpu_device_wb_free(adev, index); 887 888 return r; 889 } 890 891 /* 892 * sdma_v6_0_ring_test_ib - test an IB on the DMA engine 893 * 894 * @ring: amdgpu_ring structure holding ring information 895 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 896 * 897 * Test a simple IB in the DMA ring. 898 * Returns 0 on success, error on failure. 899 */ 900 static int sdma_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 901 { 902 struct amdgpu_device *adev = ring->adev; 903 struct amdgpu_ib ib; 904 struct dma_fence *f = NULL; 905 unsigned index; 906 long r; 907 u32 tmp = 0; 908 u64 gpu_addr; 909 volatile uint32_t *cpu_ptr = NULL; 910 911 tmp = 0xCAFEDEAD; 912 memset(&ib, 0, sizeof(ib)); 913 914 if (ring->is_mes_queue) { 915 uint32_t offset = 0; 916 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS); 917 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 918 ib.ptr = (void *)amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 919 920 offset = amdgpu_mes_ctx_get_offs(ring, 921 AMDGPU_MES_CTX_PADDING_OFFS); 922 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 923 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 924 *cpu_ptr = tmp; 925 } else { 926 r = amdgpu_device_wb_get(adev, &index); 927 if (r) { 928 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 929 return r; 930 } 931 932 gpu_addr = adev->wb.gpu_addr + (index * 4); 933 adev->wb.wb[index] = cpu_to_le32(tmp); 934 935 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib); 936 if (r) { 937 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 938 goto err0; 939 } 940 } 941 942 ib.ptr[0] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) | 943 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 944 ib.ptr[1] = lower_32_bits(gpu_addr); 945 ib.ptr[2] = upper_32_bits(gpu_addr); 946 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 947 ib.ptr[4] = 0xDEADBEEF; 948 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 949 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 950 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 951 ib.length_dw = 8; 952 953 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 954 if (r) 955 goto err1; 956 957 r = dma_fence_wait_timeout(f, false, timeout); 958 if (r == 0) { 959 DRM_ERROR("amdgpu: IB test timed out\n"); 960 r = -ETIMEDOUT; 961 goto err1; 962 } else if (r < 0) { 963 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 964 goto err1; 965 } 966 967 if (ring->is_mes_queue) 968 tmp = le32_to_cpu(*cpu_ptr); 969 else 970 tmp = le32_to_cpu(adev->wb.wb[index]); 971 972 if (tmp == 0xDEADBEEF) 973 r = 0; 974 else 975 r = -EINVAL; 976 977 err1: 978 amdgpu_ib_free(adev, &ib, NULL); 979 dma_fence_put(f); 980 err0: 981 if (!ring->is_mes_queue) 982 amdgpu_device_wb_free(adev, index); 983 return r; 984 } 985 986 987 /** 988 * sdma_v6_0_vm_copy_pte - update PTEs by copying them from the GART 989 * 990 * @ib: indirect buffer to fill with commands 991 * @pe: addr of the page entry 992 * @src: src addr to copy from 993 * @count: number of page entries to update 994 * 995 * Update PTEs by copying them from the GART using sDMA. 996 */ 997 static void sdma_v6_0_vm_copy_pte(struct amdgpu_ib *ib, 998 uint64_t pe, uint64_t src, 999 unsigned count) 1000 { 1001 unsigned bytes = count * 8; 1002 1003 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) | 1004 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1005 ib->ptr[ib->length_dw++] = bytes - 1; 1006 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1007 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1008 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1009 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1010 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1011 1012 } 1013 1014 /** 1015 * sdma_v6_0_vm_write_pte - update PTEs by writing them manually 1016 * 1017 * @ib: indirect buffer to fill with commands 1018 * @pe: addr of the page entry 1019 * @value: dst addr to write into pe 1020 * @count: number of page entries to update 1021 * @incr: increase next addr by incr bytes 1022 * 1023 * Update PTEs by writing them manually using sDMA. 1024 */ 1025 static void sdma_v6_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1026 uint64_t value, unsigned count, 1027 uint32_t incr) 1028 { 1029 unsigned ndw = count * 2; 1030 1031 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) | 1032 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1033 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1034 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1035 ib->ptr[ib->length_dw++] = ndw - 1; 1036 for (; ndw > 0; ndw -= 2) { 1037 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1038 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1039 value += incr; 1040 } 1041 } 1042 1043 /** 1044 * sdma_v6_0_vm_set_pte_pde - update the page tables using sDMA 1045 * 1046 * @ib: indirect buffer to fill with commands 1047 * @pe: addr of the page entry 1048 * @addr: dst addr to write into pe 1049 * @count: number of page entries to update 1050 * @incr: increase next addr by incr bytes 1051 * @flags: access flags 1052 * 1053 * Update the page tables using sDMA. 1054 */ 1055 static void sdma_v6_0_vm_set_pte_pde(struct amdgpu_ib *ib, 1056 uint64_t pe, 1057 uint64_t addr, unsigned count, 1058 uint32_t incr, uint64_t flags) 1059 { 1060 /* for physically contiguous pages (vram) */ 1061 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_PTEPDE); 1062 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1063 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1064 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1065 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1066 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1067 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1068 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1069 ib->ptr[ib->length_dw++] = 0; 1070 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1071 } 1072 1073 /* 1074 * sdma_v6_0_ring_pad_ib - pad the IB 1075 * @ib: indirect buffer to fill with padding 1076 * @ring: amdgpu ring pointer 1077 * 1078 * Pad the IB with NOPs to a boundary multiple of 8. 1079 */ 1080 static void sdma_v6_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1081 { 1082 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1083 u32 pad_count; 1084 int i; 1085 1086 pad_count = (-ib->length_dw) & 0x7; 1087 for (i = 0; i < pad_count; i++) 1088 if (sdma && sdma->burst_nop && (i == 0)) 1089 ib->ptr[ib->length_dw++] = 1090 SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP) | 1091 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1092 else 1093 ib->ptr[ib->length_dw++] = 1094 SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP); 1095 } 1096 1097 /** 1098 * sdma_v6_0_ring_emit_pipeline_sync - sync the pipeline 1099 * 1100 * @ring: amdgpu_ring pointer 1101 * 1102 * Make sure all previous operations are completed (CIK). 1103 */ 1104 static void sdma_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1105 { 1106 uint32_t seq = ring->fence_drv.sync_seq; 1107 uint64_t addr = ring->fence_drv.gpu_addr; 1108 1109 /* wait for idle */ 1110 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1111 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1112 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1113 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1114 amdgpu_ring_write(ring, addr & 0xfffffffc); 1115 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1116 amdgpu_ring_write(ring, seq); /* reference */ 1117 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 1118 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1119 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1120 } 1121 1122 /* 1123 * sdma_v6_0_ring_emit_vm_flush - vm flush using sDMA 1124 * 1125 * @ring: amdgpu_ring pointer 1126 * @vmid: vmid number to use 1127 * @pd_addr: address 1128 * 1129 * Update the page table base and flush the VM TLB 1130 * using sDMA. 1131 */ 1132 static void sdma_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1133 unsigned vmid, uint64_t pd_addr) 1134 { 1135 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 1136 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); 1137 1138 /* Update the PD address for this VMID. */ 1139 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 1140 (hub->ctx_addr_distance * vmid), 1141 lower_32_bits(pd_addr)); 1142 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 1143 (hub->ctx_addr_distance * vmid), 1144 upper_32_bits(pd_addr)); 1145 1146 /* Trigger invalidation. */ 1147 amdgpu_ring_write(ring, 1148 SDMA_PKT_VM_INVALIDATION_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1149 SDMA_PKT_VM_INVALIDATION_HEADER_SUB_OP(SDMA_SUBOP_VM_INVALIDATION) | 1150 SDMA_PKT_VM_INVALIDATION_HEADER_GFX_ENG_ID(ring->vm_inv_eng) | 1151 SDMA_PKT_VM_INVALIDATION_HEADER_MM_ENG_ID(0x1f)); 1152 amdgpu_ring_write(ring, req); 1153 amdgpu_ring_write(ring, 0xFFFFFFFF); 1154 amdgpu_ring_write(ring, 1155 SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_INVALIDATEACK(1 << vmid) | 1156 SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_ADDRESSRANGEHI(0x1F)); 1157 } 1158 1159 static void sdma_v6_0_ring_emit_wreg(struct amdgpu_ring *ring, 1160 uint32_t reg, uint32_t val) 1161 { 1162 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1163 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1164 amdgpu_ring_write(ring, reg); 1165 amdgpu_ring_write(ring, val); 1166 } 1167 1168 static void sdma_v6_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1169 uint32_t val, uint32_t mask) 1170 { 1171 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1172 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1173 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */ 1174 amdgpu_ring_write(ring, reg << 2); 1175 amdgpu_ring_write(ring, 0); 1176 amdgpu_ring_write(ring, val); /* reference */ 1177 amdgpu_ring_write(ring, mask); /* mask */ 1178 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1179 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); 1180 } 1181 1182 static void sdma_v6_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 1183 uint32_t reg0, uint32_t reg1, 1184 uint32_t ref, uint32_t mask) 1185 { 1186 amdgpu_ring_emit_wreg(ring, reg0, ref); 1187 /* wait for a cycle to reset vm_inv_eng*_ack */ 1188 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0); 1189 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); 1190 } 1191 1192 static struct amdgpu_sdma_ras sdma_v6_0_3_ras = { 1193 .ras_block = { 1194 .ras_late_init = amdgpu_ras_block_late_init, 1195 }, 1196 }; 1197 1198 static void sdma_v6_0_set_ras_funcs(struct amdgpu_device *adev) 1199 { 1200 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 1201 case IP_VERSION(6, 0, 3): 1202 adev->sdma.ras = &sdma_v6_0_3_ras; 1203 break; 1204 default: 1205 break; 1206 } 1207 } 1208 1209 static int sdma_v6_0_early_init(void *handle) 1210 { 1211 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1212 int r; 1213 1214 r = amdgpu_sdma_init_microcode(adev, 0, true); 1215 if (r) 1216 return r; 1217 1218 sdma_v6_0_set_ring_funcs(adev); 1219 sdma_v6_0_set_buffer_funcs(adev); 1220 sdma_v6_0_set_vm_pte_funcs(adev); 1221 sdma_v6_0_set_irq_funcs(adev); 1222 sdma_v6_0_set_mqd_funcs(adev); 1223 sdma_v6_0_set_ras_funcs(adev); 1224 1225 return 0; 1226 } 1227 1228 static int sdma_v6_0_sw_init(void *handle) 1229 { 1230 struct amdgpu_ring *ring; 1231 int r, i; 1232 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1233 1234 /* SDMA trap event */ 1235 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX, 1236 GFX_11_0_0__SRCID__SDMA_TRAP, 1237 &adev->sdma.trap_irq); 1238 if (r) 1239 return r; 1240 1241 for (i = 0; i < adev->sdma.num_instances; i++) { 1242 ring = &adev->sdma.instance[i].ring; 1243 ring->ring_obj = NULL; 1244 ring->use_doorbell = true; 1245 ring->me = i; 1246 1247 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i, 1248 ring->use_doorbell?"true":"false"); 1249 1250 ring->doorbell_index = 1251 (adev->doorbell_index.sdma_engine[i] << 1); // get DWORD offset 1252 1253 ring->vm_hub = AMDGPU_GFXHUB(0); 1254 sprintf(ring->name, "sdma%d", i); 1255 r = amdgpu_ring_init(adev, ring, 1024, 1256 &adev->sdma.trap_irq, 1257 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1258 AMDGPU_RING_PRIO_DEFAULT, NULL); 1259 if (r) 1260 return r; 1261 } 1262 1263 if (amdgpu_sdma_ras_sw_init(adev)) { 1264 dev_err(adev->dev, "Failed to initialize sdma ras block!\n"); 1265 return -EINVAL; 1266 } 1267 1268 return r; 1269 } 1270 1271 static int sdma_v6_0_sw_fini(void *handle) 1272 { 1273 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1274 int i; 1275 1276 for (i = 0; i < adev->sdma.num_instances; i++) 1277 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1278 1279 amdgpu_sdma_destroy_inst_ctx(adev, true); 1280 1281 return 0; 1282 } 1283 1284 static int sdma_v6_0_hw_init(void *handle) 1285 { 1286 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1287 1288 return sdma_v6_0_start(adev); 1289 } 1290 1291 static int sdma_v6_0_hw_fini(void *handle) 1292 { 1293 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1294 1295 if (amdgpu_sriov_vf(adev)) 1296 return 0; 1297 1298 sdma_v6_0_ctxempty_int_enable(adev, false); 1299 sdma_v6_0_enable(adev, false); 1300 1301 return 0; 1302 } 1303 1304 static int sdma_v6_0_suspend(void *handle) 1305 { 1306 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1307 1308 return sdma_v6_0_hw_fini(adev); 1309 } 1310 1311 static int sdma_v6_0_resume(void *handle) 1312 { 1313 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1314 1315 return sdma_v6_0_hw_init(adev); 1316 } 1317 1318 static bool sdma_v6_0_is_idle(void *handle) 1319 { 1320 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1321 u32 i; 1322 1323 for (i = 0; i < adev->sdma.num_instances; i++) { 1324 u32 tmp = RREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_STATUS_REG)); 1325 1326 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1327 return false; 1328 } 1329 1330 return true; 1331 } 1332 1333 static int sdma_v6_0_wait_for_idle(void *handle) 1334 { 1335 unsigned i; 1336 u32 sdma0, sdma1; 1337 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1338 1339 for (i = 0; i < adev->usec_timeout; i++) { 1340 sdma0 = RREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_STATUS_REG)); 1341 sdma1 = RREG32(sdma_v6_0_get_reg_offset(adev, 1, regSDMA0_STATUS_REG)); 1342 1343 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK) 1344 return 0; 1345 udelay(1); 1346 } 1347 return -ETIMEDOUT; 1348 } 1349 1350 static int sdma_v6_0_ring_preempt_ib(struct amdgpu_ring *ring) 1351 { 1352 int i, r = 0; 1353 struct amdgpu_device *adev = ring->adev; 1354 u32 index = 0; 1355 u64 sdma_gfx_preempt; 1356 1357 amdgpu_sdma_get_index_from_ring(ring, &index); 1358 sdma_gfx_preempt = 1359 sdma_v6_0_get_reg_offset(adev, index, regSDMA0_QUEUE0_PREEMPT); 1360 1361 /* assert preemption condition */ 1362 amdgpu_ring_set_preempt_cond_exec(ring, false); 1363 1364 /* emit the trailing fence */ 1365 ring->trail_seq += 1; 1366 amdgpu_ring_alloc(ring, 10); 1367 sdma_v6_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr, 1368 ring->trail_seq, 0); 1369 amdgpu_ring_commit(ring); 1370 1371 /* assert IB preemption */ 1372 WREG32(sdma_gfx_preempt, 1); 1373 1374 /* poll the trailing fence */ 1375 for (i = 0; i < adev->usec_timeout; i++) { 1376 if (ring->trail_seq == 1377 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 1378 break; 1379 udelay(1); 1380 } 1381 1382 if (i >= adev->usec_timeout) { 1383 r = -EINVAL; 1384 DRM_ERROR("ring %d failed to be preempted\n", ring->idx); 1385 } 1386 1387 /* deassert IB preemption */ 1388 WREG32(sdma_gfx_preempt, 0); 1389 1390 /* deassert the preemption condition */ 1391 amdgpu_ring_set_preempt_cond_exec(ring, true); 1392 return r; 1393 } 1394 1395 static int sdma_v6_0_set_trap_irq_state(struct amdgpu_device *adev, 1396 struct amdgpu_irq_src *source, 1397 unsigned type, 1398 enum amdgpu_interrupt_state state) 1399 { 1400 u32 sdma_cntl; 1401 1402 u32 reg_offset = sdma_v6_0_get_reg_offset(adev, type, regSDMA0_CNTL); 1403 1404 if (!amdgpu_sriov_vf(adev)) { 1405 sdma_cntl = RREG32(reg_offset); 1406 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1407 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1408 WREG32(reg_offset, sdma_cntl); 1409 } 1410 1411 return 0; 1412 } 1413 1414 static int sdma_v6_0_process_trap_irq(struct amdgpu_device *adev, 1415 struct amdgpu_irq_src *source, 1416 struct amdgpu_iv_entry *entry) 1417 { 1418 int instances, queue; 1419 uint32_t mes_queue_id = entry->src_data[0]; 1420 1421 DRM_DEBUG("IH: SDMA trap\n"); 1422 1423 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 1424 struct amdgpu_mes_queue *queue; 1425 1426 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 1427 1428 spin_lock(&adev->mes.queue_id_lock); 1429 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 1430 if (queue) { 1431 DRM_DEBUG("process smda queue id = %d\n", mes_queue_id); 1432 amdgpu_fence_process(queue->ring); 1433 } 1434 spin_unlock(&adev->mes.queue_id_lock); 1435 return 0; 1436 } 1437 1438 queue = entry->ring_id & 0xf; 1439 instances = (entry->ring_id & 0xf0) >> 4; 1440 if (instances > 1) { 1441 DRM_ERROR("IH: wrong ring_ID detected, as wrong sdma instance\n"); 1442 return -EINVAL; 1443 } 1444 1445 switch (entry->client_id) { 1446 case SOC21_IH_CLIENTID_GFX: 1447 switch (queue) { 1448 case 0: 1449 amdgpu_fence_process(&adev->sdma.instance[instances].ring); 1450 break; 1451 default: 1452 break; 1453 } 1454 break; 1455 } 1456 return 0; 1457 } 1458 1459 static int sdma_v6_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1460 struct amdgpu_irq_src *source, 1461 struct amdgpu_iv_entry *entry) 1462 { 1463 return 0; 1464 } 1465 1466 static int sdma_v6_0_set_clockgating_state(void *handle, 1467 enum amd_clockgating_state state) 1468 { 1469 return 0; 1470 } 1471 1472 static int sdma_v6_0_set_powergating_state(void *handle, 1473 enum amd_powergating_state state) 1474 { 1475 return 0; 1476 } 1477 1478 static void sdma_v6_0_get_clockgating_state(void *handle, u64 *flags) 1479 { 1480 } 1481 1482 const struct amd_ip_funcs sdma_v6_0_ip_funcs = { 1483 .name = "sdma_v6_0", 1484 .early_init = sdma_v6_0_early_init, 1485 .late_init = NULL, 1486 .sw_init = sdma_v6_0_sw_init, 1487 .sw_fini = sdma_v6_0_sw_fini, 1488 .hw_init = sdma_v6_0_hw_init, 1489 .hw_fini = sdma_v6_0_hw_fini, 1490 .suspend = sdma_v6_0_suspend, 1491 .resume = sdma_v6_0_resume, 1492 .is_idle = sdma_v6_0_is_idle, 1493 .wait_for_idle = sdma_v6_0_wait_for_idle, 1494 .soft_reset = sdma_v6_0_soft_reset, 1495 .check_soft_reset = sdma_v6_0_check_soft_reset, 1496 .set_clockgating_state = sdma_v6_0_set_clockgating_state, 1497 .set_powergating_state = sdma_v6_0_set_powergating_state, 1498 .get_clockgating_state = sdma_v6_0_get_clockgating_state, 1499 }; 1500 1501 static const struct amdgpu_ring_funcs sdma_v6_0_ring_funcs = { 1502 .type = AMDGPU_RING_TYPE_SDMA, 1503 .align_mask = 0xf, 1504 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1505 .support_64bit_ptrs = true, 1506 .secure_submission_supported = true, 1507 .get_rptr = sdma_v6_0_ring_get_rptr, 1508 .get_wptr = sdma_v6_0_ring_get_wptr, 1509 .set_wptr = sdma_v6_0_ring_set_wptr, 1510 .emit_frame_size = 1511 5 + /* sdma_v6_0_ring_init_cond_exec */ 1512 6 + /* sdma_v6_0_ring_emit_hdp_flush */ 1513 6 + /* sdma_v6_0_ring_emit_pipeline_sync */ 1514 /* sdma_v6_0_ring_emit_vm_flush */ 1515 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1516 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 1517 10 + 10 + 10, /* sdma_v6_0_ring_emit_fence x3 for user fence, vm fence */ 1518 .emit_ib_size = 5 + 7 + 6, /* sdma_v6_0_ring_emit_ib */ 1519 .emit_ib = sdma_v6_0_ring_emit_ib, 1520 .emit_mem_sync = sdma_v6_0_ring_emit_mem_sync, 1521 .emit_fence = sdma_v6_0_ring_emit_fence, 1522 .emit_pipeline_sync = sdma_v6_0_ring_emit_pipeline_sync, 1523 .emit_vm_flush = sdma_v6_0_ring_emit_vm_flush, 1524 .emit_hdp_flush = sdma_v6_0_ring_emit_hdp_flush, 1525 .test_ring = sdma_v6_0_ring_test_ring, 1526 .test_ib = sdma_v6_0_ring_test_ib, 1527 .insert_nop = sdma_v6_0_ring_insert_nop, 1528 .pad_ib = sdma_v6_0_ring_pad_ib, 1529 .emit_wreg = sdma_v6_0_ring_emit_wreg, 1530 .emit_reg_wait = sdma_v6_0_ring_emit_reg_wait, 1531 .emit_reg_write_reg_wait = sdma_v6_0_ring_emit_reg_write_reg_wait, 1532 .init_cond_exec = sdma_v6_0_ring_init_cond_exec, 1533 .preempt_ib = sdma_v6_0_ring_preempt_ib, 1534 }; 1535 1536 static void sdma_v6_0_set_ring_funcs(struct amdgpu_device *adev) 1537 { 1538 int i; 1539 1540 for (i = 0; i < adev->sdma.num_instances; i++) { 1541 adev->sdma.instance[i].ring.funcs = &sdma_v6_0_ring_funcs; 1542 adev->sdma.instance[i].ring.me = i; 1543 } 1544 } 1545 1546 static const struct amdgpu_irq_src_funcs sdma_v6_0_trap_irq_funcs = { 1547 .set = sdma_v6_0_set_trap_irq_state, 1548 .process = sdma_v6_0_process_trap_irq, 1549 }; 1550 1551 static const struct amdgpu_irq_src_funcs sdma_v6_0_illegal_inst_irq_funcs = { 1552 .process = sdma_v6_0_process_illegal_inst_irq, 1553 }; 1554 1555 static void sdma_v6_0_set_irq_funcs(struct amdgpu_device *adev) 1556 { 1557 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 + 1558 adev->sdma.num_instances; 1559 adev->sdma.trap_irq.funcs = &sdma_v6_0_trap_irq_funcs; 1560 adev->sdma.illegal_inst_irq.funcs = &sdma_v6_0_illegal_inst_irq_funcs; 1561 } 1562 1563 /** 1564 * sdma_v6_0_emit_copy_buffer - copy buffer using the sDMA engine 1565 * 1566 * @ib: indirect buffer to fill with commands 1567 * @src_offset: src GPU address 1568 * @dst_offset: dst GPU address 1569 * @byte_count: number of bytes to xfer 1570 * @tmz: if a secure copy should be used 1571 * 1572 * Copy GPU buffers using the DMA engine. 1573 * Used by the amdgpu ttm implementation to move pages if 1574 * registered as the asic copy callback. 1575 */ 1576 static void sdma_v6_0_emit_copy_buffer(struct amdgpu_ib *ib, 1577 uint64_t src_offset, 1578 uint64_t dst_offset, 1579 uint32_t byte_count, 1580 bool tmz) 1581 { 1582 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) | 1583 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 1584 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0); 1585 ib->ptr[ib->length_dw++] = byte_count - 1; 1586 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1587 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1588 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1589 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1590 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1591 } 1592 1593 /** 1594 * sdma_v6_0_emit_fill_buffer - fill buffer using the sDMA engine 1595 * 1596 * @ib: indirect buffer to fill 1597 * @src_data: value to write to buffer 1598 * @dst_offset: dst GPU address 1599 * @byte_count: number of bytes to xfer 1600 * 1601 * Fill GPU buffers using the DMA engine. 1602 */ 1603 static void sdma_v6_0_emit_fill_buffer(struct amdgpu_ib *ib, 1604 uint32_t src_data, 1605 uint64_t dst_offset, 1606 uint32_t byte_count) 1607 { 1608 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_CONST_FILL); 1609 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1610 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1611 ib->ptr[ib->length_dw++] = src_data; 1612 ib->ptr[ib->length_dw++] = byte_count - 1; 1613 } 1614 1615 static const struct amdgpu_buffer_funcs sdma_v6_0_buffer_funcs = { 1616 .copy_max_bytes = 0x400000, 1617 .copy_num_dw = 7, 1618 .emit_copy_buffer = sdma_v6_0_emit_copy_buffer, 1619 1620 .fill_max_bytes = 0x400000, 1621 .fill_num_dw = 5, 1622 .emit_fill_buffer = sdma_v6_0_emit_fill_buffer, 1623 }; 1624 1625 static void sdma_v6_0_set_buffer_funcs(struct amdgpu_device *adev) 1626 { 1627 adev->mman.buffer_funcs = &sdma_v6_0_buffer_funcs; 1628 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1629 } 1630 1631 static const struct amdgpu_vm_pte_funcs sdma_v6_0_vm_pte_funcs = { 1632 .copy_pte_num_dw = 7, 1633 .copy_pte = sdma_v6_0_vm_copy_pte, 1634 .write_pte = sdma_v6_0_vm_write_pte, 1635 .set_pte_pde = sdma_v6_0_vm_set_pte_pde, 1636 }; 1637 1638 static void sdma_v6_0_set_vm_pte_funcs(struct amdgpu_device *adev) 1639 { 1640 unsigned i; 1641 1642 adev->vm_manager.vm_pte_funcs = &sdma_v6_0_vm_pte_funcs; 1643 for (i = 0; i < adev->sdma.num_instances; i++) { 1644 adev->vm_manager.vm_pte_scheds[i] = 1645 &adev->sdma.instance[i].ring.sched; 1646 } 1647 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 1648 } 1649 1650 const struct amdgpu_ip_block_version sdma_v6_0_ip_block = { 1651 .type = AMD_IP_BLOCK_TYPE_SDMA, 1652 .major = 6, 1653 .minor = 0, 1654 .rev = 0, 1655 .funcs = &sdma_v6_0_ip_funcs, 1656 }; 1657