1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 33 #include "gc/gc_11_0_0_offset.h" 34 #include "gc/gc_11_0_0_sh_mask.h" 35 #include "gc/gc_11_0_0_default.h" 36 #include "hdp/hdp_6_0_0_offset.h" 37 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h" 38 39 #include "soc15_common.h" 40 #include "soc15.h" 41 #include "sdma_v6_0_0_pkt_open.h" 42 #include "nbio_v4_3.h" 43 #include "sdma_common.h" 44 #include "sdma_v6_0.h" 45 #include "v11_structs.h" 46 47 MODULE_FIRMWARE("amdgpu/sdma_6_0_0.bin"); 48 MODULE_FIRMWARE("amdgpu/sdma_6_0_1.bin"); 49 MODULE_FIRMWARE("amdgpu/sdma_6_0_2.bin"); 50 51 #define SDMA1_REG_OFFSET 0x600 52 #define SDMA0_HYP_DEC_REG_START 0x5880 53 #define SDMA0_HYP_DEC_REG_END 0x589a 54 #define SDMA1_HYP_DEC_REG_OFFSET 0x20 55 56 static void sdma_v6_0_set_ring_funcs(struct amdgpu_device *adev); 57 static void sdma_v6_0_set_buffer_funcs(struct amdgpu_device *adev); 58 static void sdma_v6_0_set_vm_pte_funcs(struct amdgpu_device *adev); 59 static void sdma_v6_0_set_irq_funcs(struct amdgpu_device *adev); 60 61 static u32 sdma_v6_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset) 62 { 63 u32 base; 64 65 if (internal_offset >= SDMA0_HYP_DEC_REG_START && 66 internal_offset <= SDMA0_HYP_DEC_REG_END) { 67 base = adev->reg_offset[GC_HWIP][0][1]; 68 if (instance != 0) 69 internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance; 70 } else { 71 base = adev->reg_offset[GC_HWIP][0][0]; 72 if (instance == 1) 73 internal_offset += SDMA1_REG_OFFSET; 74 } 75 76 return base + internal_offset; 77 } 78 79 static int sdma_v6_0_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst) 80 { 81 int err = 0; 82 const struct sdma_firmware_header_v2_0 *hdr; 83 84 err = amdgpu_ucode_validate(sdma_inst->fw); 85 if (err) 86 return err; 87 88 hdr = (const struct sdma_firmware_header_v2_0 *)sdma_inst->fw->data; 89 sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version); 90 sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version); 91 92 if (sdma_inst->feature_version >= 20) 93 sdma_inst->burst_nop = true; 94 95 return 0; 96 } 97 98 static void sdma_v6_0_destroy_inst_ctx(struct amdgpu_device *adev) 99 { 100 release_firmware(adev->sdma.instance[0].fw); 101 102 memset((void*)adev->sdma.instance, 0, 103 sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES); 104 } 105 106 /** 107 * sdma_v6_0_init_microcode - load ucode images from disk 108 * 109 * @adev: amdgpu_device pointer 110 * 111 * Use the firmware interface to load the ucode images into 112 * the driver (not loaded into hw). 113 * Returns 0 on success, error on failure. 114 */ 115 116 // emulation only, won't work on real chip 117 // sdma 6.0.0 real chip need to use PSP to load firmware 118 static int sdma_v6_0_init_microcode(struct amdgpu_device *adev) 119 { 120 char fw_name[30]; 121 char ucode_prefix[30]; 122 int err = 0, i; 123 struct amdgpu_firmware_info *info = NULL; 124 const struct sdma_firmware_header_v2_0 *sdma_hdr; 125 126 DRM_DEBUG("\n"); 127 128 amdgpu_ucode_ip_version_decode(adev, SDMA0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 129 130 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", ucode_prefix); 131 132 err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev); 133 if (err) 134 goto out; 135 136 err = sdma_v6_0_init_inst_ctx(&adev->sdma.instance[0]); 137 if (err) 138 goto out; 139 140 for (i = 1; i < adev->sdma.num_instances; i++) { 141 memcpy((void*)&adev->sdma.instance[i], 142 (void*)&adev->sdma.instance[0], 143 sizeof(struct amdgpu_sdma_instance)); 144 } 145 146 DRM_DEBUG("psp_load == '%s'\n", 147 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false"); 148 149 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 150 sdma_hdr = (const struct sdma_firmware_header_v2_0 *)adev->sdma.instance[0].fw->data; 151 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA_UCODE_TH0]; 152 info->ucode_id = AMDGPU_UCODE_ID_SDMA_UCODE_TH0; 153 info->fw = adev->sdma.instance[0].fw; 154 adev->firmware.fw_size += 155 ALIGN(le32_to_cpu(sdma_hdr->ctx_ucode_size_bytes), PAGE_SIZE); 156 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA_UCODE_TH1]; 157 info->ucode_id = AMDGPU_UCODE_ID_SDMA_UCODE_TH1; 158 info->fw = adev->sdma.instance[0].fw; 159 adev->firmware.fw_size += 160 ALIGN(le32_to_cpu(sdma_hdr->ctl_ucode_size_bytes), PAGE_SIZE); 161 } 162 163 out: 164 if (err) { 165 DRM_ERROR("sdma_v6_0: Failed to load firmware \"%s\"\n", fw_name); 166 sdma_v6_0_destroy_inst_ctx(adev); 167 } 168 return err; 169 } 170 171 static unsigned sdma_v6_0_ring_init_cond_exec(struct amdgpu_ring *ring) 172 { 173 unsigned ret; 174 175 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COND_EXE)); 176 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 177 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 178 amdgpu_ring_write(ring, 1); 179 ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */ 180 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */ 181 182 return ret; 183 } 184 185 static void sdma_v6_0_ring_patch_cond_exec(struct amdgpu_ring *ring, 186 unsigned offset) 187 { 188 unsigned cur; 189 190 BUG_ON(offset > ring->buf_mask); 191 BUG_ON(ring->ring[offset] != 0x55aa55aa); 192 193 cur = (ring->wptr - 1) & ring->buf_mask; 194 if (cur > offset) 195 ring->ring[offset] = cur - offset; 196 else 197 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 198 } 199 200 /** 201 * sdma_v6_0_ring_get_rptr - get the current read pointer 202 * 203 * @ring: amdgpu ring pointer 204 * 205 * Get the current rptr from the hardware. 206 */ 207 static uint64_t sdma_v6_0_ring_get_rptr(struct amdgpu_ring *ring) 208 { 209 u64 *rptr; 210 211 /* XXX check if swapping is necessary on BE */ 212 rptr = (u64 *)ring->rptr_cpu_addr; 213 214 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 215 return ((*rptr) >> 2); 216 } 217 218 /** 219 * sdma_v6_0_ring_get_wptr - get the current write pointer 220 * 221 * @ring: amdgpu ring pointer 222 * 223 * Get the current wptr from the hardware. 224 */ 225 static uint64_t sdma_v6_0_ring_get_wptr(struct amdgpu_ring *ring) 226 { 227 u64 wptr = 0; 228 229 if (ring->use_doorbell) { 230 /* XXX check if swapping is necessary on BE */ 231 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr)); 232 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 233 } 234 235 return wptr >> 2; 236 } 237 238 /** 239 * sdma_v6_0_ring_set_wptr - commit the write pointer 240 * 241 * @ring: amdgpu ring pointer 242 * 243 * Write the wptr back to the hardware. 244 */ 245 static void sdma_v6_0_ring_set_wptr(struct amdgpu_ring *ring) 246 { 247 struct amdgpu_device *adev = ring->adev; 248 249 DRM_DEBUG("Setting write pointer\n"); 250 if (ring->use_doorbell) { 251 DRM_DEBUG("Using doorbell -- " 252 "wptr_offs == 0x%08x " 253 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 254 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 255 ring->wptr_offs, 256 lower_32_bits(ring->wptr << 2), 257 upper_32_bits(ring->wptr << 2)); 258 /* XXX check if swapping is necessary on BE */ 259 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 260 ring->wptr << 2); 261 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 262 ring->doorbell_index, ring->wptr << 2); 263 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 264 } else { 265 DRM_DEBUG("Not using doorbell -- " 266 "regSDMA%i_GFX_RB_WPTR == 0x%08x " 267 "regSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 268 ring->me, 269 lower_32_bits(ring->wptr << 2), 270 ring->me, 271 upper_32_bits(ring->wptr << 2)); 272 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, ring->me, regSDMA0_QUEUE0_RB_WPTR), 273 lower_32_bits(ring->wptr << 2)); 274 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, ring->me, regSDMA0_QUEUE0_RB_WPTR_HI), 275 upper_32_bits(ring->wptr << 2)); 276 } 277 } 278 279 static void sdma_v6_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 280 { 281 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 282 int i; 283 284 for (i = 0; i < count; i++) 285 if (sdma && sdma->burst_nop && (i == 0)) 286 amdgpu_ring_write(ring, ring->funcs->nop | 287 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 288 else 289 amdgpu_ring_write(ring, ring->funcs->nop); 290 } 291 292 /** 293 * sdma_v6_0_ring_emit_ib - Schedule an IB on the DMA engine 294 * 295 * @ring: amdgpu ring pointer 296 * @ib: IB object to schedule 297 * 298 * Schedule an IB in the DMA ring. 299 */ 300 static void sdma_v6_0_ring_emit_ib(struct amdgpu_ring *ring, 301 struct amdgpu_job *job, 302 struct amdgpu_ib *ib, 303 uint32_t flags) 304 { 305 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 306 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid); 307 308 /* An IB packet must end on a 8 DW boundary--the next dword 309 * must be on a 8-dword boundary. Our IB packet below is 6 310 * dwords long, thus add x number of NOPs, such that, in 311 * modular arithmetic, 312 * wptr + 6 + x = 8k, k >= 0, which in C is, 313 * (wptr + 6 + x) % 8 = 0. 314 * The expression below, is a solution of x. 315 */ 316 sdma_v6_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 317 318 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_INDIRECT) | 319 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 320 /* base must be 32 byte aligned */ 321 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 322 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 323 amdgpu_ring_write(ring, ib->length_dw); 324 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); 325 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); 326 } 327 328 /** 329 * sdma_v6_0_ring_emit_mem_sync - flush the IB by graphics cache rinse 330 * 331 * @ring: amdgpu ring pointer 332 * @job: job to retrieve vmid from 333 * @ib: IB object to schedule 334 * 335 * flush the IB by graphics cache rinse. 336 */ 337 static void sdma_v6_0_ring_emit_mem_sync(struct amdgpu_ring *ring) 338 { 339 uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV | 340 SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV | 341 SDMA_GCR_GLI_INV(1); 342 343 /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */ 344 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_GCR_REQ)); 345 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0)); 346 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) | 347 SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0)); 348 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) | 349 SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16)); 350 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) | 351 SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0)); 352 } 353 354 355 /** 356 * sdma_v6_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 357 * 358 * @ring: amdgpu ring pointer 359 * 360 * Emit an hdp flush packet on the requested DMA ring. 361 */ 362 static void sdma_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 363 { 364 struct amdgpu_device *adev = ring->adev; 365 u32 ref_and_mask = 0; 366 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 367 368 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; 369 370 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) | 371 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 372 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 373 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2); 374 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2); 375 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 376 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 377 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 378 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 379 } 380 381 /** 382 * sdma_v6_0_ring_emit_fence - emit a fence on the DMA ring 383 * 384 * @ring: amdgpu ring pointer 385 * @fence: amdgpu fence object 386 * 387 * Add a DMA fence packet to the ring to write 388 * the fence seq number and DMA trap packet to generate 389 * an interrupt if needed. 390 */ 391 static void sdma_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 392 unsigned flags) 393 { 394 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 395 /* write the fence */ 396 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) | 397 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */ 398 /* zero in first two bits */ 399 BUG_ON(addr & 0x3); 400 amdgpu_ring_write(ring, lower_32_bits(addr)); 401 amdgpu_ring_write(ring, upper_32_bits(addr)); 402 amdgpu_ring_write(ring, lower_32_bits(seq)); 403 404 /* optionally write high bits as well */ 405 if (write64bit) { 406 addr += 4; 407 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) | 408 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); 409 /* zero in first two bits */ 410 BUG_ON(addr & 0x3); 411 amdgpu_ring_write(ring, lower_32_bits(addr)); 412 amdgpu_ring_write(ring, upper_32_bits(addr)); 413 amdgpu_ring_write(ring, upper_32_bits(seq)); 414 } 415 416 if (flags & AMDGPU_FENCE_FLAG_INT) { 417 uint32_t ctx = ring->is_mes_queue ? 418 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0; 419 /* generate an interrupt */ 420 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_TRAP)); 421 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(ctx)); 422 } 423 } 424 425 /** 426 * sdma_v6_0_gfx_stop - stop the gfx async dma engines 427 * 428 * @adev: amdgpu_device pointer 429 * 430 * Stop the gfx async dma ring buffers. 431 */ 432 static void sdma_v6_0_gfx_stop(struct amdgpu_device *adev) 433 { 434 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; 435 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; 436 u32 rb_cntl, ib_cntl; 437 int i; 438 439 if ((adev->mman.buffer_funcs_ring == sdma0) || 440 (adev->mman.buffer_funcs_ring == sdma1)) 441 amdgpu_ttm_set_buffer_funcs_status(adev, false); 442 443 for (i = 0; i < adev->sdma.num_instances; i++) { 444 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL)); 445 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 0); 446 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); 447 ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL)); 448 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 0); 449 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl); 450 } 451 452 sdma0->sched.ready = false; 453 sdma1->sched.ready = false; 454 } 455 456 /** 457 * sdma_v6_0_rlc_stop - stop the compute async dma engines 458 * 459 * @adev: amdgpu_device pointer 460 * 461 * Stop the compute async dma queues. 462 */ 463 static void sdma_v6_0_rlc_stop(struct amdgpu_device *adev) 464 { 465 /* XXX todo */ 466 } 467 468 /** 469 * sdma_v6_0_ctx_switch_enable - stop the async dma engines context switch 470 * 471 * @adev: amdgpu_device pointer 472 * @enable: enable/disable the DMA MEs context switch. 473 * 474 * Halt or unhalt the async dma engines context switch. 475 */ 476 static void sdma_v6_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 477 { 478 } 479 480 /** 481 * sdma_v6_0_enable - stop the async dma engines 482 * 483 * @adev: amdgpu_device pointer 484 * @enable: enable/disable the DMA MEs. 485 * 486 * Halt or unhalt the async dma engines. 487 */ 488 static void sdma_v6_0_enable(struct amdgpu_device *adev, bool enable) 489 { 490 u32 f32_cntl; 491 int i; 492 493 if (!enable) { 494 sdma_v6_0_gfx_stop(adev); 495 sdma_v6_0_rlc_stop(adev); 496 } 497 498 for (i = 0; i < adev->sdma.num_instances; i++) { 499 f32_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL)); 500 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 501 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), f32_cntl); 502 } 503 } 504 505 /** 506 * sdma_v6_0_gfx_resume - setup and start the async dma engines 507 * 508 * @adev: amdgpu_device pointer 509 * 510 * Set up the gfx DMA ring buffers and enable them. 511 * Returns 0 for success, error for failure. 512 */ 513 static int sdma_v6_0_gfx_resume(struct amdgpu_device *adev) 514 { 515 struct amdgpu_ring *ring; 516 u32 rb_cntl, ib_cntl; 517 u32 rb_bufsz; 518 u32 doorbell; 519 u32 doorbell_offset; 520 u32 temp; 521 u64 wptr_gpu_addr; 522 int i, r; 523 524 for (i = 0; i < adev->sdma.num_instances; i++) { 525 ring = &adev->sdma.instance[i].ring; 526 527 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); 528 529 /* Set ring buffer size in dwords */ 530 rb_bufsz = order_base_2(ring->ring_size / 4); 531 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL)); 532 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz); 533 #ifdef __BIG_ENDIAN 534 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SWAP_ENABLE, 1); 535 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, 536 RPTR_WRITEBACK_SWAP_ENABLE, 1); 537 #endif 538 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_PRIV, 1); 539 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); 540 541 /* Initialize the ring buffer's read and write pointers */ 542 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0); 543 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), 0); 544 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0); 545 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), 0); 546 547 /* setup the wptr shadow polling */ 548 wptr_gpu_addr = ring->wptr_gpu_addr; 549 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO), 550 lower_32_bits(wptr_gpu_addr)); 551 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI), 552 upper_32_bits(wptr_gpu_addr)); 553 554 /* set the wb address whether it's enabled or not */ 555 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_HI), 556 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); 557 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_LO), 558 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); 559 560 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 561 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 0); 562 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, F32_WPTR_POLL_ENABLE, 1); 563 564 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE), ring->gpu_addr >> 8); 565 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40); 566 567 ring->wptr = 0; 568 569 /* before programing wptr to a less value, need set minor_ptr_update first */ 570 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 1); 571 572 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ 573 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2); 574 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2); 575 } 576 577 doorbell = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL)); 578 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET)); 579 580 if (ring->use_doorbell) { 581 doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 1); 582 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_QUEUE0_DOORBELL_OFFSET, 583 OFFSET, ring->doorbell_index); 584 } else { 585 doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 0); 586 } 587 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL), doorbell); 588 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET), doorbell_offset); 589 590 if (i == 0) 591 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, 592 ring->doorbell_index, 593 adev->doorbell_index.sdma_doorbell_range * adev->sdma.num_instances); 594 595 if (amdgpu_sriov_vf(adev)) 596 sdma_v6_0_ring_set_wptr(ring); 597 598 /* set minor_ptr_update to 0 after wptr programed */ 599 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 0); 600 601 /* Set up RESP_MODE to non-copy addresses */ 602 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL)); 603 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3); 604 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9); 605 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL), temp); 606 607 /* program default cache read and write policy */ 608 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE)); 609 /* clean read policy and write policy bits */ 610 temp &= 0xFF0FFF; 611 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | 612 (CACHE_WRITE_POLICY_L2__DEFAULT << 14) | 613 SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK); 614 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE), temp); 615 616 if (!amdgpu_sriov_vf(adev)) { 617 /* unhalt engine */ 618 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL)); 619 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 620 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, TH1_RESET, 0); 621 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), temp); 622 } 623 624 /* enable DMA RB */ 625 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 1); 626 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); 627 628 ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL)); 629 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 1); 630 #ifdef __BIG_ENDIAN 631 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_SWAP_ENABLE, 1); 632 #endif 633 /* enable DMA IBs */ 634 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl); 635 636 ring->sched.ready = true; 637 638 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */ 639 sdma_v6_0_ctx_switch_enable(adev, true); 640 sdma_v6_0_enable(adev, true); 641 } 642 643 r = amdgpu_ring_test_helper(ring); 644 if (r) { 645 ring->sched.ready = false; 646 return r; 647 } 648 649 if (adev->mman.buffer_funcs_ring == ring) 650 amdgpu_ttm_set_buffer_funcs_status(adev, true); 651 } 652 653 return 0; 654 } 655 656 /** 657 * sdma_v6_0_rlc_resume - setup and start the async dma engines 658 * 659 * @adev: amdgpu_device pointer 660 * 661 * Set up the compute DMA queues and enable them. 662 * Returns 0 for success, error for failure. 663 */ 664 static int sdma_v6_0_rlc_resume(struct amdgpu_device *adev) 665 { 666 return 0; 667 } 668 669 /** 670 * sdma_v6_0_load_microcode - load the sDMA ME ucode 671 * 672 * @adev: amdgpu_device pointer 673 * 674 * Loads the sDMA0/1 ucode. 675 * Returns 0 for success, -EINVAL if the ucode is not available. 676 */ 677 static int sdma_v6_0_load_microcode(struct amdgpu_device *adev) 678 { 679 const struct sdma_firmware_header_v2_0 *hdr; 680 const __le32 *fw_data; 681 u32 fw_size; 682 int i, j; 683 bool use_broadcast; 684 685 /* halt the MEs */ 686 sdma_v6_0_enable(adev, false); 687 688 if (!adev->sdma.instance[0].fw) 689 return -EINVAL; 690 691 /* use broadcast mode to load SDMA microcode by default */ 692 use_broadcast = true; 693 694 if (use_broadcast) { 695 dev_info(adev->dev, "Use broadcast method to load SDMA firmware\n"); 696 /* load Control Thread microcode */ 697 hdr = (const struct sdma_firmware_header_v2_0 *)adev->sdma.instance[0].fw->data; 698 amdgpu_ucode_print_sdma_hdr(&hdr->header); 699 fw_size = le32_to_cpu(hdr->ctx_jt_offset + hdr->ctx_jt_size) / 4; 700 701 fw_data = (const __le32 *) 702 (adev->sdma.instance[0].fw->data + 703 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 704 705 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_ADDR), 0); 706 707 for (j = 0; j < fw_size; j++) { 708 if (amdgpu_emu_mode == 1 && j % 500 == 0) 709 msleep(1); 710 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_DATA), le32_to_cpup(fw_data++)); 711 } 712 713 /* load Context Switch microcode */ 714 fw_size = le32_to_cpu(hdr->ctl_jt_offset + hdr->ctl_jt_size) / 4; 715 716 fw_data = (const __le32 *) 717 (adev->sdma.instance[0].fw->data + 718 le32_to_cpu(hdr->ctl_ucode_offset)); 719 720 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_ADDR), 0x8000); 721 722 for (j = 0; j < fw_size; j++) { 723 if (amdgpu_emu_mode == 1 && j % 500 == 0) 724 msleep(1); 725 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_DATA), le32_to_cpup(fw_data++)); 726 } 727 } else { 728 dev_info(adev->dev, "Use legacy method to load SDMA firmware\n"); 729 for (i = 0; i < adev->sdma.num_instances; i++) { 730 /* load Control Thread microcode */ 731 hdr = (const struct sdma_firmware_header_v2_0 *)adev->sdma.instance[0].fw->data; 732 amdgpu_ucode_print_sdma_hdr(&hdr->header); 733 fw_size = le32_to_cpu(hdr->ctx_jt_offset + hdr->ctx_jt_size) / 4; 734 735 fw_data = (const __le32 *) 736 (adev->sdma.instance[0].fw->data + 737 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 738 739 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), 0); 740 741 for (j = 0; j < fw_size; j++) { 742 if (amdgpu_emu_mode == 1 && j % 500 == 0) 743 msleep(1); 744 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); 745 } 746 747 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), adev->sdma.instance[0].fw_version); 748 749 /* load Context Switch microcode */ 750 fw_size = le32_to_cpu(hdr->ctl_jt_offset + hdr->ctl_jt_size) / 4; 751 752 fw_data = (const __le32 *) 753 (adev->sdma.instance[0].fw->data + 754 le32_to_cpu(hdr->ctl_ucode_offset)); 755 756 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), 0x8000); 757 758 for (j = 0; j < fw_size; j++) { 759 if (amdgpu_emu_mode == 1 && j % 500 == 0) 760 msleep(1); 761 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); 762 } 763 764 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), adev->sdma.instance[0].fw_version); 765 } 766 } 767 768 return 0; 769 } 770 771 static int sdma_v6_0_soft_reset(void *handle) 772 { 773 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 774 u32 grbm_soft_reset; 775 u32 tmp; 776 int i; 777 778 for (i = 0; i < adev->sdma.num_instances; i++) { 779 grbm_soft_reset = REG_SET_FIELD(0, 780 GRBM_SOFT_RESET, SOFT_RESET_SDMA0, 781 1); 782 grbm_soft_reset <<= i; 783 784 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 785 tmp |= grbm_soft_reset; 786 DRM_DEBUG("GRBM_SOFT_RESET=0x%08X\n", tmp); 787 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp); 788 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 789 790 udelay(50); 791 792 tmp &= ~grbm_soft_reset; 793 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp); 794 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 795 796 udelay(50); 797 } 798 799 return 0; 800 } 801 802 /** 803 * sdma_v6_0_start - setup and start the async dma engines 804 * 805 * @adev: amdgpu_device pointer 806 * 807 * Set up the DMA engines and enable them. 808 * Returns 0 for success, error for failure. 809 */ 810 static int sdma_v6_0_start(struct amdgpu_device *adev) 811 { 812 int r = 0; 813 814 if (amdgpu_sriov_vf(adev)) { 815 sdma_v6_0_ctx_switch_enable(adev, false); 816 sdma_v6_0_enable(adev, false); 817 818 /* set RB registers */ 819 r = sdma_v6_0_gfx_resume(adev); 820 return r; 821 } 822 823 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 824 r = sdma_v6_0_load_microcode(adev); 825 if (r) 826 return r; 827 828 /* The value of regSDMA_F32_CNTL is invalid the moment after loading fw */ 829 if (amdgpu_emu_mode == 1) 830 msleep(1000); 831 } 832 833 sdma_v6_0_soft_reset(adev); 834 /* unhalt the MEs */ 835 sdma_v6_0_enable(adev, true); 836 /* enable sdma ring preemption */ 837 sdma_v6_0_ctx_switch_enable(adev, true); 838 839 /* start the gfx rings and rlc compute queues */ 840 r = sdma_v6_0_gfx_resume(adev); 841 if (r) 842 return r; 843 r = sdma_v6_0_rlc_resume(adev); 844 845 return r; 846 } 847 848 static int sdma_v6_0_mqd_init(struct amdgpu_device *adev, void *mqd, 849 struct amdgpu_mqd_prop *prop) 850 { 851 struct v11_sdma_mqd *m = mqd; 852 uint64_t wb_gpu_addr; 853 854 m->sdmax_rlcx_rb_cntl = 855 order_base_2(prop->queue_size / 4) << SDMA0_QUEUE0_RB_CNTL__RB_SIZE__SHIFT | 856 1 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 857 4 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT; 858 859 m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8); 860 m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8); 861 862 wb_gpu_addr = prop->wptr_gpu_addr; 863 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr); 864 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr); 865 866 wb_gpu_addr = prop->rptr_gpu_addr; 867 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr); 868 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr); 869 870 m->sdmax_rlcx_ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, 0, 871 regSDMA0_QUEUE0_IB_CNTL)); 872 873 m->sdmax_rlcx_doorbell_offset = 874 prop->doorbell_index << SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT; 875 876 m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_QUEUE0_DOORBELL, ENABLE, 1); 877 878 m->sdmax_rlcx_skip_cntl = 0; 879 m->sdmax_rlcx_context_status = 0; 880 m->sdmax_rlcx_doorbell_log = 0; 881 882 m->sdmax_rlcx_rb_aql_cntl = regSDMA0_QUEUE0_RB_AQL_CNTL_DEFAULT; 883 m->sdmax_rlcx_dummy_reg = regSDMA0_QUEUE0_DUMMY_REG_DEFAULT; 884 885 return 0; 886 } 887 888 static void sdma_v6_0_set_mqd_funcs(struct amdgpu_device *adev) 889 { 890 adev->mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v11_sdma_mqd); 891 adev->mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v6_0_mqd_init; 892 } 893 894 /** 895 * sdma_v6_0_ring_test_ring - simple async dma engine test 896 * 897 * @ring: amdgpu_ring structure holding ring information 898 * 899 * Test the DMA engine by writing using it to write an 900 * value to memory. 901 * Returns 0 for success, error for failure. 902 */ 903 static int sdma_v6_0_ring_test_ring(struct amdgpu_ring *ring) 904 { 905 struct amdgpu_device *adev = ring->adev; 906 unsigned i; 907 unsigned index; 908 int r; 909 u32 tmp; 910 u64 gpu_addr; 911 volatile uint32_t *cpu_ptr = NULL; 912 913 tmp = 0xCAFEDEAD; 914 915 if (ring->is_mes_queue) { 916 uint32_t offset = 0; 917 offset = amdgpu_mes_ctx_get_offs(ring, 918 AMDGPU_MES_CTX_PADDING_OFFS); 919 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 920 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 921 *cpu_ptr = tmp; 922 } else { 923 r = amdgpu_device_wb_get(adev, &index); 924 if (r) { 925 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 926 return r; 927 } 928 929 gpu_addr = adev->wb.gpu_addr + (index * 4); 930 adev->wb.wb[index] = cpu_to_le32(tmp); 931 } 932 933 r = amdgpu_ring_alloc(ring, 5); 934 if (r) { 935 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 936 amdgpu_device_wb_free(adev, index); 937 return r; 938 } 939 940 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) | 941 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 942 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 943 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 944 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 945 amdgpu_ring_write(ring, 0xDEADBEEF); 946 amdgpu_ring_commit(ring); 947 948 for (i = 0; i < adev->usec_timeout; i++) { 949 if (ring->is_mes_queue) 950 tmp = le32_to_cpu(*cpu_ptr); 951 else 952 tmp = le32_to_cpu(adev->wb.wb[index]); 953 if (tmp == 0xDEADBEEF) 954 break; 955 if (amdgpu_emu_mode == 1) 956 msleep(1); 957 else 958 udelay(1); 959 } 960 961 if (i >= adev->usec_timeout) 962 r = -ETIMEDOUT; 963 964 if (!ring->is_mes_queue) 965 amdgpu_device_wb_free(adev, index); 966 967 return r; 968 } 969 970 /** 971 * sdma_v6_0_ring_test_ib - test an IB on the DMA engine 972 * 973 * @ring: amdgpu_ring structure holding ring information 974 * 975 * Test a simple IB in the DMA ring. 976 * Returns 0 on success, error on failure. 977 */ 978 static int sdma_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 979 { 980 struct amdgpu_device *adev = ring->adev; 981 struct amdgpu_ib ib; 982 struct dma_fence *f = NULL; 983 unsigned index; 984 long r; 985 u32 tmp = 0; 986 u64 gpu_addr; 987 volatile uint32_t *cpu_ptr = NULL; 988 989 tmp = 0xCAFEDEAD; 990 memset(&ib, 0, sizeof(ib)); 991 992 if (ring->is_mes_queue) { 993 uint32_t offset = 0; 994 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS); 995 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 996 ib.ptr = (void *)amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 997 998 offset = amdgpu_mes_ctx_get_offs(ring, 999 AMDGPU_MES_CTX_PADDING_OFFS); 1000 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 1001 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 1002 *cpu_ptr = tmp; 1003 } else { 1004 r = amdgpu_device_wb_get(adev, &index); 1005 if (r) { 1006 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 1007 return r; 1008 } 1009 1010 gpu_addr = adev->wb.gpu_addr + (index * 4); 1011 adev->wb.wb[index] = cpu_to_le32(tmp); 1012 1013 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib); 1014 if (r) { 1015 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 1016 goto err0; 1017 } 1018 } 1019 1020 ib.ptr[0] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) | 1021 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1022 ib.ptr[1] = lower_32_bits(gpu_addr); 1023 ib.ptr[2] = upper_32_bits(gpu_addr); 1024 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 1025 ib.ptr[4] = 0xDEADBEEF; 1026 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1027 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1028 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1029 ib.length_dw = 8; 1030 1031 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1032 if (r) 1033 goto err1; 1034 1035 r = dma_fence_wait_timeout(f, false, timeout); 1036 if (r == 0) { 1037 DRM_ERROR("amdgpu: IB test timed out\n"); 1038 r = -ETIMEDOUT; 1039 goto err1; 1040 } else if (r < 0) { 1041 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 1042 goto err1; 1043 } 1044 1045 if (ring->is_mes_queue) 1046 tmp = le32_to_cpu(*cpu_ptr); 1047 else 1048 tmp = le32_to_cpu(adev->wb.wb[index]); 1049 1050 if (tmp == 0xDEADBEEF) 1051 r = 0; 1052 else 1053 r = -EINVAL; 1054 1055 err1: 1056 amdgpu_ib_free(adev, &ib, NULL); 1057 dma_fence_put(f); 1058 err0: 1059 if (!ring->is_mes_queue) 1060 amdgpu_device_wb_free(adev, index); 1061 return r; 1062 } 1063 1064 1065 /** 1066 * sdma_v6_0_vm_copy_pte - update PTEs by copying them from the GART 1067 * 1068 * @ib: indirect buffer to fill with commands 1069 * @pe: addr of the page entry 1070 * @src: src addr to copy from 1071 * @count: number of page entries to update 1072 * 1073 * Update PTEs by copying them from the GART using sDMA. 1074 */ 1075 static void sdma_v6_0_vm_copy_pte(struct amdgpu_ib *ib, 1076 uint64_t pe, uint64_t src, 1077 unsigned count) 1078 { 1079 unsigned bytes = count * 8; 1080 1081 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) | 1082 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1083 ib->ptr[ib->length_dw++] = bytes - 1; 1084 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1085 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1086 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1087 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1088 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1089 1090 } 1091 1092 /** 1093 * sdma_v6_0_vm_write_pte - update PTEs by writing them manually 1094 * 1095 * @ib: indirect buffer to fill with commands 1096 * @pe: addr of the page entry 1097 * @addr: dst addr to write into pe 1098 * @count: number of page entries to update 1099 * @incr: increase next addr by incr bytes 1100 * @flags: access flags 1101 * 1102 * Update PTEs by writing them manually using sDMA. 1103 */ 1104 static void sdma_v6_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1105 uint64_t value, unsigned count, 1106 uint32_t incr) 1107 { 1108 unsigned ndw = count * 2; 1109 1110 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) | 1111 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1112 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1113 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1114 ib->ptr[ib->length_dw++] = ndw - 1; 1115 for (; ndw > 0; ndw -= 2) { 1116 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1117 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1118 value += incr; 1119 } 1120 } 1121 1122 /** 1123 * sdma_v6_0_vm_set_pte_pde - update the page tables using sDMA 1124 * 1125 * @ib: indirect buffer to fill with commands 1126 * @pe: addr of the page entry 1127 * @addr: dst addr to write into pe 1128 * @count: number of page entries to update 1129 * @incr: increase next addr by incr bytes 1130 * @flags: access flags 1131 * 1132 * Update the page tables using sDMA. 1133 */ 1134 static void sdma_v6_0_vm_set_pte_pde(struct amdgpu_ib *ib, 1135 uint64_t pe, 1136 uint64_t addr, unsigned count, 1137 uint32_t incr, uint64_t flags) 1138 { 1139 /* for physically contiguous pages (vram) */ 1140 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_PTEPDE); 1141 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1142 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1143 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1144 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1145 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1146 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1147 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1148 ib->ptr[ib->length_dw++] = 0; 1149 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1150 } 1151 1152 /** 1153 * sdma_v6_0_ring_pad_ib - pad the IB 1154 * @ib: indirect buffer to fill with padding 1155 * 1156 * Pad the IB with NOPs to a boundary multiple of 8. 1157 */ 1158 static void sdma_v6_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1159 { 1160 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1161 u32 pad_count; 1162 int i; 1163 1164 pad_count = (-ib->length_dw) & 0x7; 1165 for (i = 0; i < pad_count; i++) 1166 if (sdma && sdma->burst_nop && (i == 0)) 1167 ib->ptr[ib->length_dw++] = 1168 SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP) | 1169 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1170 else 1171 ib->ptr[ib->length_dw++] = 1172 SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP); 1173 } 1174 1175 /** 1176 * sdma_v6_0_ring_emit_pipeline_sync - sync the pipeline 1177 * 1178 * @ring: amdgpu_ring pointer 1179 * 1180 * Make sure all previous operations are completed (CIK). 1181 */ 1182 static void sdma_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1183 { 1184 uint32_t seq = ring->fence_drv.sync_seq; 1185 uint64_t addr = ring->fence_drv.gpu_addr; 1186 1187 /* wait for idle */ 1188 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1189 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1190 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1191 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1192 amdgpu_ring_write(ring, addr & 0xfffffffc); 1193 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1194 amdgpu_ring_write(ring, seq); /* reference */ 1195 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 1196 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1197 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1198 } 1199 1200 /** 1201 * sdma_v6_0_ring_emit_vm_flush - vm flush using sDMA 1202 * 1203 * @ring: amdgpu_ring pointer 1204 * @vm: amdgpu_vm pointer 1205 * 1206 * Update the page table base and flush the VM TLB 1207 * using sDMA. 1208 */ 1209 static void sdma_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1210 unsigned vmid, uint64_t pd_addr) 1211 { 1212 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1213 } 1214 1215 static void sdma_v6_0_ring_emit_wreg(struct amdgpu_ring *ring, 1216 uint32_t reg, uint32_t val) 1217 { 1218 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1219 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1220 amdgpu_ring_write(ring, reg); 1221 amdgpu_ring_write(ring, val); 1222 } 1223 1224 static void sdma_v6_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1225 uint32_t val, uint32_t mask) 1226 { 1227 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1228 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1229 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */ 1230 amdgpu_ring_write(ring, reg << 2); 1231 amdgpu_ring_write(ring, 0); 1232 amdgpu_ring_write(ring, val); /* reference */ 1233 amdgpu_ring_write(ring, mask); /* mask */ 1234 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1235 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); 1236 } 1237 1238 static void sdma_v6_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 1239 uint32_t reg0, uint32_t reg1, 1240 uint32_t ref, uint32_t mask) 1241 { 1242 amdgpu_ring_emit_wreg(ring, reg0, ref); 1243 /* wait for a cycle to reset vm_inv_eng*_ack */ 1244 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0); 1245 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); 1246 } 1247 1248 static int sdma_v6_0_early_init(void *handle) 1249 { 1250 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1251 1252 sdma_v6_0_set_ring_funcs(adev); 1253 sdma_v6_0_set_buffer_funcs(adev); 1254 sdma_v6_0_set_vm_pte_funcs(adev); 1255 sdma_v6_0_set_irq_funcs(adev); 1256 sdma_v6_0_set_mqd_funcs(adev); 1257 1258 return 0; 1259 } 1260 1261 static int sdma_v6_0_sw_init(void *handle) 1262 { 1263 struct amdgpu_ring *ring; 1264 int r, i; 1265 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1266 1267 /* SDMA trap event */ 1268 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX, 1269 GFX_11_0_0__SRCID__SDMA_TRAP, 1270 &adev->sdma.trap_irq); 1271 if (r) 1272 return r; 1273 1274 r = sdma_v6_0_init_microcode(adev); 1275 if (r) { 1276 DRM_ERROR("Failed to load sdma firmware!\n"); 1277 return r; 1278 } 1279 1280 for (i = 0; i < adev->sdma.num_instances; i++) { 1281 ring = &adev->sdma.instance[i].ring; 1282 ring->ring_obj = NULL; 1283 ring->use_doorbell = true; 1284 ring->me = i; 1285 1286 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i, 1287 ring->use_doorbell?"true":"false"); 1288 1289 ring->doorbell_index = 1290 (adev->doorbell_index.sdma_engine[i] << 1); // get DWORD offset 1291 1292 sprintf(ring->name, "sdma%d", i); 1293 r = amdgpu_ring_init(adev, ring, 1024, 1294 &adev->sdma.trap_irq, 1295 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1296 AMDGPU_RING_PRIO_DEFAULT, NULL); 1297 if (r) 1298 return r; 1299 } 1300 1301 return r; 1302 } 1303 1304 static int sdma_v6_0_sw_fini(void *handle) 1305 { 1306 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1307 int i; 1308 1309 for (i = 0; i < adev->sdma.num_instances; i++) 1310 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1311 1312 sdma_v6_0_destroy_inst_ctx(adev); 1313 1314 return 0; 1315 } 1316 1317 static int sdma_v6_0_hw_init(void *handle) 1318 { 1319 int r; 1320 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1321 1322 r = sdma_v6_0_start(adev); 1323 1324 return r; 1325 } 1326 1327 static int sdma_v6_0_hw_fini(void *handle) 1328 { 1329 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1330 1331 if (amdgpu_sriov_vf(adev)) 1332 return 0; 1333 1334 sdma_v6_0_ctx_switch_enable(adev, false); 1335 sdma_v6_0_enable(adev, false); 1336 1337 return 0; 1338 } 1339 1340 static int sdma_v6_0_suspend(void *handle) 1341 { 1342 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1343 1344 return sdma_v6_0_hw_fini(adev); 1345 } 1346 1347 static int sdma_v6_0_resume(void *handle) 1348 { 1349 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1350 1351 return sdma_v6_0_hw_init(adev); 1352 } 1353 1354 static bool sdma_v6_0_is_idle(void *handle) 1355 { 1356 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1357 u32 i; 1358 1359 for (i = 0; i < adev->sdma.num_instances; i++) { 1360 u32 tmp = RREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_STATUS_REG)); 1361 1362 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1363 return false; 1364 } 1365 1366 return true; 1367 } 1368 1369 static int sdma_v6_0_wait_for_idle(void *handle) 1370 { 1371 unsigned i; 1372 u32 sdma0, sdma1; 1373 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1374 1375 for (i = 0; i < adev->usec_timeout; i++) { 1376 sdma0 = RREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_STATUS_REG)); 1377 sdma1 = RREG32(sdma_v6_0_get_reg_offset(adev, 1, regSDMA0_STATUS_REG)); 1378 1379 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK) 1380 return 0; 1381 udelay(1); 1382 } 1383 return -ETIMEDOUT; 1384 } 1385 1386 static int sdma_v6_0_ring_preempt_ib(struct amdgpu_ring *ring) 1387 { 1388 int i, r = 0; 1389 struct amdgpu_device *adev = ring->adev; 1390 u32 index = 0; 1391 u64 sdma_gfx_preempt; 1392 1393 amdgpu_sdma_get_index_from_ring(ring, &index); 1394 sdma_gfx_preempt = 1395 sdma_v6_0_get_reg_offset(adev, index, regSDMA0_QUEUE0_PREEMPT); 1396 1397 /* assert preemption condition */ 1398 amdgpu_ring_set_preempt_cond_exec(ring, false); 1399 1400 /* emit the trailing fence */ 1401 ring->trail_seq += 1; 1402 amdgpu_ring_alloc(ring, 10); 1403 sdma_v6_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr, 1404 ring->trail_seq, 0); 1405 amdgpu_ring_commit(ring); 1406 1407 /* assert IB preemption */ 1408 WREG32(sdma_gfx_preempt, 1); 1409 1410 /* poll the trailing fence */ 1411 for (i = 0; i < adev->usec_timeout; i++) { 1412 if (ring->trail_seq == 1413 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 1414 break; 1415 udelay(1); 1416 } 1417 1418 if (i >= adev->usec_timeout) { 1419 r = -EINVAL; 1420 DRM_ERROR("ring %d failed to be preempted\n", ring->idx); 1421 } 1422 1423 /* deassert IB preemption */ 1424 WREG32(sdma_gfx_preempt, 0); 1425 1426 /* deassert the preemption condition */ 1427 amdgpu_ring_set_preempt_cond_exec(ring, true); 1428 return r; 1429 } 1430 1431 static int sdma_v6_0_set_trap_irq_state(struct amdgpu_device *adev, 1432 struct amdgpu_irq_src *source, 1433 unsigned type, 1434 enum amdgpu_interrupt_state state) 1435 { 1436 u32 sdma_cntl; 1437 1438 u32 reg_offset = sdma_v6_0_get_reg_offset(adev, type, regSDMA0_CNTL); 1439 1440 sdma_cntl = RREG32(reg_offset); 1441 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1442 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1443 WREG32(reg_offset, sdma_cntl); 1444 1445 return 0; 1446 } 1447 1448 static int sdma_v6_0_process_trap_irq(struct amdgpu_device *adev, 1449 struct amdgpu_irq_src *source, 1450 struct amdgpu_iv_entry *entry) 1451 { 1452 int instances, queue; 1453 uint32_t mes_queue_id = entry->src_data[0]; 1454 1455 DRM_DEBUG("IH: SDMA trap\n"); 1456 1457 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 1458 struct amdgpu_mes_queue *queue; 1459 1460 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 1461 1462 spin_lock(&adev->mes.queue_id_lock); 1463 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 1464 if (queue) { 1465 DRM_DEBUG("process smda queue id = %d\n", mes_queue_id); 1466 amdgpu_fence_process(queue->ring); 1467 } 1468 spin_unlock(&adev->mes.queue_id_lock); 1469 return 0; 1470 } 1471 1472 queue = entry->ring_id & 0xf; 1473 instances = (entry->ring_id & 0xf0) >> 4; 1474 if (instances > 1) { 1475 DRM_ERROR("IH: wrong ring_ID detected, as wrong sdma instance\n"); 1476 return -EINVAL; 1477 } 1478 1479 switch (entry->client_id) { 1480 case SOC21_IH_CLIENTID_GFX: 1481 switch (queue) { 1482 case 0: 1483 amdgpu_fence_process(&adev->sdma.instance[instances].ring); 1484 break; 1485 default: 1486 break; 1487 } 1488 break; 1489 } 1490 return 0; 1491 } 1492 1493 static int sdma_v6_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1494 struct amdgpu_irq_src *source, 1495 struct amdgpu_iv_entry *entry) 1496 { 1497 return 0; 1498 } 1499 1500 static int sdma_v6_0_set_clockgating_state(void *handle, 1501 enum amd_clockgating_state state) 1502 { 1503 return 0; 1504 } 1505 1506 static int sdma_v6_0_set_powergating_state(void *handle, 1507 enum amd_powergating_state state) 1508 { 1509 return 0; 1510 } 1511 1512 static void sdma_v6_0_get_clockgating_state(void *handle, u64 *flags) 1513 { 1514 } 1515 1516 const struct amd_ip_funcs sdma_v6_0_ip_funcs = { 1517 .name = "sdma_v6_0", 1518 .early_init = sdma_v6_0_early_init, 1519 .late_init = NULL, 1520 .sw_init = sdma_v6_0_sw_init, 1521 .sw_fini = sdma_v6_0_sw_fini, 1522 .hw_init = sdma_v6_0_hw_init, 1523 .hw_fini = sdma_v6_0_hw_fini, 1524 .suspend = sdma_v6_0_suspend, 1525 .resume = sdma_v6_0_resume, 1526 .is_idle = sdma_v6_0_is_idle, 1527 .wait_for_idle = sdma_v6_0_wait_for_idle, 1528 .soft_reset = sdma_v6_0_soft_reset, 1529 .set_clockgating_state = sdma_v6_0_set_clockgating_state, 1530 .set_powergating_state = sdma_v6_0_set_powergating_state, 1531 .get_clockgating_state = sdma_v6_0_get_clockgating_state, 1532 }; 1533 1534 static const struct amdgpu_ring_funcs sdma_v6_0_ring_funcs = { 1535 .type = AMDGPU_RING_TYPE_SDMA, 1536 .align_mask = 0xf, 1537 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1538 .support_64bit_ptrs = true, 1539 .vmhub = AMDGPU_GFXHUB_0, 1540 .get_rptr = sdma_v6_0_ring_get_rptr, 1541 .get_wptr = sdma_v6_0_ring_get_wptr, 1542 .set_wptr = sdma_v6_0_ring_set_wptr, 1543 .emit_frame_size = 1544 5 + /* sdma_v6_0_ring_init_cond_exec */ 1545 6 + /* sdma_v6_0_ring_emit_hdp_flush */ 1546 6 + /* sdma_v6_0_ring_emit_pipeline_sync */ 1547 /* sdma_v6_0_ring_emit_vm_flush */ 1548 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1549 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 1550 10 + 10 + 10, /* sdma_v6_0_ring_emit_fence x3 for user fence, vm fence */ 1551 .emit_ib_size = 5 + 7 + 6, /* sdma_v6_0_ring_emit_ib */ 1552 .emit_ib = sdma_v6_0_ring_emit_ib, 1553 .emit_mem_sync = sdma_v6_0_ring_emit_mem_sync, 1554 .emit_fence = sdma_v6_0_ring_emit_fence, 1555 .emit_pipeline_sync = sdma_v6_0_ring_emit_pipeline_sync, 1556 .emit_vm_flush = sdma_v6_0_ring_emit_vm_flush, 1557 .emit_hdp_flush = sdma_v6_0_ring_emit_hdp_flush, 1558 .test_ring = sdma_v6_0_ring_test_ring, 1559 .test_ib = sdma_v6_0_ring_test_ib, 1560 .insert_nop = sdma_v6_0_ring_insert_nop, 1561 .pad_ib = sdma_v6_0_ring_pad_ib, 1562 .emit_wreg = sdma_v6_0_ring_emit_wreg, 1563 .emit_reg_wait = sdma_v6_0_ring_emit_reg_wait, 1564 .emit_reg_write_reg_wait = sdma_v6_0_ring_emit_reg_write_reg_wait, 1565 .init_cond_exec = sdma_v6_0_ring_init_cond_exec, 1566 .patch_cond_exec = sdma_v6_0_ring_patch_cond_exec, 1567 .preempt_ib = sdma_v6_0_ring_preempt_ib, 1568 }; 1569 1570 static void sdma_v6_0_set_ring_funcs(struct amdgpu_device *adev) 1571 { 1572 int i; 1573 1574 for (i = 0; i < adev->sdma.num_instances; i++) { 1575 adev->sdma.instance[i].ring.funcs = &sdma_v6_0_ring_funcs; 1576 adev->sdma.instance[i].ring.me = i; 1577 } 1578 } 1579 1580 static const struct amdgpu_irq_src_funcs sdma_v6_0_trap_irq_funcs = { 1581 .set = sdma_v6_0_set_trap_irq_state, 1582 .process = sdma_v6_0_process_trap_irq, 1583 }; 1584 1585 static const struct amdgpu_irq_src_funcs sdma_v6_0_illegal_inst_irq_funcs = { 1586 .process = sdma_v6_0_process_illegal_inst_irq, 1587 }; 1588 1589 static void sdma_v6_0_set_irq_funcs(struct amdgpu_device *adev) 1590 { 1591 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 + 1592 adev->sdma.num_instances; 1593 adev->sdma.trap_irq.funcs = &sdma_v6_0_trap_irq_funcs; 1594 adev->sdma.illegal_inst_irq.funcs = &sdma_v6_0_illegal_inst_irq_funcs; 1595 } 1596 1597 /** 1598 * sdma_v6_0_emit_copy_buffer - copy buffer using the sDMA engine 1599 * 1600 * @ring: amdgpu_ring structure holding ring information 1601 * @src_offset: src GPU address 1602 * @dst_offset: dst GPU address 1603 * @byte_count: number of bytes to xfer 1604 * 1605 * Copy GPU buffers using the DMA engine. 1606 * Used by the amdgpu ttm implementation to move pages if 1607 * registered as the asic copy callback. 1608 */ 1609 static void sdma_v6_0_emit_copy_buffer(struct amdgpu_ib *ib, 1610 uint64_t src_offset, 1611 uint64_t dst_offset, 1612 uint32_t byte_count, 1613 bool tmz) 1614 { 1615 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) | 1616 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 1617 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0); 1618 ib->ptr[ib->length_dw++] = byte_count - 1; 1619 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1620 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1621 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1622 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1623 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1624 } 1625 1626 /** 1627 * sdma_v6_0_emit_fill_buffer - fill buffer using the sDMA engine 1628 * 1629 * @ring: amdgpu_ring structure holding ring information 1630 * @src_data: value to write to buffer 1631 * @dst_offset: dst GPU address 1632 * @byte_count: number of bytes to xfer 1633 * 1634 * Fill GPU buffers using the DMA engine. 1635 */ 1636 static void sdma_v6_0_emit_fill_buffer(struct amdgpu_ib *ib, 1637 uint32_t src_data, 1638 uint64_t dst_offset, 1639 uint32_t byte_count) 1640 { 1641 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_CONST_FILL); 1642 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1643 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1644 ib->ptr[ib->length_dw++] = src_data; 1645 ib->ptr[ib->length_dw++] = byte_count - 1; 1646 } 1647 1648 static const struct amdgpu_buffer_funcs sdma_v6_0_buffer_funcs = { 1649 .copy_max_bytes = 0x400000, 1650 .copy_num_dw = 7, 1651 .emit_copy_buffer = sdma_v6_0_emit_copy_buffer, 1652 1653 .fill_max_bytes = 0x400000, 1654 .fill_num_dw = 5, 1655 .emit_fill_buffer = sdma_v6_0_emit_fill_buffer, 1656 }; 1657 1658 static void sdma_v6_0_set_buffer_funcs(struct amdgpu_device *adev) 1659 { 1660 adev->mman.buffer_funcs = &sdma_v6_0_buffer_funcs; 1661 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1662 } 1663 1664 static const struct amdgpu_vm_pte_funcs sdma_v6_0_vm_pte_funcs = { 1665 .copy_pte_num_dw = 7, 1666 .copy_pte = sdma_v6_0_vm_copy_pte, 1667 .write_pte = sdma_v6_0_vm_write_pte, 1668 .set_pte_pde = sdma_v6_0_vm_set_pte_pde, 1669 }; 1670 1671 static void sdma_v6_0_set_vm_pte_funcs(struct amdgpu_device *adev) 1672 { 1673 unsigned i; 1674 1675 adev->vm_manager.vm_pte_funcs = &sdma_v6_0_vm_pte_funcs; 1676 for (i = 0; i < adev->sdma.num_instances; i++) { 1677 adev->vm_manager.vm_pte_scheds[i] = 1678 &adev->sdma.instance[i].ring.sched; 1679 } 1680 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 1681 } 1682 1683 const struct amdgpu_ip_block_version sdma_v6_0_ip_block = { 1684 .type = AMD_IP_BLOCK_TYPE_SDMA, 1685 .major = 6, 1686 .minor = 0, 1687 .rev = 0, 1688 .funcs = &sdma_v6_0_ip_funcs, 1689 }; 1690