1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 25 #include "amdgpu.h" 26 #include "amdgpu_trace.h" 27 #include "si.h" 28 #include "sid.h" 29 30 const u32 sdma_offsets[SDMA_MAX_INSTANCE] = 31 { 32 DMA0_REGISTER_OFFSET, 33 DMA1_REGISTER_OFFSET 34 }; 35 36 static void si_dma_set_ring_funcs(struct amdgpu_device *adev); 37 static void si_dma_set_buffer_funcs(struct amdgpu_device *adev); 38 static void si_dma_set_vm_pte_funcs(struct amdgpu_device *adev); 39 static void si_dma_set_irq_funcs(struct amdgpu_device *adev); 40 41 static uint64_t si_dma_ring_get_rptr(struct amdgpu_ring *ring) 42 { 43 return *ring->rptr_cpu_addr; 44 } 45 46 static uint64_t si_dma_ring_get_wptr(struct amdgpu_ring *ring) 47 { 48 struct amdgpu_device *adev = ring->adev; 49 u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1; 50 51 return (RREG32(DMA_RB_WPTR + sdma_offsets[me]) & 0x3fffc) >> 2; 52 } 53 54 static void si_dma_ring_set_wptr(struct amdgpu_ring *ring) 55 { 56 struct amdgpu_device *adev = ring->adev; 57 u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1; 58 59 WREG32(DMA_RB_WPTR + sdma_offsets[me], (ring->wptr << 2) & 0x3fffc); 60 } 61 62 static void si_dma_ring_emit_ib(struct amdgpu_ring *ring, 63 struct amdgpu_job *job, 64 struct amdgpu_ib *ib, 65 uint32_t flags) 66 { 67 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 68 /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring. 69 * Pad as necessary with NOPs. 70 */ 71 while ((lower_32_bits(ring->wptr) & 7) != 5) 72 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0)); 73 amdgpu_ring_write(ring, DMA_IB_PACKET(DMA_PACKET_INDIRECT_BUFFER, vmid, 0)); 74 amdgpu_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); 75 amdgpu_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); 76 77 } 78 79 /** 80 * si_dma_ring_emit_fence - emit a fence on the DMA ring 81 * 82 * @ring: amdgpu ring pointer 83 * @addr: address 84 * @seq: sequence number 85 * @flags: fence related flags 86 * 87 * Add a DMA fence packet to the ring to write 88 * the fence seq number and DMA trap packet to generate 89 * an interrupt if needed (VI). 90 */ 91 static void si_dma_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 92 unsigned flags) 93 { 94 95 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 96 /* write the fence */ 97 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0, 0)); 98 amdgpu_ring_write(ring, addr & 0xfffffffc); 99 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xff)); 100 amdgpu_ring_write(ring, seq); 101 /* optionally write high bits as well */ 102 if (write64bit) { 103 addr += 4; 104 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0, 0)); 105 amdgpu_ring_write(ring, addr & 0xfffffffc); 106 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xff)); 107 amdgpu_ring_write(ring, upper_32_bits(seq)); 108 } 109 /* generate an interrupt */ 110 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0, 0)); 111 } 112 113 static void si_dma_stop(struct amdgpu_device *adev) 114 { 115 struct amdgpu_ring *ring; 116 u32 rb_cntl; 117 unsigned i; 118 119 amdgpu_sdma_unset_buffer_funcs_helper(adev); 120 121 for (i = 0; i < adev->sdma.num_instances; i++) { 122 ring = &adev->sdma.instance[i].ring; 123 /* dma0 */ 124 rb_cntl = RREG32(DMA_RB_CNTL + sdma_offsets[i]); 125 rb_cntl &= ~DMA_RB_ENABLE; 126 WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl); 127 } 128 } 129 130 static int si_dma_start(struct amdgpu_device *adev) 131 { 132 struct amdgpu_ring *ring; 133 u32 rb_cntl, dma_cntl, ib_cntl, rb_bufsz; 134 int i, r; 135 uint64_t rptr_addr; 136 137 for (i = 0; i < adev->sdma.num_instances; i++) { 138 ring = &adev->sdma.instance[i].ring; 139 140 WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0); 141 WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); 142 143 /* Set ring buffer size in dwords */ 144 rb_bufsz = order_base_2(ring->ring_size / 4); 145 rb_cntl = rb_bufsz << 1; 146 #ifdef __BIG_ENDIAN 147 rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE; 148 #endif 149 WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl); 150 151 /* Initialize the ring buffer's read and write pointers */ 152 WREG32(DMA_RB_RPTR + sdma_offsets[i], 0); 153 WREG32(DMA_RB_WPTR + sdma_offsets[i], 0); 154 155 rptr_addr = ring->rptr_gpu_addr; 156 157 WREG32(DMA_RB_RPTR_ADDR_LO + sdma_offsets[i], lower_32_bits(rptr_addr)); 158 WREG32(DMA_RB_RPTR_ADDR_HI + sdma_offsets[i], upper_32_bits(rptr_addr) & 0xFF); 159 160 rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE; 161 162 WREG32(DMA_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); 163 164 /* enable DMA IBs */ 165 ib_cntl = DMA_IB_ENABLE | CMD_VMID_FORCE; 166 #ifdef __BIG_ENDIAN 167 ib_cntl |= DMA_IB_SWAP_ENABLE; 168 #endif 169 WREG32(DMA_IB_CNTL + sdma_offsets[i], ib_cntl); 170 171 dma_cntl = RREG32(DMA_CNTL + sdma_offsets[i]); 172 dma_cntl &= ~CTXEMPTY_INT_ENABLE; 173 WREG32(DMA_CNTL + sdma_offsets[i], dma_cntl); 174 175 ring->wptr = 0; 176 WREG32(DMA_RB_WPTR + sdma_offsets[i], ring->wptr << 2); 177 WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl | DMA_RB_ENABLE); 178 179 ring->sched.ready = true; 180 181 r = amdgpu_ring_test_helper(ring); 182 if (r) 183 return r; 184 185 if (adev->mman.buffer_funcs_ring == ring) 186 amdgpu_ttm_set_buffer_funcs_status(adev, true); 187 } 188 189 return 0; 190 } 191 192 /** 193 * si_dma_ring_test_ring - simple async dma engine test 194 * 195 * @ring: amdgpu_ring structure holding ring information 196 * 197 * Test the DMA engine by writing using it to write an 198 * value to memory. (VI). 199 * Returns 0 for success, error for failure. 200 */ 201 static int si_dma_ring_test_ring(struct amdgpu_ring *ring) 202 { 203 struct amdgpu_device *adev = ring->adev; 204 unsigned i; 205 unsigned index; 206 int r; 207 u32 tmp; 208 u64 gpu_addr; 209 210 r = amdgpu_device_wb_get(adev, &index); 211 if (r) 212 return r; 213 214 gpu_addr = adev->wb.gpu_addr + (index * 4); 215 tmp = 0xCAFEDEAD; 216 adev->wb.wb[index] = cpu_to_le32(tmp); 217 218 r = amdgpu_ring_alloc(ring, 4); 219 if (r) 220 goto error_free_wb; 221 222 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 0, 1)); 223 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 224 amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xff); 225 amdgpu_ring_write(ring, 0xDEADBEEF); 226 amdgpu_ring_commit(ring); 227 228 for (i = 0; i < adev->usec_timeout; i++) { 229 tmp = le32_to_cpu(adev->wb.wb[index]); 230 if (tmp == 0xDEADBEEF) 231 break; 232 udelay(1); 233 } 234 235 if (i >= adev->usec_timeout) 236 r = -ETIMEDOUT; 237 238 error_free_wb: 239 amdgpu_device_wb_free(adev, index); 240 return r; 241 } 242 243 /** 244 * si_dma_ring_test_ib - test an IB on the DMA engine 245 * 246 * @ring: amdgpu_ring structure holding ring information 247 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 248 * 249 * Test a simple IB in the DMA ring (VI). 250 * Returns 0 on success, error on failure. 251 */ 252 static int si_dma_ring_test_ib(struct amdgpu_ring *ring, long timeout) 253 { 254 struct amdgpu_device *adev = ring->adev; 255 struct amdgpu_ib ib; 256 struct dma_fence *f = NULL; 257 unsigned index; 258 u32 tmp = 0; 259 u64 gpu_addr; 260 long r; 261 262 r = amdgpu_device_wb_get(adev, &index); 263 if (r) 264 return r; 265 266 gpu_addr = adev->wb.gpu_addr + (index * 4); 267 tmp = 0xCAFEDEAD; 268 adev->wb.wb[index] = cpu_to_le32(tmp); 269 memset(&ib, 0, sizeof(ib)); 270 r = amdgpu_ib_get(adev, NULL, 256, 271 AMDGPU_IB_POOL_DIRECT, &ib); 272 if (r) 273 goto err0; 274 275 ib.ptr[0] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 0, 1); 276 ib.ptr[1] = lower_32_bits(gpu_addr); 277 ib.ptr[2] = upper_32_bits(gpu_addr) & 0xff; 278 ib.ptr[3] = 0xDEADBEEF; 279 ib.length_dw = 4; 280 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 281 if (r) 282 goto err1; 283 284 r = dma_fence_wait_timeout(f, false, timeout); 285 if (r == 0) { 286 r = -ETIMEDOUT; 287 goto err1; 288 } else if (r < 0) { 289 goto err1; 290 } 291 tmp = le32_to_cpu(adev->wb.wb[index]); 292 if (tmp == 0xDEADBEEF) 293 r = 0; 294 else 295 r = -EINVAL; 296 297 err1: 298 amdgpu_ib_free(adev, &ib, NULL); 299 dma_fence_put(f); 300 err0: 301 amdgpu_device_wb_free(adev, index); 302 return r; 303 } 304 305 /** 306 * si_dma_vm_copy_pte - update PTEs by copying them from the GART 307 * 308 * @ib: indirect buffer to fill with commands 309 * @pe: addr of the page entry 310 * @src: src addr to copy from 311 * @count: number of page entries to update 312 * 313 * Update PTEs by copying them from the GART using DMA (SI). 314 */ 315 static void si_dma_vm_copy_pte(struct amdgpu_ib *ib, 316 uint64_t pe, uint64_t src, 317 unsigned count) 318 { 319 unsigned bytes = count * 8; 320 321 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_COPY, 322 1, 0, 0, bytes); 323 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 324 ib->ptr[ib->length_dw++] = lower_32_bits(src); 325 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; 326 ib->ptr[ib->length_dw++] = upper_32_bits(src) & 0xff; 327 } 328 329 /** 330 * si_dma_vm_write_pte - update PTEs by writing them manually 331 * 332 * @ib: indirect buffer to fill with commands 333 * @pe: addr of the page entry 334 * @value: dst addr to write into pe 335 * @count: number of page entries to update 336 * @incr: increase next addr by incr bytes 337 * 338 * Update PTEs by writing them manually using DMA (SI). 339 */ 340 static void si_dma_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 341 uint64_t value, unsigned count, 342 uint32_t incr) 343 { 344 unsigned ndw = count * 2; 345 346 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 0, ndw); 347 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 348 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 349 for (; ndw > 0; ndw -= 2) { 350 ib->ptr[ib->length_dw++] = lower_32_bits(value); 351 ib->ptr[ib->length_dw++] = upper_32_bits(value); 352 value += incr; 353 } 354 } 355 356 /** 357 * si_dma_vm_set_pte_pde - update the page tables using sDMA 358 * 359 * @ib: indirect buffer to fill with commands 360 * @pe: addr of the page entry 361 * @addr: dst addr to write into pe 362 * @count: number of page entries to update 363 * @incr: increase next addr by incr bytes 364 * @flags: access flags 365 * 366 * Update the page tables using sDMA (CIK). 367 */ 368 static void si_dma_vm_set_pte_pde(struct amdgpu_ib *ib, 369 uint64_t pe, 370 uint64_t addr, unsigned count, 371 uint32_t incr, uint64_t flags) 372 { 373 uint64_t value; 374 unsigned ndw; 375 376 while (count) { 377 ndw = count * 2; 378 if (ndw > 0xFFFFE) 379 ndw = 0xFFFFE; 380 381 if (flags & AMDGPU_PTE_VALID) 382 value = addr; 383 else 384 value = 0; 385 386 /* for physically contiguous pages (vram) */ 387 ib->ptr[ib->length_dw++] = DMA_PTE_PDE_PACKET(ndw); 388 ib->ptr[ib->length_dw++] = pe; /* dst addr */ 389 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; 390 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 391 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 392 ib->ptr[ib->length_dw++] = value; /* value */ 393 ib->ptr[ib->length_dw++] = upper_32_bits(value); 394 ib->ptr[ib->length_dw++] = incr; /* increment size */ 395 ib->ptr[ib->length_dw++] = 0; 396 pe += ndw * 4; 397 addr += (ndw / 2) * incr; 398 count -= ndw / 2; 399 } 400 } 401 402 /** 403 * si_dma_ring_pad_ib - pad the IB to the required number of dw 404 * 405 * @ring: amdgpu_ring pointer 406 * @ib: indirect buffer to fill with padding 407 * 408 */ 409 static void si_dma_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 410 { 411 while (ib->length_dw & 0x7) 412 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0); 413 } 414 415 /** 416 * si_dma_ring_emit_pipeline_sync - sync the pipeline 417 * 418 * @ring: amdgpu_ring pointer 419 * 420 * Make sure all previous operations are completed (CIK). 421 */ 422 static void si_dma_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 423 { 424 uint32_t seq = ring->fence_drv.sync_seq; 425 uint64_t addr = ring->fence_drv.gpu_addr; 426 427 /* wait for idle */ 428 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_POLL_REG_MEM, 0, 0, 0, 0) | 429 (1 << 27)); /* Poll memory */ 430 amdgpu_ring_write(ring, lower_32_bits(addr)); 431 amdgpu_ring_write(ring, (0xff << 16) | upper_32_bits(addr)); /* retry, addr_hi */ 432 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 433 amdgpu_ring_write(ring, seq); /* value */ 434 amdgpu_ring_write(ring, (3 << 28) | 0x20); /* func(equal) | poll interval */ 435 } 436 437 /** 438 * si_dma_ring_emit_vm_flush - cik vm flush using sDMA 439 * 440 * @ring: amdgpu_ring pointer 441 * @vmid: vmid number to use 442 * @pd_addr: address 443 * 444 * Update the page table base and flush the VM TLB 445 * using sDMA (VI). 446 */ 447 static void si_dma_ring_emit_vm_flush(struct amdgpu_ring *ring, 448 unsigned vmid, uint64_t pd_addr) 449 { 450 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 451 452 /* wait for invalidate to complete */ 453 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_POLL_REG_MEM, 0, 0, 0, 0)); 454 amdgpu_ring_write(ring, VM_INVALIDATE_REQUEST); 455 amdgpu_ring_write(ring, 0xff << 16); /* retry */ 456 amdgpu_ring_write(ring, 1 << vmid); /* mask */ 457 amdgpu_ring_write(ring, 0); /* value */ 458 amdgpu_ring_write(ring, (0 << 28) | 0x20); /* func(always) | poll interval */ 459 } 460 461 static void si_dma_ring_emit_wreg(struct amdgpu_ring *ring, 462 uint32_t reg, uint32_t val) 463 { 464 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0)); 465 amdgpu_ring_write(ring, (0xf << 16) | reg); 466 amdgpu_ring_write(ring, val); 467 } 468 469 static int si_dma_early_init(void *handle) 470 { 471 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 472 473 adev->sdma.num_instances = 2; 474 475 si_dma_set_ring_funcs(adev); 476 si_dma_set_buffer_funcs(adev); 477 si_dma_set_vm_pte_funcs(adev); 478 si_dma_set_irq_funcs(adev); 479 480 return 0; 481 } 482 483 static int si_dma_sw_init(void *handle) 484 { 485 struct amdgpu_ring *ring; 486 int r, i; 487 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 488 489 /* DMA0 trap event */ 490 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 224, 491 &adev->sdma.trap_irq); 492 if (r) 493 return r; 494 495 /* DMA1 trap event */ 496 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 244, 497 &adev->sdma.trap_irq); 498 if (r) 499 return r; 500 501 for (i = 0; i < adev->sdma.num_instances; i++) { 502 ring = &adev->sdma.instance[i].ring; 503 ring->ring_obj = NULL; 504 ring->use_doorbell = false; 505 sprintf(ring->name, "sdma%d", i); 506 r = amdgpu_ring_init(adev, ring, 1024, 507 &adev->sdma.trap_irq, 508 (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 : 509 AMDGPU_SDMA_IRQ_INSTANCE1, 510 AMDGPU_RING_PRIO_DEFAULT, NULL); 511 if (r) 512 return r; 513 } 514 515 return r; 516 } 517 518 static int si_dma_sw_fini(void *handle) 519 { 520 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 521 int i; 522 523 for (i = 0; i < adev->sdma.num_instances; i++) 524 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 525 526 return 0; 527 } 528 529 static int si_dma_hw_init(void *handle) 530 { 531 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 532 533 return si_dma_start(adev); 534 } 535 536 static int si_dma_hw_fini(void *handle) 537 { 538 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 539 540 si_dma_stop(adev); 541 542 return 0; 543 } 544 545 static int si_dma_suspend(void *handle) 546 { 547 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 548 549 return si_dma_hw_fini(adev); 550 } 551 552 static int si_dma_resume(void *handle) 553 { 554 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 555 556 return si_dma_hw_init(adev); 557 } 558 559 static bool si_dma_is_idle(void *handle) 560 { 561 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 562 u32 tmp = RREG32(SRBM_STATUS2); 563 564 if (tmp & (DMA_BUSY_MASK | DMA1_BUSY_MASK)) 565 return false; 566 567 return true; 568 } 569 570 static int si_dma_wait_for_idle(void *handle) 571 { 572 unsigned i; 573 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 574 575 for (i = 0; i < adev->usec_timeout; i++) { 576 if (si_dma_is_idle(handle)) 577 return 0; 578 udelay(1); 579 } 580 return -ETIMEDOUT; 581 } 582 583 static int si_dma_soft_reset(void *handle) 584 { 585 DRM_INFO("si_dma_soft_reset --- not implemented !!!!!!!\n"); 586 return 0; 587 } 588 589 static int si_dma_set_trap_irq_state(struct amdgpu_device *adev, 590 struct amdgpu_irq_src *src, 591 unsigned type, 592 enum amdgpu_interrupt_state state) 593 { 594 u32 sdma_cntl; 595 596 switch (type) { 597 case AMDGPU_SDMA_IRQ_INSTANCE0: 598 switch (state) { 599 case AMDGPU_IRQ_STATE_DISABLE: 600 sdma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET); 601 sdma_cntl &= ~TRAP_ENABLE; 602 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl); 603 break; 604 case AMDGPU_IRQ_STATE_ENABLE: 605 sdma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET); 606 sdma_cntl |= TRAP_ENABLE; 607 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl); 608 break; 609 default: 610 break; 611 } 612 break; 613 case AMDGPU_SDMA_IRQ_INSTANCE1: 614 switch (state) { 615 case AMDGPU_IRQ_STATE_DISABLE: 616 sdma_cntl = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET); 617 sdma_cntl &= ~TRAP_ENABLE; 618 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, sdma_cntl); 619 break; 620 case AMDGPU_IRQ_STATE_ENABLE: 621 sdma_cntl = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET); 622 sdma_cntl |= TRAP_ENABLE; 623 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, sdma_cntl); 624 break; 625 default: 626 break; 627 } 628 break; 629 default: 630 break; 631 } 632 return 0; 633 } 634 635 static int si_dma_process_trap_irq(struct amdgpu_device *adev, 636 struct amdgpu_irq_src *source, 637 struct amdgpu_iv_entry *entry) 638 { 639 if (entry->src_id == 224) 640 amdgpu_fence_process(&adev->sdma.instance[0].ring); 641 else 642 amdgpu_fence_process(&adev->sdma.instance[1].ring); 643 return 0; 644 } 645 646 static int si_dma_set_clockgating_state(void *handle, 647 enum amd_clockgating_state state) 648 { 649 u32 orig, data, offset; 650 int i; 651 bool enable; 652 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 653 654 enable = (state == AMD_CG_STATE_GATE); 655 656 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 657 for (i = 0; i < adev->sdma.num_instances; i++) { 658 if (i == 0) 659 offset = DMA0_REGISTER_OFFSET; 660 else 661 offset = DMA1_REGISTER_OFFSET; 662 orig = data = RREG32(DMA_POWER_CNTL + offset); 663 data &= ~MEM_POWER_OVERRIDE; 664 if (data != orig) 665 WREG32(DMA_POWER_CNTL + offset, data); 666 WREG32(DMA_CLK_CTRL + offset, 0x00000100); 667 } 668 } else { 669 for (i = 0; i < adev->sdma.num_instances; i++) { 670 if (i == 0) 671 offset = DMA0_REGISTER_OFFSET; 672 else 673 offset = DMA1_REGISTER_OFFSET; 674 orig = data = RREG32(DMA_POWER_CNTL + offset); 675 data |= MEM_POWER_OVERRIDE; 676 if (data != orig) 677 WREG32(DMA_POWER_CNTL + offset, data); 678 679 orig = data = RREG32(DMA_CLK_CTRL + offset); 680 data = 0xff000000; 681 if (data != orig) 682 WREG32(DMA_CLK_CTRL + offset, data); 683 } 684 } 685 686 return 0; 687 } 688 689 static int si_dma_set_powergating_state(void *handle, 690 enum amd_powergating_state state) 691 { 692 u32 tmp; 693 694 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 695 696 WREG32(DMA_PGFSM_WRITE, 0x00002000); 697 WREG32(DMA_PGFSM_CONFIG, 0x100010ff); 698 699 for (tmp = 0; tmp < 5; tmp++) 700 WREG32(DMA_PGFSM_WRITE, 0); 701 702 return 0; 703 } 704 705 static const struct amd_ip_funcs si_dma_ip_funcs = { 706 .name = "si_dma", 707 .early_init = si_dma_early_init, 708 .late_init = NULL, 709 .sw_init = si_dma_sw_init, 710 .sw_fini = si_dma_sw_fini, 711 .hw_init = si_dma_hw_init, 712 .hw_fini = si_dma_hw_fini, 713 .suspend = si_dma_suspend, 714 .resume = si_dma_resume, 715 .is_idle = si_dma_is_idle, 716 .wait_for_idle = si_dma_wait_for_idle, 717 .soft_reset = si_dma_soft_reset, 718 .set_clockgating_state = si_dma_set_clockgating_state, 719 .set_powergating_state = si_dma_set_powergating_state, 720 }; 721 722 static const struct amdgpu_ring_funcs si_dma_ring_funcs = { 723 .type = AMDGPU_RING_TYPE_SDMA, 724 .align_mask = 0xf, 725 .nop = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0), 726 .support_64bit_ptrs = false, 727 .get_rptr = si_dma_ring_get_rptr, 728 .get_wptr = si_dma_ring_get_wptr, 729 .set_wptr = si_dma_ring_set_wptr, 730 .emit_frame_size = 731 3 + 3 + /* hdp flush / invalidate */ 732 6 + /* si_dma_ring_emit_pipeline_sync */ 733 SI_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* si_dma_ring_emit_vm_flush */ 734 9 + 9 + 9, /* si_dma_ring_emit_fence x3 for user fence, vm fence */ 735 .emit_ib_size = 7 + 3, /* si_dma_ring_emit_ib */ 736 .emit_ib = si_dma_ring_emit_ib, 737 .emit_fence = si_dma_ring_emit_fence, 738 .emit_pipeline_sync = si_dma_ring_emit_pipeline_sync, 739 .emit_vm_flush = si_dma_ring_emit_vm_flush, 740 .test_ring = si_dma_ring_test_ring, 741 .test_ib = si_dma_ring_test_ib, 742 .insert_nop = amdgpu_ring_insert_nop, 743 .pad_ib = si_dma_ring_pad_ib, 744 .emit_wreg = si_dma_ring_emit_wreg, 745 }; 746 747 static void si_dma_set_ring_funcs(struct amdgpu_device *adev) 748 { 749 int i; 750 751 for (i = 0; i < adev->sdma.num_instances; i++) 752 adev->sdma.instance[i].ring.funcs = &si_dma_ring_funcs; 753 } 754 755 static const struct amdgpu_irq_src_funcs si_dma_trap_irq_funcs = { 756 .set = si_dma_set_trap_irq_state, 757 .process = si_dma_process_trap_irq, 758 }; 759 760 static void si_dma_set_irq_funcs(struct amdgpu_device *adev) 761 { 762 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 763 adev->sdma.trap_irq.funcs = &si_dma_trap_irq_funcs; 764 } 765 766 /** 767 * si_dma_emit_copy_buffer - copy buffer using the sDMA engine 768 * 769 * @ib: indirect buffer to copy to 770 * @src_offset: src GPU address 771 * @dst_offset: dst GPU address 772 * @byte_count: number of bytes to xfer 773 * @tmz: is this a secure operation 774 * 775 * Copy GPU buffers using the DMA engine (VI). 776 * Used by the amdgpu ttm implementation to move pages if 777 * registered as the asic copy callback. 778 */ 779 static void si_dma_emit_copy_buffer(struct amdgpu_ib *ib, 780 uint64_t src_offset, 781 uint64_t dst_offset, 782 uint32_t byte_count, 783 bool tmz) 784 { 785 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_COPY, 786 1, 0, 0, byte_count); 787 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 788 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 789 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset) & 0xff; 790 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset) & 0xff; 791 } 792 793 /** 794 * si_dma_emit_fill_buffer - fill buffer using the sDMA engine 795 * 796 * @ib: indirect buffer to copy to 797 * @src_data: value to write to buffer 798 * @dst_offset: dst GPU address 799 * @byte_count: number of bytes to xfer 800 * 801 * Fill GPU buffers using the DMA engine (VI). 802 */ 803 static void si_dma_emit_fill_buffer(struct amdgpu_ib *ib, 804 uint32_t src_data, 805 uint64_t dst_offset, 806 uint32_t byte_count) 807 { 808 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_CONSTANT_FILL, 809 0, 0, 0, byte_count / 4); 810 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 811 ib->ptr[ib->length_dw++] = src_data; 812 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset) << 16; 813 } 814 815 816 static const struct amdgpu_buffer_funcs si_dma_buffer_funcs = { 817 .copy_max_bytes = 0xffff8, 818 .copy_num_dw = 5, 819 .emit_copy_buffer = si_dma_emit_copy_buffer, 820 821 .fill_max_bytes = 0xffff8, 822 .fill_num_dw = 4, 823 .emit_fill_buffer = si_dma_emit_fill_buffer, 824 }; 825 826 static void si_dma_set_buffer_funcs(struct amdgpu_device *adev) 827 { 828 adev->mman.buffer_funcs = &si_dma_buffer_funcs; 829 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 830 } 831 832 static const struct amdgpu_vm_pte_funcs si_dma_vm_pte_funcs = { 833 .copy_pte_num_dw = 5, 834 .copy_pte = si_dma_vm_copy_pte, 835 836 .write_pte = si_dma_vm_write_pte, 837 .set_pte_pde = si_dma_vm_set_pte_pde, 838 }; 839 840 static void si_dma_set_vm_pte_funcs(struct amdgpu_device *adev) 841 { 842 unsigned i; 843 844 adev->vm_manager.vm_pte_funcs = &si_dma_vm_pte_funcs; 845 for (i = 0; i < adev->sdma.num_instances; i++) { 846 adev->vm_manager.vm_pte_scheds[i] = 847 &adev->sdma.instance[i].ring.sched; 848 } 849 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 850 } 851 852 const struct amdgpu_ip_block_version si_dma_ip_block = 853 { 854 .type = AMD_IP_BLOCK_TYPE_SDMA, 855 .major = 1, 856 .minor = 0, 857 .rev = 0, 858 .funcs = &si_dma_ip_funcs, 859 }; 860