1/* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23/* To compile this assembly code: 24 * 25 * Navi1x: 26 * cpp -DASIC_FAMILY=CHIP_NAVI10 cwsr_trap_handler_gfx10.asm -P -o nv1x.sp3 27 * sp3 nv1x.sp3 -hex nv1x.hex 28 * 29 * gfx10: 30 * cpp -DASIC_FAMILY=CHIP_SIENNA_CICHLID cwsr_trap_handler_gfx10.asm -P -o gfx10.sp3 31 * sp3 gfx10.sp3 -hex gfx10.hex 32 * 33 * gfx11: 34 * cpp -DASIC_FAMILY=CHIP_PLUM_BONITO cwsr_trap_handler_gfx10.asm -P -o gfx11.sp3 35 * sp3 gfx11.sp3 -hex gfx11.hex 36 */ 37 38#define CHIP_NAVI10 26 39#define CHIP_SIENNA_CICHLID 30 40#define CHIP_PLUM_BONITO 36 41 42#define NO_SQC_STORE (ASIC_FAMILY >= CHIP_SIENNA_CICHLID) 43#define HAVE_XNACK (ASIC_FAMILY < CHIP_SIENNA_CICHLID) 44#define HAVE_SENDMSG_RTN (ASIC_FAMILY >= CHIP_PLUM_BONITO) 45#define HAVE_BUFFER_LDS_LOAD (ASIC_FAMILY < CHIP_PLUM_BONITO) 46#define SW_SA_TRAP (ASIC_FAMILY >= CHIP_PLUM_BONITO) 47 48var SINGLE_STEP_MISSED_WORKAROUND = 1 //workaround for lost MODE.DEBUG_EN exception when SAVECTX raised 49 50var SQ_WAVE_STATUS_SPI_PRIO_MASK = 0x00000006 51var SQ_WAVE_STATUS_HALT_MASK = 0x2000 52var SQ_WAVE_STATUS_ECC_ERR_MASK = 0x20000 53var SQ_WAVE_STATUS_TRAP_EN_SHIFT = 6 54 55var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT = 12 56var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE = 9 57var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE = 8 58var SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SHIFT = 24 59var SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SIZE = 4 60var SQ_WAVE_IB_STS2_WAVE64_SHIFT = 11 61var SQ_WAVE_IB_STS2_WAVE64_SIZE = 1 62 63#if ASIC_FAMILY < CHIP_PLUM_BONITO 64var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT = 8 65#else 66var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT = 12 67#endif 68 69var SQ_WAVE_TRAPSTS_SAVECTX_MASK = 0x400 70var SQ_WAVE_TRAPSTS_EXCP_MASK = 0x1FF 71var SQ_WAVE_TRAPSTS_SAVECTX_SHIFT = 10 72var SQ_WAVE_TRAPSTS_ADDR_WATCH_MASK = 0x80 73var SQ_WAVE_TRAPSTS_ADDR_WATCH_SHIFT = 7 74var SQ_WAVE_TRAPSTS_MEM_VIOL_MASK = 0x100 75var SQ_WAVE_TRAPSTS_MEM_VIOL_SHIFT = 8 76var SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK = 0x3FF 77var SQ_WAVE_TRAPSTS_PRE_SAVECTX_SHIFT = 0x0 78var SQ_WAVE_TRAPSTS_PRE_SAVECTX_SIZE = 10 79var SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK = 0xFFFFF800 80var SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT = 11 81var SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE = 21 82var SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK = 0x800 83var SQ_WAVE_TRAPSTS_EXCP_HI_MASK = 0x7000 84#if ASIC_FAMILY >= CHIP_PLUM_BONITO 85var SQ_WAVE_TRAPSTS_WAVE_START_MASK = 0x20000 86var SQ_WAVE_TRAPSTS_WAVE_END_MASK = 0x40000 87var SQ_WAVE_TRAPSTS_TRAP_AFTER_INST_MASK = 0x100000 88#endif 89 90var SQ_WAVE_MODE_EXCP_EN_SHIFT = 12 91var SQ_WAVE_MODE_EXCP_EN_ADDR_WATCH_SHIFT = 19 92 93var SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT = 15 94var SQ_WAVE_IB_STS_REPLAY_W64H_SHIFT = 25 95var SQ_WAVE_IB_STS_REPLAY_W64H_MASK = 0x02000000 96var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK = 0x003F8000 97 98var SQ_WAVE_MODE_DEBUG_EN_MASK = 0x800 99 100#if ASIC_FAMILY < CHIP_PLUM_BONITO 101var S_TRAPSTS_NON_MASKABLE_EXCP_MASK = SQ_WAVE_TRAPSTS_MEM_VIOL_MASK|SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK 102#else 103var S_TRAPSTS_NON_MASKABLE_EXCP_MASK = SQ_WAVE_TRAPSTS_MEM_VIOL_MASK |\ 104 SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK |\ 105 SQ_WAVE_TRAPSTS_WAVE_START_MASK |\ 106 SQ_WAVE_TRAPSTS_WAVE_END_MASK |\ 107 SQ_WAVE_TRAPSTS_TRAP_AFTER_INST_MASK 108#endif 109 110// bits [31:24] unused by SPI debug data 111var TTMP11_SAVE_REPLAY_W64H_SHIFT = 31 112var TTMP11_SAVE_REPLAY_W64H_MASK = 0x80000000 113var TTMP11_SAVE_RCNT_FIRST_REPLAY_SHIFT = 24 114var TTMP11_SAVE_RCNT_FIRST_REPLAY_MASK = 0x7F000000 115var TTMP11_DEBUG_TRAP_ENABLED_SHIFT = 23 116var TTMP11_DEBUG_TRAP_ENABLED_MASK = 0x800000 117 118// SQ_SEL_X/Y/Z/W, BUF_NUM_FORMAT_FLOAT, (0 for MUBUF stride[17:14] 119// when ADD_TID_ENABLE and BUF_DATA_FORMAT_32 for MTBUF), ADD_TID_ENABLE 120var S_SAVE_BUF_RSRC_WORD1_STRIDE = 0x00040000 121var S_SAVE_BUF_RSRC_WORD3_MISC = 0x10807FAC 122var S_SAVE_PC_HI_TRAP_ID_MASK = 0x00FF0000 123var S_SAVE_PC_HI_HT_MASK = 0x01000000 124var S_SAVE_SPI_INIT_FIRST_WAVE_MASK = 0x04000000 125var S_SAVE_SPI_INIT_FIRST_WAVE_SHIFT = 26 126 127var S_SAVE_PC_HI_FIRST_WAVE_MASK = 0x80000000 128var S_SAVE_PC_HI_FIRST_WAVE_SHIFT = 31 129 130var s_sgpr_save_num = 108 131 132var s_save_spi_init_lo = exec_lo 133var s_save_spi_init_hi = exec_hi 134var s_save_pc_lo = ttmp0 135var s_save_pc_hi = ttmp1 136var s_save_exec_lo = ttmp2 137var s_save_exec_hi = ttmp3 138var s_save_status = ttmp12 139var s_save_trapsts = ttmp15 140var s_save_xnack_mask = s_save_trapsts 141var s_wave_size = ttmp7 142var s_save_buf_rsrc0 = ttmp8 143var s_save_buf_rsrc1 = ttmp9 144var s_save_buf_rsrc2 = ttmp10 145var s_save_buf_rsrc3 = ttmp11 146var s_save_mem_offset = ttmp4 147var s_save_alloc_size = s_save_trapsts 148var s_save_tmp = ttmp14 149var s_save_m0 = ttmp5 150var s_save_ttmps_lo = s_save_tmp 151var s_save_ttmps_hi = s_save_trapsts 152 153var S_RESTORE_BUF_RSRC_WORD1_STRIDE = S_SAVE_BUF_RSRC_WORD1_STRIDE 154var S_RESTORE_BUF_RSRC_WORD3_MISC = S_SAVE_BUF_RSRC_WORD3_MISC 155 156var S_RESTORE_SPI_INIT_FIRST_WAVE_MASK = 0x04000000 157var S_RESTORE_SPI_INIT_FIRST_WAVE_SHIFT = 26 158var S_WAVE_SIZE = 25 159 160var s_restore_spi_init_lo = exec_lo 161var s_restore_spi_init_hi = exec_hi 162var s_restore_mem_offset = ttmp12 163var s_restore_alloc_size = ttmp3 164var s_restore_tmp = ttmp2 165var s_restore_mem_offset_save = s_restore_tmp 166var s_restore_m0 = s_restore_alloc_size 167var s_restore_mode = ttmp7 168var s_restore_flat_scratch = s_restore_tmp 169var s_restore_pc_lo = ttmp0 170var s_restore_pc_hi = ttmp1 171var s_restore_exec_lo = ttmp4 172var s_restore_exec_hi = ttmp5 173var s_restore_status = ttmp14 174var s_restore_trapsts = ttmp15 175var s_restore_xnack_mask = ttmp13 176var s_restore_buf_rsrc0 = ttmp8 177var s_restore_buf_rsrc1 = ttmp9 178var s_restore_buf_rsrc2 = ttmp10 179var s_restore_buf_rsrc3 = ttmp11 180var s_restore_size = ttmp6 181var s_restore_ttmps_lo = s_restore_tmp 182var s_restore_ttmps_hi = s_restore_alloc_size 183 184shader main 185 asic(DEFAULT) 186 type(CS) 187 wave_size(32) 188 189 s_branch L_SKIP_RESTORE //NOT restore. might be a regular trap or save 190 191L_JUMP_TO_RESTORE: 192 s_branch L_RESTORE 193 194L_SKIP_RESTORE: 195 s_getreg_b32 s_save_status, hwreg(HW_REG_STATUS) //save STATUS since we will change SCC 196 197 // Clear SPI_PRIO: do not save with elevated priority. 198 // Clear ECC_ERR: prevents SQC store and triggers FATAL_HALT if setreg'd. 199 s_andn2_b32 s_save_status, s_save_status, SQ_WAVE_STATUS_SPI_PRIO_MASK|SQ_WAVE_STATUS_ECC_ERR_MASK 200 201 s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) 202 203#if SW_SA_TRAP 204 // If ttmp1[30] is set then issue s_barrier to unblock dependent waves. 205 s_bitcmp1_b32 s_save_pc_hi, 30 206 s_cbranch_scc0 L_TRAP_NO_BARRIER 207 s_barrier 208 209L_TRAP_NO_BARRIER: 210 // If ttmp1[31] is set then trap may occur early. 211 // Spin wait until SAVECTX exception is raised. 212 s_bitcmp1_b32 s_save_pc_hi, 31 213 s_cbranch_scc1 L_CHECK_SAVE 214#endif 215 216 s_and_b32 ttmp2, s_save_status, SQ_WAVE_STATUS_HALT_MASK 217 s_cbranch_scc0 L_NOT_HALTED 218 219L_HALTED: 220 // Host trap may occur while wave is halted. 221 s_and_b32 ttmp2, s_save_pc_hi, S_SAVE_PC_HI_TRAP_ID_MASK 222 s_cbranch_scc1 L_FETCH_2ND_TRAP 223 224L_CHECK_SAVE: 225 s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_SAVECTX_MASK 226 s_cbranch_scc1 L_SAVE 227 228 // Wave is halted but neither host trap nor SAVECTX is raised. 229 // Caused by instruction fetch memory violation. 230 // Spin wait until context saved to prevent interrupt storm. 231 s_sleep 0x10 232 s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) 233 s_branch L_CHECK_SAVE 234 235L_NOT_HALTED: 236 // Let second-level handle non-SAVECTX exception or trap. 237 // Any concurrent SAVECTX will be handled upon re-entry once halted. 238 239 // Check non-maskable exceptions. memory_violation, illegal_instruction 240 // and xnack_error exceptions always cause the wave to enter the trap 241 // handler. 242 s_and_b32 ttmp2, s_save_trapsts, S_TRAPSTS_NON_MASKABLE_EXCP_MASK 243 s_cbranch_scc1 L_FETCH_2ND_TRAP 244 245 // Check for maskable exceptions in trapsts.excp and trapsts.excp_hi. 246 // Maskable exceptions only cause the wave to enter the trap handler if 247 // their respective bit in mode.excp_en is set. 248 s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_EXCP_MASK|SQ_WAVE_TRAPSTS_EXCP_HI_MASK 249 s_cbranch_scc0 L_CHECK_TRAP_ID 250 251 s_and_b32 ttmp3, s_save_trapsts, SQ_WAVE_TRAPSTS_ADDR_WATCH_MASK|SQ_WAVE_TRAPSTS_EXCP_HI_MASK 252 s_cbranch_scc0 L_NOT_ADDR_WATCH 253 s_bitset1_b32 ttmp2, SQ_WAVE_TRAPSTS_ADDR_WATCH_SHIFT // Check all addr_watch[123] exceptions against excp_en.addr_watch 254 255L_NOT_ADDR_WATCH: 256 s_getreg_b32 ttmp3, hwreg(HW_REG_MODE) 257 s_lshl_b32 ttmp2, ttmp2, SQ_WAVE_MODE_EXCP_EN_SHIFT 258 s_and_b32 ttmp2, ttmp2, ttmp3 259 s_cbranch_scc1 L_FETCH_2ND_TRAP 260 261L_CHECK_TRAP_ID: 262 // Check trap_id != 0 263 s_and_b32 ttmp2, s_save_pc_hi, S_SAVE_PC_HI_TRAP_ID_MASK 264 s_cbranch_scc1 L_FETCH_2ND_TRAP 265 266if SINGLE_STEP_MISSED_WORKAROUND 267 // Prioritize single step exception over context save. 268 // Second-level trap will halt wave and RFE, re-entering for SAVECTX. 269 s_getreg_b32 ttmp2, hwreg(HW_REG_MODE) 270 s_and_b32 ttmp2, ttmp2, SQ_WAVE_MODE_DEBUG_EN_MASK 271 s_cbranch_scc1 L_FETCH_2ND_TRAP 272end 273 274 s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_SAVECTX_MASK 275 s_cbranch_scc1 L_SAVE 276 277L_FETCH_2ND_TRAP: 278#if HAVE_XNACK 279 save_and_clear_ib_sts(ttmp14, ttmp15) 280#endif 281 282 // Read second-level TBA/TMA from first-level TMA and jump if available. 283 // ttmp[2:5] and ttmp12 can be used (others hold SPI-initialized debug data) 284 // ttmp12 holds SQ_WAVE_STATUS 285#if HAVE_SENDMSG_RTN 286 s_sendmsg_rtn_b64 [ttmp14, ttmp15], sendmsg(MSG_RTN_GET_TMA) 287 s_waitcnt lgkmcnt(0) 288#else 289 s_getreg_b32 ttmp14, hwreg(HW_REG_SHADER_TMA_LO) 290 s_getreg_b32 ttmp15, hwreg(HW_REG_SHADER_TMA_HI) 291#endif 292 s_lshl_b64 [ttmp14, ttmp15], [ttmp14, ttmp15], 0x8 293 294 s_bitcmp1_b32 ttmp15, 0xF 295 s_cbranch_scc0 L_NO_SIGN_EXTEND_TMA 296 s_or_b32 ttmp15, ttmp15, 0xFFFF0000 297L_NO_SIGN_EXTEND_TMA: 298 299 s_load_dword ttmp2, [ttmp14, ttmp15], 0x10 glc:1 // debug trap enabled flag 300 s_waitcnt lgkmcnt(0) 301 s_lshl_b32 ttmp2, ttmp2, TTMP11_DEBUG_TRAP_ENABLED_SHIFT 302 s_andn2_b32 ttmp11, ttmp11, TTMP11_DEBUG_TRAP_ENABLED_MASK 303 s_or_b32 ttmp11, ttmp11, ttmp2 304 305 s_load_dwordx2 [ttmp2, ttmp3], [ttmp14, ttmp15], 0x0 glc:1 // second-level TBA 306 s_waitcnt lgkmcnt(0) 307 s_load_dwordx2 [ttmp14, ttmp15], [ttmp14, ttmp15], 0x8 glc:1 // second-level TMA 308 s_waitcnt lgkmcnt(0) 309 310 s_and_b64 [ttmp2, ttmp3], [ttmp2, ttmp3], [ttmp2, ttmp3] 311 s_cbranch_scc0 L_NO_NEXT_TRAP // second-level trap handler not been set 312 s_setpc_b64 [ttmp2, ttmp3] // jump to second-level trap handler 313 314L_NO_NEXT_TRAP: 315 // If not caused by trap then halt wave to prevent re-entry. 316 s_and_b32 ttmp2, s_save_pc_hi, (S_SAVE_PC_HI_TRAP_ID_MASK|S_SAVE_PC_HI_HT_MASK) 317 s_cbranch_scc1 L_TRAP_CASE 318 s_or_b32 s_save_status, s_save_status, SQ_WAVE_STATUS_HALT_MASK 319 320 // If the PC points to S_ENDPGM then context save will fail if STATUS.HALT is set. 321 // Rewind the PC to prevent this from occurring. 322 s_sub_u32 ttmp0, ttmp0, 0x8 323 s_subb_u32 ttmp1, ttmp1, 0x0 324 325 s_branch L_EXIT_TRAP 326 327L_TRAP_CASE: 328 // Host trap will not cause trap re-entry. 329 s_and_b32 ttmp2, s_save_pc_hi, S_SAVE_PC_HI_HT_MASK 330 s_cbranch_scc1 L_EXIT_TRAP 331 332 // Advance past trap instruction to prevent re-entry. 333 s_add_u32 ttmp0, ttmp0, 0x4 334 s_addc_u32 ttmp1, ttmp1, 0x0 335 336L_EXIT_TRAP: 337 s_and_b32 ttmp1, ttmp1, 0xFFFF 338 339#if HAVE_XNACK 340 restore_ib_sts(ttmp14, ttmp15) 341#endif 342 343 // Restore SQ_WAVE_STATUS. 344 s_and_b64 exec, exec, exec // Restore STATUS.EXECZ, not writable by s_setreg_b32 345 s_and_b64 vcc, vcc, vcc // Restore STATUS.VCCZ, not writable by s_setreg_b32 346 s_setreg_b32 hwreg(HW_REG_STATUS), s_save_status 347 348 s_rfe_b64 [ttmp0, ttmp1] 349 350L_SAVE: 351 s_and_b32 s_save_pc_hi, s_save_pc_hi, 0x0000ffff //pc[47:32] 352 s_mov_b32 s_save_tmp, 0 353 s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_SAVECTX_SHIFT, 1), s_save_tmp //clear saveCtx bit 354 355#if HAVE_XNACK 356 save_and_clear_ib_sts(s_save_tmp, s_save_trapsts) 357#endif 358 359 /* inform SPI the readiness and wait for SPI's go signal */ 360 s_mov_b32 s_save_exec_lo, exec_lo //save EXEC and use EXEC for the go signal from SPI 361 s_mov_b32 s_save_exec_hi, exec_hi 362 s_mov_b64 exec, 0x0 //clear EXEC to get ready to receive 363 364#if HAVE_SENDMSG_RTN 365 s_sendmsg_rtn_b64 [exec_lo, exec_hi], sendmsg(MSG_RTN_SAVE_WAVE) 366#else 367 s_sendmsg sendmsg(MSG_SAVEWAVE) //send SPI a message and wait for SPI's write to EXEC 368#endif 369 370#if ASIC_FAMILY < CHIP_SIENNA_CICHLID 371L_SLEEP: 372 // sleep 1 (64clk) is not enough for 8 waves per SIMD, which will cause 373 // SQ hang, since the 7,8th wave could not get arbit to exec inst, while 374 // other waves are stuck into the sleep-loop and waiting for wrexec!=0 375 s_sleep 0x2 376 s_cbranch_execz L_SLEEP 377#else 378 s_waitcnt lgkmcnt(0) 379#endif 380 381 // Save first_wave flag so we can clear high bits of save address. 382 s_and_b32 s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK 383 s_lshl_b32 s_save_tmp, s_save_tmp, (S_SAVE_PC_HI_FIRST_WAVE_SHIFT - S_SAVE_SPI_INIT_FIRST_WAVE_SHIFT) 384 s_or_b32 s_save_pc_hi, s_save_pc_hi, s_save_tmp 385 386#if NO_SQC_STORE 387#if ASIC_FAMILY <= CHIP_SIENNA_CICHLID 388 // gfx10: If there was a VALU exception, the exception state must be 389 // cleared before executing the VALU instructions below. 390 v_clrexcp 391#endif 392 393 // Trap temporaries must be saved via VGPR but all VGPRs are in use. 394 // There is no ttmp space to hold the resource constant for VGPR save. 395 // Save v0 by itself since it requires only two SGPRs. 396 s_mov_b32 s_save_ttmps_lo, exec_lo 397 s_and_b32 s_save_ttmps_hi, exec_hi, 0xFFFF 398 s_mov_b32 exec_lo, 0xFFFFFFFF 399 s_mov_b32 exec_hi, 0xFFFFFFFF 400 global_store_dword_addtid v0, [s_save_ttmps_lo, s_save_ttmps_hi] slc:1 glc:1 401 v_mov_b32 v0, 0x0 402 s_mov_b32 exec_lo, s_save_ttmps_lo 403 s_mov_b32 exec_hi, s_save_ttmps_hi 404#endif 405 406 // Save trap temporaries 4-11, 13 initialized by SPI debug dispatch logic 407 // ttmp SR memory offset : size(VGPR)+size(SVGPR)+size(SGPR)+0x40 408 get_wave_size(s_save_ttmps_hi) 409 get_vgpr_size_bytes(s_save_ttmps_lo, s_save_ttmps_hi) 410 get_svgpr_size_bytes(s_save_ttmps_hi) 411 s_add_u32 s_save_ttmps_lo, s_save_ttmps_lo, s_save_ttmps_hi 412 s_and_b32 s_save_ttmps_hi, s_save_spi_init_hi, 0xFFFF 413 s_add_u32 s_save_ttmps_lo, s_save_ttmps_lo, get_sgpr_size_bytes() 414 s_add_u32 s_save_ttmps_lo, s_save_ttmps_lo, s_save_spi_init_lo 415 s_addc_u32 s_save_ttmps_hi, s_save_ttmps_hi, 0x0 416 417#if NO_SQC_STORE 418 v_writelane_b32 v0, ttmp4, 0x4 419 v_writelane_b32 v0, ttmp5, 0x5 420 v_writelane_b32 v0, ttmp6, 0x6 421 v_writelane_b32 v0, ttmp7, 0x7 422 v_writelane_b32 v0, ttmp8, 0x8 423 v_writelane_b32 v0, ttmp9, 0x9 424 v_writelane_b32 v0, ttmp10, 0xA 425 v_writelane_b32 v0, ttmp11, 0xB 426 v_writelane_b32 v0, ttmp13, 0xD 427 v_writelane_b32 v0, exec_lo, 0xE 428 v_writelane_b32 v0, exec_hi, 0xF 429 430 s_mov_b32 exec_lo, 0x3FFF 431 s_mov_b32 exec_hi, 0x0 432 global_store_dword_addtid v0, [s_save_ttmps_lo, s_save_ttmps_hi] inst_offset:0x40 slc:1 glc:1 433 v_readlane_b32 ttmp14, v0, 0xE 434 v_readlane_b32 ttmp15, v0, 0xF 435 s_mov_b32 exec_lo, ttmp14 436 s_mov_b32 exec_hi, ttmp15 437#else 438 s_store_dwordx4 [ttmp4, ttmp5, ttmp6, ttmp7], [s_save_ttmps_lo, s_save_ttmps_hi], 0x50 glc:1 439 s_store_dwordx4 [ttmp8, ttmp9, ttmp10, ttmp11], [s_save_ttmps_lo, s_save_ttmps_hi], 0x60 glc:1 440 s_store_dword ttmp13, [s_save_ttmps_lo, s_save_ttmps_hi], 0x74 glc:1 441#endif 442 443 /* setup Resource Contants */ 444 s_mov_b32 s_save_buf_rsrc0, s_save_spi_init_lo //base_addr_lo 445 s_and_b32 s_save_buf_rsrc1, s_save_spi_init_hi, 0x0000FFFF //base_addr_hi 446 s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, S_SAVE_BUF_RSRC_WORD1_STRIDE 447 s_mov_b32 s_save_buf_rsrc2, 0 //NUM_RECORDS initial value = 0 (in bytes) although not neccessarily inited 448 s_mov_b32 s_save_buf_rsrc3, S_SAVE_BUF_RSRC_WORD3_MISC 449 450 s_mov_b32 s_save_m0, m0 451 452 /* global mem offset */ 453 s_mov_b32 s_save_mem_offset, 0x0 454 get_wave_size(s_wave_size) 455 456#if HAVE_XNACK 457 // Save and clear vector XNACK state late to free up SGPRs. 458 s_getreg_b32 s_save_xnack_mask, hwreg(HW_REG_SHADER_XNACK_MASK) 459 s_setreg_imm32_b32 hwreg(HW_REG_SHADER_XNACK_MASK), 0x0 460#endif 461 462 /* save first 4 VGPRs, needed for SGPR save */ 463 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on 464 s_lshr_b32 m0, s_wave_size, S_WAVE_SIZE 465 s_and_b32 m0, m0, 1 466 s_cmp_eq_u32 m0, 1 467 s_cbranch_scc1 L_ENABLE_SAVE_4VGPR_EXEC_HI 468 s_mov_b32 exec_hi, 0x00000000 469 s_branch L_SAVE_4VGPR_WAVE32 470L_ENABLE_SAVE_4VGPR_EXEC_HI: 471 s_mov_b32 exec_hi, 0xFFFFFFFF 472 s_branch L_SAVE_4VGPR_WAVE64 473L_SAVE_4VGPR_WAVE32: 474 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 475 476 // VGPR Allocated in 4-GPR granularity 477 478#if !NO_SQC_STORE 479 buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 480#endif 481 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:128 482 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:128*2 483 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:128*3 484 s_branch L_SAVE_HWREG 485 486L_SAVE_4VGPR_WAVE64: 487 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 488 489 // VGPR Allocated in 4-GPR granularity 490 491#if !NO_SQC_STORE 492 buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 493#endif 494 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256 495 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*2 496 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3 497 498 /* save HW registers */ 499 500L_SAVE_HWREG: 501 // HWREG SR memory offset : size(VGPR)+size(SVGPR)+size(SGPR) 502 get_vgpr_size_bytes(s_save_mem_offset, s_wave_size) 503 get_svgpr_size_bytes(s_save_tmp) 504 s_add_u32 s_save_mem_offset, s_save_mem_offset, s_save_tmp 505 s_add_u32 s_save_mem_offset, s_save_mem_offset, get_sgpr_size_bytes() 506 507 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 508 509#if NO_SQC_STORE 510 v_mov_b32 v0, 0x0 //Offset[31:0] from buffer resource 511 v_mov_b32 v1, 0x0 //Offset[63:32] from buffer resource 512 v_mov_b32 v2, 0x0 //Set of SGPRs for TCP store 513 s_mov_b32 m0, 0x0 //Next lane of v2 to write to 514#endif 515 516 write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset) 517 write_hwreg_to_mem(s_save_pc_lo, s_save_buf_rsrc0, s_save_mem_offset) 518 s_andn2_b32 s_save_tmp, s_save_pc_hi, S_SAVE_PC_HI_FIRST_WAVE_MASK 519 write_hwreg_to_mem(s_save_tmp, s_save_buf_rsrc0, s_save_mem_offset) 520 write_hwreg_to_mem(s_save_exec_lo, s_save_buf_rsrc0, s_save_mem_offset) 521 write_hwreg_to_mem(s_save_exec_hi, s_save_buf_rsrc0, s_save_mem_offset) 522 write_hwreg_to_mem(s_save_status, s_save_buf_rsrc0, s_save_mem_offset) 523 524 s_getreg_b32 s_save_tmp, hwreg(HW_REG_TRAPSTS) 525 write_hwreg_to_mem(s_save_tmp, s_save_buf_rsrc0, s_save_mem_offset) 526 527 // Not used on Sienna_Cichlid but keep layout same for debugger. 528 write_hwreg_to_mem(s_save_xnack_mask, s_save_buf_rsrc0, s_save_mem_offset) 529 530 s_getreg_b32 s_save_m0, hwreg(HW_REG_MODE) 531 write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset) 532 533 s_getreg_b32 s_save_m0, hwreg(HW_REG_SHADER_FLAT_SCRATCH_LO) 534 write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset) 535 536 s_getreg_b32 s_save_m0, hwreg(HW_REG_SHADER_FLAT_SCRATCH_HI) 537 write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset) 538 539#if NO_SQC_STORE 540 // Write HWREGs with 16 VGPR lanes. TTMPs occupy space after this. 541 s_mov_b32 exec_lo, 0xFFFF 542 s_mov_b32 exec_hi, 0x0 543 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 544 545 // Write SGPRs with 32 VGPR lanes. This works in wave32 and wave64 mode. 546 s_mov_b32 exec_lo, 0xFFFFFFFF 547#endif 548 549 /* save SGPRs */ 550 // Save SGPR before LDS save, then the s0 to s4 can be used during LDS save... 551 552 // SGPR SR memory offset : size(VGPR)+size(SVGPR) 553 get_vgpr_size_bytes(s_save_mem_offset, s_wave_size) 554 get_svgpr_size_bytes(s_save_tmp) 555 s_add_u32 s_save_mem_offset, s_save_mem_offset, s_save_tmp 556 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 557 558#if NO_SQC_STORE 559 s_mov_b32 ttmp13, 0x0 //next VGPR lane to copy SGPR into 560#else 561 // backup s_save_buf_rsrc0,1 to s_save_pc_lo/hi, since write_16sgpr_to_mem function will change the rsrc0 562 s_mov_b32 s_save_xnack_mask, s_save_buf_rsrc0 563 s_add_u32 s_save_buf_rsrc0, s_save_buf_rsrc0, s_save_mem_offset 564 s_addc_u32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0 565#endif 566 567 s_mov_b32 m0, 0x0 //SGPR initial index value =0 568 s_nop 0x0 //Manually inserted wait states 569L_SAVE_SGPR_LOOP: 570 // SGPR is allocated in 16 SGPR granularity 571 s_movrels_b64 s0, s0 //s0 = s[0+m0], s1 = s[1+m0] 572 s_movrels_b64 s2, s2 //s2 = s[2+m0], s3 = s[3+m0] 573 s_movrels_b64 s4, s4 //s4 = s[4+m0], s5 = s[5+m0] 574 s_movrels_b64 s6, s6 //s6 = s[6+m0], s7 = s[7+m0] 575 s_movrels_b64 s8, s8 //s8 = s[8+m0], s9 = s[9+m0] 576 s_movrels_b64 s10, s10 //s10 = s[10+m0], s11 = s[11+m0] 577 s_movrels_b64 s12, s12 //s12 = s[12+m0], s13 = s[13+m0] 578 s_movrels_b64 s14, s14 //s14 = s[14+m0], s15 = s[15+m0] 579 580 write_16sgpr_to_mem(s0, s_save_buf_rsrc0, s_save_mem_offset) 581 582#if NO_SQC_STORE 583 s_cmp_eq_u32 ttmp13, 0x20 //have 32 VGPR lanes filled? 584 s_cbranch_scc0 L_SAVE_SGPR_SKIP_TCP_STORE 585 586 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 587 s_add_u32 s_save_mem_offset, s_save_mem_offset, 0x80 588 s_mov_b32 ttmp13, 0x0 589 v_mov_b32 v2, 0x0 590L_SAVE_SGPR_SKIP_TCP_STORE: 591#endif 592 593 s_add_u32 m0, m0, 16 //next sgpr index 594 s_cmp_lt_u32 m0, 96 //scc = (m0 < first 96 SGPR) ? 1 : 0 595 s_cbranch_scc1 L_SAVE_SGPR_LOOP //first 96 SGPR save is complete? 596 597 //save the rest 12 SGPR 598 s_movrels_b64 s0, s0 //s0 = s[0+m0], s1 = s[1+m0] 599 s_movrels_b64 s2, s2 //s2 = s[2+m0], s3 = s[3+m0] 600 s_movrels_b64 s4, s4 //s4 = s[4+m0], s5 = s[5+m0] 601 s_movrels_b64 s6, s6 //s6 = s[6+m0], s7 = s[7+m0] 602 s_movrels_b64 s8, s8 //s8 = s[8+m0], s9 = s[9+m0] 603 s_movrels_b64 s10, s10 //s10 = s[10+m0], s11 = s[11+m0] 604 write_12sgpr_to_mem(s0, s_save_buf_rsrc0, s_save_mem_offset) 605 606#if NO_SQC_STORE 607 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 608#else 609 // restore s_save_buf_rsrc0,1 610 s_mov_b32 s_save_buf_rsrc0, s_save_xnack_mask 611#endif 612 613 /* save LDS */ 614 615L_SAVE_LDS: 616 // Change EXEC to all threads... 617 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on 618 s_lshr_b32 m0, s_wave_size, S_WAVE_SIZE 619 s_and_b32 m0, m0, 1 620 s_cmp_eq_u32 m0, 1 621 s_cbranch_scc1 L_ENABLE_SAVE_LDS_EXEC_HI 622 s_mov_b32 exec_hi, 0x00000000 623 s_branch L_SAVE_LDS_NORMAL 624L_ENABLE_SAVE_LDS_EXEC_HI: 625 s_mov_b32 exec_hi, 0xFFFFFFFF 626L_SAVE_LDS_NORMAL: 627 s_getreg_b32 s_save_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) 628 s_and_b32 s_save_alloc_size, s_save_alloc_size, 0xFFFFFFFF //lds_size is zero? 629 s_cbranch_scc0 L_SAVE_LDS_DONE //no lds used? jump to L_SAVE_DONE 630 631 s_barrier //LDS is used? wait for other waves in the same TG 632 s_and_b32 s_save_tmp, s_save_pc_hi, S_SAVE_PC_HI_FIRST_WAVE_MASK 633 s_cbranch_scc0 L_SAVE_LDS_DONE 634 635 // first wave do LDS save; 636 637 s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 6 //LDS size in dwords = lds_size * 64dw 638 s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 2 //LDS size in bytes 639 s_mov_b32 s_save_buf_rsrc2, s_save_alloc_size //NUM_RECORDS in bytes 640 641 // LDS at offset: size(VGPR)+size(SVGPR)+SIZE(SGPR)+SIZE(HWREG) 642 // 643 get_vgpr_size_bytes(s_save_mem_offset, s_wave_size) 644 get_svgpr_size_bytes(s_save_tmp) 645 s_add_u32 s_save_mem_offset, s_save_mem_offset, s_save_tmp 646 s_add_u32 s_save_mem_offset, s_save_mem_offset, get_sgpr_size_bytes() 647 s_add_u32 s_save_mem_offset, s_save_mem_offset, get_hwreg_size_bytes() 648 649 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 650 651 //load 0~63*4(byte address) to vgpr v0 652 v_mbcnt_lo_u32_b32 v0, -1, 0 653 v_mbcnt_hi_u32_b32 v0, -1, v0 654 v_mul_u32_u24 v0, 4, v0 655 656 s_lshr_b32 m0, s_wave_size, S_WAVE_SIZE 657 s_and_b32 m0, m0, 1 658 s_cmp_eq_u32 m0, 1 659 s_mov_b32 m0, 0x0 660 s_cbranch_scc1 L_SAVE_LDS_W64 661 662L_SAVE_LDS_W32: 663 s_mov_b32 s3, 128 664 s_nop 0 665 s_nop 0 666 s_nop 0 667L_SAVE_LDS_LOOP_W32: 668 ds_read_b32 v1, v0 669 s_waitcnt 0 670 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 671 672 s_add_u32 m0, m0, s3 //every buffer_store_lds does 256 bytes 673 s_add_u32 s_save_mem_offset, s_save_mem_offset, s3 674 v_add_nc_u32 v0, v0, 128 //mem offset increased by 128 bytes 675 s_cmp_lt_u32 m0, s_save_alloc_size //scc=(m0 < s_save_alloc_size) ? 1 : 0 676 s_cbranch_scc1 L_SAVE_LDS_LOOP_W32 //LDS save is complete? 677 678 s_branch L_SAVE_LDS_DONE 679 680L_SAVE_LDS_W64: 681 s_mov_b32 s3, 256 682 s_nop 0 683 s_nop 0 684 s_nop 0 685L_SAVE_LDS_LOOP_W64: 686 ds_read_b32 v1, v0 687 s_waitcnt 0 688 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 689 690 s_add_u32 m0, m0, s3 //every buffer_store_lds does 256 bytes 691 s_add_u32 s_save_mem_offset, s_save_mem_offset, s3 692 v_add_nc_u32 v0, v0, 256 //mem offset increased by 256 bytes 693 s_cmp_lt_u32 m0, s_save_alloc_size //scc=(m0 < s_save_alloc_size) ? 1 : 0 694 s_cbranch_scc1 L_SAVE_LDS_LOOP_W64 //LDS save is complete? 695 696L_SAVE_LDS_DONE: 697 /* save VGPRs - set the Rest VGPRs */ 698L_SAVE_VGPR: 699 // VGPR SR memory offset: 0 700 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on 701 s_lshr_b32 m0, s_wave_size, S_WAVE_SIZE 702 s_and_b32 m0, m0, 1 703 s_cmp_eq_u32 m0, 1 704 s_cbranch_scc1 L_ENABLE_SAVE_VGPR_EXEC_HI 705 s_mov_b32 s_save_mem_offset, (0+128*4) // for the rest VGPRs 706 s_mov_b32 exec_hi, 0x00000000 707 s_branch L_SAVE_VGPR_NORMAL 708L_ENABLE_SAVE_VGPR_EXEC_HI: 709 s_mov_b32 s_save_mem_offset, (0+256*4) // for the rest VGPRs 710 s_mov_b32 exec_hi, 0xFFFFFFFF 711L_SAVE_VGPR_NORMAL: 712 s_getreg_b32 s_save_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) 713 s_add_u32 s_save_alloc_size, s_save_alloc_size, 1 714 s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 2 //Number of VGPRs = (vgpr_size + 1) * 4 (non-zero value) 715 //determine it is wave32 or wave64 716 s_lshr_b32 m0, s_wave_size, S_WAVE_SIZE 717 s_and_b32 m0, m0, 1 718 s_cmp_eq_u32 m0, 1 719 s_cbranch_scc1 L_SAVE_VGPR_WAVE64 720 721 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 722 723 // VGPR Allocated in 4-GPR granularity 724 725 // VGPR store using dw burst 726 s_mov_b32 m0, 0x4 //VGPR initial index value =4 727 s_cmp_lt_u32 m0, s_save_alloc_size 728 s_cbranch_scc0 L_SAVE_VGPR_END 729 730L_SAVE_VGPR_W32_LOOP: 731 v_movrels_b32 v0, v0 //v0 = v[0+m0] 732 v_movrels_b32 v1, v1 //v1 = v[1+m0] 733 v_movrels_b32 v2, v2 //v2 = v[2+m0] 734 v_movrels_b32 v3, v3 //v3 = v[3+m0] 735 736 buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 737 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:128 738 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:128*2 739 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:128*3 740 741 s_add_u32 m0, m0, 4 //next vgpr index 742 s_add_u32 s_save_mem_offset, s_save_mem_offset, 128*4 //every buffer_store_dword does 128 bytes 743 s_cmp_lt_u32 m0, s_save_alloc_size //scc = (m0 < s_save_alloc_size) ? 1 : 0 744 s_cbranch_scc1 L_SAVE_VGPR_W32_LOOP //VGPR save is complete? 745 746 s_branch L_SAVE_VGPR_END 747 748L_SAVE_VGPR_WAVE64: 749 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 750 751 // VGPR store using dw burst 752 s_mov_b32 m0, 0x4 //VGPR initial index value =4 753 s_cmp_lt_u32 m0, s_save_alloc_size 754 s_cbranch_scc0 L_SAVE_SHARED_VGPR 755 756L_SAVE_VGPR_W64_LOOP: 757 v_movrels_b32 v0, v0 //v0 = v[0+m0] 758 v_movrels_b32 v1, v1 //v1 = v[1+m0] 759 v_movrels_b32 v2, v2 //v2 = v[2+m0] 760 v_movrels_b32 v3, v3 //v3 = v[3+m0] 761 762 buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 763 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256 764 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*2 765 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3 766 767 s_add_u32 m0, m0, 4 //next vgpr index 768 s_add_u32 s_save_mem_offset, s_save_mem_offset, 256*4 //every buffer_store_dword does 256 bytes 769 s_cmp_lt_u32 m0, s_save_alloc_size //scc = (m0 < s_save_alloc_size) ? 1 : 0 770 s_cbranch_scc1 L_SAVE_VGPR_W64_LOOP //VGPR save is complete? 771 772L_SAVE_SHARED_VGPR: 773 //Below part will be the save shared vgpr part (new for gfx10) 774 s_getreg_b32 s_save_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SIZE) 775 s_and_b32 s_save_alloc_size, s_save_alloc_size, 0xFFFFFFFF //shared_vgpr_size is zero? 776 s_cbranch_scc0 L_SAVE_VGPR_END //no shared_vgpr used? jump to L_SAVE_LDS 777 s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 3 //Number of SHARED_VGPRs = shared_vgpr_size * 8 (non-zero value) 778 //m0 now has the value of normal vgpr count, just add the m0 with shared_vgpr count to get the total count. 779 //save shared_vgpr will start from the index of m0 780 s_add_u32 s_save_alloc_size, s_save_alloc_size, m0 781 s_mov_b32 exec_lo, 0xFFFFFFFF 782 s_mov_b32 exec_hi, 0x00000000 783L_SAVE_SHARED_VGPR_WAVE64_LOOP: 784 v_movrels_b32 v0, v0 //v0 = v[0+m0] 785 buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 786 s_add_u32 m0, m0, 1 //next vgpr index 787 s_add_u32 s_save_mem_offset, s_save_mem_offset, 128 788 s_cmp_lt_u32 m0, s_save_alloc_size //scc = (m0 < s_save_alloc_size) ? 1 : 0 789 s_cbranch_scc1 L_SAVE_SHARED_VGPR_WAVE64_LOOP //SHARED_VGPR save is complete? 790 791L_SAVE_VGPR_END: 792 s_branch L_END_PGM 793 794L_RESTORE: 795 /* Setup Resource Contants */ 796 s_mov_b32 s_restore_buf_rsrc0, s_restore_spi_init_lo //base_addr_lo 797 s_and_b32 s_restore_buf_rsrc1, s_restore_spi_init_hi, 0x0000FFFF //base_addr_hi 798 s_or_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, S_RESTORE_BUF_RSRC_WORD1_STRIDE 799 s_mov_b32 s_restore_buf_rsrc2, 0 //NUM_RECORDS initial value = 0 (in bytes) 800 s_mov_b32 s_restore_buf_rsrc3, S_RESTORE_BUF_RSRC_WORD3_MISC 801 802 //determine it is wave32 or wave64 803 get_wave_size(s_restore_size) 804 805 s_and_b32 s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_FIRST_WAVE_MASK 806 s_cbranch_scc0 L_RESTORE_VGPR 807 808 /* restore LDS */ 809L_RESTORE_LDS: 810 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on 811 s_lshr_b32 m0, s_restore_size, S_WAVE_SIZE 812 s_and_b32 m0, m0, 1 813 s_cmp_eq_u32 m0, 1 814 s_cbranch_scc1 L_ENABLE_RESTORE_LDS_EXEC_HI 815 s_mov_b32 exec_hi, 0x00000000 816 s_branch L_RESTORE_LDS_NORMAL 817L_ENABLE_RESTORE_LDS_EXEC_HI: 818 s_mov_b32 exec_hi, 0xFFFFFFFF 819L_RESTORE_LDS_NORMAL: 820 s_getreg_b32 s_restore_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) 821 s_and_b32 s_restore_alloc_size, s_restore_alloc_size, 0xFFFFFFFF //lds_size is zero? 822 s_cbranch_scc0 L_RESTORE_VGPR //no lds used? jump to L_RESTORE_VGPR 823 s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 6 //LDS size in dwords = lds_size * 64dw 824 s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 2 //LDS size in bytes 825 s_mov_b32 s_restore_buf_rsrc2, s_restore_alloc_size //NUM_RECORDS in bytes 826 827 // LDS at offset: size(VGPR)+size(SVGPR)+SIZE(SGPR)+SIZE(HWREG) 828 // 829 get_vgpr_size_bytes(s_restore_mem_offset, s_restore_size) 830 get_svgpr_size_bytes(s_restore_tmp) 831 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp 832 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, get_sgpr_size_bytes() 833 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, get_hwreg_size_bytes() 834 835 s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 836 837 s_lshr_b32 m0, s_restore_size, S_WAVE_SIZE 838 s_and_b32 m0, m0, 1 839 s_cmp_eq_u32 m0, 1 840 s_mov_b32 m0, 0x0 841 s_cbranch_scc1 L_RESTORE_LDS_LOOP_W64 842 843L_RESTORE_LDS_LOOP_W32: 844#if HAVE_BUFFER_LDS_LOAD 845 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1 // first 64DW 846#else 847 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset 848 s_waitcnt vmcnt(0) 849 ds_store_addtid_b32 v0 850#endif 851 s_add_u32 m0, m0, 128 // 128 DW 852 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 128 //mem offset increased by 128DW 853 s_cmp_lt_u32 m0, s_restore_alloc_size //scc=(m0 < s_restore_alloc_size) ? 1 : 0 854 s_cbranch_scc1 L_RESTORE_LDS_LOOP_W32 //LDS restore is complete? 855 s_branch L_RESTORE_VGPR 856 857L_RESTORE_LDS_LOOP_W64: 858#if HAVE_BUFFER_LDS_LOAD 859 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1 // first 64DW 860#else 861 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset 862 s_waitcnt vmcnt(0) 863 ds_store_addtid_b32 v0 864#endif 865 s_add_u32 m0, m0, 256 // 256 DW 866 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256 //mem offset increased by 256DW 867 s_cmp_lt_u32 m0, s_restore_alloc_size //scc=(m0 < s_restore_alloc_size) ? 1 : 0 868 s_cbranch_scc1 L_RESTORE_LDS_LOOP_W64 //LDS restore is complete? 869 870 /* restore VGPRs */ 871L_RESTORE_VGPR: 872 // VGPR SR memory offset : 0 873 s_mov_b32 s_restore_mem_offset, 0x0 874 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on 875 s_lshr_b32 m0, s_restore_size, S_WAVE_SIZE 876 s_and_b32 m0, m0, 1 877 s_cmp_eq_u32 m0, 1 878 s_cbranch_scc1 L_ENABLE_RESTORE_VGPR_EXEC_HI 879 s_mov_b32 exec_hi, 0x00000000 880 s_branch L_RESTORE_VGPR_NORMAL 881L_ENABLE_RESTORE_VGPR_EXEC_HI: 882 s_mov_b32 exec_hi, 0xFFFFFFFF 883L_RESTORE_VGPR_NORMAL: 884 s_getreg_b32 s_restore_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) 885 s_add_u32 s_restore_alloc_size, s_restore_alloc_size, 1 886 s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 2 //Number of VGPRs = (vgpr_size + 1) * 4 (non-zero value) 887 //determine it is wave32 or wave64 888 s_lshr_b32 m0, s_restore_size, S_WAVE_SIZE 889 s_and_b32 m0, m0, 1 890 s_cmp_eq_u32 m0, 1 891 s_cbranch_scc1 L_RESTORE_VGPR_WAVE64 892 893 s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 894 895 // VGPR load using dw burst 896 s_mov_b32 s_restore_mem_offset_save, s_restore_mem_offset // restore start with v1, v0 will be the last 897 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 128*4 898 s_mov_b32 m0, 4 //VGPR initial index value = 4 899 s_cmp_lt_u32 m0, s_restore_alloc_size 900 s_cbranch_scc0 L_RESTORE_SGPR 901 902L_RESTORE_VGPR_WAVE32_LOOP: 903 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 904 buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:128 905 buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:128*2 906 buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:128*3 907 s_waitcnt vmcnt(0) 908 v_movreld_b32 v0, v0 //v[0+m0] = v0 909 v_movreld_b32 v1, v1 910 v_movreld_b32 v2, v2 911 v_movreld_b32 v3, v3 912 s_add_u32 m0, m0, 4 //next vgpr index 913 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 128*4 //every buffer_load_dword does 128 bytes 914 s_cmp_lt_u32 m0, s_restore_alloc_size //scc = (m0 < s_restore_alloc_size) ? 1 : 0 915 s_cbranch_scc1 L_RESTORE_VGPR_WAVE32_LOOP //VGPR restore (except v0) is complete? 916 917 /* VGPR restore on v0 */ 918 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 919 buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:128 920 buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:128*2 921 buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:128*3 922 s_waitcnt vmcnt(0) 923 924 s_branch L_RESTORE_SGPR 925 926L_RESTORE_VGPR_WAVE64: 927 s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 928 929 // VGPR load using dw burst 930 s_mov_b32 s_restore_mem_offset_save, s_restore_mem_offset // restore start with v4, v0 will be the last 931 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 932 s_mov_b32 m0, 4 //VGPR initial index value = 4 933 s_cmp_lt_u32 m0, s_restore_alloc_size 934 s_cbranch_scc0 L_RESTORE_SHARED_VGPR 935 936L_RESTORE_VGPR_WAVE64_LOOP: 937 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 938 buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256 939 buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256*2 940 buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256*3 941 s_waitcnt vmcnt(0) 942 v_movreld_b32 v0, v0 //v[0+m0] = v0 943 v_movreld_b32 v1, v1 944 v_movreld_b32 v2, v2 945 v_movreld_b32 v3, v3 946 s_add_u32 m0, m0, 4 //next vgpr index 947 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 //every buffer_load_dword does 256 bytes 948 s_cmp_lt_u32 m0, s_restore_alloc_size //scc = (m0 < s_restore_alloc_size) ? 1 : 0 949 s_cbranch_scc1 L_RESTORE_VGPR_WAVE64_LOOP //VGPR restore (except v0) is complete? 950 951L_RESTORE_SHARED_VGPR: 952 //Below part will be the restore shared vgpr part (new for gfx10) 953 s_getreg_b32 s_restore_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SIZE) //shared_vgpr_size 954 s_and_b32 s_restore_alloc_size, s_restore_alloc_size, 0xFFFFFFFF //shared_vgpr_size is zero? 955 s_cbranch_scc0 L_RESTORE_V0 //no shared_vgpr used? 956 s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 3 //Number of SHARED_VGPRs = shared_vgpr_size * 8 (non-zero value) 957 //m0 now has the value of normal vgpr count, just add the m0 with shared_vgpr count to get the total count. 958 //restore shared_vgpr will start from the index of m0 959 s_add_u32 s_restore_alloc_size, s_restore_alloc_size, m0 960 s_mov_b32 exec_lo, 0xFFFFFFFF 961 s_mov_b32 exec_hi, 0x00000000 962L_RESTORE_SHARED_VGPR_WAVE64_LOOP: 963 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 964 s_waitcnt vmcnt(0) 965 v_movreld_b32 v0, v0 //v[0+m0] = v0 966 s_add_u32 m0, m0, 1 //next vgpr index 967 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 128 968 s_cmp_lt_u32 m0, s_restore_alloc_size //scc = (m0 < s_restore_alloc_size) ? 1 : 0 969 s_cbranch_scc1 L_RESTORE_SHARED_VGPR_WAVE64_LOOP //VGPR restore (except v0) is complete? 970 971 s_mov_b32 exec_hi, 0xFFFFFFFF //restore back exec_hi before restoring V0!! 972 973 /* VGPR restore on v0 */ 974L_RESTORE_V0: 975 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 976 buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256 977 buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256*2 978 buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256*3 979 s_waitcnt vmcnt(0) 980 981 /* restore SGPRs */ 982 //will be 2+8+16*6 983 // SGPR SR memory offset : size(VGPR)+size(SVGPR) 984L_RESTORE_SGPR: 985 get_vgpr_size_bytes(s_restore_mem_offset, s_restore_size) 986 get_svgpr_size_bytes(s_restore_tmp) 987 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp 988 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, get_sgpr_size_bytes() 989 s_sub_u32 s_restore_mem_offset, s_restore_mem_offset, 20*4 //s108~s127 is not saved 990 991 s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 992 993 s_mov_b32 m0, s_sgpr_save_num 994 995 read_4sgpr_from_mem(s0, s_restore_buf_rsrc0, s_restore_mem_offset) 996 s_waitcnt lgkmcnt(0) 997 998 s_sub_u32 m0, m0, 4 // Restore from S[0] to S[104] 999 s_nop 0 // hazard SALU M0=> S_MOVREL 1000 1001 s_movreld_b64 s0, s0 //s[0+m0] = s0 1002 s_movreld_b64 s2, s2 1003 1004 read_8sgpr_from_mem(s0, s_restore_buf_rsrc0, s_restore_mem_offset) 1005 s_waitcnt lgkmcnt(0) 1006 1007 s_sub_u32 m0, m0, 8 // Restore from S[0] to S[96] 1008 s_nop 0 // hazard SALU M0=> S_MOVREL 1009 1010 s_movreld_b64 s0, s0 //s[0+m0] = s0 1011 s_movreld_b64 s2, s2 1012 s_movreld_b64 s4, s4 1013 s_movreld_b64 s6, s6 1014 1015 L_RESTORE_SGPR_LOOP: 1016 read_16sgpr_from_mem(s0, s_restore_buf_rsrc0, s_restore_mem_offset) 1017 s_waitcnt lgkmcnt(0) 1018 1019 s_sub_u32 m0, m0, 16 // Restore from S[n] to S[0] 1020 s_nop 0 // hazard SALU M0=> S_MOVREL 1021 1022 s_movreld_b64 s0, s0 //s[0+m0] = s0 1023 s_movreld_b64 s2, s2 1024 s_movreld_b64 s4, s4 1025 s_movreld_b64 s6, s6 1026 s_movreld_b64 s8, s8 1027 s_movreld_b64 s10, s10 1028 s_movreld_b64 s12, s12 1029 s_movreld_b64 s14, s14 1030 1031 s_cmp_eq_u32 m0, 0 //scc = (m0 < s_sgpr_save_num) ? 1 : 0 1032 s_cbranch_scc0 L_RESTORE_SGPR_LOOP 1033 1034 // s_barrier with MODE.DEBUG_EN=1, STATUS.PRIV=1 incorrectly asserts debug exception. 1035 // Clear DEBUG_EN before and restore MODE after the barrier. 1036 s_setreg_imm32_b32 hwreg(HW_REG_MODE), 0 1037 s_barrier //barrier to ensure the readiness of LDS before access attemps from any other wave in the same TG 1038 1039 /* restore HW registers */ 1040L_RESTORE_HWREG: 1041 // HWREG SR memory offset : size(VGPR)+size(SVGPR)+size(SGPR) 1042 get_vgpr_size_bytes(s_restore_mem_offset, s_restore_size) 1043 get_svgpr_size_bytes(s_restore_tmp) 1044 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp 1045 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, get_sgpr_size_bytes() 1046 1047 s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 1048 1049 read_hwreg_from_mem(s_restore_m0, s_restore_buf_rsrc0, s_restore_mem_offset) 1050 read_hwreg_from_mem(s_restore_pc_lo, s_restore_buf_rsrc0, s_restore_mem_offset) 1051 read_hwreg_from_mem(s_restore_pc_hi, s_restore_buf_rsrc0, s_restore_mem_offset) 1052 read_hwreg_from_mem(s_restore_exec_lo, s_restore_buf_rsrc0, s_restore_mem_offset) 1053 read_hwreg_from_mem(s_restore_exec_hi, s_restore_buf_rsrc0, s_restore_mem_offset) 1054 read_hwreg_from_mem(s_restore_status, s_restore_buf_rsrc0, s_restore_mem_offset) 1055 read_hwreg_from_mem(s_restore_trapsts, s_restore_buf_rsrc0, s_restore_mem_offset) 1056 read_hwreg_from_mem(s_restore_xnack_mask, s_restore_buf_rsrc0, s_restore_mem_offset) 1057 read_hwreg_from_mem(s_restore_mode, s_restore_buf_rsrc0, s_restore_mem_offset) 1058 read_hwreg_from_mem(s_restore_flat_scratch, s_restore_buf_rsrc0, s_restore_mem_offset) 1059 s_waitcnt lgkmcnt(0) 1060 1061 s_setreg_b32 hwreg(HW_REG_SHADER_FLAT_SCRATCH_LO), s_restore_flat_scratch 1062 1063 read_hwreg_from_mem(s_restore_flat_scratch, s_restore_buf_rsrc0, s_restore_mem_offset) 1064 s_waitcnt lgkmcnt(0) //from now on, it is safe to restore STATUS and IB_STS 1065 1066 s_setreg_b32 hwreg(HW_REG_SHADER_FLAT_SCRATCH_HI), s_restore_flat_scratch 1067 1068 s_mov_b32 m0, s_restore_m0 1069 s_mov_b32 exec_lo, s_restore_exec_lo 1070 s_mov_b32 exec_hi, s_restore_exec_hi 1071 1072 s_and_b32 s_restore_m0, SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK, s_restore_trapsts 1073 s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_PRE_SAVECTX_SHIFT, SQ_WAVE_TRAPSTS_PRE_SAVECTX_SIZE), s_restore_m0 1074 1075#if HAVE_XNACK 1076 s_setreg_b32 hwreg(HW_REG_SHADER_XNACK_MASK), s_restore_xnack_mask 1077#endif 1078 1079 s_and_b32 s_restore_m0, SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK, s_restore_trapsts 1080 s_lshr_b32 s_restore_m0, s_restore_m0, SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT 1081 s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT, SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE), s_restore_m0 1082 s_setreg_b32 hwreg(HW_REG_MODE), s_restore_mode 1083 1084 // Restore trap temporaries 4-11, 13 initialized by SPI debug dispatch logic 1085 // ttmp SR memory offset : size(VGPR)+size(SVGPR)+size(SGPR)+0x40 1086 get_vgpr_size_bytes(s_restore_ttmps_lo, s_restore_size) 1087 get_svgpr_size_bytes(s_restore_ttmps_hi) 1088 s_add_u32 s_restore_ttmps_lo, s_restore_ttmps_lo, s_restore_ttmps_hi 1089 s_add_u32 s_restore_ttmps_lo, s_restore_ttmps_lo, get_sgpr_size_bytes() 1090 s_add_u32 s_restore_ttmps_lo, s_restore_ttmps_lo, s_restore_buf_rsrc0 1091 s_addc_u32 s_restore_ttmps_hi, s_restore_buf_rsrc1, 0x0 1092 s_and_b32 s_restore_ttmps_hi, s_restore_ttmps_hi, 0xFFFF 1093 s_load_dwordx4 [ttmp4, ttmp5, ttmp6, ttmp7], [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x50 glc:1 1094 s_load_dwordx4 [ttmp8, ttmp9, ttmp10, ttmp11], [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x60 glc:1 1095 s_load_dword ttmp13, [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x74 glc:1 1096 s_waitcnt lgkmcnt(0) 1097 1098#if HAVE_XNACK 1099 restore_ib_sts(s_restore_tmp, s_restore_m0) 1100#endif 1101 1102 s_and_b32 s_restore_pc_hi, s_restore_pc_hi, 0x0000ffff //pc[47:32] //Do it here in order not to affect STATUS 1103 s_and_b64 exec, exec, exec // Restore STATUS.EXECZ, not writable by s_setreg_b32 1104 s_and_b64 vcc, vcc, vcc // Restore STATUS.VCCZ, not writable by s_setreg_b32 1105 1106#if SW_SA_TRAP 1107 // If traps are enabled then return to the shader with PRIV=0. 1108 // Otherwise retain PRIV=1 for subsequent context save requests. 1109 s_getreg_b32 s_restore_tmp, hwreg(HW_REG_STATUS) 1110 s_bitcmp1_b32 s_restore_tmp, SQ_WAVE_STATUS_TRAP_EN_SHIFT 1111 s_cbranch_scc1 L_RETURN_WITHOUT_PRIV 1112 1113 s_setreg_b32 hwreg(HW_REG_STATUS), s_restore_status // SCC is included, which is changed by previous salu 1114 s_setpc_b64 [s_restore_pc_lo, s_restore_pc_hi] 1115L_RETURN_WITHOUT_PRIV: 1116#endif 1117 1118 s_setreg_b32 hwreg(HW_REG_STATUS), s_restore_status // SCC is included, which is changed by previous salu 1119 s_rfe_b64 s_restore_pc_lo //Return to the main shader program and resume execution 1120 1121L_END_PGM: 1122 s_endpgm_saved 1123end 1124 1125function write_hwreg_to_mem(s, s_rsrc, s_mem_offset) 1126#if NO_SQC_STORE 1127 // Copy into VGPR for later TCP store. 1128 v_writelane_b32 v2, s, m0 1129 s_add_u32 m0, m0, 0x1 1130#else 1131 s_mov_b32 exec_lo, m0 1132 s_mov_b32 m0, s_mem_offset 1133 s_buffer_store_dword s, s_rsrc, m0 glc:1 1134 s_add_u32 s_mem_offset, s_mem_offset, 4 1135 s_mov_b32 m0, exec_lo 1136#endif 1137end 1138 1139 1140function write_16sgpr_to_mem(s, s_rsrc, s_mem_offset) 1141#if NO_SQC_STORE 1142 // Copy into VGPR for later TCP store. 1143 for var sgpr_idx = 0; sgpr_idx < 16; sgpr_idx ++ 1144 v_writelane_b32 v2, s[sgpr_idx], ttmp13 1145 s_add_u32 ttmp13, ttmp13, 0x1 1146 end 1147#else 1148 s_buffer_store_dwordx4 s[0], s_rsrc, 0 glc:1 1149 s_buffer_store_dwordx4 s[4], s_rsrc, 16 glc:1 1150 s_buffer_store_dwordx4 s[8], s_rsrc, 32 glc:1 1151 s_buffer_store_dwordx4 s[12], s_rsrc, 48 glc:1 1152 s_add_u32 s_rsrc[0], s_rsrc[0], 4*16 1153 s_addc_u32 s_rsrc[1], s_rsrc[1], 0x0 1154#endif 1155end 1156 1157function write_12sgpr_to_mem(s, s_rsrc, s_mem_offset) 1158#if NO_SQC_STORE 1159 // Copy into VGPR for later TCP store. 1160 for var sgpr_idx = 0; sgpr_idx < 12; sgpr_idx ++ 1161 v_writelane_b32 v2, s[sgpr_idx], ttmp13 1162 s_add_u32 ttmp13, ttmp13, 0x1 1163 end 1164#else 1165 s_buffer_store_dwordx4 s[0], s_rsrc, 0 glc:1 1166 s_buffer_store_dwordx4 s[4], s_rsrc, 16 glc:1 1167 s_buffer_store_dwordx4 s[8], s_rsrc, 32 glc:1 1168 s_add_u32 s_rsrc[0], s_rsrc[0], 4*12 1169 s_addc_u32 s_rsrc[1], s_rsrc[1], 0x0 1170#endif 1171end 1172 1173function read_hwreg_from_mem(s, s_rsrc, s_mem_offset) 1174 s_buffer_load_dword s, s_rsrc, s_mem_offset glc:1 1175 s_add_u32 s_mem_offset, s_mem_offset, 4 1176end 1177 1178function read_16sgpr_from_mem(s, s_rsrc, s_mem_offset) 1179 s_sub_u32 s_mem_offset, s_mem_offset, 4*16 1180 s_buffer_load_dwordx16 s, s_rsrc, s_mem_offset glc:1 1181end 1182 1183function read_8sgpr_from_mem(s, s_rsrc, s_mem_offset) 1184 s_sub_u32 s_mem_offset, s_mem_offset, 4*8 1185 s_buffer_load_dwordx8 s, s_rsrc, s_mem_offset glc:1 1186end 1187 1188function read_4sgpr_from_mem(s, s_rsrc, s_mem_offset) 1189 s_sub_u32 s_mem_offset, s_mem_offset, 4*4 1190 s_buffer_load_dwordx4 s, s_rsrc, s_mem_offset glc:1 1191end 1192 1193 1194function get_lds_size_bytes(s_lds_size_byte) 1195 s_getreg_b32 s_lds_size_byte, hwreg(HW_REG_LDS_ALLOC, SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT, SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) 1196 s_lshl_b32 s_lds_size_byte, s_lds_size_byte, 8 //LDS size in dwords = lds_size * 64 *4Bytes // granularity 64DW 1197end 1198 1199function get_vgpr_size_bytes(s_vgpr_size_byte, s_size) 1200 s_getreg_b32 s_vgpr_size_byte, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) 1201 s_add_u32 s_vgpr_size_byte, s_vgpr_size_byte, 1 1202 s_bitcmp1_b32 s_size, S_WAVE_SIZE 1203 s_cbranch_scc1 L_ENABLE_SHIFT_W64 1204 s_lshl_b32 s_vgpr_size_byte, s_vgpr_size_byte, (2+7) //Number of VGPRs = (vgpr_size + 1) * 4 * 32 * 4 (non-zero value) 1205 s_branch L_SHIFT_DONE 1206L_ENABLE_SHIFT_W64: 1207 s_lshl_b32 s_vgpr_size_byte, s_vgpr_size_byte, (2+8) //Number of VGPRs = (vgpr_size + 1) * 4 * 64 * 4 (non-zero value) 1208L_SHIFT_DONE: 1209end 1210 1211function get_svgpr_size_bytes(s_svgpr_size_byte) 1212 s_getreg_b32 s_svgpr_size_byte, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SIZE) 1213 s_lshl_b32 s_svgpr_size_byte, s_svgpr_size_byte, (3+7) 1214end 1215 1216function get_sgpr_size_bytes 1217 return 512 1218end 1219 1220function get_hwreg_size_bytes 1221 return 128 1222end 1223 1224function get_wave_size(s_reg) 1225 s_getreg_b32 s_reg, hwreg(HW_REG_IB_STS2,SQ_WAVE_IB_STS2_WAVE64_SHIFT,SQ_WAVE_IB_STS2_WAVE64_SIZE) 1226 s_lshl_b32 s_reg, s_reg, S_WAVE_SIZE 1227end 1228 1229function save_and_clear_ib_sts(tmp1, tmp2) 1230 // Preserve and clear scalar XNACK state before issuing scalar loads. 1231 // Save IB_STS.REPLAY_W64H[25], RCNT[21:16], FIRST_REPLAY[15] into 1232 // unused space ttmp11[31:24]. 1233 s_andn2_b32 ttmp11, ttmp11, (TTMP11_SAVE_REPLAY_W64H_MASK | TTMP11_SAVE_RCNT_FIRST_REPLAY_MASK) 1234 s_getreg_b32 tmp1, hwreg(HW_REG_IB_STS) 1235 s_and_b32 tmp2, tmp1, SQ_WAVE_IB_STS_REPLAY_W64H_MASK 1236 s_lshl_b32 tmp2, tmp2, (TTMP11_SAVE_REPLAY_W64H_SHIFT - SQ_WAVE_IB_STS_REPLAY_W64H_SHIFT) 1237 s_or_b32 ttmp11, ttmp11, tmp2 1238 s_and_b32 tmp2, tmp1, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK 1239 s_lshl_b32 tmp2, tmp2, (TTMP11_SAVE_RCNT_FIRST_REPLAY_SHIFT - SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT) 1240 s_or_b32 ttmp11, ttmp11, tmp2 1241 s_andn2_b32 tmp1, tmp1, (SQ_WAVE_IB_STS_REPLAY_W64H_MASK | SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK) 1242 s_setreg_b32 hwreg(HW_REG_IB_STS), tmp1 1243end 1244 1245function restore_ib_sts(tmp1, tmp2) 1246 s_lshr_b32 tmp1, ttmp11, (TTMP11_SAVE_RCNT_FIRST_REPLAY_SHIFT - SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT) 1247 s_and_b32 tmp2, tmp1, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK 1248 s_lshr_b32 tmp1, ttmp11, (TTMP11_SAVE_REPLAY_W64H_SHIFT - SQ_WAVE_IB_STS_REPLAY_W64H_SHIFT) 1249 s_and_b32 tmp1, tmp1, SQ_WAVE_IB_STS_REPLAY_W64H_MASK 1250 s_or_b32 tmp1, tmp1, tmp2 1251 s_setreg_b32 hwreg(HW_REG_IB_STS), tmp1 1252end 1253