1/* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23/* To compile this assembly code: 24 * 25 * gfx9: 26 * cpp -DASIC_FAMILY=CHIP_VEGAM cwsr_trap_handler_gfx9.asm -P -o gfx9.sp3 27 * sp3 gfx9.sp3 -hex gfx9.hex 28 * 29 * arcturus: 30 * cpp -DASIC_FAMILY=CHIP_ARCTURUS cwsr_trap_handler_gfx9.asm -P -o arcturus.sp3 31 * sp3 arcturus.sp3 -hex arcturus.hex 32 * 33 * aldebaran: 34 * cpp -DASIC_FAMILY=CHIP_ALDEBARAN cwsr_trap_handler_gfx9.asm -P -o aldebaran.sp3 35 * sp3 aldebaran.sp3 -hex aldebaran.hex 36 * 37 * gc_9_4_3: 38 * cpp -DASIC_FAMILY=GC_9_4_3 cwsr_trap_handler_gfx9.asm -P -o gc_9_4_3.sp3 39 * sp3 gc_9_4_3.sp3 -hex gc_9_4_3.hex 40 */ 41 42#define CHIP_VEGAM 18 43#define CHIP_ARCTURUS 23 44#define CHIP_ALDEBARAN 25 45#define CHIP_GC_9_4_3 26 46 47var ACK_SQC_STORE = 1 //workaround for suspected SQC store bug causing incorrect stores under concurrency 48var SAVE_AFTER_XNACK_ERROR = 1 //workaround for TCP store failure after XNACK error when ALLOW_REPLAY=0, for debugger 49var SINGLE_STEP_MISSED_WORKAROUND = (ASIC_FAMILY <= CHIP_ALDEBARAN) //workaround for lost MODE.DEBUG_EN exception when SAVECTX raised 50 51/**************************************************************************/ 52/* variables */ 53/**************************************************************************/ 54var SQ_WAVE_STATUS_SPI_PRIO_SHIFT = 1 55var SQ_WAVE_STATUS_SPI_PRIO_MASK = 0x00000006 56var SQ_WAVE_STATUS_HALT_MASK = 0x2000 57var SQ_WAVE_STATUS_PRE_SPI_PRIO_SHIFT = 0 58var SQ_WAVE_STATUS_PRE_SPI_PRIO_SIZE = 1 59var SQ_WAVE_STATUS_POST_SPI_PRIO_SHIFT = 3 60var SQ_WAVE_STATUS_POST_SPI_PRIO_SIZE = 29 61var SQ_WAVE_STATUS_ALLOW_REPLAY_MASK = 0x400000 62var SQ_WAVE_STATUS_ECC_ERR_MASK = 0x20000 63 64var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT = 12 65var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE = 9 66var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE = 6 67var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE = 3 //FIXME sq.blk still has 4 bits at this time while SQ programming guide has 3 bits 68var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT = 24 69 70#if ASIC_FAMILY >= CHIP_ALDEBARAN 71var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT = 6 72var SQ_WAVE_GPR_ALLOC_ACCV_OFFSET_SHIFT = 12 73var SQ_WAVE_GPR_ALLOC_ACCV_OFFSET_SIZE = 6 74#else 75var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT = 8 76#endif 77 78var SQ_WAVE_TRAPSTS_SAVECTX_MASK = 0x400 79var SQ_WAVE_TRAPSTS_EXCP_MASK = 0x1FF 80var SQ_WAVE_TRAPSTS_SAVECTX_SHIFT = 10 81var SQ_WAVE_TRAPSTS_ADDR_WATCH_MASK = 0x80 82var SQ_WAVE_TRAPSTS_ADDR_WATCH_SHIFT = 7 83var SQ_WAVE_TRAPSTS_MEM_VIOL_MASK = 0x100 84var SQ_WAVE_TRAPSTS_MEM_VIOL_SHIFT = 8 85var SQ_WAVE_TRAPSTS_HOST_TRAP_MASK = 0x400000 86var SQ_WAVE_TRAPSTS_WAVE_BEGIN_MASK = 0x800000 87var SQ_WAVE_TRAPSTS_WAVE_END_MASK = 0x1000000 88var SQ_WAVE_TRAPSTS_TRAP_AFTER_INST_MASK = 0x2000000 89var SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK = 0x3FF 90var SQ_WAVE_TRAPSTS_PRE_SAVECTX_SHIFT = 0x0 91var SQ_WAVE_TRAPSTS_PRE_SAVECTX_SIZE = 10 92var SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK = 0xFFFFF800 93var SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT = 11 94var SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE = 21 95var SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK = 0x800 96var SQ_WAVE_TRAPSTS_EXCP_HI_MASK = 0x7000 97var SQ_WAVE_TRAPSTS_XNACK_ERROR_MASK = 0x10000000 98 99var SQ_WAVE_MODE_EXCP_EN_SHIFT = 12 100var SQ_WAVE_MODE_EXCP_EN_ADDR_WATCH_SHIFT = 19 101 102var SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT = 15 //FIXME 103var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK = 0x1F8000 104 105var SQ_WAVE_MODE_DEBUG_EN_MASK = 0x800 106 107var TTMP_SAVE_RCNT_FIRST_REPLAY_SHIFT = 26 // bits [31:26] unused by SPI debug data 108var TTMP_SAVE_RCNT_FIRST_REPLAY_MASK = 0xFC000000 109var TTMP_DEBUG_TRAP_ENABLED_SHIFT = 23 110var TTMP_DEBUG_TRAP_ENABLED_MASK = 0x800000 111 112/* Save */ 113var S_SAVE_BUF_RSRC_WORD1_STRIDE = 0x00040000 //stride is 4 bytes 114var S_SAVE_BUF_RSRC_WORD3_MISC = 0x00807FAC //SQ_SEL_X/Y/Z/W, BUF_NUM_FORMAT_FLOAT, (0 for MUBUF stride[17:14] when ADD_TID_ENABLE and BUF_DATA_FORMAT_32 for MTBUF), ADD_TID_ENABLE 115var S_SAVE_PC_HI_TRAP_ID_MASK = 0x00FF0000 116var S_SAVE_PC_HI_HT_MASK = 0x01000000 117var S_SAVE_SPI_INIT_FIRST_WAVE_MASK = 0x04000000 //bit[26]: FirstWaveInTG 118var S_SAVE_SPI_INIT_FIRST_WAVE_SHIFT = 26 119 120var s_save_spi_init_lo = exec_lo 121var s_save_spi_init_hi = exec_hi 122 123var s_save_pc_lo = ttmp0 //{TTMP1, TTMP0} = {3'h0,pc_rewind[3:0], HT[0],trapID[7:0], PC[47:0]} 124var s_save_pc_hi = ttmp1 125var s_save_exec_lo = ttmp2 126var s_save_exec_hi = ttmp3 127var s_save_tmp = ttmp14 128var s_save_trapsts = ttmp15 //not really used until the end of the SAVE routine 129var s_save_xnack_mask_lo = ttmp6 130var s_save_xnack_mask_hi = ttmp7 131var s_save_buf_rsrc0 = ttmp8 132var s_save_buf_rsrc1 = ttmp9 133var s_save_buf_rsrc2 = ttmp10 134var s_save_buf_rsrc3 = ttmp11 135var s_save_status = ttmp12 136var s_save_mem_offset = ttmp4 137var s_save_alloc_size = s_save_trapsts //conflict 138var s_save_m0 = ttmp5 139var s_save_ttmps_lo = s_save_tmp //no conflict 140var s_save_ttmps_hi = s_save_trapsts //no conflict 141#if ASIC_FAMILY >= CHIP_GC_9_4_3 142var s_save_ib_sts = ttmp13 143#else 144var s_save_ib_sts = ttmp11 145#endif 146 147/* Restore */ 148var S_RESTORE_BUF_RSRC_WORD1_STRIDE = S_SAVE_BUF_RSRC_WORD1_STRIDE 149var S_RESTORE_BUF_RSRC_WORD3_MISC = S_SAVE_BUF_RSRC_WORD3_MISC 150 151var S_RESTORE_SPI_INIT_FIRST_WAVE_MASK = 0x04000000 //bit[26]: FirstWaveInTG 152var S_RESTORE_SPI_INIT_FIRST_WAVE_SHIFT = 26 153 154var s_restore_spi_init_lo = exec_lo 155var s_restore_spi_init_hi = exec_hi 156 157var s_restore_mem_offset = ttmp12 158var s_restore_tmp2 = ttmp13 159var s_restore_alloc_size = ttmp3 160var s_restore_tmp = ttmp2 161var s_restore_mem_offset_save = s_restore_tmp //no conflict 162var s_restore_accvgpr_offset_save = ttmp7 163 164var s_restore_m0 = s_restore_alloc_size //no conflict 165 166var s_restore_mode = s_restore_accvgpr_offset_save 167 168var s_restore_pc_lo = ttmp0 169var s_restore_pc_hi = ttmp1 170var s_restore_exec_lo = ttmp4 171var s_restore_exec_hi = ttmp5 172var s_restore_status = ttmp14 173var s_restore_trapsts = ttmp15 174var s_restore_xnack_mask_lo = xnack_mask_lo 175var s_restore_xnack_mask_hi = xnack_mask_hi 176var s_restore_buf_rsrc0 = ttmp8 177var s_restore_buf_rsrc1 = ttmp9 178var s_restore_buf_rsrc2 = ttmp10 179var s_restore_buf_rsrc3 = ttmp11 180var s_restore_ttmps_lo = s_restore_tmp //no conflict 181var s_restore_ttmps_hi = s_restore_alloc_size //no conflict 182 183/**************************************************************************/ 184/* trap handler entry points */ 185/**************************************************************************/ 186/* Shader Main*/ 187 188shader main 189 asic(DEFAULT) 190 type(CS) 191 192 193 s_branch L_SKIP_RESTORE //NOT restore. might be a regular trap or save 194 195L_JUMP_TO_RESTORE: 196 s_branch L_RESTORE //restore 197 198L_SKIP_RESTORE: 199 200 s_getreg_b32 s_save_status, hwreg(HW_REG_STATUS) //save STATUS since we will change SCC 201 202 // Clear SPI_PRIO: do not save with elevated priority. 203 // Clear ECC_ERR: prevents SQC store and triggers FATAL_HALT if setreg'd. 204 s_andn2_b32 s_save_status, s_save_status, SQ_WAVE_STATUS_SPI_PRIO_MASK|SQ_WAVE_STATUS_ECC_ERR_MASK 205 206 s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) 207 208 s_and_b32 ttmp2, s_save_status, SQ_WAVE_STATUS_HALT_MASK 209 s_cbranch_scc0 L_NOT_HALTED 210 211L_HALTED: 212 // Host trap may occur while wave is halted. 213 s_and_b32 ttmp2, s_save_pc_hi, S_SAVE_PC_HI_TRAP_ID_MASK 214 s_cbranch_scc1 L_FETCH_2ND_TRAP 215 216L_CHECK_SAVE: 217 s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_SAVECTX_MASK //check whether this is for save 218 s_cbranch_scc1 L_SAVE //this is the operation for save 219 220 // Wave is halted but neither host trap nor SAVECTX is raised. 221 // Caused by instruction fetch memory violation. 222 // Spin wait until context saved to prevent interrupt storm. 223 s_sleep 0x10 224 s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) 225 s_branch L_CHECK_SAVE 226 227L_NOT_HALTED: 228 // Let second-level handle non-SAVECTX exception or trap. 229 // Any concurrent SAVECTX will be handled upon re-entry once halted. 230 231 // Check non-maskable exceptions. memory_violation, illegal_instruction 232 // and debugger (host trap, wave start/end, trap after instruction) 233 // exceptions always cause the wave to enter the trap handler. 234 s_and_b32 ttmp2, s_save_trapsts, \ 235 SQ_WAVE_TRAPSTS_MEM_VIOL_MASK | \ 236 SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK | \ 237 SQ_WAVE_TRAPSTS_HOST_TRAP_MASK | \ 238 SQ_WAVE_TRAPSTS_WAVE_BEGIN_MASK | \ 239 SQ_WAVE_TRAPSTS_WAVE_END_MASK | \ 240 SQ_WAVE_TRAPSTS_TRAP_AFTER_INST_MASK 241 s_cbranch_scc1 L_FETCH_2ND_TRAP 242 243 // Check for maskable exceptions in trapsts.excp and trapsts.excp_hi. 244 // Maskable exceptions only cause the wave to enter the trap handler if 245 // their respective bit in mode.excp_en is set. 246 s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_EXCP_MASK|SQ_WAVE_TRAPSTS_EXCP_HI_MASK 247 s_cbranch_scc0 L_CHECK_TRAP_ID 248 249 s_and_b32 ttmp3, s_save_trapsts, SQ_WAVE_TRAPSTS_ADDR_WATCH_MASK|SQ_WAVE_TRAPSTS_EXCP_HI_MASK 250 s_cbranch_scc0 L_NOT_ADDR_WATCH 251 s_bitset1_b32 ttmp2, SQ_WAVE_TRAPSTS_ADDR_WATCH_SHIFT // Check all addr_watch[123] exceptions against excp_en.addr_watch 252 253L_NOT_ADDR_WATCH: 254 s_getreg_b32 ttmp3, hwreg(HW_REG_MODE) 255 s_lshl_b32 ttmp2, ttmp2, SQ_WAVE_MODE_EXCP_EN_SHIFT 256 s_and_b32 ttmp2, ttmp2, ttmp3 257 s_cbranch_scc1 L_FETCH_2ND_TRAP 258 259L_CHECK_TRAP_ID: 260 // Check trap_id != 0 261 s_and_b32 ttmp2, s_save_pc_hi, S_SAVE_PC_HI_TRAP_ID_MASK 262 s_cbranch_scc1 L_FETCH_2ND_TRAP 263 264if SINGLE_STEP_MISSED_WORKAROUND 265 // Prioritize single step exception over context save. 266 // Second-level trap will halt wave and RFE, re-entering for SAVECTX. 267 s_getreg_b32 ttmp2, hwreg(HW_REG_MODE) 268 s_and_b32 ttmp2, ttmp2, SQ_WAVE_MODE_DEBUG_EN_MASK 269 s_cbranch_scc1 L_FETCH_2ND_TRAP 270end 271 272 s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_SAVECTX_MASK 273 s_cbranch_scc1 L_SAVE 274 275L_FETCH_2ND_TRAP: 276 // Preserve and clear scalar XNACK state before issuing scalar reads. 277 save_and_clear_ib_sts(ttmp14) 278 279 // Read second-level TBA/TMA from first-level TMA and jump if available. 280 // ttmp[2:5] and ttmp12 can be used (others hold SPI-initialized debug data) 281 // ttmp12 holds SQ_WAVE_STATUS 282 s_getreg_b32 ttmp14, hwreg(HW_REG_SQ_SHADER_TMA_LO) 283 s_getreg_b32 ttmp15, hwreg(HW_REG_SQ_SHADER_TMA_HI) 284 s_lshl_b64 [ttmp14, ttmp15], [ttmp14, ttmp15], 0x8 285 286 s_load_dword ttmp2, [ttmp14, ttmp15], 0x10 glc:1 // debug trap enabled flag 287 s_waitcnt lgkmcnt(0) 288 s_lshl_b32 ttmp2, ttmp2, TTMP_DEBUG_TRAP_ENABLED_SHIFT 289 s_andn2_b32 s_save_ib_sts, s_save_ib_sts, TTMP_DEBUG_TRAP_ENABLED_MASK 290 s_or_b32 s_save_ib_sts, s_save_ib_sts, ttmp2 291 292 s_load_dwordx2 [ttmp2, ttmp3], [ttmp14, ttmp15], 0x0 glc:1 // second-level TBA 293 s_waitcnt lgkmcnt(0) 294 s_load_dwordx2 [ttmp14, ttmp15], [ttmp14, ttmp15], 0x8 glc:1 // second-level TMA 295 s_waitcnt lgkmcnt(0) 296 297 s_and_b64 [ttmp2, ttmp3], [ttmp2, ttmp3], [ttmp2, ttmp3] 298 s_cbranch_scc0 L_NO_NEXT_TRAP // second-level trap handler not been set 299 s_setpc_b64 [ttmp2, ttmp3] // jump to second-level trap handler 300 301L_NO_NEXT_TRAP: 302 // If not caused by trap then halt wave to prevent re-entry. 303 s_and_b32 ttmp2, s_save_pc_hi, (S_SAVE_PC_HI_TRAP_ID_MASK|S_SAVE_PC_HI_HT_MASK) 304 s_cbranch_scc1 L_TRAP_CASE 305 s_or_b32 s_save_status, s_save_status, SQ_WAVE_STATUS_HALT_MASK 306 307 // If the PC points to S_ENDPGM then context save will fail if STATUS.HALT is set. 308 // Rewind the PC to prevent this from occurring. 309 s_sub_u32 ttmp0, ttmp0, 0x8 310 s_subb_u32 ttmp1, ttmp1, 0x0 311 312 s_branch L_EXIT_TRAP 313 314L_TRAP_CASE: 315 // Host trap will not cause trap re-entry. 316 s_and_b32 ttmp2, s_save_pc_hi, S_SAVE_PC_HI_HT_MASK 317 s_cbranch_scc1 L_EXIT_TRAP 318 319 // Advance past trap instruction to prevent re-entry. 320 s_add_u32 ttmp0, ttmp0, 0x4 321 s_addc_u32 ttmp1, ttmp1, 0x0 322 323L_EXIT_TRAP: 324 s_and_b32 ttmp1, ttmp1, 0xFFFF 325 326 restore_ib_sts(ttmp14) 327 328 // Restore SQ_WAVE_STATUS. 329 s_and_b64 exec, exec, exec // Restore STATUS.EXECZ, not writable by s_setreg_b32 330 s_and_b64 vcc, vcc, vcc // Restore STATUS.VCCZ, not writable by s_setreg_b32 331 set_status_without_spi_prio(s_save_status, ttmp2) 332 333 s_rfe_b64 [ttmp0, ttmp1] 334 335 // ********* End handling of non-CWSR traps ******************* 336 337/**************************************************************************/ 338/* save routine */ 339/**************************************************************************/ 340 341L_SAVE: 342 s_and_b32 s_save_pc_hi, s_save_pc_hi, 0x0000ffff //pc[47:32] 343 344 s_mov_b32 s_save_tmp, 0 //clear saveCtx bit 345 s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_SAVECTX_SHIFT, 1), s_save_tmp //clear saveCtx bit 346 347 save_and_clear_ib_sts(s_save_tmp) 348 349 /* inform SPI the readiness and wait for SPI's go signal */ 350 s_mov_b32 s_save_exec_lo, exec_lo //save EXEC and use EXEC for the go signal from SPI 351 s_mov_b32 s_save_exec_hi, exec_hi 352 s_mov_b64 exec, 0x0 //clear EXEC to get ready to receive 353 354 s_sendmsg sendmsg(MSG_SAVEWAVE) //send SPI a message and wait for SPI's write to EXEC 355 356 // Set SPI_PRIO=2 to avoid starving instruction fetch in the waves we're waiting for. 357 s_or_b32 s_save_tmp, s_save_status, (2 << SQ_WAVE_STATUS_SPI_PRIO_SHIFT) 358 s_setreg_b32 hwreg(HW_REG_STATUS), s_save_tmp 359 360 L_SLEEP: 361 s_sleep 0x2 // sleep 1 (64clk) is not enough for 8 waves per SIMD, which will cause SQ hang, since the 7,8th wave could not get arbit to exec inst, while other waves are stuck into the sleep-loop and waiting for wrexec!=0 362 363 s_cbranch_execz L_SLEEP 364 365 // Save trap temporaries 4-11, 13 initialized by SPI debug dispatch logic 366 // ttmp SR memory offset : size(VGPR)+size(SGPR)+0x40 367 get_vgpr_size_bytes(s_save_ttmps_lo) 368 get_sgpr_size_bytes(s_save_ttmps_hi) 369 s_add_u32 s_save_ttmps_lo, s_save_ttmps_lo, s_save_ttmps_hi 370 s_add_u32 s_save_ttmps_lo, s_save_ttmps_lo, s_save_spi_init_lo 371 s_addc_u32 s_save_ttmps_hi, s_save_spi_init_hi, 0x0 372 s_and_b32 s_save_ttmps_hi, s_save_ttmps_hi, 0xFFFF 373 s_store_dwordx4 [ttmp4, ttmp5, ttmp6, ttmp7], [s_save_ttmps_lo, s_save_ttmps_hi], 0x50 glc:1 374 ack_sqc_store_workaround() 375 s_store_dwordx4 [ttmp8, ttmp9, ttmp10, ttmp11], [s_save_ttmps_lo, s_save_ttmps_hi], 0x60 glc:1 376 ack_sqc_store_workaround() 377 s_store_dword ttmp13, [s_save_ttmps_lo, s_save_ttmps_hi], 0x74 glc:1 378 ack_sqc_store_workaround() 379 380 /* setup Resource Contants */ 381 s_mov_b32 s_save_buf_rsrc0, s_save_spi_init_lo //base_addr_lo 382 s_and_b32 s_save_buf_rsrc1, s_save_spi_init_hi, 0x0000FFFF //base_addr_hi 383 s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, S_SAVE_BUF_RSRC_WORD1_STRIDE 384 s_mov_b32 s_save_buf_rsrc2, 0 //NUM_RECORDS initial value = 0 (in bytes) although not neccessarily inited 385 s_mov_b32 s_save_buf_rsrc3, S_SAVE_BUF_RSRC_WORD3_MISC 386 387 //FIXME right now s_save_m0/s_save_mem_offset use tma_lo/tma_hi (might need to save them before using them?) 388 s_mov_b32 s_save_m0, m0 //save M0 389 390 /* global mem offset */ 391 s_mov_b32 s_save_mem_offset, 0x0 //mem offset initial value = 0 392 393 394 395 396 /* save HW registers */ 397 ////////////////////////////// 398 399 L_SAVE_HWREG: 400 // HWREG SR memory offset : size(VGPR)+size(SGPR) 401 get_vgpr_size_bytes(s_save_mem_offset) 402 get_sgpr_size_bytes(s_save_tmp) 403 s_add_u32 s_save_mem_offset, s_save_mem_offset, s_save_tmp 404 405 406 s_mov_b32 s_save_buf_rsrc2, 0x4 //NUM_RECORDS in bytes 407 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 408 409 410 write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset) //M0 411 write_hwreg_to_mem(s_save_pc_lo, s_save_buf_rsrc0, s_save_mem_offset) //PC 412 write_hwreg_to_mem(s_save_pc_hi, s_save_buf_rsrc0, s_save_mem_offset) 413 write_hwreg_to_mem(s_save_exec_lo, s_save_buf_rsrc0, s_save_mem_offset) //EXEC 414 write_hwreg_to_mem(s_save_exec_hi, s_save_buf_rsrc0, s_save_mem_offset) 415 write_hwreg_to_mem(s_save_status, s_save_buf_rsrc0, s_save_mem_offset) //STATUS 416 417 //s_save_trapsts conflicts with s_save_alloc_size 418 s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) 419 write_hwreg_to_mem(s_save_trapsts, s_save_buf_rsrc0, s_save_mem_offset) //TRAPSTS 420 421 write_hwreg_to_mem(xnack_mask_lo, s_save_buf_rsrc0, s_save_mem_offset) //XNACK_MASK_LO 422 write_hwreg_to_mem(xnack_mask_hi, s_save_buf_rsrc0, s_save_mem_offset) //XNACK_MASK_HI 423 424 //use s_save_tmp would introduce conflict here between s_save_tmp and s_save_buf_rsrc2 425 s_getreg_b32 s_save_m0, hwreg(HW_REG_MODE) //MODE 426 write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset) 427 428 429 430 /* the first wave in the threadgroup */ 431 s_and_b32 s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK // extract fisrt wave bit 432 s_mov_b32 s_save_exec_hi, 0x0 433 s_or_b32 s_save_exec_hi, s_save_tmp, s_save_exec_hi // save first wave bit to s_save_exec_hi.bits[26] 434 435 436 /* save SGPRs */ 437 // Save SGPR before LDS save, then the s0 to s4 can be used during LDS save... 438 ////////////////////////////// 439 440 // SGPR SR memory offset : size(VGPR) 441 get_vgpr_size_bytes(s_save_mem_offset) 442 // TODO, change RSRC word to rearrange memory layout for SGPRS 443 444 s_getreg_b32 s_save_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE) //spgr_size 445 s_add_u32 s_save_alloc_size, s_save_alloc_size, 1 446 s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 4 //Number of SGPRs = (sgpr_size + 1) * 16 (non-zero value) 447 448 s_lshl_b32 s_save_buf_rsrc2, s_save_alloc_size, 2 //NUM_RECORDS in bytes 449 450 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 451 452 453 // backup s_save_buf_rsrc0,1 to s_save_pc_lo/hi, since write_16sgpr_to_mem function will change the rsrc0 454 //s_mov_b64 s_save_pc_lo, s_save_buf_rsrc0 455 s_mov_b64 s_save_xnack_mask_lo, s_save_buf_rsrc0 456 s_add_u32 s_save_buf_rsrc0, s_save_buf_rsrc0, s_save_mem_offset 457 s_addc_u32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0 458 459 s_mov_b32 m0, 0x0 //SGPR initial index value =0 460 s_nop 0x0 //Manually inserted wait states 461 L_SAVE_SGPR_LOOP: 462 // SGPR is allocated in 16 SGPR granularity 463 s_movrels_b64 s0, s0 //s0 = s[0+m0], s1 = s[1+m0] 464 s_movrels_b64 s2, s2 //s2 = s[2+m0], s3 = s[3+m0] 465 s_movrels_b64 s4, s4 //s4 = s[4+m0], s5 = s[5+m0] 466 s_movrels_b64 s6, s6 //s6 = s[6+m0], s7 = s[7+m0] 467 s_movrels_b64 s8, s8 //s8 = s[8+m0], s9 = s[9+m0] 468 s_movrels_b64 s10, s10 //s10 = s[10+m0], s11 = s[11+m0] 469 s_movrels_b64 s12, s12 //s12 = s[12+m0], s13 = s[13+m0] 470 s_movrels_b64 s14, s14 //s14 = s[14+m0], s15 = s[15+m0] 471 472 write_16sgpr_to_mem(s0, s_save_buf_rsrc0, s_save_mem_offset) //PV: the best performance should be using s_buffer_store_dwordx4 473 s_add_u32 m0, m0, 16 //next sgpr index 474 s_cmp_lt_u32 m0, s_save_alloc_size //scc = (m0 < s_save_alloc_size) ? 1 : 0 475 s_cbranch_scc1 L_SAVE_SGPR_LOOP //SGPR save is complete? 476 // restore s_save_buf_rsrc0,1 477 //s_mov_b64 s_save_buf_rsrc0, s_save_pc_lo 478 s_mov_b64 s_save_buf_rsrc0, s_save_xnack_mask_lo 479 480 481 482 483 /* save first 4 VGPR, then LDS save could use */ 484 // each wave will alloc 4 vgprs at least... 485 ///////////////////////////////////////////////////////////////////////////////////// 486 487 s_mov_b32 s_save_mem_offset, 0 488 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on 489 s_mov_b32 exec_hi, 0xFFFFFFFF 490 s_mov_b32 xnack_mask_lo, 0x0 491 s_mov_b32 xnack_mask_hi, 0x0 492 493 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 494 495 496 // VGPR Allocated in 4-GPR granularity 497 498if SAVE_AFTER_XNACK_ERROR 499 check_if_tcp_store_ok() 500 s_cbranch_scc1 L_SAVE_FIRST_VGPRS_WITH_TCP 501 502 write_vgprs_to_mem_with_sqc(v0, 4, s_save_buf_rsrc0, s_save_mem_offset) 503 s_branch L_SAVE_LDS 504 505L_SAVE_FIRST_VGPRS_WITH_TCP: 506end 507 508 write_4vgprs_to_mem(s_save_buf_rsrc0, s_save_mem_offset) 509 510 /* save LDS */ 511 ////////////////////////////// 512 513 L_SAVE_LDS: 514 515 // Change EXEC to all threads... 516 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on 517 s_mov_b32 exec_hi, 0xFFFFFFFF 518 519 s_getreg_b32 s_save_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) //lds_size 520 s_and_b32 s_save_alloc_size, s_save_alloc_size, 0xFFFFFFFF //lds_size is zero? 521 s_cbranch_scc0 L_SAVE_LDS_DONE //no lds used? jump to L_SAVE_DONE 522 523 s_barrier //LDS is used? wait for other waves in the same TG 524 s_and_b32 s_save_tmp, s_save_exec_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK //exec is still used here 525 s_cbranch_scc0 L_SAVE_LDS_DONE 526 527 // first wave do LDS save; 528 529 s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 6 //LDS size in dwords = lds_size * 64dw 530 s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 2 //LDS size in bytes 531 s_mov_b32 s_save_buf_rsrc2, s_save_alloc_size //NUM_RECORDS in bytes 532 533 // LDS at offset: size(VGPR)+SIZE(SGPR)+SIZE(HWREG) 534 // 535 get_vgpr_size_bytes(s_save_mem_offset) 536 get_sgpr_size_bytes(s_save_tmp) 537 s_add_u32 s_save_mem_offset, s_save_mem_offset, s_save_tmp 538 s_add_u32 s_save_mem_offset, s_save_mem_offset, get_hwreg_size_bytes() 539 540 541 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 542 543 s_mov_b32 m0, 0x0 //lds_offset initial value = 0 544 545 546 v_mbcnt_lo_u32_b32 v2, 0xffffffff, 0x0 547 v_mbcnt_hi_u32_b32 v3, 0xffffffff, v2 // tid 548 549if SAVE_AFTER_XNACK_ERROR 550 check_if_tcp_store_ok() 551 s_cbranch_scc1 L_SAVE_LDS_WITH_TCP 552 553 v_lshlrev_b32 v2, 2, v3 554L_SAVE_LDS_LOOP_SQC: 555 ds_read2_b32 v[0:1], v2 offset0:0 offset1:0x40 556 s_waitcnt lgkmcnt(0) 557 558 write_vgprs_to_mem_with_sqc(v0, 2, s_save_buf_rsrc0, s_save_mem_offset) 559 560 v_add_u32 v2, 0x200, v2 561 v_cmp_lt_u32 vcc[0:1], v2, s_save_alloc_size 562 s_cbranch_vccnz L_SAVE_LDS_LOOP_SQC 563 564 s_branch L_SAVE_LDS_DONE 565 566L_SAVE_LDS_WITH_TCP: 567end 568 569 v_mul_i32_i24 v2, v3, 8 // tid*8 570 v_mov_b32 v3, 256*2 571 s_mov_b32 m0, 0x10000 572 s_mov_b32 s0, s_save_buf_rsrc3 573 s_and_b32 s_save_buf_rsrc3, s_save_buf_rsrc3, 0xFF7FFFFF // disable add_tid 574 s_or_b32 s_save_buf_rsrc3, s_save_buf_rsrc3, 0x58000 //DFMT 575 576L_SAVE_LDS_LOOP_VECTOR: 577 ds_read_b64 v[0:1], v2 //x =LDS[a], byte address 578 s_waitcnt lgkmcnt(0) 579 buffer_store_dwordx2 v[0:1], v2, s_save_buf_rsrc0, s_save_mem_offset offen:1 glc:1 slc:1 580// s_waitcnt vmcnt(0) 581// v_add_u32 v2, vcc[0:1], v2, v3 582 v_add_u32 v2, v2, v3 583 v_cmp_lt_u32 vcc[0:1], v2, s_save_alloc_size 584 s_cbranch_vccnz L_SAVE_LDS_LOOP_VECTOR 585 586 // restore rsrc3 587 s_mov_b32 s_save_buf_rsrc3, s0 588 589L_SAVE_LDS_DONE: 590 591 592 /* save VGPRs - set the Rest VGPRs */ 593 ////////////////////////////////////////////////////////////////////////////////////// 594 L_SAVE_VGPR: 595 // VGPR SR memory offset: 0 596 // TODO rearrange the RSRC words to use swizzle for VGPR save... 597 598 s_mov_b32 s_save_mem_offset, (0+256*4) // for the rest VGPRs 599 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on 600 s_mov_b32 exec_hi, 0xFFFFFFFF 601 602 get_num_arch_vgprs(s_save_alloc_size) 603 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 604 605 606 // VGPR store using dw burst 607 s_mov_b32 m0, 0x4 //VGPR initial index value =0 608 s_cmp_lt_u32 m0, s_save_alloc_size 609 s_cbranch_scc0 L_SAVE_VGPR_END 610 611 612 s_set_gpr_idx_on m0, 0x1 //M0[7:0] = M0[7:0] and M0[15:12] = 0x1 613 s_add_u32 s_save_alloc_size, s_save_alloc_size, 0x1000 //add 0x1000 since we compare m0 against it later 614 615if SAVE_AFTER_XNACK_ERROR 616 check_if_tcp_store_ok() 617 s_cbranch_scc1 L_SAVE_VGPR_LOOP 618 619L_SAVE_VGPR_LOOP_SQC: 620 write_vgprs_to_mem_with_sqc(v0, 4, s_save_buf_rsrc0, s_save_mem_offset) 621 622 s_add_u32 m0, m0, 4 623 s_cmp_lt_u32 m0, s_save_alloc_size 624 s_cbranch_scc1 L_SAVE_VGPR_LOOP_SQC 625 626 s_set_gpr_idx_off 627 s_branch L_SAVE_VGPR_END 628end 629 630 L_SAVE_VGPR_LOOP: 631 v_mov_b32 v0, v0 //v0 = v[0+m0] 632 v_mov_b32 v1, v1 //v0 = v[0+m0] 633 v_mov_b32 v2, v2 //v0 = v[0+m0] 634 v_mov_b32 v3, v3 //v0 = v[0+m0] 635 636 write_4vgprs_to_mem(s_save_buf_rsrc0, s_save_mem_offset) 637 638 s_add_u32 m0, m0, 4 //next vgpr index 639 s_add_u32 s_save_mem_offset, s_save_mem_offset, 256*4 //every buffer_store_dword does 256 bytes 640 s_cmp_lt_u32 m0, s_save_alloc_size //scc = (m0 < s_save_alloc_size) ? 1 : 0 641 s_cbranch_scc1 L_SAVE_VGPR_LOOP //VGPR save is complete? 642 s_set_gpr_idx_off 643 644L_SAVE_VGPR_END: 645 646#if ASIC_FAMILY >= CHIP_ARCTURUS 647 // Save ACC VGPRs 648 649#if ASIC_FAMILY >= CHIP_ALDEBARAN 650 // ACC VGPR count may differ from ARCH VGPR count. 651 get_num_acc_vgprs(s_save_alloc_size, s_save_tmp) 652 s_and_b32 s_save_alloc_size, s_save_alloc_size, s_save_alloc_size 653 s_cbranch_scc0 L_SAVE_ACCVGPR_END 654 s_add_u32 s_save_alloc_size, s_save_alloc_size, 0x1000 //add 0x1000 since we compare m0 against it later 655#endif 656 657 s_mov_b32 m0, 0x0 //VGPR initial index value =0 658 s_set_gpr_idx_on m0, 0x1 //M0[7:0] = M0[7:0] and M0[15:12] = 0x1 659 660if SAVE_AFTER_XNACK_ERROR 661 check_if_tcp_store_ok() 662 s_cbranch_scc1 L_SAVE_ACCVGPR_LOOP 663 664L_SAVE_ACCVGPR_LOOP_SQC: 665 for var vgpr = 0; vgpr < 4; ++ vgpr 666 v_accvgpr_read v[vgpr], acc[vgpr] // v[N] = acc[N+m0] 667 end 668 669 write_vgprs_to_mem_with_sqc(v0, 4, s_save_buf_rsrc0, s_save_mem_offset) 670 671 s_add_u32 m0, m0, 4 672 s_cmp_lt_u32 m0, s_save_alloc_size 673 s_cbranch_scc1 L_SAVE_ACCVGPR_LOOP_SQC 674 675 s_set_gpr_idx_off 676 s_branch L_SAVE_ACCVGPR_END 677end 678 679L_SAVE_ACCVGPR_LOOP: 680 for var vgpr = 0; vgpr < 4; ++ vgpr 681 v_accvgpr_read v[vgpr], acc[vgpr] // v[N] = acc[N+m0] 682 end 683 684 write_4vgprs_to_mem(s_save_buf_rsrc0, s_save_mem_offset) 685 686 s_add_u32 m0, m0, 4 687 s_add_u32 s_save_mem_offset, s_save_mem_offset, 256*4 688 s_cmp_lt_u32 m0, s_save_alloc_size 689 s_cbranch_scc1 L_SAVE_ACCVGPR_LOOP 690 s_set_gpr_idx_off 691 692L_SAVE_ACCVGPR_END: 693#endif 694 695 s_branch L_END_PGM 696 697 698 699/**************************************************************************/ 700/* restore routine */ 701/**************************************************************************/ 702 703L_RESTORE: 704 /* Setup Resource Contants */ 705 s_mov_b32 s_restore_buf_rsrc0, s_restore_spi_init_lo //base_addr_lo 706 s_and_b32 s_restore_buf_rsrc1, s_restore_spi_init_hi, 0x0000FFFF //base_addr_hi 707 s_or_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, S_RESTORE_BUF_RSRC_WORD1_STRIDE 708 s_mov_b32 s_restore_buf_rsrc2, 0 //NUM_RECORDS initial value = 0 (in bytes) 709 s_mov_b32 s_restore_buf_rsrc3, S_RESTORE_BUF_RSRC_WORD3_MISC 710 711 /* global mem offset */ 712// s_mov_b32 s_restore_mem_offset, 0x0 //mem offset initial value = 0 713 714 /* the first wave in the threadgroup */ 715 s_and_b32 s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_FIRST_WAVE_MASK 716 s_cbranch_scc0 L_RESTORE_VGPR 717 718 /* restore LDS */ 719 ////////////////////////////// 720 L_RESTORE_LDS: 721 722 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on //be consistent with SAVE although can be moved ahead 723 s_mov_b32 exec_hi, 0xFFFFFFFF 724 725 s_getreg_b32 s_restore_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) //lds_size 726 s_and_b32 s_restore_alloc_size, s_restore_alloc_size, 0xFFFFFFFF //lds_size is zero? 727 s_cbranch_scc0 L_RESTORE_VGPR //no lds used? jump to L_RESTORE_VGPR 728 s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 6 //LDS size in dwords = lds_size * 64dw 729 s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 2 //LDS size in bytes 730 s_mov_b32 s_restore_buf_rsrc2, s_restore_alloc_size //NUM_RECORDS in bytes 731 732 // LDS at offset: size(VGPR)+SIZE(SGPR)+SIZE(HWREG) 733 // 734 get_vgpr_size_bytes(s_restore_mem_offset) 735 get_sgpr_size_bytes(s_restore_tmp) 736 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp 737 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, get_hwreg_size_bytes() //FIXME, Check if offset overflow??? 738 739 740 s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 741 s_mov_b32 m0, 0x0 //lds_offset initial value = 0 742 743 L_RESTORE_LDS_LOOP: 744 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1 // first 64DW 745 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1 offset:256 // second 64DW 746 s_add_u32 m0, m0, 256*2 // 128 DW 747 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*2 //mem offset increased by 128DW 748 s_cmp_lt_u32 m0, s_restore_alloc_size //scc=(m0 < s_restore_alloc_size) ? 1 : 0 749 s_cbranch_scc1 L_RESTORE_LDS_LOOP //LDS restore is complete? 750 751 752 /* restore VGPRs */ 753 ////////////////////////////// 754 L_RESTORE_VGPR: 755 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on //be consistent with SAVE although can be moved ahead 756 s_mov_b32 exec_hi, 0xFFFFFFFF 757 s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 758 759 // Save ARCH VGPRs 4-N, then all ACC VGPRs, then ARCH VGPRs 0-3. 760 get_num_arch_vgprs(s_restore_alloc_size) 761 s_add_u32 s_restore_alloc_size, s_restore_alloc_size, 0x8000 //add 0x8000 since we compare m0 against it later 762 763 // ARCH VGPRs at offset: 0 764 s_mov_b32 s_restore_mem_offset, 0x0 765 s_mov_b32 s_restore_mem_offset_save, s_restore_mem_offset // restore start with v1, v0 will be the last 766 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 767 s_mov_b32 m0, 4 //VGPR initial index value = 1 768 s_set_gpr_idx_on m0, 0x8 //M0[7:0] = M0[7:0] and M0[15:12] = 0x8 769 770 L_RESTORE_VGPR_LOOP: 771 read_4vgprs_from_mem(s_restore_buf_rsrc0, s_restore_mem_offset) 772 v_mov_b32 v0, v0 //v[0+m0] = v0 773 v_mov_b32 v1, v1 774 v_mov_b32 v2, v2 775 v_mov_b32 v3, v3 776 s_add_u32 m0, m0, 4 //next vgpr index 777 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 //every buffer_load_dword does 256 bytes 778 s_cmp_lt_u32 m0, s_restore_alloc_size //scc = (m0 < s_restore_alloc_size) ? 1 : 0 779 s_cbranch_scc1 L_RESTORE_VGPR_LOOP //VGPR restore (except v0) is complete? 780 781#if ASIC_FAMILY >= CHIP_ALDEBARAN 782 // ACC VGPR count may differ from ARCH VGPR count. 783 get_num_acc_vgprs(s_restore_alloc_size, s_restore_tmp2) 784 s_and_b32 s_restore_alloc_size, s_restore_alloc_size, s_restore_alloc_size 785 s_cbranch_scc0 L_RESTORE_ACCVGPR_END 786 s_add_u32 s_restore_alloc_size, s_restore_alloc_size, 0x8000 //add 0x8000 since we compare m0 against it later 787#endif 788 789#if ASIC_FAMILY >= CHIP_ARCTURUS 790 // ACC VGPRs at offset: size(ARCH VGPRs) 791 s_mov_b32 m0, 0 792 s_set_gpr_idx_on m0, 0x8 //M0[7:0] = M0[7:0] and M0[15:12] = 0x8 793 794 L_RESTORE_ACCVGPR_LOOP: 795 read_4vgprs_from_mem(s_restore_buf_rsrc0, s_restore_mem_offset) 796 797 for var vgpr = 0; vgpr < 4; ++ vgpr 798 v_accvgpr_write acc[vgpr], v[vgpr] 799 end 800 801 s_add_u32 m0, m0, 4 //next vgpr index 802 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 //every buffer_load_dword does 256 bytes 803 s_cmp_lt_u32 m0, s_restore_alloc_size //scc = (m0 < s_restore_alloc_size) ? 1 : 0 804 s_cbranch_scc1 L_RESTORE_ACCVGPR_LOOP //VGPR restore (except v0) is complete? 805 L_RESTORE_ACCVGPR_END: 806#endif 807 808 s_set_gpr_idx_off 809 810 // Restore VGPRs 0-3 last, no longer needed. 811 read_4vgprs_from_mem(s_restore_buf_rsrc0, s_restore_mem_offset_save) 812 813 /* restore SGPRs */ 814 ////////////////////////////// 815 816 // SGPR SR memory offset : size(VGPR) 817 get_vgpr_size_bytes(s_restore_mem_offset) 818 get_sgpr_size_bytes(s_restore_tmp) 819 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp 820 s_sub_u32 s_restore_mem_offset, s_restore_mem_offset, 16*4 // restore SGPR from S[n] to S[0], by 16 sgprs group 821 // TODO, change RSRC word to rearrange memory layout for SGPRS 822 823 s_getreg_b32 s_restore_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE) //spgr_size 824 s_add_u32 s_restore_alloc_size, s_restore_alloc_size, 1 825 s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 4 //Number of SGPRs = (sgpr_size + 1) * 16 (non-zero value) 826 827 s_lshl_b32 s_restore_buf_rsrc2, s_restore_alloc_size, 2 //NUM_RECORDS in bytes 828 s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 829 830 s_mov_b32 m0, s_restore_alloc_size 831 832 L_RESTORE_SGPR_LOOP: 833 read_16sgpr_from_mem(s0, s_restore_buf_rsrc0, s_restore_mem_offset) //PV: further performance improvement can be made 834 s_waitcnt lgkmcnt(0) //ensure data ready 835 836 s_sub_u32 m0, m0, 16 // Restore from S[n] to S[0] 837 s_nop 0 // hazard SALU M0=> S_MOVREL 838 839 s_movreld_b64 s0, s0 //s[0+m0] = s0 840 s_movreld_b64 s2, s2 841 s_movreld_b64 s4, s4 842 s_movreld_b64 s6, s6 843 s_movreld_b64 s8, s8 844 s_movreld_b64 s10, s10 845 s_movreld_b64 s12, s12 846 s_movreld_b64 s14, s14 847 848 s_cmp_eq_u32 m0, 0 //scc = (m0 < s_restore_alloc_size) ? 1 : 0 849 s_cbranch_scc0 L_RESTORE_SGPR_LOOP //SGPR restore (except s0) is complete? 850 851 /* restore HW registers */ 852 ////////////////////////////// 853 L_RESTORE_HWREG: 854 855 856 // HWREG SR memory offset : size(VGPR)+size(SGPR) 857 get_vgpr_size_bytes(s_restore_mem_offset) 858 get_sgpr_size_bytes(s_restore_tmp) 859 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp 860 861 862 s_mov_b32 s_restore_buf_rsrc2, 0x4 //NUM_RECORDS in bytes 863 s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 864 865 read_hwreg_from_mem(s_restore_m0, s_restore_buf_rsrc0, s_restore_mem_offset) //M0 866 read_hwreg_from_mem(s_restore_pc_lo, s_restore_buf_rsrc0, s_restore_mem_offset) //PC 867 read_hwreg_from_mem(s_restore_pc_hi, s_restore_buf_rsrc0, s_restore_mem_offset) 868 read_hwreg_from_mem(s_restore_exec_lo, s_restore_buf_rsrc0, s_restore_mem_offset) //EXEC 869 read_hwreg_from_mem(s_restore_exec_hi, s_restore_buf_rsrc0, s_restore_mem_offset) 870 read_hwreg_from_mem(s_restore_status, s_restore_buf_rsrc0, s_restore_mem_offset) //STATUS 871 read_hwreg_from_mem(s_restore_trapsts, s_restore_buf_rsrc0, s_restore_mem_offset) //TRAPSTS 872 read_hwreg_from_mem(xnack_mask_lo, s_restore_buf_rsrc0, s_restore_mem_offset) //XNACK_MASK_LO 873 read_hwreg_from_mem(xnack_mask_hi, s_restore_buf_rsrc0, s_restore_mem_offset) //XNACK_MASK_HI 874 read_hwreg_from_mem(s_restore_mode, s_restore_buf_rsrc0, s_restore_mem_offset) //MODE 875 876 s_waitcnt lgkmcnt(0) //from now on, it is safe to restore STATUS and IB_STS 877 878 s_mov_b32 m0, s_restore_m0 879 s_mov_b32 exec_lo, s_restore_exec_lo 880 s_mov_b32 exec_hi, s_restore_exec_hi 881 882 s_and_b32 s_restore_m0, SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK, s_restore_trapsts 883 s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_PRE_SAVECTX_SHIFT, SQ_WAVE_TRAPSTS_PRE_SAVECTX_SIZE), s_restore_m0 884 s_and_b32 s_restore_m0, SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK, s_restore_trapsts 885 s_lshr_b32 s_restore_m0, s_restore_m0, SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT 886 s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT, SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE), s_restore_m0 887 //s_setreg_b32 hwreg(HW_REG_TRAPSTS), s_restore_trapsts //don't overwrite SAVECTX bit as it may be set through external SAVECTX during restore 888 s_setreg_b32 hwreg(HW_REG_MODE), s_restore_mode 889 890 // Restore trap temporaries 4-11, 13 initialized by SPI debug dispatch logic 891 // ttmp SR memory offset : size(VGPR)+size(SGPR)+0x40 892 get_vgpr_size_bytes(s_restore_ttmps_lo) 893 get_sgpr_size_bytes(s_restore_ttmps_hi) 894 s_add_u32 s_restore_ttmps_lo, s_restore_ttmps_lo, s_restore_ttmps_hi 895 s_add_u32 s_restore_ttmps_lo, s_restore_ttmps_lo, s_restore_buf_rsrc0 896 s_addc_u32 s_restore_ttmps_hi, s_restore_buf_rsrc1, 0x0 897 s_and_b32 s_restore_ttmps_hi, s_restore_ttmps_hi, 0xFFFF 898 s_load_dwordx4 [ttmp4, ttmp5, ttmp6, ttmp7], [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x50 glc:1 899 s_load_dwordx4 [ttmp8, ttmp9, ttmp10, ttmp11], [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x60 glc:1 900 s_load_dword ttmp13, [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x74 glc:1 901 s_waitcnt lgkmcnt(0) 902 903 restore_ib_sts(s_restore_tmp) 904 905 s_and_b32 s_restore_pc_hi, s_restore_pc_hi, 0x0000ffff //pc[47:32] //Do it here in order not to affect STATUS 906 s_and_b64 exec, exec, exec // Restore STATUS.EXECZ, not writable by s_setreg_b32 907 s_and_b64 vcc, vcc, vcc // Restore STATUS.VCCZ, not writable by s_setreg_b32 908 set_status_without_spi_prio(s_restore_status, s_restore_tmp) // SCC is included, which is changed by previous salu 909 910 s_barrier //barrier to ensure the readiness of LDS before access attempts from any other wave in the same TG //FIXME not performance-optimal at this time 911 912 s_rfe_b64 s_restore_pc_lo //Return to the main shader program and resume execution 913 914 915/**************************************************************************/ 916/* the END */ 917/**************************************************************************/ 918L_END_PGM: 919 s_endpgm 920 921end 922 923 924/**************************************************************************/ 925/* the helper functions */ 926/**************************************************************************/ 927 928//Only for save hwreg to mem 929function write_hwreg_to_mem(s, s_rsrc, s_mem_offset) 930 s_mov_b32 exec_lo, m0 //assuming exec_lo is not needed anymore from this point on 931 s_mov_b32 m0, s_mem_offset 932 s_buffer_store_dword s, s_rsrc, m0 glc:1 933 ack_sqc_store_workaround() 934 s_add_u32 s_mem_offset, s_mem_offset, 4 935 s_mov_b32 m0, exec_lo 936end 937 938 939// HWREG are saved before SGPRs, so all HWREG could be use. 940function write_16sgpr_to_mem(s, s_rsrc, s_mem_offset) 941 942 s_buffer_store_dwordx4 s[0], s_rsrc, 0 glc:1 943 ack_sqc_store_workaround() 944 s_buffer_store_dwordx4 s[4], s_rsrc, 16 glc:1 945 ack_sqc_store_workaround() 946 s_buffer_store_dwordx4 s[8], s_rsrc, 32 glc:1 947 ack_sqc_store_workaround() 948 s_buffer_store_dwordx4 s[12], s_rsrc, 48 glc:1 949 ack_sqc_store_workaround() 950 s_add_u32 s_rsrc[0], s_rsrc[0], 4*16 951 s_addc_u32 s_rsrc[1], s_rsrc[1], 0x0 // +scc 952end 953 954 955function read_hwreg_from_mem(s, s_rsrc, s_mem_offset) 956 s_buffer_load_dword s, s_rsrc, s_mem_offset glc:1 957 s_add_u32 s_mem_offset, s_mem_offset, 4 958end 959 960function read_16sgpr_from_mem(s, s_rsrc, s_mem_offset) 961 s_buffer_load_dwordx16 s, s_rsrc, s_mem_offset glc:1 962 s_sub_u32 s_mem_offset, s_mem_offset, 4*16 963end 964 965function check_if_tcp_store_ok 966 // If STATUS.ALLOW_REPLAY=0 and TRAPSTS.XNACK_ERROR=1 then TCP stores will fail. 967 s_and_b32 s_save_tmp, s_save_status, SQ_WAVE_STATUS_ALLOW_REPLAY_MASK 968 s_cbranch_scc1 L_TCP_STORE_CHECK_DONE 969 970 s_getreg_b32 s_save_tmp, hwreg(HW_REG_TRAPSTS) 971 s_andn2_b32 s_save_tmp, SQ_WAVE_TRAPSTS_XNACK_ERROR_MASK, s_save_tmp 972 973L_TCP_STORE_CHECK_DONE: 974end 975 976function write_4vgprs_to_mem(s_rsrc, s_mem_offset) 977 buffer_store_dword v0, v0, s_rsrc, s_mem_offset slc:1 glc:1 978 buffer_store_dword v1, v0, s_rsrc, s_mem_offset slc:1 glc:1 offset:256 979 buffer_store_dword v2, v0, s_rsrc, s_mem_offset slc:1 glc:1 offset:256*2 980 buffer_store_dword v3, v0, s_rsrc, s_mem_offset slc:1 glc:1 offset:256*3 981end 982 983function read_4vgprs_from_mem(s_rsrc, s_mem_offset) 984 buffer_load_dword v0, v0, s_rsrc, s_mem_offset slc:1 glc:1 985 buffer_load_dword v1, v0, s_rsrc, s_mem_offset slc:1 glc:1 offset:256 986 buffer_load_dword v2, v0, s_rsrc, s_mem_offset slc:1 glc:1 offset:256*2 987 buffer_load_dword v3, v0, s_rsrc, s_mem_offset slc:1 glc:1 offset:256*3 988 s_waitcnt vmcnt(0) 989end 990 991function write_vgpr_to_mem_with_sqc(v, s_rsrc, s_mem_offset) 992 s_mov_b32 s4, 0 993 994L_WRITE_VGPR_LANE_LOOP: 995 for var lane = 0; lane < 4; ++ lane 996 v_readlane_b32 s[lane], v, s4 997 s_add_u32 s4, s4, 1 998 end 999 1000 s_buffer_store_dwordx4 s[0:3], s_rsrc, s_mem_offset glc:1 1001 ack_sqc_store_workaround() 1002 1003 s_add_u32 s_mem_offset, s_mem_offset, 0x10 1004 s_cmp_eq_u32 s4, 0x40 1005 s_cbranch_scc0 L_WRITE_VGPR_LANE_LOOP 1006end 1007 1008function write_vgprs_to_mem_with_sqc(v, n_vgprs, s_rsrc, s_mem_offset) 1009 for var vgpr = 0; vgpr < n_vgprs; ++ vgpr 1010 write_vgpr_to_mem_with_sqc(v[vgpr], s_rsrc, s_mem_offset) 1011 end 1012end 1013 1014function get_lds_size_bytes(s_lds_size_byte) 1015 // SQ LDS granularity is 64DW, while PGM_RSRC2.lds_size is in granularity 128DW 1016 s_getreg_b32 s_lds_size_byte, hwreg(HW_REG_LDS_ALLOC, SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT, SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) // lds_size 1017 s_lshl_b32 s_lds_size_byte, s_lds_size_byte, 8 //LDS size in dwords = lds_size * 64 *4Bytes // granularity 64DW 1018end 1019 1020function get_vgpr_size_bytes(s_vgpr_size_byte) 1021 s_getreg_b32 s_vgpr_size_byte, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) //vpgr_size 1022 s_add_u32 s_vgpr_size_byte, s_vgpr_size_byte, 1 1023 s_lshl_b32 s_vgpr_size_byte, s_vgpr_size_byte, (2+8) //Number of VGPRs = (vgpr_size + 1) * 4 * 64 * 4 (non-zero value) //FIXME for GFX, zero is possible 1024 1025#if ASIC_FAMILY >= CHIP_ARCTURUS 1026 s_lshl_b32 s_vgpr_size_byte, s_vgpr_size_byte, 1 // Double size for ACC VGPRs 1027#endif 1028end 1029 1030function get_sgpr_size_bytes(s_sgpr_size_byte) 1031 s_getreg_b32 s_sgpr_size_byte, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE) //spgr_size 1032 s_add_u32 s_sgpr_size_byte, s_sgpr_size_byte, 1 1033 s_lshl_b32 s_sgpr_size_byte, s_sgpr_size_byte, 6 //Number of SGPRs = (sgpr_size + 1) * 16 *4 (non-zero value) 1034end 1035 1036function get_hwreg_size_bytes 1037 return 128 //HWREG size 128 bytes 1038end 1039 1040function get_num_arch_vgprs(s_num_arch_vgprs) 1041#if ASIC_FAMILY >= CHIP_ALDEBARAN 1042 // VGPR count includes ACC VGPRs, use ACC VGPR offset for ARCH VGPR count. 1043 s_getreg_b32 s_num_arch_vgprs, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_ACCV_OFFSET_SHIFT,SQ_WAVE_GPR_ALLOC_ACCV_OFFSET_SIZE) 1044#else 1045 s_getreg_b32 s_num_arch_vgprs, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) 1046#endif 1047 1048 // Number of VGPRs = (vgpr_size + 1) * 4 1049 s_add_u32 s_num_arch_vgprs, s_num_arch_vgprs, 1 1050 s_lshl_b32 s_num_arch_vgprs, s_num_arch_vgprs, 2 1051end 1052 1053#if ASIC_FAMILY >= CHIP_ALDEBARAN 1054function get_num_acc_vgprs(s_num_acc_vgprs, s_tmp) 1055 // VGPR count = (GPR_ALLOC.VGPR_SIZE + 1) * 8 1056 s_getreg_b32 s_num_acc_vgprs, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) 1057 s_add_u32 s_num_acc_vgprs, s_num_acc_vgprs, 1 1058 s_lshl_b32 s_num_acc_vgprs, s_num_acc_vgprs, 3 1059 1060 // ACC VGPR count = VGPR count - ARCH VGPR count. 1061 get_num_arch_vgprs(s_tmp) 1062 s_sub_u32 s_num_acc_vgprs, s_num_acc_vgprs, s_tmp 1063end 1064#endif 1065 1066function ack_sqc_store_workaround 1067 if ACK_SQC_STORE 1068 s_waitcnt lgkmcnt(0) 1069 end 1070end 1071 1072function set_status_without_spi_prio(status, tmp) 1073 // Do not restore STATUS.SPI_PRIO since scheduler may have raised it. 1074 s_lshr_b32 tmp, status, SQ_WAVE_STATUS_POST_SPI_PRIO_SHIFT 1075 s_setreg_b32 hwreg(HW_REG_STATUS, SQ_WAVE_STATUS_POST_SPI_PRIO_SHIFT, SQ_WAVE_STATUS_POST_SPI_PRIO_SIZE), tmp 1076 s_nop 0x2 // avoid S_SETREG => S_SETREG hazard 1077 s_setreg_b32 hwreg(HW_REG_STATUS, SQ_WAVE_STATUS_PRE_SPI_PRIO_SHIFT, SQ_WAVE_STATUS_PRE_SPI_PRIO_SIZE), status 1078end 1079 1080function save_and_clear_ib_sts(tmp) 1081 // Save IB_STS.FIRST_REPLAY[15] and IB_STS.RCNT[20:16] into unused space s_save_ib_sts[31:26]. 1082 s_getreg_b32 tmp, hwreg(HW_REG_IB_STS) 1083 s_and_b32 tmp, tmp, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK 1084 s_lshl_b32 tmp, tmp, (TTMP_SAVE_RCNT_FIRST_REPLAY_SHIFT - SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT) 1085 s_andn2_b32 s_save_ib_sts, s_save_ib_sts, TTMP_SAVE_RCNT_FIRST_REPLAY_MASK 1086 s_or_b32 s_save_ib_sts, s_save_ib_sts, tmp 1087 s_setreg_imm32_b32 hwreg(HW_REG_IB_STS), 0x0 1088end 1089 1090function restore_ib_sts(tmp) 1091 s_lshr_b32 tmp, s_save_ib_sts, (TTMP_SAVE_RCNT_FIRST_REPLAY_SHIFT - SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT) 1092 s_and_b32 tmp, tmp, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK 1093 s_setreg_b32 hwreg(HW_REG_IB_STS), tmp 1094end 1095