1 /*
2  * Copyright 2014 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #include "kfd_mqd_manager.h"
25 #include "amdgpu_amdkfd.h"
26 
27 struct mqd_manager *mqd_manager_init(enum KFD_MQD_TYPE type,
28 					struct kfd_dev *dev)
29 {
30 	switch (dev->device_info->asic_family) {
31 	case CHIP_KAVERI:
32 		return mqd_manager_init_cik(type, dev);
33 	case CHIP_HAWAII:
34 		return mqd_manager_init_cik_hawaii(type, dev);
35 	case CHIP_CARRIZO:
36 		return mqd_manager_init_vi(type, dev);
37 	case CHIP_TONGA:
38 	case CHIP_FIJI:
39 	case CHIP_POLARIS10:
40 	case CHIP_POLARIS11:
41 	case CHIP_POLARIS12:
42 		return mqd_manager_init_vi_tonga(type, dev);
43 	case CHIP_VEGA10:
44 	case CHIP_VEGA12:
45 	case CHIP_VEGA20:
46 	case CHIP_RAVEN:
47 		return mqd_manager_init_v9(type, dev);
48 	default:
49 		WARN(1, "Unexpected ASIC family %u",
50 		     dev->device_info->asic_family);
51 	}
52 
53 	return NULL;
54 }
55 
56 void mqd_symmetrically_map_cu_mask(struct mqd_manager *mm,
57 		const uint32_t *cu_mask, uint32_t cu_mask_count,
58 		uint32_t *se_mask)
59 {
60 	struct kfd_cu_info cu_info;
61 	uint32_t cu_per_sh[4] = {0};
62 	int i, se, cu = 0;
63 
64 	amdgpu_amdkfd_get_cu_info(mm->dev->kgd, &cu_info);
65 
66 	if (cu_mask_count > cu_info.cu_active_number)
67 		cu_mask_count = cu_info.cu_active_number;
68 
69 	for (se = 0; se < cu_info.num_shader_engines; se++)
70 		for (i = 0; i < 4; i++)
71 			cu_per_sh[se] += hweight32(cu_info.cu_bitmap[se][i]);
72 
73 	/* Symmetrically map cu_mask to all SEs:
74 	 * cu_mask[0] bit0 -> se_mask[0] bit0;
75 	 * cu_mask[0] bit1 -> se_mask[1] bit0;
76 	 * ... (if # SE is 4)
77 	 * cu_mask[0] bit4 -> se_mask[0] bit1;
78 	 * ...
79 	 */
80 	se = 0;
81 	for (i = 0; i < cu_mask_count; i++) {
82 		if (cu_mask[i / 32] & (1 << (i % 32)))
83 			se_mask[se] |= 1 << cu;
84 
85 		do {
86 			se++;
87 			if (se == cu_info.num_shader_engines) {
88 				se = 0;
89 				cu++;
90 			}
91 		} while (cu >= cu_per_sh[se] && cu < 32);
92 	}
93 }
94