1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/printk.h> 25 #include <linux/slab.h> 26 #include <linux/mm_types.h> 27 28 #include "kfd_priv.h" 29 #include "kfd_mqd_manager.h" 30 #include "vi_structs.h" 31 #include "gca/gfx_8_0_sh_mask.h" 32 #include "gca/gfx_8_0_enum.h" 33 #include "oss/oss_3_0_sh_mask.h" 34 35 #define CP_MQD_CONTROL__PRIV_STATE__SHIFT 0x8 36 37 static inline struct vi_mqd *get_mqd(void *mqd) 38 { 39 return (struct vi_mqd *)mqd; 40 } 41 42 static inline struct vi_sdma_mqd *get_sdma_mqd(void *mqd) 43 { 44 return (struct vi_sdma_mqd *)mqd; 45 } 46 47 static void update_cu_mask(struct mqd_manager *mm, void *mqd, 48 struct queue_properties *q) 49 { 50 struct vi_mqd *m; 51 uint32_t se_mask[4] = {0}; /* 4 is the max # of SEs */ 52 53 if (q->cu_mask_count == 0) 54 return; 55 56 mqd_symmetrically_map_cu_mask(mm, 57 q->cu_mask, q->cu_mask_count, se_mask); 58 59 m = get_mqd(mqd); 60 m->compute_static_thread_mgmt_se0 = se_mask[0]; 61 m->compute_static_thread_mgmt_se1 = se_mask[1]; 62 m->compute_static_thread_mgmt_se2 = se_mask[2]; 63 m->compute_static_thread_mgmt_se3 = se_mask[3]; 64 65 pr_debug("Update cu mask to %#x %#x %#x %#x\n", 66 m->compute_static_thread_mgmt_se0, 67 m->compute_static_thread_mgmt_se1, 68 m->compute_static_thread_mgmt_se2, 69 m->compute_static_thread_mgmt_se3); 70 } 71 72 static void set_priority(struct vi_mqd *m, struct queue_properties *q) 73 { 74 m->cp_hqd_pipe_priority = pipe_priority_map[q->priority]; 75 m->cp_hqd_queue_priority = q->priority; 76 } 77 78 static struct kfd_mem_obj *allocate_mqd(struct kfd_dev *kfd, 79 struct queue_properties *q) 80 { 81 struct kfd_mem_obj *mqd_mem_obj; 82 83 if (kfd_gtt_sa_allocate(kfd, sizeof(struct vi_mqd), 84 &mqd_mem_obj)) 85 return NULL; 86 87 return mqd_mem_obj; 88 } 89 90 static void init_mqd(struct mqd_manager *mm, void **mqd, 91 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 92 struct queue_properties *q) 93 { 94 uint64_t addr; 95 struct vi_mqd *m; 96 97 m = (struct vi_mqd *) mqd_mem_obj->cpu_ptr; 98 addr = mqd_mem_obj->gpu_addr; 99 100 memset(m, 0, sizeof(struct vi_mqd)); 101 102 m->header = 0xC0310800; 103 m->compute_pipelinestat_enable = 1; 104 m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF; 105 m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF; 106 m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF; 107 m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF; 108 109 m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK | 110 0x53 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT; 111 112 m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT | 113 MTYPE_UC << CP_MQD_CONTROL__MTYPE__SHIFT; 114 115 m->cp_mqd_base_addr_lo = lower_32_bits(addr); 116 m->cp_mqd_base_addr_hi = upper_32_bits(addr); 117 118 m->cp_hqd_quantum = 1 << CP_HQD_QUANTUM__QUANTUM_EN__SHIFT | 119 1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT | 120 1 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT; 121 122 set_priority(m, q); 123 m->cp_hqd_eop_rptr = 1 << CP_HQD_EOP_RPTR__INIT_FETCHER__SHIFT; 124 125 if (q->format == KFD_QUEUE_FORMAT_AQL) 126 m->cp_hqd_iq_rptr = 1; 127 128 if (q->tba_addr) { 129 m->compute_tba_lo = lower_32_bits(q->tba_addr >> 8); 130 m->compute_tba_hi = upper_32_bits(q->tba_addr >> 8); 131 m->compute_tma_lo = lower_32_bits(q->tma_addr >> 8); 132 m->compute_tma_hi = upper_32_bits(q->tma_addr >> 8); 133 m->compute_pgm_rsrc2 |= 134 (1 << COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT); 135 } 136 137 if (mm->dev->cwsr_enabled && q->ctx_save_restore_area_address) { 138 m->cp_hqd_persistent_state |= 139 (1 << CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT); 140 m->cp_hqd_ctx_save_base_addr_lo = 141 lower_32_bits(q->ctx_save_restore_area_address); 142 m->cp_hqd_ctx_save_base_addr_hi = 143 upper_32_bits(q->ctx_save_restore_area_address); 144 m->cp_hqd_ctx_save_size = q->ctx_save_restore_area_size; 145 m->cp_hqd_cntl_stack_size = q->ctl_stack_size; 146 m->cp_hqd_cntl_stack_offset = q->ctl_stack_size; 147 m->cp_hqd_wg_state_offset = q->ctl_stack_size; 148 } 149 150 *mqd = m; 151 if (gart_addr) 152 *gart_addr = addr; 153 mm->update_mqd(mm, m, q, NULL); 154 } 155 156 static int load_mqd(struct mqd_manager *mm, void *mqd, 157 uint32_t pipe_id, uint32_t queue_id, 158 struct queue_properties *p, struct mm_struct *mms) 159 { 160 /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */ 161 uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0); 162 uint32_t wptr_mask = (uint32_t)((p->queue_size / 4) - 1); 163 164 return mm->dev->kfd2kgd->hqd_load(mm->dev->kgd, mqd, pipe_id, queue_id, 165 (uint32_t __user *)p->write_ptr, 166 wptr_shift, wptr_mask, mms); 167 } 168 169 static void __update_mqd(struct mqd_manager *mm, void *mqd, 170 struct queue_properties *q, struct mqd_update_info *minfo, 171 unsigned int mtype, unsigned int atc_bit) 172 { 173 struct vi_mqd *m; 174 175 m = get_mqd(mqd); 176 177 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT | 178 atc_bit << CP_HQD_PQ_CONTROL__PQ_ATC__SHIFT | 179 mtype << CP_HQD_PQ_CONTROL__MTYPE__SHIFT; 180 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; 181 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); 182 183 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); 184 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); 185 186 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 187 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 188 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); 189 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); 190 191 m->cp_hqd_pq_doorbell_control = 192 q->doorbell_off << 193 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 194 pr_debug("cp_hqd_pq_doorbell_control 0x%x\n", 195 m->cp_hqd_pq_doorbell_control); 196 197 m->cp_hqd_eop_control = atc_bit << CP_HQD_EOP_CONTROL__EOP_ATC__SHIFT | 198 mtype << CP_HQD_EOP_CONTROL__MTYPE__SHIFT; 199 200 m->cp_hqd_ib_control = atc_bit << CP_HQD_IB_CONTROL__IB_ATC__SHIFT | 201 3 << CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT | 202 mtype << CP_HQD_IB_CONTROL__MTYPE__SHIFT; 203 204 /* 205 * HW does not clamp this field correctly. Maximum EOP queue size 206 * is constrained by per-SE EOP done signal count, which is 8-bit. 207 * Limit is 0xFF EOP entries (= 0x7F8 dwords). CP will not submit 208 * more than (EOP entry count - 1) so a queue size of 0x800 dwords 209 * is safe, giving a maximum field value of 0xA. 210 */ 211 m->cp_hqd_eop_control |= min(0xA, 212 order_base_2(q->eop_ring_buffer_size / 4) - 1); 213 m->cp_hqd_eop_base_addr_lo = 214 lower_32_bits(q->eop_ring_buffer_address >> 8); 215 m->cp_hqd_eop_base_addr_hi = 216 upper_32_bits(q->eop_ring_buffer_address >> 8); 217 218 m->cp_hqd_iq_timer = atc_bit << CP_HQD_IQ_TIMER__IQ_ATC__SHIFT | 219 mtype << CP_HQD_IQ_TIMER__MTYPE__SHIFT; 220 221 m->cp_hqd_vmid = q->vmid; 222 223 if (q->format == KFD_QUEUE_FORMAT_AQL) { 224 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | 225 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT; 226 } 227 228 if (mm->dev->cwsr_enabled && q->ctx_save_restore_area_address) 229 m->cp_hqd_ctx_save_control = 230 atc_bit << CP_HQD_CTX_SAVE_CONTROL__ATC__SHIFT | 231 mtype << CP_HQD_CTX_SAVE_CONTROL__MTYPE__SHIFT; 232 233 update_cu_mask(mm, mqd, q); 234 set_priority(m, q); 235 236 q->is_active = QUEUE_IS_ACTIVE(*q); 237 } 238 239 240 static void update_mqd(struct mqd_manager *mm, void *mqd, 241 struct queue_properties *q, 242 struct mqd_update_info *minfo) 243 { 244 __update_mqd(mm, mqd, q, minfo, MTYPE_CC, 1); 245 } 246 247 static uint32_t read_doorbell_id(void *mqd) 248 { 249 struct vi_mqd *m = (struct vi_mqd *)mqd; 250 251 return m->queue_doorbell_id0; 252 } 253 254 static void update_mqd_tonga(struct mqd_manager *mm, void *mqd, 255 struct queue_properties *q, 256 struct mqd_update_info *minfo) 257 { 258 __update_mqd(mm, mqd, q, minfo, MTYPE_UC, 0); 259 } 260 261 static int destroy_mqd(struct mqd_manager *mm, void *mqd, 262 enum kfd_preempt_type type, 263 unsigned int timeout, uint32_t pipe_id, 264 uint32_t queue_id) 265 { 266 return mm->dev->kfd2kgd->hqd_destroy 267 (mm->dev->kgd, mqd, type, timeout, 268 pipe_id, queue_id); 269 } 270 271 static void free_mqd(struct mqd_manager *mm, void *mqd, 272 struct kfd_mem_obj *mqd_mem_obj) 273 { 274 kfd_gtt_sa_free(mm->dev, mqd_mem_obj); 275 } 276 277 static bool is_occupied(struct mqd_manager *mm, void *mqd, 278 uint64_t queue_address, uint32_t pipe_id, 279 uint32_t queue_id) 280 { 281 return mm->dev->kfd2kgd->hqd_is_occupied( 282 mm->dev->kgd, queue_address, 283 pipe_id, queue_id); 284 } 285 286 static int get_wave_state(struct mqd_manager *mm, void *mqd, 287 void __user *ctl_stack, 288 u32 *ctl_stack_used_size, 289 u32 *save_area_used_size) 290 { 291 struct vi_mqd *m; 292 293 m = get_mqd(mqd); 294 295 *ctl_stack_used_size = m->cp_hqd_cntl_stack_size - 296 m->cp_hqd_cntl_stack_offset; 297 *save_area_used_size = m->cp_hqd_wg_state_offset - 298 m->cp_hqd_cntl_stack_size; 299 300 /* Control stack is not copied to user mode for GFXv8 because 301 * it's part of the context save area that is already 302 * accessible to user mode 303 */ 304 305 return 0; 306 } 307 308 static void init_mqd_hiq(struct mqd_manager *mm, void **mqd, 309 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 310 struct queue_properties *q) 311 { 312 struct vi_mqd *m; 313 init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q); 314 315 m = get_mqd(*mqd); 316 317 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | 318 1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT; 319 } 320 321 static void update_mqd_hiq(struct mqd_manager *mm, void *mqd, 322 struct queue_properties *q, 323 struct mqd_update_info *minfo) 324 { 325 __update_mqd(mm, mqd, q, minfo, MTYPE_UC, 0); 326 } 327 328 static void init_mqd_sdma(struct mqd_manager *mm, void **mqd, 329 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 330 struct queue_properties *q) 331 { 332 struct vi_sdma_mqd *m; 333 334 m = (struct vi_sdma_mqd *) mqd_mem_obj->cpu_ptr; 335 336 memset(m, 0, sizeof(struct vi_sdma_mqd)); 337 338 *mqd = m; 339 if (gart_addr) 340 *gart_addr = mqd_mem_obj->gpu_addr; 341 342 mm->update_mqd(mm, m, q, NULL); 343 } 344 345 static int load_mqd_sdma(struct mqd_manager *mm, void *mqd, 346 uint32_t pipe_id, uint32_t queue_id, 347 struct queue_properties *p, struct mm_struct *mms) 348 { 349 return mm->dev->kfd2kgd->hqd_sdma_load(mm->dev->kgd, mqd, 350 (uint32_t __user *)p->write_ptr, 351 mms); 352 } 353 354 static void update_mqd_sdma(struct mqd_manager *mm, void *mqd, 355 struct queue_properties *q, 356 struct mqd_update_info *minfo) 357 { 358 struct vi_sdma_mqd *m; 359 360 m = get_sdma_mqd(mqd); 361 m->sdmax_rlcx_rb_cntl = order_base_2(q->queue_size / 4) 362 << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT | 363 q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT | 364 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 365 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT; 366 367 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); 368 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); 369 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 370 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 371 m->sdmax_rlcx_doorbell = 372 q->doorbell_off << SDMA0_RLC0_DOORBELL__OFFSET__SHIFT; 373 374 m->sdmax_rlcx_virtual_addr = q->sdma_vm_addr; 375 376 m->sdma_engine_id = q->sdma_engine_id; 377 m->sdma_queue_id = q->sdma_queue_id; 378 379 q->is_active = QUEUE_IS_ACTIVE(*q); 380 } 381 382 /* 383 * * preempt type here is ignored because there is only one way 384 * * to preempt sdma queue 385 */ 386 static int destroy_mqd_sdma(struct mqd_manager *mm, void *mqd, 387 enum kfd_preempt_type type, 388 unsigned int timeout, uint32_t pipe_id, 389 uint32_t queue_id) 390 { 391 return mm->dev->kfd2kgd->hqd_sdma_destroy(mm->dev->kgd, mqd, timeout); 392 } 393 394 static bool is_occupied_sdma(struct mqd_manager *mm, void *mqd, 395 uint64_t queue_address, uint32_t pipe_id, 396 uint32_t queue_id) 397 { 398 return mm->dev->kfd2kgd->hqd_sdma_is_occupied(mm->dev->kgd, mqd); 399 } 400 401 #if defined(CONFIG_DEBUG_FS) 402 403 static int debugfs_show_mqd(struct seq_file *m, void *data) 404 { 405 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 406 data, sizeof(struct vi_mqd), false); 407 return 0; 408 } 409 410 static int debugfs_show_mqd_sdma(struct seq_file *m, void *data) 411 { 412 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 413 data, sizeof(struct vi_sdma_mqd), false); 414 return 0; 415 } 416 417 #endif 418 419 struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type, 420 struct kfd_dev *dev) 421 { 422 struct mqd_manager *mqd; 423 424 if (WARN_ON(type >= KFD_MQD_TYPE_MAX)) 425 return NULL; 426 427 mqd = kzalloc(sizeof(*mqd), GFP_KERNEL); 428 if (!mqd) 429 return NULL; 430 431 mqd->dev = dev; 432 433 switch (type) { 434 case KFD_MQD_TYPE_CP: 435 mqd->allocate_mqd = allocate_mqd; 436 mqd->init_mqd = init_mqd; 437 mqd->free_mqd = free_mqd; 438 mqd->load_mqd = load_mqd; 439 mqd->update_mqd = update_mqd; 440 mqd->destroy_mqd = destroy_mqd; 441 mqd->is_occupied = is_occupied; 442 mqd->get_wave_state = get_wave_state; 443 mqd->mqd_size = sizeof(struct vi_mqd); 444 #if defined(CONFIG_DEBUG_FS) 445 mqd->debugfs_show_mqd = debugfs_show_mqd; 446 #endif 447 break; 448 case KFD_MQD_TYPE_HIQ: 449 mqd->allocate_mqd = allocate_hiq_mqd; 450 mqd->init_mqd = init_mqd_hiq; 451 mqd->free_mqd = free_mqd_hiq_sdma; 452 mqd->load_mqd = load_mqd; 453 mqd->update_mqd = update_mqd_hiq; 454 mqd->destroy_mqd = destroy_mqd; 455 mqd->is_occupied = is_occupied; 456 mqd->mqd_size = sizeof(struct vi_mqd); 457 #if defined(CONFIG_DEBUG_FS) 458 mqd->debugfs_show_mqd = debugfs_show_mqd; 459 #endif 460 mqd->read_doorbell_id = read_doorbell_id; 461 break; 462 case KFD_MQD_TYPE_DIQ: 463 mqd->allocate_mqd = allocate_mqd; 464 mqd->init_mqd = init_mqd_hiq; 465 mqd->free_mqd = free_mqd; 466 mqd->load_mqd = load_mqd; 467 mqd->update_mqd = update_mqd_hiq; 468 mqd->destroy_mqd = destroy_mqd; 469 mqd->is_occupied = is_occupied; 470 mqd->mqd_size = sizeof(struct vi_mqd); 471 #if defined(CONFIG_DEBUG_FS) 472 mqd->debugfs_show_mqd = debugfs_show_mqd; 473 #endif 474 break; 475 case KFD_MQD_TYPE_SDMA: 476 mqd->allocate_mqd = allocate_sdma_mqd; 477 mqd->init_mqd = init_mqd_sdma; 478 mqd->free_mqd = free_mqd_hiq_sdma; 479 mqd->load_mqd = load_mqd_sdma; 480 mqd->update_mqd = update_mqd_sdma; 481 mqd->destroy_mqd = destroy_mqd_sdma; 482 mqd->is_occupied = is_occupied_sdma; 483 mqd->mqd_size = sizeof(struct vi_sdma_mqd); 484 #if defined(CONFIG_DEBUG_FS) 485 mqd->debugfs_show_mqd = debugfs_show_mqd_sdma; 486 #endif 487 break; 488 default: 489 kfree(mqd); 490 return NULL; 491 } 492 493 return mqd; 494 } 495 496 struct mqd_manager *mqd_manager_init_vi_tonga(enum KFD_MQD_TYPE type, 497 struct kfd_dev *dev) 498 { 499 struct mqd_manager *mqd; 500 501 mqd = mqd_manager_init_vi(type, dev); 502 if (!mqd) 503 return NULL; 504 if (type == KFD_MQD_TYPE_CP) 505 mqd->update_mqd = update_mqd_tonga; 506 return mqd; 507 } 508