1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <drm/drm_crtc.h> 27 #include <drm/drm_vblank.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_dm.h" 31 #include "dc.h" 32 33 static const char *const pipe_crc_sources[] = { 34 "none", 35 "crtc", 36 "crtc dither", 37 "dprx", 38 "dprx dither", 39 "auto", 40 }; 41 42 static enum amdgpu_dm_pipe_crc_source dm_parse_crc_source(const char *source) 43 { 44 if (!source || !strcmp(source, "none")) 45 return AMDGPU_DM_PIPE_CRC_SOURCE_NONE; 46 if (!strcmp(source, "auto") || !strcmp(source, "crtc")) 47 return AMDGPU_DM_PIPE_CRC_SOURCE_CRTC; 48 if (!strcmp(source, "dprx")) 49 return AMDGPU_DM_PIPE_CRC_SOURCE_DPRX; 50 if (!strcmp(source, "crtc dither")) 51 return AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER; 52 if (!strcmp(source, "dprx dither")) 53 return AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER; 54 55 return AMDGPU_DM_PIPE_CRC_SOURCE_INVALID; 56 } 57 58 static bool dm_is_crc_source_crtc(enum amdgpu_dm_pipe_crc_source src) 59 { 60 return (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC) || 61 (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER); 62 } 63 64 static bool dm_is_crc_source_dprx(enum amdgpu_dm_pipe_crc_source src) 65 { 66 return (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX) || 67 (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER); 68 } 69 70 static bool dm_need_crc_dither(enum amdgpu_dm_pipe_crc_source src) 71 { 72 return (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER) || 73 (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER) || 74 (src == AMDGPU_DM_PIPE_CRC_SOURCE_NONE); 75 } 76 77 const char *const *amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc, 78 size_t *count) 79 { 80 *count = ARRAY_SIZE(pipe_crc_sources); 81 return pipe_crc_sources; 82 } 83 84 int 85 amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc, const char *src_name, 86 size_t *values_cnt) 87 { 88 enum amdgpu_dm_pipe_crc_source source = dm_parse_crc_source(src_name); 89 90 if (source < 0) { 91 DRM_DEBUG_DRIVER("Unknown CRC source %s for CRTC%d\n", 92 src_name, crtc->index); 93 return -EINVAL; 94 } 95 96 *values_cnt = 3; 97 return 0; 98 } 99 100 int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc, 101 struct dm_crtc_state *dm_crtc_state, 102 enum amdgpu_dm_pipe_crc_source source) 103 { 104 struct amdgpu_device *adev = crtc->dev->dev_private; 105 struct dc_stream_state *stream_state = dm_crtc_state->stream; 106 bool enable = amdgpu_dm_is_valid_crc_source(source); 107 int ret = 0; 108 109 /* Configuration will be deferred to stream enable. */ 110 if (!stream_state) 111 return 0; 112 113 mutex_lock(&adev->dm.dc_lock); 114 115 /* Enable CRTC CRC generation if necessary. */ 116 if (dm_is_crc_source_crtc(source)) { 117 if (!dc_stream_configure_crc(stream_state->ctx->dc, 118 stream_state, enable, enable)) { 119 ret = -EINVAL; 120 goto unlock; 121 } 122 } 123 124 /* Configure dithering */ 125 if (!dm_need_crc_dither(source)) 126 dc_stream_set_dither_option(stream_state, DITHER_OPTION_TRUN8); 127 else 128 dc_stream_set_dither_option(stream_state, 129 DITHER_OPTION_DEFAULT); 130 131 unlock: 132 mutex_unlock(&adev->dm.dc_lock); 133 134 return ret; 135 } 136 137 int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name) 138 { 139 enum amdgpu_dm_pipe_crc_source source = dm_parse_crc_source(src_name); 140 struct drm_crtc_commit *commit; 141 struct dm_crtc_state *crtc_state; 142 struct drm_dp_aux *aux = NULL; 143 bool enable = false; 144 bool enabled = false; 145 int ret = 0; 146 147 if (source < 0) { 148 DRM_DEBUG_DRIVER("Unknown CRC source %s for CRTC%d\n", 149 src_name, crtc->index); 150 return -EINVAL; 151 } 152 153 ret = drm_modeset_lock(&crtc->mutex, NULL); 154 if (ret) 155 return ret; 156 157 spin_lock(&crtc->commit_lock); 158 commit = list_first_entry_or_null(&crtc->commit_list, 159 struct drm_crtc_commit, commit_entry); 160 if (commit) 161 drm_crtc_commit_get(commit); 162 spin_unlock(&crtc->commit_lock); 163 164 if (commit) { 165 /* 166 * Need to wait for all outstanding programming to complete 167 * in commit tail since it can modify CRC related fields and 168 * hardware state. Since we're holding the CRTC lock we're 169 * guaranteed that no other commit work can be queued off 170 * before we modify the state below. 171 */ 172 ret = wait_for_completion_interruptible_timeout( 173 &commit->hw_done, 10 * HZ); 174 if (ret) 175 goto cleanup; 176 } 177 178 enable = amdgpu_dm_is_valid_crc_source(source); 179 crtc_state = to_dm_crtc_state(crtc->state); 180 181 /* 182 * USER REQ SRC | CURRENT SRC | BEHAVIOR 183 * ----------------------------- 184 * None | None | Do nothing 185 * None | CRTC | Disable CRTC CRC, set default to dither 186 * None | DPRX | Disable DPRX CRC, need 'aux', set default to dither 187 * None | CRTC DITHER | Disable CRTC CRC 188 * None | DPRX DITHER | Disable DPRX CRC, need 'aux' 189 * CRTC | XXXX | Enable CRTC CRC, no dither 190 * DPRX | XXXX | Enable DPRX CRC, need 'aux', no dither 191 * CRTC DITHER | XXXX | Enable CRTC CRC, set dither 192 * DPRX DITHER | XXXX | Enable DPRX CRC, need 'aux', set dither 193 */ 194 if (dm_is_crc_source_dprx(source) || 195 (source == AMDGPU_DM_PIPE_CRC_SOURCE_NONE && 196 dm_is_crc_source_dprx(crtc_state->crc_src))) { 197 struct amdgpu_dm_connector *aconn = NULL; 198 struct drm_connector *connector; 199 struct drm_connector_list_iter conn_iter; 200 201 drm_connector_list_iter_begin(crtc->dev, &conn_iter); 202 drm_for_each_connector_iter(connector, &conn_iter) { 203 if (!connector->state || connector->state->crtc != crtc) 204 continue; 205 206 aconn = to_amdgpu_dm_connector(connector); 207 break; 208 } 209 drm_connector_list_iter_end(&conn_iter); 210 211 if (!aconn) { 212 DRM_DEBUG_DRIVER("No amd connector matching CRTC-%d\n", crtc->index); 213 ret = -EINVAL; 214 goto cleanup; 215 } 216 217 aux = &aconn->dm_dp_aux.aux; 218 219 if (!aux) { 220 DRM_DEBUG_DRIVER("No dp aux for amd connector\n"); 221 ret = -EINVAL; 222 goto cleanup; 223 } 224 } 225 226 if (amdgpu_dm_crtc_configure_crc_source(crtc, crtc_state, source)) { 227 ret = -EINVAL; 228 goto cleanup; 229 } 230 231 /* 232 * Reading the CRC requires the vblank interrupt handler to be 233 * enabled. Keep a reference until CRC capture stops. 234 */ 235 enabled = amdgpu_dm_is_valid_crc_source(crtc_state->crc_src); 236 if (!enabled && enable) { 237 ret = drm_crtc_vblank_get(crtc); 238 if (ret) 239 goto cleanup; 240 241 if (dm_is_crc_source_dprx(source)) { 242 if (drm_dp_start_crc(aux, crtc)) { 243 DRM_DEBUG_DRIVER("dp start crc failed\n"); 244 ret = -EINVAL; 245 goto cleanup; 246 } 247 } 248 } else if (enabled && !enable) { 249 drm_crtc_vblank_put(crtc); 250 if (dm_is_crc_source_dprx(source)) { 251 if (drm_dp_stop_crc(aux)) { 252 DRM_DEBUG_DRIVER("dp stop crc failed\n"); 253 ret = -EINVAL; 254 goto cleanup; 255 } 256 } 257 } 258 259 crtc_state->crc_src = source; 260 261 /* Reset crc_skipped on dm state */ 262 crtc_state->crc_skip_count = 0; 263 264 cleanup: 265 if (commit) 266 drm_crtc_commit_put(commit); 267 268 drm_modeset_unlock(&crtc->mutex); 269 270 return ret; 271 } 272 273 /** 274 * amdgpu_dm_crtc_handle_crc_irq: Report to DRM the CRC on given CRTC. 275 * @crtc: DRM CRTC object. 276 * 277 * This function should be called at the end of a vblank, when the fb has been 278 * fully processed through the pipe. 279 */ 280 void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc) 281 { 282 struct dm_crtc_state *crtc_state; 283 struct dc_stream_state *stream_state; 284 uint32_t crcs[3]; 285 286 if (crtc == NULL) 287 return; 288 289 crtc_state = to_dm_crtc_state(crtc->state); 290 stream_state = crtc_state->stream; 291 292 /* Early return if CRC capture is not enabled. */ 293 if (!amdgpu_dm_is_valid_crc_source(crtc_state->crc_src)) 294 return; 295 296 /* 297 * Since flipping and crc enablement happen asynchronously, we - more 298 * often than not - will be returning an 'uncooked' crc on first frame. 299 * Probably because hw isn't ready yet. For added security, skip the 300 * first two CRC values. 301 */ 302 if (crtc_state->crc_skip_count < 2) { 303 crtc_state->crc_skip_count += 1; 304 return; 305 } 306 307 if (dm_is_crc_source_crtc(crtc_state->crc_src)) { 308 if (!dc_stream_get_crc(stream_state->ctx->dc, stream_state, 309 &crcs[0], &crcs[1], &crcs[2])) 310 return; 311 312 drm_crtc_add_crc_entry(crtc, true, 313 drm_crtc_accurate_vblank_count(crtc), crcs); 314 } 315 } 316