1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <drm/drm_crtc.h> 27 #include <drm/drm_vblank.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_dm.h" 31 #include "dc.h" 32 #include "amdgpu_securedisplay.h" 33 34 static const char *const pipe_crc_sources[] = { 35 "none", 36 "crtc", 37 "crtc dither", 38 "dprx", 39 "dprx dither", 40 "auto", 41 }; 42 43 static enum amdgpu_dm_pipe_crc_source dm_parse_crc_source(const char *source) 44 { 45 if (!source || !strcmp(source, "none")) 46 return AMDGPU_DM_PIPE_CRC_SOURCE_NONE; 47 if (!strcmp(source, "auto") || !strcmp(source, "crtc")) 48 return AMDGPU_DM_PIPE_CRC_SOURCE_CRTC; 49 if (!strcmp(source, "dprx")) 50 return AMDGPU_DM_PIPE_CRC_SOURCE_DPRX; 51 if (!strcmp(source, "crtc dither")) 52 return AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER; 53 if (!strcmp(source, "dprx dither")) 54 return AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER; 55 56 return AMDGPU_DM_PIPE_CRC_SOURCE_INVALID; 57 } 58 59 static bool dm_is_crc_source_crtc(enum amdgpu_dm_pipe_crc_source src) 60 { 61 return (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC) || 62 (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER); 63 } 64 65 static bool dm_is_crc_source_dprx(enum amdgpu_dm_pipe_crc_source src) 66 { 67 return (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX) || 68 (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER); 69 } 70 71 static bool dm_need_crc_dither(enum amdgpu_dm_pipe_crc_source src) 72 { 73 return (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER) || 74 (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER) || 75 (src == AMDGPU_DM_PIPE_CRC_SOURCE_NONE); 76 } 77 78 const char *const *amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc, 79 size_t *count) 80 { 81 *count = ARRAY_SIZE(pipe_crc_sources); 82 return pipe_crc_sources; 83 } 84 85 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 86 static void amdgpu_dm_set_crc_window_default(struct drm_crtc *crtc) 87 { 88 struct drm_device *drm_dev = crtc->dev; 89 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 90 91 spin_lock_irq(&drm_dev->event_lock); 92 acrtc->dm_irq_params.window_param.x_start = 0; 93 acrtc->dm_irq_params.window_param.y_start = 0; 94 acrtc->dm_irq_params.window_param.x_end = 0; 95 acrtc->dm_irq_params.window_param.y_end = 0; 96 acrtc->dm_irq_params.window_param.activated = false; 97 acrtc->dm_irq_params.window_param.update_win = false; 98 acrtc->dm_irq_params.window_param.skip_frame_cnt = 0; 99 spin_unlock_irq(&drm_dev->event_lock); 100 } 101 102 static void amdgpu_dm_crtc_notify_ta_to_read(struct work_struct *work) 103 { 104 struct secure_display_context *secure_display_ctx; 105 struct psp_context *psp; 106 struct ta_securedisplay_cmd *securedisplay_cmd; 107 struct drm_crtc *crtc; 108 struct dc_stream_state *stream; 109 uint8_t phy_inst; 110 int ret; 111 112 secure_display_ctx = container_of(work, struct secure_display_context, notify_ta_work); 113 crtc = secure_display_ctx->crtc; 114 115 if (!crtc) { 116 return; 117 } 118 119 psp = &drm_to_adev(crtc->dev)->psp; 120 121 if (!psp->securedisplay_context.context.initialized) { 122 DRM_DEBUG_DRIVER("Secure Display fails to notify PSP TA\n"); 123 return; 124 } 125 126 stream = to_amdgpu_crtc(crtc)->dm_irq_params.stream; 127 phy_inst = stream->link->link_enc_hw_inst; 128 129 /* need lock for multiple crtcs to use the command buffer */ 130 mutex_lock(&psp->securedisplay_context.mutex); 131 132 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 133 TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC); 134 135 securedisplay_cmd->securedisplay_in_message.send_roi_crc.phy_id = phy_inst; 136 137 /* PSP TA is expected to finish data transmission over I2C within current frame, 138 * even there are up to 4 crtcs request to send in this frame. 139 */ 140 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC); 141 142 if (!ret) { 143 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 144 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 145 } 146 } 147 148 mutex_unlock(&psp->securedisplay_context.mutex); 149 } 150 151 static void 152 amdgpu_dm_forward_crc_window(struct work_struct *work) 153 { 154 struct secure_display_context *secure_display_ctx; 155 struct amdgpu_display_manager *dm; 156 struct drm_crtc *crtc; 157 struct dc_stream_state *stream; 158 159 secure_display_ctx = container_of(work, struct secure_display_context, forward_roi_work); 160 crtc = secure_display_ctx->crtc; 161 162 if (!crtc) 163 return; 164 165 dm = &drm_to_adev(crtc->dev)->dm; 166 stream = to_amdgpu_crtc(crtc)->dm_irq_params.stream; 167 168 mutex_lock(&dm->dc_lock); 169 dc_stream_forward_crc_window(stream, &secure_display_ctx->rect, false); 170 mutex_unlock(&dm->dc_lock); 171 } 172 173 bool amdgpu_dm_crc_window_is_activated(struct drm_crtc *crtc) 174 { 175 struct drm_device *drm_dev = crtc->dev; 176 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 177 bool ret = false; 178 179 spin_lock_irq(&drm_dev->event_lock); 180 ret = acrtc->dm_irq_params.window_param.activated; 181 spin_unlock_irq(&drm_dev->event_lock); 182 183 return ret; 184 } 185 #endif 186 187 int 188 amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc, const char *src_name, 189 size_t *values_cnt) 190 { 191 enum amdgpu_dm_pipe_crc_source source = dm_parse_crc_source(src_name); 192 193 if (source < 0) { 194 DRM_DEBUG_DRIVER("Unknown CRC source %s for CRTC%d\n", 195 src_name, crtc->index); 196 return -EINVAL; 197 } 198 199 *values_cnt = 3; 200 return 0; 201 } 202 203 int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc, 204 struct dm_crtc_state *dm_crtc_state, 205 enum amdgpu_dm_pipe_crc_source source) 206 { 207 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 208 int i; 209 #endif 210 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 211 struct dc_stream_state *stream_state = dm_crtc_state->stream; 212 bool enable = amdgpu_dm_is_valid_crc_source(source); 213 int ret = 0; 214 215 /* Configuration will be deferred to stream enable. */ 216 if (!stream_state) 217 return -EINVAL; 218 219 mutex_lock(&adev->dm.dc_lock); 220 221 /* Enable or disable CRTC CRC generation */ 222 if (dm_is_crc_source_crtc(source) || source == AMDGPU_DM_PIPE_CRC_SOURCE_NONE) { 223 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 224 /* Disable secure_display if it was enabled */ 225 if (!enable) { 226 for (i = 0; i < adev->mode_info.num_crtc; i++) { 227 if (adev->dm.secure_display_ctxs[i].crtc == crtc) { 228 /* stop ROI update on this crtc */ 229 flush_work(&adev->dm.secure_display_ctxs[i].notify_ta_work); 230 flush_work(&adev->dm.secure_display_ctxs[i].forward_roi_work); 231 dc_stream_forward_crc_window(stream_state, NULL, true); 232 } 233 } 234 } 235 #endif 236 if (!dc_stream_configure_crc(stream_state->ctx->dc, 237 stream_state, NULL, enable, enable)) { 238 ret = -EINVAL; 239 goto unlock; 240 } 241 } 242 243 /* Configure dithering */ 244 if (!dm_need_crc_dither(source)) { 245 dc_stream_set_dither_option(stream_state, DITHER_OPTION_TRUN8); 246 dc_stream_set_dyn_expansion(stream_state->ctx->dc, stream_state, 247 DYN_EXPANSION_DISABLE); 248 } else { 249 dc_stream_set_dither_option(stream_state, 250 DITHER_OPTION_DEFAULT); 251 dc_stream_set_dyn_expansion(stream_state->ctx->dc, stream_state, 252 DYN_EXPANSION_AUTO); 253 } 254 255 unlock: 256 mutex_unlock(&adev->dm.dc_lock); 257 258 return ret; 259 } 260 261 int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name) 262 { 263 enum amdgpu_dm_pipe_crc_source source = dm_parse_crc_source(src_name); 264 enum amdgpu_dm_pipe_crc_source cur_crc_src; 265 struct drm_crtc_commit *commit; 266 struct dm_crtc_state *crtc_state; 267 struct drm_device *drm_dev = crtc->dev; 268 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 269 struct drm_dp_aux *aux = NULL; 270 bool enable = false; 271 bool enabled = false; 272 int ret = 0; 273 274 if (source < 0) { 275 DRM_DEBUG_DRIVER("Unknown CRC source %s for CRTC%d\n", 276 src_name, crtc->index); 277 return -EINVAL; 278 } 279 280 ret = drm_modeset_lock(&crtc->mutex, NULL); 281 if (ret) 282 return ret; 283 284 spin_lock(&crtc->commit_lock); 285 commit = list_first_entry_or_null(&crtc->commit_list, 286 struct drm_crtc_commit, commit_entry); 287 if (commit) 288 drm_crtc_commit_get(commit); 289 spin_unlock(&crtc->commit_lock); 290 291 if (commit) { 292 /* 293 * Need to wait for all outstanding programming to complete 294 * in commit tail since it can modify CRC related fields and 295 * hardware state. Since we're holding the CRTC lock we're 296 * guaranteed that no other commit work can be queued off 297 * before we modify the state below. 298 */ 299 ret = wait_for_completion_interruptible_timeout( 300 &commit->hw_done, 10 * HZ); 301 if (ret) 302 goto cleanup; 303 } 304 305 enable = amdgpu_dm_is_valid_crc_source(source); 306 crtc_state = to_dm_crtc_state(crtc->state); 307 spin_lock_irq(&drm_dev->event_lock); 308 cur_crc_src = acrtc->dm_irq_params.crc_src; 309 spin_unlock_irq(&drm_dev->event_lock); 310 311 /* 312 * USER REQ SRC | CURRENT SRC | BEHAVIOR 313 * ----------------------------- 314 * None | None | Do nothing 315 * None | CRTC | Disable CRTC CRC, set default to dither 316 * None | DPRX | Disable DPRX CRC, need 'aux', set default to dither 317 * None | CRTC DITHER | Disable CRTC CRC 318 * None | DPRX DITHER | Disable DPRX CRC, need 'aux' 319 * CRTC | XXXX | Enable CRTC CRC, no dither 320 * DPRX | XXXX | Enable DPRX CRC, need 'aux', no dither 321 * CRTC DITHER | XXXX | Enable CRTC CRC, set dither 322 * DPRX DITHER | XXXX | Enable DPRX CRC, need 'aux', set dither 323 */ 324 if (dm_is_crc_source_dprx(source) || 325 (source == AMDGPU_DM_PIPE_CRC_SOURCE_NONE && 326 dm_is_crc_source_dprx(cur_crc_src))) { 327 struct amdgpu_dm_connector *aconn = NULL; 328 struct drm_connector *connector; 329 struct drm_connector_list_iter conn_iter; 330 331 drm_connector_list_iter_begin(crtc->dev, &conn_iter); 332 drm_for_each_connector_iter(connector, &conn_iter) { 333 if (!connector->state || connector->state->crtc != crtc) 334 continue; 335 336 aconn = to_amdgpu_dm_connector(connector); 337 break; 338 } 339 drm_connector_list_iter_end(&conn_iter); 340 341 if (!aconn) { 342 DRM_DEBUG_DRIVER("No amd connector matching CRTC-%d\n", crtc->index); 343 ret = -EINVAL; 344 goto cleanup; 345 } 346 347 aux = (aconn->mst_output_port) ? &aconn->mst_output_port->aux : &aconn->dm_dp_aux.aux; 348 349 if (!aux) { 350 DRM_DEBUG_DRIVER("No dp aux for amd connector\n"); 351 ret = -EINVAL; 352 goto cleanup; 353 } 354 355 if ((aconn->base.connector_type != DRM_MODE_CONNECTOR_DisplayPort) && 356 (aconn->base.connector_type != DRM_MODE_CONNECTOR_eDP)) { 357 DRM_DEBUG_DRIVER("No DP connector available for CRC source\n"); 358 ret = -EINVAL; 359 goto cleanup; 360 } 361 362 } 363 364 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 365 /* Reset secure_display when we change crc source from debugfs */ 366 amdgpu_dm_set_crc_window_default(crtc); 367 #endif 368 369 if (amdgpu_dm_crtc_configure_crc_source(crtc, crtc_state, source)) { 370 ret = -EINVAL; 371 goto cleanup; 372 } 373 374 /* 375 * Reading the CRC requires the vblank interrupt handler to be 376 * enabled. Keep a reference until CRC capture stops. 377 */ 378 enabled = amdgpu_dm_is_valid_crc_source(cur_crc_src); 379 if (!enabled && enable) { 380 ret = drm_crtc_vblank_get(crtc); 381 if (ret) 382 goto cleanup; 383 384 if (dm_is_crc_source_dprx(source)) { 385 if (drm_dp_start_crc(aux, crtc)) { 386 DRM_DEBUG_DRIVER("dp start crc failed\n"); 387 ret = -EINVAL; 388 goto cleanup; 389 } 390 } 391 } else if (enabled && !enable) { 392 drm_crtc_vblank_put(crtc); 393 if (dm_is_crc_source_dprx(source)) { 394 if (drm_dp_stop_crc(aux)) { 395 DRM_DEBUG_DRIVER("dp stop crc failed\n"); 396 ret = -EINVAL; 397 goto cleanup; 398 } 399 } 400 } 401 402 spin_lock_irq(&drm_dev->event_lock); 403 acrtc->dm_irq_params.crc_src = source; 404 spin_unlock_irq(&drm_dev->event_lock); 405 406 /* Reset crc_skipped on dm state */ 407 crtc_state->crc_skip_count = 0; 408 409 cleanup: 410 if (commit) 411 drm_crtc_commit_put(commit); 412 413 drm_modeset_unlock(&crtc->mutex); 414 415 return ret; 416 } 417 418 /** 419 * amdgpu_dm_crtc_handle_crc_irq: Report to DRM the CRC on given CRTC. 420 * @crtc: DRM CRTC object. 421 * 422 * This function should be called at the end of a vblank, when the fb has been 423 * fully processed through the pipe. 424 */ 425 void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc) 426 { 427 struct dm_crtc_state *crtc_state; 428 struct dc_stream_state *stream_state; 429 struct drm_device *drm_dev = NULL; 430 enum amdgpu_dm_pipe_crc_source cur_crc_src; 431 struct amdgpu_crtc *acrtc = NULL; 432 uint32_t crcs[3]; 433 unsigned long flags; 434 435 if (crtc == NULL) 436 return; 437 438 crtc_state = to_dm_crtc_state(crtc->state); 439 stream_state = crtc_state->stream; 440 acrtc = to_amdgpu_crtc(crtc); 441 drm_dev = crtc->dev; 442 443 spin_lock_irqsave(&drm_dev->event_lock, flags); 444 cur_crc_src = acrtc->dm_irq_params.crc_src; 445 spin_unlock_irqrestore(&drm_dev->event_lock, flags); 446 447 /* Early return if CRC capture is not enabled. */ 448 if (!amdgpu_dm_is_valid_crc_source(cur_crc_src)) 449 return; 450 451 /* 452 * Since flipping and crc enablement happen asynchronously, we - more 453 * often than not - will be returning an 'uncooked' crc on first frame. 454 * Probably because hw isn't ready yet. For added security, skip the 455 * first two CRC values. 456 */ 457 if (crtc_state->crc_skip_count < 2) { 458 crtc_state->crc_skip_count += 1; 459 return; 460 } 461 462 if (dm_is_crc_source_crtc(cur_crc_src)) { 463 if (!dc_stream_get_crc(stream_state->ctx->dc, stream_state, 464 &crcs[0], &crcs[1], &crcs[2])) 465 return; 466 467 drm_crtc_add_crc_entry(crtc, true, 468 drm_crtc_accurate_vblank_count(crtc), crcs); 469 } 470 } 471 472 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 473 void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc) 474 { 475 struct drm_device *drm_dev = NULL; 476 enum amdgpu_dm_pipe_crc_source cur_crc_src; 477 struct amdgpu_crtc *acrtc = NULL; 478 struct amdgpu_device *adev = NULL; 479 struct secure_display_context *secure_display_ctx = NULL; 480 unsigned long flags1; 481 482 if (crtc == NULL) 483 return; 484 485 acrtc = to_amdgpu_crtc(crtc); 486 adev = drm_to_adev(crtc->dev); 487 drm_dev = crtc->dev; 488 489 spin_lock_irqsave(&drm_dev->event_lock, flags1); 490 cur_crc_src = acrtc->dm_irq_params.crc_src; 491 492 /* Early return if CRC capture is not enabled. */ 493 if (!amdgpu_dm_is_valid_crc_source(cur_crc_src) || 494 !dm_is_crc_source_crtc(cur_crc_src)) 495 goto cleanup; 496 497 if (!acrtc->dm_irq_params.window_param.activated) 498 goto cleanup; 499 500 if (acrtc->dm_irq_params.window_param.skip_frame_cnt) { 501 acrtc->dm_irq_params.window_param.skip_frame_cnt -= 1; 502 goto cleanup; 503 } 504 505 secure_display_ctx = &adev->dm.secure_display_ctxs[acrtc->crtc_id]; 506 if (WARN_ON(secure_display_ctx->crtc != crtc)) { 507 /* We have set the crtc when creating secure_display_context, 508 * don't expect it to be changed here. 509 */ 510 secure_display_ctx->crtc = crtc; 511 } 512 513 if (acrtc->dm_irq_params.window_param.update_win) { 514 /* prepare work for dmub to update ROI */ 515 secure_display_ctx->rect.x = acrtc->dm_irq_params.window_param.x_start; 516 secure_display_ctx->rect.y = acrtc->dm_irq_params.window_param.y_start; 517 secure_display_ctx->rect.width = acrtc->dm_irq_params.window_param.x_end - 518 acrtc->dm_irq_params.window_param.x_start; 519 secure_display_ctx->rect.height = acrtc->dm_irq_params.window_param.y_end - 520 acrtc->dm_irq_params.window_param.y_start; 521 schedule_work(&secure_display_ctx->forward_roi_work); 522 523 acrtc->dm_irq_params.window_param.update_win = false; 524 525 /* Statically skip 1 frame, because we may need to wait below things 526 * before sending ROI to dmub: 527 * 1. We defer the work by using system workqueue. 528 * 2. We may need to wait for dc_lock before accessing dmub. 529 */ 530 acrtc->dm_irq_params.window_param.skip_frame_cnt = 1; 531 532 } else { 533 /* prepare work for psp to read ROI/CRC and send to I2C */ 534 schedule_work(&secure_display_ctx->notify_ta_work); 535 } 536 537 cleanup: 538 spin_unlock_irqrestore(&drm_dev->event_lock, flags1); 539 } 540 541 struct secure_display_context * 542 amdgpu_dm_crtc_secure_display_create_contexts(struct amdgpu_device *adev) 543 { 544 struct secure_display_context *secure_display_ctxs = NULL; 545 int i; 546 547 secure_display_ctxs = kcalloc(adev->mode_info.num_crtc, 548 sizeof(struct secure_display_context), 549 GFP_KERNEL); 550 551 if (!secure_display_ctxs) 552 return NULL; 553 554 for (i = 0; i < adev->mode_info.num_crtc; i++) { 555 INIT_WORK(&secure_display_ctxs[i].forward_roi_work, amdgpu_dm_forward_crc_window); 556 INIT_WORK(&secure_display_ctxs[i].notify_ta_work, amdgpu_dm_crtc_notify_ta_to_read); 557 secure_display_ctxs[i].crtc = &adev->mode_info.crtcs[i]->base; 558 } 559 560 return secure_display_ctxs; 561 } 562 #endif 563