1 /*
2  * Copyright 2015 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #ifndef __AMDGPU_DM_IRQ_H__
25 #define __AMDGPU_DM_IRQ_H__
26 
27 #include "irq_types.h" /* DAL irq definitions */
28 
29 /*
30  * Display Manager IRQ-related interfaces (for use by DAL).
31  */
32 
33 /**
34  * amdgpu_dm_irq_init - Initialize internal structures of 'amdgpu_dm_irq'.
35  *
36  * This function should be called exactly once - during DM initialization.
37  *
38  * Returns:
39  *	0 - success
40  *	non-zero - error
41  */
42 int amdgpu_dm_irq_init(struct amdgpu_device *adev);
43 
44 /**
45  * amdgpu_dm_irq_fini - deallocate internal structures of 'amdgpu_dm_irq'.
46  *
47  * This function should be called exactly once - during DM destruction.
48  *
49  */
50 void amdgpu_dm_irq_fini(struct amdgpu_device *adev);
51 
52 /**
53  * amdgpu_dm_irq_register_interrupt - register irq handler for Display block.
54  *
55  * @adev: AMD DRM device
56  * @int_params: parameters for the irq
57  * @ih: pointer to the irq hander function
58  * @handler_args: arguments which will be passed to ih
59  *
60  * Returns:
61  * 	IRQ Handler Index on success.
62  * 	NULL on failure.
63  *
64  * Cannot be called from an interrupt handler.
65  */
66 void *amdgpu_dm_irq_register_interrupt(struct amdgpu_device *adev,
67 				       struct dc_interrupt_params *int_params,
68 				       void (*ih)(void *),
69 				       void *handler_args);
70 
71 /**
72  * amdgpu_dm_irq_unregister_interrupt - unregister handler which was registered
73  *	by amdgpu_dm_irq_register_interrupt().
74  *
75  * @adev: AMD DRM device.
76  * @ih_index: irq handler index which was returned by
77  *	amdgpu_dm_irq_register_interrupt
78  */
79 void amdgpu_dm_irq_unregister_interrupt(struct amdgpu_device *adev,
80 					enum dc_irq_source irq_source,
81 					void *ih_index);
82 
83 void amdgpu_dm_set_irq_funcs(struct amdgpu_device *adev);
84 
85 void amdgpu_dm_outbox_init(struct amdgpu_device *adev);
86 void amdgpu_dm_hpd_init(struct amdgpu_device *adev);
87 void amdgpu_dm_hpd_fini(struct amdgpu_device *adev);
88 
89 /**
90  * amdgpu_dm_irq_suspend - disable ASIC interrupt during suspend.
91  *
92  */
93 int amdgpu_dm_irq_suspend(struct amdgpu_device *adev);
94 
95 /**
96  * amdgpu_dm_irq_resume_early - enable HPDRX ASIC interrupts during resume.
97  * amdgpu_dm_irq_resume - enable ASIC interrupt during resume.
98  *
99  */
100 int amdgpu_dm_irq_resume_early(struct amdgpu_device *adev);
101 int amdgpu_dm_irq_resume_late(struct amdgpu_device *adev);
102 
103 #endif /* __AMDGPU_DM_IRQ_H__ */
104