1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 28 #include "ObjectID.h" 29 #include "atomfirmware.h" 30 31 #include "dc_bios_types.h" 32 #include "include/grph_object_ctrl_defs.h" 33 #include "include/bios_parser_interface.h" 34 #include "include/i2caux_interface.h" 35 #include "include/logger_interface.h" 36 37 #include "command_table2.h" 38 39 #include "bios_parser_helper.h" 40 #include "command_table_helper2.h" 41 #include "bios_parser2.h" 42 #include "bios_parser_types_internal2.h" 43 #include "bios_parser_interface.h" 44 45 #include "bios_parser_common.h" 46 47 /* Temporarily add in defines until ObjectID.h patch is updated in a few days */ 48 #ifndef GENERIC_OBJECT_ID_BRACKET_LAYOUT 49 #define GENERIC_OBJECT_ID_BRACKET_LAYOUT 0x05 50 #endif /* GENERIC_OBJECT_ID_BRACKET_LAYOUT */ 51 52 #ifndef GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1 53 #define GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1 \ 54 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\ 55 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 56 GENERIC_OBJECT_ID_BRACKET_LAYOUT << OBJECT_ID_SHIFT) 57 #endif /* GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1 */ 58 59 #ifndef GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2 60 #define GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2 \ 61 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\ 62 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ 63 GENERIC_OBJECT_ID_BRACKET_LAYOUT << OBJECT_ID_SHIFT) 64 #endif /* GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2 */ 65 66 #define DC_LOGGER \ 67 bp->base.ctx->logger 68 69 #define LAST_RECORD_TYPE 0xff 70 #define SMU9_SYSPLL0_ID 0 71 72 struct i2c_id_config_access { 73 uint8_t bfI2C_LineMux:4; 74 uint8_t bfHW_EngineID:3; 75 uint8_t bfHW_Capable:1; 76 uint8_t ucAccess; 77 }; 78 79 static enum bp_result get_gpio_i2c_info(struct bios_parser *bp, 80 struct atom_i2c_record *record, 81 struct graphics_object_i2c_info *info); 82 83 static enum bp_result bios_parser_get_firmware_info( 84 struct dc_bios *dcb, 85 struct dc_firmware_info *info); 86 87 static enum bp_result bios_parser_get_encoder_cap_info( 88 struct dc_bios *dcb, 89 struct graphics_object_id object_id, 90 struct bp_encoder_cap_info *info); 91 92 static enum bp_result get_firmware_info_v3_1( 93 struct bios_parser *bp, 94 struct dc_firmware_info *info); 95 96 static enum bp_result get_firmware_info_v3_2( 97 struct bios_parser *bp, 98 struct dc_firmware_info *info); 99 100 static struct atom_hpd_int_record *get_hpd_record(struct bios_parser *bp, 101 struct atom_display_object_path_v2 *object); 102 103 static struct atom_encoder_caps_record *get_encoder_cap_record( 104 struct bios_parser *bp, 105 struct atom_display_object_path_v2 *object); 106 107 #define BIOS_IMAGE_SIZE_OFFSET 2 108 #define BIOS_IMAGE_SIZE_UNIT 512 109 110 #define DATA_TABLES(table) (bp->master_data_tbl->listOfdatatables.table) 111 112 static void destruct(struct bios_parser *bp) 113 { 114 kfree(bp->base.bios_local_image); 115 kfree(bp->base.integrated_info); 116 } 117 118 static void firmware_parser_destroy(struct dc_bios **dcb) 119 { 120 struct bios_parser *bp = BP_FROM_DCB(*dcb); 121 122 if (!bp) { 123 BREAK_TO_DEBUGGER(); 124 return; 125 } 126 127 destruct(bp); 128 129 kfree(bp); 130 *dcb = NULL; 131 } 132 133 static void get_atom_data_table_revision( 134 struct atom_common_table_header *atom_data_tbl, 135 struct atom_data_revision *tbl_revision) 136 { 137 if (!tbl_revision) 138 return; 139 140 /* initialize the revision to 0 which is invalid revision */ 141 tbl_revision->major = 0; 142 tbl_revision->minor = 0; 143 144 if (!atom_data_tbl) 145 return; 146 147 tbl_revision->major = 148 (uint32_t) atom_data_tbl->format_revision & 0x3f; 149 tbl_revision->minor = 150 (uint32_t) atom_data_tbl->content_revision & 0x3f; 151 } 152 153 /* BIOS oject table displaypath is per connector. 154 * There is extra path not for connector. BIOS fill its encoderid as 0 155 */ 156 static uint8_t bios_parser_get_connectors_number(struct dc_bios *dcb) 157 { 158 struct bios_parser *bp = BP_FROM_DCB(dcb); 159 unsigned int count = 0; 160 unsigned int i; 161 162 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) { 163 if (bp->object_info_tbl.v1_4->display_path[i].encoderobjid != 0) 164 count++; 165 } 166 return count; 167 } 168 169 static struct graphics_object_id bios_parser_get_connector_id( 170 struct dc_bios *dcb, 171 uint8_t i) 172 { 173 struct bios_parser *bp = BP_FROM_DCB(dcb); 174 struct graphics_object_id object_id = dal_graphics_object_id_init( 175 0, ENUM_ID_UNKNOWN, OBJECT_TYPE_UNKNOWN); 176 struct object_info_table *tbl = &bp->object_info_tbl; 177 struct display_object_info_table_v1_4 *v1_4 = tbl->v1_4; 178 179 if (v1_4->number_of_path > i) { 180 /* If display_objid is generic object id, the encoderObj 181 * /extencoderobjId should be 0 182 */ 183 if (v1_4->display_path[i].encoderobjid != 0 && 184 v1_4->display_path[i].display_objid != 0) 185 object_id = object_id_from_bios_object_id( 186 v1_4->display_path[i].display_objid); 187 } 188 189 return object_id; 190 } 191 192 static enum bp_result bios_parser_get_src_obj(struct dc_bios *dcb, 193 struct graphics_object_id object_id, uint32_t index, 194 struct graphics_object_id *src_object_id) 195 { 196 struct bios_parser *bp = BP_FROM_DCB(dcb); 197 unsigned int i; 198 enum bp_result bp_result = BP_RESULT_BADINPUT; 199 struct graphics_object_id obj_id = {0}; 200 struct object_info_table *tbl = &bp->object_info_tbl; 201 202 if (!src_object_id) 203 return bp_result; 204 205 switch (object_id.type) { 206 /* Encoder's Source is GPU. BIOS does not provide GPU, since all 207 * displaypaths point to same GPU (0x1100). Hardcode GPU object type 208 */ 209 case OBJECT_TYPE_ENCODER: 210 /* TODO: since num of src must be less than 2. 211 * If found in for loop, should break. 212 * DAL2 implementation may be changed too 213 */ 214 for (i = 0; i < tbl->v1_4->number_of_path; i++) { 215 obj_id = object_id_from_bios_object_id( 216 tbl->v1_4->display_path[i].encoderobjid); 217 if (object_id.type == obj_id.type && 218 object_id.id == obj_id.id && 219 object_id.enum_id == 220 obj_id.enum_id) { 221 *src_object_id = 222 object_id_from_bios_object_id(0x1100); 223 /* break; */ 224 } 225 } 226 bp_result = BP_RESULT_OK; 227 break; 228 case OBJECT_TYPE_CONNECTOR: 229 for (i = 0; i < tbl->v1_4->number_of_path; i++) { 230 obj_id = object_id_from_bios_object_id( 231 tbl->v1_4->display_path[i].display_objid); 232 233 if (object_id.type == obj_id.type && 234 object_id.id == obj_id.id && 235 object_id.enum_id == obj_id.enum_id) { 236 *src_object_id = 237 object_id_from_bios_object_id( 238 tbl->v1_4->display_path[i].encoderobjid); 239 /* break; */ 240 } 241 } 242 bp_result = BP_RESULT_OK; 243 break; 244 default: 245 break; 246 } 247 248 return bp_result; 249 } 250 251 /* from graphics_object_id, find display path which includes the object_id */ 252 static struct atom_display_object_path_v2 *get_bios_object( 253 struct bios_parser *bp, 254 struct graphics_object_id id) 255 { 256 unsigned int i; 257 struct graphics_object_id obj_id = {0}; 258 259 switch (id.type) { 260 case OBJECT_TYPE_ENCODER: 261 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) { 262 obj_id = object_id_from_bios_object_id( 263 bp->object_info_tbl.v1_4->display_path[i].encoderobjid); 264 if (id.type == obj_id.type && id.id == obj_id.id 265 && id.enum_id == obj_id.enum_id) 266 return &bp->object_info_tbl.v1_4->display_path[i]; 267 } 268 /* fall through */ 269 case OBJECT_TYPE_CONNECTOR: 270 case OBJECT_TYPE_GENERIC: 271 /* Both Generic and Connector Object ID 272 * will be stored on display_objid 273 */ 274 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) { 275 obj_id = object_id_from_bios_object_id( 276 bp->object_info_tbl.v1_4->display_path[i].display_objid); 277 if (id.type == obj_id.type && id.id == obj_id.id 278 && id.enum_id == obj_id.enum_id) 279 return &bp->object_info_tbl.v1_4->display_path[i]; 280 } 281 /* fall through */ 282 default: 283 return NULL; 284 } 285 } 286 287 static enum bp_result bios_parser_get_i2c_info(struct dc_bios *dcb, 288 struct graphics_object_id id, 289 struct graphics_object_i2c_info *info) 290 { 291 uint32_t offset; 292 struct atom_display_object_path_v2 *object; 293 struct atom_common_record_header *header; 294 struct atom_i2c_record *record; 295 struct bios_parser *bp = BP_FROM_DCB(dcb); 296 297 if (!info) 298 return BP_RESULT_BADINPUT; 299 300 object = get_bios_object(bp, id); 301 302 if (!object) 303 return BP_RESULT_BADINPUT; 304 305 offset = object->disp_recordoffset + bp->object_info_tbl_offset; 306 307 for (;;) { 308 header = GET_IMAGE(struct atom_common_record_header, offset); 309 310 if (!header) 311 return BP_RESULT_BADBIOSTABLE; 312 313 if (header->record_type == LAST_RECORD_TYPE || 314 !header->record_size) 315 break; 316 317 if (header->record_type == ATOM_I2C_RECORD_TYPE 318 && sizeof(struct atom_i2c_record) <= 319 header->record_size) { 320 /* get the I2C info */ 321 record = (struct atom_i2c_record *) header; 322 323 if (get_gpio_i2c_info(bp, record, info) == 324 BP_RESULT_OK) 325 return BP_RESULT_OK; 326 } 327 328 offset += header->record_size; 329 } 330 331 return BP_RESULT_NORECORD; 332 } 333 334 static enum bp_result get_gpio_i2c_info( 335 struct bios_parser *bp, 336 struct atom_i2c_record *record, 337 struct graphics_object_i2c_info *info) 338 { 339 struct atom_gpio_pin_lut_v2_1 *header; 340 uint32_t count = 0; 341 unsigned int table_index = 0; 342 343 if (!info) 344 return BP_RESULT_BADINPUT; 345 346 /* get the GPIO_I2C info */ 347 if (!DATA_TABLES(gpio_pin_lut)) 348 return BP_RESULT_BADBIOSTABLE; 349 350 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1, 351 DATA_TABLES(gpio_pin_lut)); 352 if (!header) 353 return BP_RESULT_BADBIOSTABLE; 354 355 if (sizeof(struct atom_common_table_header) + 356 sizeof(struct atom_gpio_pin_assignment) > 357 le16_to_cpu(header->table_header.structuresize)) 358 return BP_RESULT_BADBIOSTABLE; 359 360 /* TODO: is version change? */ 361 if (header->table_header.content_revision != 1) 362 return BP_RESULT_UNSUPPORTED; 363 364 /* get data count */ 365 count = (le16_to_cpu(header->table_header.structuresize) 366 - sizeof(struct atom_common_table_header)) 367 / sizeof(struct atom_gpio_pin_assignment); 368 369 table_index = record->i2c_id & I2C_HW_LANE_MUX; 370 371 if (count < table_index) { 372 bool find_valid = false; 373 374 for (table_index = 0; table_index < count; table_index++) { 375 if (((record->i2c_id & I2C_HW_CAP) == ( 376 header->gpio_pin[table_index].gpio_id & 377 I2C_HW_CAP)) && 378 ((record->i2c_id & I2C_HW_ENGINE_ID_MASK) == 379 (header->gpio_pin[table_index].gpio_id & 380 I2C_HW_ENGINE_ID_MASK)) && 381 ((record->i2c_id & I2C_HW_LANE_MUX) == 382 (header->gpio_pin[table_index].gpio_id & 383 I2C_HW_LANE_MUX))) { 384 /* still valid */ 385 find_valid = true; 386 break; 387 } 388 } 389 /* If we don't find the entry that we are looking for then 390 * we will return BP_Result_BadBiosTable. 391 */ 392 if (find_valid == false) 393 return BP_RESULT_BADBIOSTABLE; 394 } 395 396 /* get the GPIO_I2C_INFO */ 397 info->i2c_hw_assist = (record->i2c_id & I2C_HW_CAP) ? true : false; 398 info->i2c_line = record->i2c_id & I2C_HW_LANE_MUX; 399 info->i2c_engine_id = (record->i2c_id & I2C_HW_ENGINE_ID_MASK) >> 4; 400 info->i2c_slave_address = record->i2c_slave_addr; 401 402 /* TODO: check how to get register offset for en, Y, etc. */ 403 info->gpio_info.clk_a_register_index = 404 le16_to_cpu( 405 header->gpio_pin[table_index].data_a_reg_index); 406 info->gpio_info.clk_a_shift = 407 header->gpio_pin[table_index].gpio_bitshift; 408 409 return BP_RESULT_OK; 410 } 411 412 static enum bp_result bios_parser_get_hpd_info( 413 struct dc_bios *dcb, 414 struct graphics_object_id id, 415 struct graphics_object_hpd_info *info) 416 { 417 struct bios_parser *bp = BP_FROM_DCB(dcb); 418 struct atom_display_object_path_v2 *object; 419 struct atom_hpd_int_record *record = NULL; 420 421 if (!info) 422 return BP_RESULT_BADINPUT; 423 424 object = get_bios_object(bp, id); 425 426 if (!object) 427 return BP_RESULT_BADINPUT; 428 429 record = get_hpd_record(bp, object); 430 431 if (record != NULL) { 432 info->hpd_int_gpio_uid = record->pin_id; 433 info->hpd_active = record->plugin_pin_state; 434 return BP_RESULT_OK; 435 } 436 437 return BP_RESULT_NORECORD; 438 } 439 440 static struct atom_hpd_int_record *get_hpd_record( 441 struct bios_parser *bp, 442 struct atom_display_object_path_v2 *object) 443 { 444 struct atom_common_record_header *header; 445 uint32_t offset; 446 447 if (!object) { 448 BREAK_TO_DEBUGGER(); /* Invalid object */ 449 return NULL; 450 } 451 452 offset = le16_to_cpu(object->disp_recordoffset) 453 + bp->object_info_tbl_offset; 454 455 for (;;) { 456 header = GET_IMAGE(struct atom_common_record_header, offset); 457 458 if (!header) 459 return NULL; 460 461 if (header->record_type == LAST_RECORD_TYPE || 462 !header->record_size) 463 break; 464 465 if (header->record_type == ATOM_HPD_INT_RECORD_TYPE 466 && sizeof(struct atom_hpd_int_record) <= 467 header->record_size) 468 return (struct atom_hpd_int_record *) header; 469 470 offset += header->record_size; 471 } 472 473 return NULL; 474 } 475 476 /** 477 * bios_parser_get_gpio_pin_info 478 * Get GpioPin information of input gpio id 479 * 480 * @param gpio_id, GPIO ID 481 * @param info, GpioPin information structure 482 * @return Bios parser result code 483 * @note 484 * to get the GPIO PIN INFO, we need: 485 * 1. get the GPIO_ID from other object table, see GetHPDInfo() 486 * 2. in DATA_TABLE.GPIO_Pin_LUT, search all records, 487 * to get the registerA offset/mask 488 */ 489 static enum bp_result bios_parser_get_gpio_pin_info( 490 struct dc_bios *dcb, 491 uint32_t gpio_id, 492 struct gpio_pin_info *info) 493 { 494 struct bios_parser *bp = BP_FROM_DCB(dcb); 495 struct atom_gpio_pin_lut_v2_1 *header; 496 uint32_t count = 0; 497 uint32_t i = 0; 498 499 if (!DATA_TABLES(gpio_pin_lut)) 500 return BP_RESULT_BADBIOSTABLE; 501 502 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1, 503 DATA_TABLES(gpio_pin_lut)); 504 if (!header) 505 return BP_RESULT_BADBIOSTABLE; 506 507 if (sizeof(struct atom_common_table_header) + 508 sizeof(struct atom_gpio_pin_assignment) 509 > le16_to_cpu(header->table_header.structuresize)) 510 return BP_RESULT_BADBIOSTABLE; 511 512 if (header->table_header.content_revision != 1) 513 return BP_RESULT_UNSUPPORTED; 514 515 /* Temporary hard code gpio pin info */ 516 #if defined(FOR_SIMNOW_BOOT) 517 { 518 struct atom_gpio_pin_assignment gpio_pin[8] = { 519 {0x5db5, 0, 0, 1, 0}, 520 {0x5db5, 8, 8, 2, 0}, 521 {0x5db5, 0x10, 0x10, 3, 0}, 522 {0x5db5, 0x18, 0x14, 4, 0}, 523 {0x5db5, 0x1A, 0x18, 5, 0}, 524 {0x5db5, 0x1C, 0x1C, 6, 0}, 525 }; 526 527 count = 6; 528 memmove(header->gpio_pin, gpio_pin, sizeof(gpio_pin)); 529 } 530 #else 531 count = (le16_to_cpu(header->table_header.structuresize) 532 - sizeof(struct atom_common_table_header)) 533 / sizeof(struct atom_gpio_pin_assignment); 534 #endif 535 for (i = 0; i < count; ++i) { 536 if (header->gpio_pin[i].gpio_id != gpio_id) 537 continue; 538 539 info->offset = 540 (uint32_t) le16_to_cpu( 541 header->gpio_pin[i].data_a_reg_index); 542 info->offset_y = info->offset + 2; 543 info->offset_en = info->offset + 1; 544 info->offset_mask = info->offset - 1; 545 546 info->mask = (uint32_t) (1 << 547 header->gpio_pin[i].gpio_bitshift); 548 info->mask_y = info->mask + 2; 549 info->mask_en = info->mask + 1; 550 info->mask_mask = info->mask - 1; 551 552 return BP_RESULT_OK; 553 } 554 555 return BP_RESULT_NORECORD; 556 } 557 558 static struct device_id device_type_from_device_id(uint16_t device_id) 559 { 560 561 struct device_id result_device_id; 562 563 result_device_id.raw_device_tag = device_id; 564 565 switch (device_id) { 566 case ATOM_DISPLAY_LCD1_SUPPORT: 567 result_device_id.device_type = DEVICE_TYPE_LCD; 568 result_device_id.enum_id = 1; 569 break; 570 571 case ATOM_DISPLAY_DFP1_SUPPORT: 572 result_device_id.device_type = DEVICE_TYPE_DFP; 573 result_device_id.enum_id = 1; 574 break; 575 576 case ATOM_DISPLAY_DFP2_SUPPORT: 577 result_device_id.device_type = DEVICE_TYPE_DFP; 578 result_device_id.enum_id = 2; 579 break; 580 581 case ATOM_DISPLAY_DFP3_SUPPORT: 582 result_device_id.device_type = DEVICE_TYPE_DFP; 583 result_device_id.enum_id = 3; 584 break; 585 586 case ATOM_DISPLAY_DFP4_SUPPORT: 587 result_device_id.device_type = DEVICE_TYPE_DFP; 588 result_device_id.enum_id = 4; 589 break; 590 591 case ATOM_DISPLAY_DFP5_SUPPORT: 592 result_device_id.device_type = DEVICE_TYPE_DFP; 593 result_device_id.enum_id = 5; 594 break; 595 596 case ATOM_DISPLAY_DFP6_SUPPORT: 597 result_device_id.device_type = DEVICE_TYPE_DFP; 598 result_device_id.enum_id = 6; 599 break; 600 601 default: 602 BREAK_TO_DEBUGGER(); /* Invalid device Id */ 603 result_device_id.device_type = DEVICE_TYPE_UNKNOWN; 604 result_device_id.enum_id = 0; 605 } 606 return result_device_id; 607 } 608 609 static enum bp_result bios_parser_get_device_tag( 610 struct dc_bios *dcb, 611 struct graphics_object_id connector_object_id, 612 uint32_t device_tag_index, 613 struct connector_device_tag_info *info) 614 { 615 struct bios_parser *bp = BP_FROM_DCB(dcb); 616 struct atom_display_object_path_v2 *object; 617 618 if (!info) 619 return BP_RESULT_BADINPUT; 620 621 /* getBiosObject will return MXM object */ 622 object = get_bios_object(bp, connector_object_id); 623 624 if (!object) { 625 BREAK_TO_DEBUGGER(); /* Invalid object id */ 626 return BP_RESULT_BADINPUT; 627 } 628 629 info->acpi_device = 0; /* BIOS no longer provides this */ 630 info->dev_id = device_type_from_device_id(object->device_tag); 631 632 return BP_RESULT_OK; 633 } 634 635 static enum bp_result get_ss_info_v4_1( 636 struct bios_parser *bp, 637 uint32_t id, 638 uint32_t index, 639 struct spread_spectrum_info *ss_info) 640 { 641 enum bp_result result = BP_RESULT_OK; 642 struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL; 643 struct atom_smu_info_v3_3 *smu_info = NULL; 644 645 if (!ss_info) 646 return BP_RESULT_BADINPUT; 647 648 if (!DATA_TABLES(dce_info)) 649 return BP_RESULT_BADBIOSTABLE; 650 651 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_1, 652 DATA_TABLES(dce_info)); 653 if (!disp_cntl_tbl) 654 return BP_RESULT_BADBIOSTABLE; 655 656 657 ss_info->type.STEP_AND_DELAY_INFO = false; 658 ss_info->spread_percentage_divider = 1000; 659 /* BIOS no longer uses target clock. Always enable for now */ 660 ss_info->target_clock_range = 0xffffffff; 661 662 switch (id) { 663 case AS_SIGNAL_TYPE_DVI: 664 ss_info->spread_spectrum_percentage = 665 disp_cntl_tbl->dvi_ss_percentage; 666 ss_info->spread_spectrum_range = 667 disp_cntl_tbl->dvi_ss_rate_10hz * 10; 668 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 669 ss_info->type.CENTER_MODE = true; 670 break; 671 case AS_SIGNAL_TYPE_HDMI: 672 ss_info->spread_spectrum_percentage = 673 disp_cntl_tbl->hdmi_ss_percentage; 674 ss_info->spread_spectrum_range = 675 disp_cntl_tbl->hdmi_ss_rate_10hz * 10; 676 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 677 ss_info->type.CENTER_MODE = true; 678 break; 679 /* TODO LVDS not support anymore? */ 680 case AS_SIGNAL_TYPE_DISPLAY_PORT: 681 ss_info->spread_spectrum_percentage = 682 disp_cntl_tbl->dp_ss_percentage; 683 ss_info->spread_spectrum_range = 684 disp_cntl_tbl->dp_ss_rate_10hz * 10; 685 if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 686 ss_info->type.CENTER_MODE = true; 687 break; 688 case AS_SIGNAL_TYPE_GPU_PLL: 689 /* atom_firmware: DAL only get data from dce_info table. 690 * if data within smu_info is needed for DAL, VBIOS should 691 * copy it into dce_info 692 */ 693 result = BP_RESULT_UNSUPPORTED; 694 break; 695 case AS_SIGNAL_TYPE_XGMI: 696 smu_info = GET_IMAGE(struct atom_smu_info_v3_3, 697 DATA_TABLES(smu_info)); 698 if (!smu_info) 699 return BP_RESULT_BADBIOSTABLE; 700 701 ss_info->spread_spectrum_percentage = 702 smu_info->waflclk_ss_percentage; 703 ss_info->spread_spectrum_range = 704 smu_info->gpuclk_ss_rate_10hz * 10; 705 if (smu_info->waflclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 706 ss_info->type.CENTER_MODE = true; 707 break; 708 default: 709 result = BP_RESULT_UNSUPPORTED; 710 } 711 712 return result; 713 } 714 715 static enum bp_result get_ss_info_v4_2( 716 struct bios_parser *bp, 717 uint32_t id, 718 uint32_t index, 719 struct spread_spectrum_info *ss_info) 720 { 721 enum bp_result result = BP_RESULT_OK; 722 struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL; 723 struct atom_smu_info_v3_1 *smu_info = NULL; 724 725 if (!ss_info) 726 return BP_RESULT_BADINPUT; 727 728 if (!DATA_TABLES(dce_info)) 729 return BP_RESULT_BADBIOSTABLE; 730 731 if (!DATA_TABLES(smu_info)) 732 return BP_RESULT_BADBIOSTABLE; 733 734 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_2, 735 DATA_TABLES(dce_info)); 736 if (!disp_cntl_tbl) 737 return BP_RESULT_BADBIOSTABLE; 738 739 smu_info = GET_IMAGE(struct atom_smu_info_v3_1, DATA_TABLES(smu_info)); 740 if (!smu_info) 741 return BP_RESULT_BADBIOSTABLE; 742 743 ss_info->type.STEP_AND_DELAY_INFO = false; 744 ss_info->spread_percentage_divider = 1000; 745 /* BIOS no longer uses target clock. Always enable for now */ 746 ss_info->target_clock_range = 0xffffffff; 747 748 switch (id) { 749 case AS_SIGNAL_TYPE_DVI: 750 ss_info->spread_spectrum_percentage = 751 disp_cntl_tbl->dvi_ss_percentage; 752 ss_info->spread_spectrum_range = 753 disp_cntl_tbl->dvi_ss_rate_10hz * 10; 754 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 755 ss_info->type.CENTER_MODE = true; 756 break; 757 case AS_SIGNAL_TYPE_HDMI: 758 ss_info->spread_spectrum_percentage = 759 disp_cntl_tbl->hdmi_ss_percentage; 760 ss_info->spread_spectrum_range = 761 disp_cntl_tbl->hdmi_ss_rate_10hz * 10; 762 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 763 ss_info->type.CENTER_MODE = true; 764 break; 765 /* TODO LVDS not support anymore? */ 766 case AS_SIGNAL_TYPE_DISPLAY_PORT: 767 ss_info->spread_spectrum_percentage = 768 smu_info->gpuclk_ss_percentage; 769 ss_info->spread_spectrum_range = 770 smu_info->gpuclk_ss_rate_10hz * 10; 771 if (smu_info->gpuclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 772 ss_info->type.CENTER_MODE = true; 773 break; 774 case AS_SIGNAL_TYPE_GPU_PLL: 775 /* atom_firmware: DAL only get data from dce_info table. 776 * if data within smu_info is needed for DAL, VBIOS should 777 * copy it into dce_info 778 */ 779 result = BP_RESULT_UNSUPPORTED; 780 break; 781 default: 782 result = BP_RESULT_UNSUPPORTED; 783 } 784 785 return result; 786 } 787 788 /** 789 * bios_parser_get_spread_spectrum_info 790 * Get spread spectrum information from the ASIC_InternalSS_Info(ver 2.1 or 791 * ver 3.1) or SS_Info table from the VBIOS. Currently ASIC_InternalSS_Info 792 * ver 2.1 can co-exist with SS_Info table. Expect ASIC_InternalSS_Info 793 * ver 3.1, 794 * there is only one entry for each signal /ss id. However, there is 795 * no planning of supporting multiple spread Sprectum entry for EverGreen 796 * @param [in] this 797 * @param [in] signal, ASSignalType to be converted to info index 798 * @param [in] index, number of entries that match the converted info index 799 * @param [out] ss_info, sprectrum information structure, 800 * @return Bios parser result code 801 */ 802 static enum bp_result bios_parser_get_spread_spectrum_info( 803 struct dc_bios *dcb, 804 enum as_signal_type signal, 805 uint32_t index, 806 struct spread_spectrum_info *ss_info) 807 { 808 struct bios_parser *bp = BP_FROM_DCB(dcb); 809 enum bp_result result = BP_RESULT_UNSUPPORTED; 810 struct atom_common_table_header *header; 811 struct atom_data_revision tbl_revision; 812 813 if (!ss_info) /* check for bad input */ 814 return BP_RESULT_BADINPUT; 815 816 if (!DATA_TABLES(dce_info)) 817 return BP_RESULT_UNSUPPORTED; 818 819 header = GET_IMAGE(struct atom_common_table_header, 820 DATA_TABLES(dce_info)); 821 get_atom_data_table_revision(header, &tbl_revision); 822 823 switch (tbl_revision.major) { 824 case 4: 825 switch (tbl_revision.minor) { 826 case 1: 827 return get_ss_info_v4_1(bp, signal, index, ss_info); 828 case 2: 829 return get_ss_info_v4_2(bp, signal, index, ss_info); 830 default: 831 break; 832 } 833 break; 834 default: 835 break; 836 } 837 /* there can not be more then one entry for SS Info table */ 838 return result; 839 } 840 841 static enum bp_result get_embedded_panel_info_v2_1( 842 struct bios_parser *bp, 843 struct embedded_panel_info *info) 844 { 845 struct lcd_info_v2_1 *lvds; 846 847 if (!info) 848 return BP_RESULT_BADINPUT; 849 850 if (!DATA_TABLES(lcd_info)) 851 return BP_RESULT_UNSUPPORTED; 852 853 lvds = GET_IMAGE(struct lcd_info_v2_1, DATA_TABLES(lcd_info)); 854 855 if (!lvds) 856 return BP_RESULT_BADBIOSTABLE; 857 858 /* TODO: previous vv1_3, should v2_1 */ 859 if (!((lvds->table_header.format_revision == 2) 860 && (lvds->table_header.content_revision >= 1))) 861 return BP_RESULT_UNSUPPORTED; 862 863 memset(info, 0, sizeof(struct embedded_panel_info)); 864 865 /* We need to convert from 10KHz units into KHz units */ 866 info->lcd_timing.pixel_clk = le16_to_cpu(lvds->lcd_timing.pixclk) * 10; 867 /* usHActive does not include borders, according to VBIOS team */ 868 info->lcd_timing.horizontal_addressable = le16_to_cpu(lvds->lcd_timing.h_active); 869 /* usHBlanking_Time includes borders, so we should really be 870 * subtractingborders duing this translation, but LVDS generally 871 * doesn't have borders, so we should be okay leaving this as is for 872 * now. May need to revisit if we ever have LVDS with borders 873 */ 874 info->lcd_timing.horizontal_blanking_time = le16_to_cpu(lvds->lcd_timing.h_blanking_time); 875 /* usVActive does not include borders, according to VBIOS team*/ 876 info->lcd_timing.vertical_addressable = le16_to_cpu(lvds->lcd_timing.v_active); 877 /* usVBlanking_Time includes borders, so we should really be 878 * subtracting borders duing this translation, but LVDS generally 879 * doesn't have borders, so we should be okay leaving this as is for 880 * now. May need to revisit if we ever have LVDS with borders 881 */ 882 info->lcd_timing.vertical_blanking_time = le16_to_cpu(lvds->lcd_timing.v_blanking_time); 883 info->lcd_timing.horizontal_sync_offset = le16_to_cpu(lvds->lcd_timing.h_sync_offset); 884 info->lcd_timing.horizontal_sync_width = le16_to_cpu(lvds->lcd_timing.h_sync_width); 885 info->lcd_timing.vertical_sync_offset = le16_to_cpu(lvds->lcd_timing.v_sync_offset); 886 info->lcd_timing.vertical_sync_width = le16_to_cpu(lvds->lcd_timing.v_syncwidth); 887 info->lcd_timing.horizontal_border = lvds->lcd_timing.h_border; 888 info->lcd_timing.vertical_border = lvds->lcd_timing.v_border; 889 890 /* not provided by VBIOS */ 891 info->lcd_timing.misc_info.HORIZONTAL_CUT_OFF = 0; 892 893 info->lcd_timing.misc_info.H_SYNC_POLARITY = ~(uint32_t) (lvds->lcd_timing.miscinfo 894 & ATOM_HSYNC_POLARITY); 895 info->lcd_timing.misc_info.V_SYNC_POLARITY = ~(uint32_t) (lvds->lcd_timing.miscinfo 896 & ATOM_VSYNC_POLARITY); 897 898 /* not provided by VBIOS */ 899 info->lcd_timing.misc_info.VERTICAL_CUT_OFF = 0; 900 901 info->lcd_timing.misc_info.H_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo 902 & ATOM_H_REPLICATIONBY2); 903 info->lcd_timing.misc_info.V_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo 904 & ATOM_V_REPLICATIONBY2); 905 info->lcd_timing.misc_info.COMPOSITE_SYNC = !!(lvds->lcd_timing.miscinfo 906 & ATOM_COMPOSITESYNC); 907 info->lcd_timing.misc_info.INTERLACE = !!(lvds->lcd_timing.miscinfo & ATOM_INTERLACE); 908 909 /* not provided by VBIOS*/ 910 info->lcd_timing.misc_info.DOUBLE_CLOCK = 0; 911 /* not provided by VBIOS*/ 912 info->ss_id = 0; 913 914 info->realtek_eDPToLVDS = !!(lvds->dplvdsrxid == eDP_TO_LVDS_REALTEK_ID); 915 916 return BP_RESULT_OK; 917 } 918 919 static enum bp_result bios_parser_get_embedded_panel_info( 920 struct dc_bios *dcb, 921 struct embedded_panel_info *info) 922 { 923 struct bios_parser 924 *bp = BP_FROM_DCB(dcb); 925 struct atom_common_table_header *header; 926 struct atom_data_revision tbl_revision; 927 928 if (!DATA_TABLES(lcd_info)) 929 return BP_RESULT_FAILURE; 930 931 header = GET_IMAGE(struct atom_common_table_header, DATA_TABLES(lcd_info)); 932 933 if (!header) 934 return BP_RESULT_BADBIOSTABLE; 935 936 get_atom_data_table_revision(header, &tbl_revision); 937 938 switch (tbl_revision.major) { 939 case 2: 940 switch (tbl_revision.minor) { 941 case 1: 942 return get_embedded_panel_info_v2_1(bp, info); 943 default: 944 break; 945 } 946 default: 947 break; 948 } 949 950 return BP_RESULT_FAILURE; 951 } 952 953 static uint32_t get_support_mask_for_device_id(struct device_id device_id) 954 { 955 enum dal_device_type device_type = device_id.device_type; 956 uint32_t enum_id = device_id.enum_id; 957 958 switch (device_type) { 959 case DEVICE_TYPE_LCD: 960 switch (enum_id) { 961 case 1: 962 return ATOM_DISPLAY_LCD1_SUPPORT; 963 default: 964 break; 965 } 966 break; 967 case DEVICE_TYPE_DFP: 968 switch (enum_id) { 969 case 1: 970 return ATOM_DISPLAY_DFP1_SUPPORT; 971 case 2: 972 return ATOM_DISPLAY_DFP2_SUPPORT; 973 case 3: 974 return ATOM_DISPLAY_DFP3_SUPPORT; 975 case 4: 976 return ATOM_DISPLAY_DFP4_SUPPORT; 977 case 5: 978 return ATOM_DISPLAY_DFP5_SUPPORT; 979 case 6: 980 return ATOM_DISPLAY_DFP6_SUPPORT; 981 default: 982 break; 983 } 984 break; 985 default: 986 break; 987 }; 988 989 /* Unidentified device ID, return empty support mask. */ 990 return 0; 991 } 992 993 static bool bios_parser_is_device_id_supported( 994 struct dc_bios *dcb, 995 struct device_id id) 996 { 997 struct bios_parser *bp = BP_FROM_DCB(dcb); 998 999 uint32_t mask = get_support_mask_for_device_id(id); 1000 1001 return (le16_to_cpu(bp->object_info_tbl.v1_4->supporteddevices) & 1002 mask) != 0; 1003 } 1004 1005 static uint32_t bios_parser_get_ss_entry_number( 1006 struct dc_bios *dcb, 1007 enum as_signal_type signal) 1008 { 1009 /* TODO: DAL2 atomfirmware implementation does not need this. 1010 * why DAL3 need this? 1011 */ 1012 return 1; 1013 } 1014 1015 static enum bp_result bios_parser_transmitter_control( 1016 struct dc_bios *dcb, 1017 struct bp_transmitter_control *cntl) 1018 { 1019 struct bios_parser *bp = BP_FROM_DCB(dcb); 1020 1021 if (!bp->cmd_tbl.transmitter_control) 1022 return BP_RESULT_FAILURE; 1023 1024 return bp->cmd_tbl.transmitter_control(bp, cntl); 1025 } 1026 1027 static enum bp_result bios_parser_encoder_control( 1028 struct dc_bios *dcb, 1029 struct bp_encoder_control *cntl) 1030 { 1031 struct bios_parser *bp = BP_FROM_DCB(dcb); 1032 1033 if (!bp->cmd_tbl.dig_encoder_control) 1034 return BP_RESULT_FAILURE; 1035 1036 return bp->cmd_tbl.dig_encoder_control(bp, cntl); 1037 } 1038 1039 static enum bp_result bios_parser_set_pixel_clock( 1040 struct dc_bios *dcb, 1041 struct bp_pixel_clock_parameters *bp_params) 1042 { 1043 struct bios_parser *bp = BP_FROM_DCB(dcb); 1044 1045 if (!bp->cmd_tbl.set_pixel_clock) 1046 return BP_RESULT_FAILURE; 1047 1048 return bp->cmd_tbl.set_pixel_clock(bp, bp_params); 1049 } 1050 1051 static enum bp_result bios_parser_set_dce_clock( 1052 struct dc_bios *dcb, 1053 struct bp_set_dce_clock_parameters *bp_params) 1054 { 1055 struct bios_parser *bp = BP_FROM_DCB(dcb); 1056 1057 if (!bp->cmd_tbl.set_dce_clock) 1058 return BP_RESULT_FAILURE; 1059 1060 return bp->cmd_tbl.set_dce_clock(bp, bp_params); 1061 } 1062 1063 static enum bp_result bios_parser_program_crtc_timing( 1064 struct dc_bios *dcb, 1065 struct bp_hw_crtc_timing_parameters *bp_params) 1066 { 1067 struct bios_parser *bp = BP_FROM_DCB(dcb); 1068 1069 if (!bp->cmd_tbl.set_crtc_timing) 1070 return BP_RESULT_FAILURE; 1071 1072 return bp->cmd_tbl.set_crtc_timing(bp, bp_params); 1073 } 1074 1075 static enum bp_result bios_parser_enable_crtc( 1076 struct dc_bios *dcb, 1077 enum controller_id id, 1078 bool enable) 1079 { 1080 struct bios_parser *bp = BP_FROM_DCB(dcb); 1081 1082 if (!bp->cmd_tbl.enable_crtc) 1083 return BP_RESULT_FAILURE; 1084 1085 return bp->cmd_tbl.enable_crtc(bp, id, enable); 1086 } 1087 1088 static enum bp_result bios_parser_enable_disp_power_gating( 1089 struct dc_bios *dcb, 1090 enum controller_id controller_id, 1091 enum bp_pipe_control_action action) 1092 { 1093 struct bios_parser *bp = BP_FROM_DCB(dcb); 1094 1095 if (!bp->cmd_tbl.enable_disp_power_gating) 1096 return BP_RESULT_FAILURE; 1097 1098 return bp->cmd_tbl.enable_disp_power_gating(bp, controller_id, 1099 action); 1100 } 1101 1102 static bool bios_parser_is_accelerated_mode( 1103 struct dc_bios *dcb) 1104 { 1105 return bios_is_accelerated_mode(dcb); 1106 } 1107 1108 /** 1109 * bios_parser_set_scratch_critical_state 1110 * 1111 * @brief 1112 * update critical state bit in VBIOS scratch register 1113 * 1114 * @param 1115 * bool - to set or reset state 1116 */ 1117 static void bios_parser_set_scratch_critical_state( 1118 struct dc_bios *dcb, 1119 bool state) 1120 { 1121 bios_set_scratch_critical_state(dcb, state); 1122 } 1123 1124 static enum bp_result bios_parser_get_firmware_info( 1125 struct dc_bios *dcb, 1126 struct dc_firmware_info *info) 1127 { 1128 struct bios_parser *bp = BP_FROM_DCB(dcb); 1129 enum bp_result result = BP_RESULT_BADBIOSTABLE; 1130 struct atom_common_table_header *header; 1131 1132 struct atom_data_revision revision; 1133 1134 if (info && DATA_TABLES(firmwareinfo)) { 1135 header = GET_IMAGE(struct atom_common_table_header, 1136 DATA_TABLES(firmwareinfo)); 1137 get_atom_data_table_revision(header, &revision); 1138 switch (revision.major) { 1139 case 3: 1140 switch (revision.minor) { 1141 case 1: 1142 result = get_firmware_info_v3_1(bp, info); 1143 break; 1144 case 2: 1145 result = get_firmware_info_v3_2(bp, info); 1146 break; 1147 case 3: 1148 result = get_firmware_info_v3_2(bp, info); 1149 break; 1150 default: 1151 break; 1152 } 1153 break; 1154 default: 1155 break; 1156 } 1157 } 1158 1159 return result; 1160 } 1161 1162 static enum bp_result get_firmware_info_v3_1( 1163 struct bios_parser *bp, 1164 struct dc_firmware_info *info) 1165 { 1166 struct atom_firmware_info_v3_1 *firmware_info; 1167 struct atom_display_controller_info_v4_1 *dce_info = NULL; 1168 1169 if (!info) 1170 return BP_RESULT_BADINPUT; 1171 1172 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_1, 1173 DATA_TABLES(firmwareinfo)); 1174 1175 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1, 1176 DATA_TABLES(dce_info)); 1177 1178 if (!firmware_info || !dce_info) 1179 return BP_RESULT_BADBIOSTABLE; 1180 1181 memset(info, 0, sizeof(*info)); 1182 1183 /* Pixel clock pll information. */ 1184 /* We need to convert from 10KHz units into KHz units */ 1185 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10; 1186 info->default_engine_clk = firmware_info->bootup_sclk_in10khz * 10; 1187 1188 /* 27MHz for Vega10: */ 1189 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10; 1190 1191 /* Hardcode frequency if BIOS gives no DCE Ref Clk */ 1192 if (info->pll_info.crystal_frequency == 0) 1193 info->pll_info.crystal_frequency = 27000; 1194 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/ 1195 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10; 1196 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10; 1197 1198 /* Get GPU PLL VCO Clock */ 1199 1200 if (bp->cmd_tbl.get_smu_clock_info != NULL) { 1201 /* VBIOS gives in 10KHz */ 1202 info->smu_gpu_pll_output_freq = 1203 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10; 1204 } 1205 1206 return BP_RESULT_OK; 1207 } 1208 1209 static enum bp_result get_firmware_info_v3_2( 1210 struct bios_parser *bp, 1211 struct dc_firmware_info *info) 1212 { 1213 struct atom_firmware_info_v3_2 *firmware_info; 1214 struct atom_display_controller_info_v4_1 *dce_info = NULL; 1215 struct atom_common_table_header *header; 1216 struct atom_data_revision revision; 1217 struct atom_smu_info_v3_2 *smu_info_v3_2 = NULL; 1218 struct atom_smu_info_v3_3 *smu_info_v3_3 = NULL; 1219 1220 if (!info) 1221 return BP_RESULT_BADINPUT; 1222 1223 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_2, 1224 DATA_TABLES(firmwareinfo)); 1225 1226 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1, 1227 DATA_TABLES(dce_info)); 1228 1229 if (!firmware_info || !dce_info) 1230 return BP_RESULT_BADBIOSTABLE; 1231 1232 memset(info, 0, sizeof(*info)); 1233 1234 header = GET_IMAGE(struct atom_common_table_header, 1235 DATA_TABLES(smu_info)); 1236 get_atom_data_table_revision(header, &revision); 1237 1238 if (revision.minor == 2) { 1239 /* Vega12 */ 1240 smu_info_v3_2 = GET_IMAGE(struct atom_smu_info_v3_2, 1241 DATA_TABLES(smu_info)); 1242 1243 if (!smu_info_v3_2) 1244 return BP_RESULT_BADBIOSTABLE; 1245 1246 info->default_engine_clk = smu_info_v3_2->bootup_dcefclk_10khz * 10; 1247 } else if (revision.minor == 3) { 1248 /* Vega20 */ 1249 smu_info_v3_3 = GET_IMAGE(struct atom_smu_info_v3_3, 1250 DATA_TABLES(smu_info)); 1251 1252 if (!smu_info_v3_3) 1253 return BP_RESULT_BADBIOSTABLE; 1254 1255 info->default_engine_clk = smu_info_v3_3->bootup_dcefclk_10khz * 10; 1256 } 1257 1258 // We need to convert from 10KHz units into KHz units. 1259 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10; 1260 1261 /* 27MHz for Vega10 & Vega12; 100MHz for Vega20 */ 1262 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10; 1263 /* Hardcode frequency if BIOS gives no DCE Ref Clk */ 1264 if (info->pll_info.crystal_frequency == 0) { 1265 if (revision.minor == 2) 1266 info->pll_info.crystal_frequency = 27000; 1267 else if (revision.minor == 3) 1268 info->pll_info.crystal_frequency = 100000; 1269 } 1270 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/ 1271 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10; 1272 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10; 1273 1274 /* Get GPU PLL VCO Clock */ 1275 if (bp->cmd_tbl.get_smu_clock_info != NULL) { 1276 if (revision.minor == 2) 1277 info->smu_gpu_pll_output_freq = 1278 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10; 1279 else if (revision.minor == 3) 1280 info->smu_gpu_pll_output_freq = 1281 bp->cmd_tbl.get_smu_clock_info(bp, SMU11_SYSPLL3_0_ID) * 10; 1282 } 1283 1284 return BP_RESULT_OK; 1285 } 1286 1287 static enum bp_result bios_parser_get_encoder_cap_info( 1288 struct dc_bios *dcb, 1289 struct graphics_object_id object_id, 1290 struct bp_encoder_cap_info *info) 1291 { 1292 struct bios_parser *bp = BP_FROM_DCB(dcb); 1293 struct atom_display_object_path_v2 *object; 1294 struct atom_encoder_caps_record *record = NULL; 1295 1296 if (!info) 1297 return BP_RESULT_BADINPUT; 1298 1299 object = get_bios_object(bp, object_id); 1300 1301 if (!object) 1302 return BP_RESULT_BADINPUT; 1303 1304 record = get_encoder_cap_record(bp, object); 1305 if (!record) 1306 return BP_RESULT_NORECORD; 1307 1308 info->DP_HBR2_CAP = (record->encodercaps & 1309 ATOM_ENCODER_CAP_RECORD_HBR2) ? 1 : 0; 1310 info->DP_HBR2_EN = (record->encodercaps & 1311 ATOM_ENCODER_CAP_RECORD_HBR2_EN) ? 1 : 0; 1312 info->DP_HBR3_EN = (record->encodercaps & 1313 ATOM_ENCODER_CAP_RECORD_HBR3_EN) ? 1 : 0; 1314 info->HDMI_6GB_EN = (record->encodercaps & 1315 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN) ? 1 : 0; 1316 1317 return BP_RESULT_OK; 1318 } 1319 1320 1321 static struct atom_encoder_caps_record *get_encoder_cap_record( 1322 struct bios_parser *bp, 1323 struct atom_display_object_path_v2 *object) 1324 { 1325 struct atom_common_record_header *header; 1326 uint32_t offset; 1327 1328 if (!object) { 1329 BREAK_TO_DEBUGGER(); /* Invalid object */ 1330 return NULL; 1331 } 1332 1333 offset = object->encoder_recordoffset + bp->object_info_tbl_offset; 1334 1335 for (;;) { 1336 header = GET_IMAGE(struct atom_common_record_header, offset); 1337 1338 if (!header) 1339 return NULL; 1340 1341 offset += header->record_size; 1342 1343 if (header->record_type == LAST_RECORD_TYPE || 1344 !header->record_size) 1345 break; 1346 1347 if (header->record_type != ATOM_ENCODER_CAP_RECORD_TYPE) 1348 continue; 1349 1350 if (sizeof(struct atom_encoder_caps_record) <= 1351 header->record_size) 1352 return (struct atom_encoder_caps_record *)header; 1353 } 1354 1355 return NULL; 1356 } 1357 1358 /* 1359 * get_integrated_info_v11 1360 * 1361 * @brief 1362 * Get V8 integrated BIOS information 1363 * 1364 * @param 1365 * bios_parser *bp - [in]BIOS parser handler to get master data table 1366 * integrated_info *info - [out] store and output integrated info 1367 * 1368 * @return 1369 * enum bp_result - BP_RESULT_OK if information is available, 1370 * BP_RESULT_BADBIOSTABLE otherwise. 1371 */ 1372 static enum bp_result get_integrated_info_v11( 1373 struct bios_parser *bp, 1374 struct integrated_info *info) 1375 { 1376 struct atom_integrated_system_info_v1_11 *info_v11; 1377 uint32_t i; 1378 1379 info_v11 = GET_IMAGE(struct atom_integrated_system_info_v1_11, 1380 DATA_TABLES(integratedsysteminfo)); 1381 1382 if (info_v11 == NULL) 1383 return BP_RESULT_BADBIOSTABLE; 1384 1385 info->gpu_cap_info = 1386 le32_to_cpu(info_v11->gpucapinfo); 1387 /* 1388 * system_config: Bit[0] = 0 : PCIE power gating disabled 1389 * = 1 : PCIE power gating enabled 1390 * Bit[1] = 0 : DDR-PLL shut down disabled 1391 * = 1 : DDR-PLL shut down enabled 1392 * Bit[2] = 0 : DDR-PLL power down disabled 1393 * = 1 : DDR-PLL power down enabled 1394 */ 1395 info->system_config = le32_to_cpu(info_v11->system_config); 1396 info->cpu_cap_info = le32_to_cpu(info_v11->cpucapinfo); 1397 info->memory_type = info_v11->memorytype; 1398 info->ma_channel_number = info_v11->umachannelnumber; 1399 info->lvds_ss_percentage = 1400 le16_to_cpu(info_v11->lvds_ss_percentage); 1401 info->lvds_sspread_rate_in_10hz = 1402 le16_to_cpu(info_v11->lvds_ss_rate_10hz); 1403 info->hdmi_ss_percentage = 1404 le16_to_cpu(info_v11->hdmi_ss_percentage); 1405 info->hdmi_sspread_rate_in_10hz = 1406 le16_to_cpu(info_v11->hdmi_ss_rate_10hz); 1407 info->dvi_ss_percentage = 1408 le16_to_cpu(info_v11->dvi_ss_percentage); 1409 info->dvi_sspread_rate_in_10_hz = 1410 le16_to_cpu(info_v11->dvi_ss_rate_10hz); 1411 info->lvds_misc = info_v11->lvds_misc; 1412 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) { 1413 info->ext_disp_conn_info.gu_id[i] = 1414 info_v11->extdispconninfo.guid[i]; 1415 } 1416 1417 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) { 1418 info->ext_disp_conn_info.path[i].device_connector_id = 1419 object_id_from_bios_object_id( 1420 le16_to_cpu(info_v11->extdispconninfo.path[i].connectorobjid)); 1421 1422 info->ext_disp_conn_info.path[i].ext_encoder_obj_id = 1423 object_id_from_bios_object_id( 1424 le16_to_cpu( 1425 info_v11->extdispconninfo.path[i].ext_encoder_objid)); 1426 1427 info->ext_disp_conn_info.path[i].device_tag = 1428 le16_to_cpu( 1429 info_v11->extdispconninfo.path[i].device_tag); 1430 info->ext_disp_conn_info.path[i].device_acpi_enum = 1431 le16_to_cpu( 1432 info_v11->extdispconninfo.path[i].device_acpi_enum); 1433 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index = 1434 info_v11->extdispconninfo.path[i].auxddclut_index; 1435 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index = 1436 info_v11->extdispconninfo.path[i].hpdlut_index; 1437 info->ext_disp_conn_info.path[i].channel_mapping.raw = 1438 info_v11->extdispconninfo.path[i].channelmapping; 1439 info->ext_disp_conn_info.path[i].caps = 1440 le16_to_cpu(info_v11->extdispconninfo.path[i].caps); 1441 } 1442 info->ext_disp_conn_info.checksum = 1443 info_v11->extdispconninfo.checksum; 1444 1445 info->dp0_ext_hdmi_slv_addr = info_v11->dp0_retimer_set.HdmiSlvAddr; 1446 info->dp0_ext_hdmi_reg_num = info_v11->dp0_retimer_set.HdmiRegNum; 1447 for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) { 1448 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index = 1449 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 1450 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val = 1451 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 1452 } 1453 info->dp0_ext_hdmi_6g_reg_num = info_v11->dp0_retimer_set.Hdmi6GRegNum; 1454 for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) { 1455 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 1456 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 1457 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 1458 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 1459 } 1460 1461 info->dp1_ext_hdmi_slv_addr = info_v11->dp1_retimer_set.HdmiSlvAddr; 1462 info->dp1_ext_hdmi_reg_num = info_v11->dp1_retimer_set.HdmiRegNum; 1463 for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) { 1464 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index = 1465 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 1466 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val = 1467 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 1468 } 1469 info->dp1_ext_hdmi_6g_reg_num = info_v11->dp1_retimer_set.Hdmi6GRegNum; 1470 for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) { 1471 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 1472 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 1473 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 1474 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 1475 } 1476 1477 info->dp2_ext_hdmi_slv_addr = info_v11->dp2_retimer_set.HdmiSlvAddr; 1478 info->dp2_ext_hdmi_reg_num = info_v11->dp2_retimer_set.HdmiRegNum; 1479 for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) { 1480 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index = 1481 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 1482 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val = 1483 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 1484 } 1485 info->dp2_ext_hdmi_6g_reg_num = info_v11->dp2_retimer_set.Hdmi6GRegNum; 1486 for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) { 1487 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 1488 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 1489 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 1490 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 1491 } 1492 1493 info->dp3_ext_hdmi_slv_addr = info_v11->dp3_retimer_set.HdmiSlvAddr; 1494 info->dp3_ext_hdmi_reg_num = info_v11->dp3_retimer_set.HdmiRegNum; 1495 for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) { 1496 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index = 1497 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 1498 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val = 1499 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 1500 } 1501 info->dp3_ext_hdmi_6g_reg_num = info_v11->dp3_retimer_set.Hdmi6GRegNum; 1502 for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) { 1503 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 1504 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 1505 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 1506 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 1507 } 1508 1509 1510 /** TODO - review **/ 1511 #if 0 1512 info->boot_up_engine_clock = le32_to_cpu(info_v11->ulBootUpEngineClock) 1513 * 10; 1514 info->dentist_vco_freq = le32_to_cpu(info_v11->ulDentistVCOFreq) * 10; 1515 info->boot_up_uma_clock = le32_to_cpu(info_v8->ulBootUpUMAClock) * 10; 1516 1517 for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) { 1518 /* Convert [10KHz] into [KHz] */ 1519 info->disp_clk_voltage[i].max_supported_clk = 1520 le32_to_cpu(info_v11->sDISPCLK_Voltage[i]. 1521 ulMaximumSupportedCLK) * 10; 1522 info->disp_clk_voltage[i].voltage_index = 1523 le32_to_cpu(info_v11->sDISPCLK_Voltage[i].ulVoltageIndex); 1524 } 1525 1526 info->boot_up_req_display_vector = 1527 le32_to_cpu(info_v11->ulBootUpReqDisplayVector); 1528 info->boot_up_nb_voltage = 1529 le16_to_cpu(info_v11->usBootUpNBVoltage); 1530 info->ext_disp_conn_info_offset = 1531 le16_to_cpu(info_v11->usExtDispConnInfoOffset); 1532 info->gmc_restore_reset_time = 1533 le32_to_cpu(info_v11->ulGMCRestoreResetTime); 1534 info->minimum_n_clk = 1535 le32_to_cpu(info_v11->ulNbpStateNClkFreq[0]); 1536 for (i = 1; i < 4; ++i) 1537 info->minimum_n_clk = 1538 info->minimum_n_clk < 1539 le32_to_cpu(info_v11->ulNbpStateNClkFreq[i]) ? 1540 info->minimum_n_clk : le32_to_cpu( 1541 info_v11->ulNbpStateNClkFreq[i]); 1542 1543 info->idle_n_clk = le32_to_cpu(info_v11->ulIdleNClk); 1544 info->ddr_dll_power_up_time = 1545 le32_to_cpu(info_v11->ulDDR_DLL_PowerUpTime); 1546 info->ddr_pll_power_up_time = 1547 le32_to_cpu(info_v11->ulDDR_PLL_PowerUpTime); 1548 info->pcie_clk_ss_type = le16_to_cpu(info_v11->usPCIEClkSSType); 1549 info->max_lvds_pclk_freq_in_single_link = 1550 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink); 1551 info->max_lvds_pclk_freq_in_single_link = 1552 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink); 1553 info->lvds_pwr_on_seq_dig_on_to_de_in_4ms = 1554 info_v11->ucLVDSPwrOnSeqDIGONtoDE_in4Ms; 1555 info->lvds_pwr_on_seq_de_to_vary_bl_in_4ms = 1556 info_v11->ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; 1557 info->lvds_pwr_on_seq_vary_bl_to_blon_in_4ms = 1558 info_v11->ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; 1559 info->lvds_pwr_off_seq_vary_bl_to_de_in4ms = 1560 info_v11->ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; 1561 info->lvds_pwr_off_seq_de_to_dig_on_in4ms = 1562 info_v11->ucLVDSPwrOffSeqDEtoDIGON_in4Ms; 1563 info->lvds_pwr_off_seq_blon_to_vary_bl_in_4ms = 1564 info_v11->ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; 1565 info->lvds_off_to_on_delay_in_4ms = 1566 info_v11->ucLVDSOffToOnDelay_in4Ms; 1567 info->lvds_bit_depth_control_val = 1568 le32_to_cpu(info_v11->ulLCDBitDepthControlVal); 1569 1570 for (i = 0; i < NUMBER_OF_AVAILABLE_SCLK; ++i) { 1571 /* Convert [10KHz] into [KHz] */ 1572 info->avail_s_clk[i].supported_s_clk = 1573 le32_to_cpu(info_v11->sAvail_SCLK[i].ulSupportedSCLK) 1574 * 10; 1575 info->avail_s_clk[i].voltage_index = 1576 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageIndex); 1577 info->avail_s_clk[i].voltage_id = 1578 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageID); 1579 } 1580 #endif /* TODO*/ 1581 1582 return BP_RESULT_OK; 1583 } 1584 1585 1586 /* 1587 * construct_integrated_info 1588 * 1589 * @brief 1590 * Get integrated BIOS information based on table revision 1591 * 1592 * @param 1593 * bios_parser *bp - [in]BIOS parser handler to get master data table 1594 * integrated_info *info - [out] store and output integrated info 1595 * 1596 * @return 1597 * enum bp_result - BP_RESULT_OK if information is available, 1598 * BP_RESULT_BADBIOSTABLE otherwise. 1599 */ 1600 static enum bp_result construct_integrated_info( 1601 struct bios_parser *bp, 1602 struct integrated_info *info) 1603 { 1604 enum bp_result result = BP_RESULT_BADBIOSTABLE; 1605 1606 struct atom_common_table_header *header; 1607 struct atom_data_revision revision; 1608 1609 struct clock_voltage_caps temp = {0, 0}; 1610 uint32_t i; 1611 uint32_t j; 1612 1613 if (info && DATA_TABLES(integratedsysteminfo)) { 1614 header = GET_IMAGE(struct atom_common_table_header, 1615 DATA_TABLES(integratedsysteminfo)); 1616 1617 get_atom_data_table_revision(header, &revision); 1618 1619 /* Don't need to check major revision as they are all 1 */ 1620 switch (revision.minor) { 1621 case 11: 1622 result = get_integrated_info_v11(bp, info); 1623 break; 1624 default: 1625 return result; 1626 } 1627 } 1628 1629 if (result != BP_RESULT_OK) 1630 return result; 1631 1632 /* Sort voltage table from low to high*/ 1633 for (i = 1; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) { 1634 for (j = i; j > 0; --j) { 1635 if (info->disp_clk_voltage[j].max_supported_clk < 1636 info->disp_clk_voltage[j-1].max_supported_clk 1637 ) { 1638 /* swap j and j - 1*/ 1639 temp = info->disp_clk_voltage[j-1]; 1640 info->disp_clk_voltage[j-1] = 1641 info->disp_clk_voltage[j]; 1642 info->disp_clk_voltage[j] = temp; 1643 } 1644 } 1645 } 1646 1647 return result; 1648 } 1649 1650 static struct integrated_info *bios_parser_create_integrated_info( 1651 struct dc_bios *dcb) 1652 { 1653 struct bios_parser *bp = BP_FROM_DCB(dcb); 1654 struct integrated_info *info = NULL; 1655 1656 info = kzalloc(sizeof(struct integrated_info), GFP_KERNEL); 1657 1658 if (info == NULL) { 1659 ASSERT_CRITICAL(0); 1660 return NULL; 1661 } 1662 1663 if (construct_integrated_info(bp, info) == BP_RESULT_OK) 1664 return info; 1665 1666 kfree(info); 1667 1668 return NULL; 1669 } 1670 1671 static enum bp_result update_slot_layout_info( 1672 struct dc_bios *dcb, 1673 unsigned int i, 1674 struct slot_layout_info *slot_layout_info) 1675 { 1676 unsigned int record_offset; 1677 unsigned int j; 1678 struct atom_display_object_path_v2 *object; 1679 struct atom_bracket_layout_record *record; 1680 struct atom_common_record_header *record_header; 1681 enum bp_result result; 1682 struct bios_parser *bp; 1683 struct object_info_table *tbl; 1684 struct display_object_info_table_v1_4 *v1_4; 1685 1686 record = NULL; 1687 record_header = NULL; 1688 result = BP_RESULT_NORECORD; 1689 1690 bp = BP_FROM_DCB(dcb); 1691 tbl = &bp->object_info_tbl; 1692 v1_4 = tbl->v1_4; 1693 1694 object = &v1_4->display_path[i]; 1695 record_offset = (unsigned int) 1696 (object->disp_recordoffset) + 1697 (unsigned int)(bp->object_info_tbl_offset); 1698 1699 for (;;) { 1700 1701 record_header = (struct atom_common_record_header *) 1702 GET_IMAGE(struct atom_common_record_header, 1703 record_offset); 1704 if (record_header == NULL) { 1705 result = BP_RESULT_BADBIOSTABLE; 1706 break; 1707 } 1708 1709 /* the end of the list */ 1710 if (record_header->record_type == 0xff || 1711 record_header->record_size == 0) { 1712 break; 1713 } 1714 1715 if (record_header->record_type == 1716 ATOM_BRACKET_LAYOUT_RECORD_TYPE && 1717 sizeof(struct atom_bracket_layout_record) 1718 <= record_header->record_size) { 1719 record = (struct atom_bracket_layout_record *) 1720 (record_header); 1721 result = BP_RESULT_OK; 1722 break; 1723 } 1724 1725 record_offset += record_header->record_size; 1726 } 1727 1728 /* return if the record not found */ 1729 if (result != BP_RESULT_OK) 1730 return result; 1731 1732 /* get slot sizes */ 1733 slot_layout_info->length = record->bracketlen; 1734 slot_layout_info->width = record->bracketwidth; 1735 1736 /* get info for each connector in the slot */ 1737 slot_layout_info->num_of_connectors = record->conn_num; 1738 for (j = 0; j < slot_layout_info->num_of_connectors; ++j) { 1739 slot_layout_info->connectors[j].connector_type = 1740 (enum connector_layout_type) 1741 (record->conn_info[j].connector_type); 1742 switch (record->conn_info[j].connector_type) { 1743 case CONNECTOR_TYPE_DVI_D: 1744 slot_layout_info->connectors[j].connector_type = 1745 CONNECTOR_LAYOUT_TYPE_DVI_D; 1746 slot_layout_info->connectors[j].length = 1747 CONNECTOR_SIZE_DVI; 1748 break; 1749 1750 case CONNECTOR_TYPE_HDMI: 1751 slot_layout_info->connectors[j].connector_type = 1752 CONNECTOR_LAYOUT_TYPE_HDMI; 1753 slot_layout_info->connectors[j].length = 1754 CONNECTOR_SIZE_HDMI; 1755 break; 1756 1757 case CONNECTOR_TYPE_DISPLAY_PORT: 1758 slot_layout_info->connectors[j].connector_type = 1759 CONNECTOR_LAYOUT_TYPE_DP; 1760 slot_layout_info->connectors[j].length = 1761 CONNECTOR_SIZE_DP; 1762 break; 1763 1764 case CONNECTOR_TYPE_MINI_DISPLAY_PORT: 1765 slot_layout_info->connectors[j].connector_type = 1766 CONNECTOR_LAYOUT_TYPE_MINI_DP; 1767 slot_layout_info->connectors[j].length = 1768 CONNECTOR_SIZE_MINI_DP; 1769 break; 1770 1771 default: 1772 slot_layout_info->connectors[j].connector_type = 1773 CONNECTOR_LAYOUT_TYPE_UNKNOWN; 1774 slot_layout_info->connectors[j].length = 1775 CONNECTOR_SIZE_UNKNOWN; 1776 } 1777 1778 slot_layout_info->connectors[j].position = 1779 record->conn_info[j].position; 1780 slot_layout_info->connectors[j].connector_id = 1781 object_id_from_bios_object_id( 1782 record->conn_info[j].connectorobjid); 1783 } 1784 return result; 1785 } 1786 1787 1788 static enum bp_result get_bracket_layout_record( 1789 struct dc_bios *dcb, 1790 unsigned int bracket_layout_id, 1791 struct slot_layout_info *slot_layout_info) 1792 { 1793 unsigned int i; 1794 struct bios_parser *bp = BP_FROM_DCB(dcb); 1795 enum bp_result result; 1796 struct object_info_table *tbl; 1797 struct display_object_info_table_v1_4 *v1_4; 1798 1799 if (slot_layout_info == NULL) { 1800 DC_LOG_DETECTION_EDID_PARSER("Invalid slot_layout_info\n"); 1801 return BP_RESULT_BADINPUT; 1802 } 1803 tbl = &bp->object_info_tbl; 1804 v1_4 = tbl->v1_4; 1805 1806 result = BP_RESULT_NORECORD; 1807 for (i = 0; i < v1_4->number_of_path; ++i) { 1808 1809 if (bracket_layout_id == 1810 v1_4->display_path[i].display_objid) { 1811 result = update_slot_layout_info(dcb, i, 1812 slot_layout_info); 1813 break; 1814 } 1815 } 1816 return result; 1817 } 1818 1819 static enum bp_result bios_get_board_layout_info( 1820 struct dc_bios *dcb, 1821 struct board_layout_info *board_layout_info) 1822 { 1823 unsigned int i; 1824 struct bios_parser *bp; 1825 enum bp_result record_result; 1826 1827 const unsigned int slot_index_to_vbios_id[MAX_BOARD_SLOTS] = { 1828 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1, 1829 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2, 1830 0, 0 1831 }; 1832 1833 bp = BP_FROM_DCB(dcb); 1834 if (board_layout_info == NULL) { 1835 DC_LOG_DETECTION_EDID_PARSER("Invalid board_layout_info\n"); 1836 return BP_RESULT_BADINPUT; 1837 } 1838 1839 board_layout_info->num_of_slots = 0; 1840 1841 for (i = 0; i < MAX_BOARD_SLOTS; ++i) { 1842 record_result = get_bracket_layout_record(dcb, 1843 slot_index_to_vbios_id[i], 1844 &board_layout_info->slots[i]); 1845 1846 if (record_result == BP_RESULT_NORECORD && i > 0) 1847 break; /* no more slots present in bios */ 1848 else if (record_result != BP_RESULT_OK) 1849 return record_result; /* fail */ 1850 1851 ++board_layout_info->num_of_slots; 1852 } 1853 1854 /* all data is valid */ 1855 board_layout_info->is_number_of_slots_valid = 1; 1856 board_layout_info->is_slots_size_valid = 1; 1857 board_layout_info->is_connector_offsets_valid = 1; 1858 board_layout_info->is_connector_lengths_valid = 1; 1859 1860 return BP_RESULT_OK; 1861 } 1862 1863 static const struct dc_vbios_funcs vbios_funcs = { 1864 .get_connectors_number = bios_parser_get_connectors_number, 1865 1866 .get_connector_id = bios_parser_get_connector_id, 1867 1868 .get_src_obj = bios_parser_get_src_obj, 1869 1870 .get_i2c_info = bios_parser_get_i2c_info, 1871 1872 .get_hpd_info = bios_parser_get_hpd_info, 1873 1874 .get_device_tag = bios_parser_get_device_tag, 1875 1876 .get_firmware_info = bios_parser_get_firmware_info, 1877 1878 .get_spread_spectrum_info = bios_parser_get_spread_spectrum_info, 1879 1880 .get_ss_entry_number = bios_parser_get_ss_entry_number, 1881 1882 .get_embedded_panel_info = bios_parser_get_embedded_panel_info, 1883 1884 .get_gpio_pin_info = bios_parser_get_gpio_pin_info, 1885 1886 .get_encoder_cap_info = bios_parser_get_encoder_cap_info, 1887 1888 .is_device_id_supported = bios_parser_is_device_id_supported, 1889 1890 .is_accelerated_mode = bios_parser_is_accelerated_mode, 1891 1892 .set_scratch_critical_state = bios_parser_set_scratch_critical_state, 1893 1894 1895 /* COMMANDS */ 1896 .encoder_control = bios_parser_encoder_control, 1897 1898 .transmitter_control = bios_parser_transmitter_control, 1899 1900 .enable_crtc = bios_parser_enable_crtc, 1901 1902 .set_pixel_clock = bios_parser_set_pixel_clock, 1903 1904 .set_dce_clock = bios_parser_set_dce_clock, 1905 1906 .program_crtc_timing = bios_parser_program_crtc_timing, 1907 1908 .enable_disp_power_gating = bios_parser_enable_disp_power_gating, 1909 1910 .bios_parser_destroy = firmware_parser_destroy, 1911 1912 .get_board_layout_info = bios_get_board_layout_info, 1913 }; 1914 1915 static bool bios_parser_construct( 1916 struct bios_parser *bp, 1917 struct bp_init_data *init, 1918 enum dce_version dce_version) 1919 { 1920 uint16_t *rom_header_offset = NULL; 1921 struct atom_rom_header_v2_2 *rom_header = NULL; 1922 struct display_object_info_table_v1_4 *object_info_tbl; 1923 struct atom_data_revision tbl_rev = {0}; 1924 1925 if (!init) 1926 return false; 1927 1928 if (!init->bios) 1929 return false; 1930 1931 bp->base.funcs = &vbios_funcs; 1932 bp->base.bios = init->bios; 1933 bp->base.bios_size = bp->base.bios[OFFSET_TO_ATOM_ROM_IMAGE_SIZE] * BIOS_IMAGE_SIZE_UNIT; 1934 1935 bp->base.ctx = init->ctx; 1936 1937 bp->base.bios_local_image = NULL; 1938 1939 rom_header_offset = 1940 GET_IMAGE(uint16_t, OFFSET_TO_ATOM_ROM_HEADER_POINTER); 1941 1942 if (!rom_header_offset) 1943 return false; 1944 1945 rom_header = GET_IMAGE(struct atom_rom_header_v2_2, *rom_header_offset); 1946 1947 if (!rom_header) 1948 return false; 1949 1950 get_atom_data_table_revision(&rom_header->table_header, &tbl_rev); 1951 if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 2)) 1952 return false; 1953 1954 bp->master_data_tbl = 1955 GET_IMAGE(struct atom_master_data_table_v2_1, 1956 rom_header->masterdatatable_offset); 1957 1958 if (!bp->master_data_tbl) 1959 return false; 1960 1961 bp->object_info_tbl_offset = DATA_TABLES(displayobjectinfo); 1962 1963 if (!bp->object_info_tbl_offset) 1964 return false; 1965 1966 object_info_tbl = 1967 GET_IMAGE(struct display_object_info_table_v1_4, 1968 bp->object_info_tbl_offset); 1969 1970 if (!object_info_tbl) 1971 return false; 1972 1973 get_atom_data_table_revision(&object_info_tbl->table_header, 1974 &bp->object_info_tbl.revision); 1975 1976 if (bp->object_info_tbl.revision.major == 1 1977 && bp->object_info_tbl.revision.minor >= 4) { 1978 struct display_object_info_table_v1_4 *tbl_v1_4; 1979 1980 tbl_v1_4 = GET_IMAGE(struct display_object_info_table_v1_4, 1981 bp->object_info_tbl_offset); 1982 if (!tbl_v1_4) 1983 return false; 1984 1985 bp->object_info_tbl.v1_4 = tbl_v1_4; 1986 } else 1987 return false; 1988 1989 dal_firmware_parser_init_cmd_tbl(bp); 1990 dal_bios_parser_init_cmd_tbl_helper2(&bp->cmd_helper, dce_version); 1991 1992 bp->base.integrated_info = bios_parser_create_integrated_info(&bp->base); 1993 1994 return true; 1995 } 1996 1997 struct dc_bios *firmware_parser_create( 1998 struct bp_init_data *init, 1999 enum dce_version dce_version) 2000 { 2001 struct bios_parser *bp = NULL; 2002 2003 bp = kzalloc(sizeof(struct bios_parser), GFP_KERNEL); 2004 if (!bp) 2005 return NULL; 2006 2007 if (bios_parser_construct(bp, init, dce_version)) 2008 return &bp->base; 2009 2010 kfree(bp); 2011 return NULL; 2012 } 2013 2014 2015