1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dccg.h" 27 #include "clk_mgr_internal.h" 28 29 #include "dce100/dce_clk_mgr.h" 30 #include "reg_helper.h" 31 #include "core_types.h" 32 #include "dm_helpers.h" 33 34 #include "navi10_ip_offset.h" 35 #include "dcn/dcn_2_0_0_offset.h" 36 #include "dcn/dcn_2_0_0_sh_mask.h" 37 #include "clk/clk_11_0_0_offset.h" 38 #include "clk/clk_11_0_0_sh_mask.h" 39 40 #undef FN 41 #define FN(reg_name, field_name) \ 42 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name 43 44 #define REG(reg) \ 45 (clk_mgr->regs->reg) 46 47 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 48 49 #define BASE(seg) BASE_INNER(seg) 50 51 #define SR(reg_name)\ 52 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 53 mm ## reg_name 54 55 #define CLK_BASE_INNER(seg) \ 56 CLK_BASE__INST0_SEG ## seg 57 58 59 static const struct clk_mgr_registers clk_mgr_regs = { 60 CLK_REG_LIST_NV10() 61 }; 62 63 static const struct clk_mgr_shift clk_mgr_shift = { 64 CLK_MASK_SH_LIST_NV10(__SHIFT) 65 }; 66 67 static const struct clk_mgr_mask clk_mgr_mask = { 68 CLK_MASK_SH_LIST_NV10(_MASK) 69 }; 70 71 uint32_t dentist_get_did_from_divider(int divider) 72 { 73 uint32_t divider_id; 74 75 /* we want to floor here to get higher clock than required rather than lower */ 76 if (divider < DENTIST_DIVIDER_RANGE_2_START) { 77 if (divider < DENTIST_DIVIDER_RANGE_1_START) 78 divider_id = DENTIST_BASE_DID_1; 79 else 80 divider_id = DENTIST_BASE_DID_1 81 + (divider - DENTIST_DIVIDER_RANGE_1_START) 82 / DENTIST_DIVIDER_RANGE_1_STEP; 83 } else if (divider < DENTIST_DIVIDER_RANGE_3_START) { 84 divider_id = DENTIST_BASE_DID_2 85 + (divider - DENTIST_DIVIDER_RANGE_2_START) 86 / DENTIST_DIVIDER_RANGE_2_STEP; 87 } else if (divider < DENTIST_DIVIDER_RANGE_4_START) { 88 divider_id = DENTIST_BASE_DID_3 89 + (divider - DENTIST_DIVIDER_RANGE_3_START) 90 / DENTIST_DIVIDER_RANGE_3_STEP; 91 } else { 92 divider_id = DENTIST_BASE_DID_4 93 + (divider - DENTIST_DIVIDER_RANGE_4_START) 94 / DENTIST_DIVIDER_RANGE_4_STEP; 95 if (divider_id > DENTIST_MAX_DID) 96 divider_id = DENTIST_MAX_DID; 97 } 98 99 return divider_id; 100 } 101 102 void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr, 103 struct dc_state *context) 104 { 105 int i; 106 107 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz; 108 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { 109 int dpp_inst, dppclk_khz; 110 111 /* Loop index will match dpp->inst if resource exists, 112 * and we want to avoid dependency on dpp object 113 */ 114 dpp_inst = i; 115 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz; 116 117 clk_mgr->dccg->funcs->update_dpp_dto( 118 clk_mgr->dccg, dpp_inst, dppclk_khz); 119 } 120 } 121 122 void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr) 123 { 124 int dpp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR 125 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz; 126 int disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR 127 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz; 128 129 uint32_t dppclk_wdivider = dentist_get_did_from_divider(dpp_divider); 130 uint32_t dispclk_wdivider = dentist_get_did_from_divider(disp_divider); 131 132 REG_UPDATE(DENTIST_DISPCLK_CNTL, 133 DENTIST_DISPCLK_WDIVIDER, dispclk_wdivider); 134 // REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 5, 100); 135 REG_UPDATE(DENTIST_DISPCLK_CNTL, 136 DENTIST_DPPCLK_WDIVIDER, dppclk_wdivider); 137 REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, 1, 5, 100); 138 } 139 140 141 void dcn2_update_clocks(struct clk_mgr *clk_mgr_base, 142 struct dc_state *context, 143 bool safe_to_lower) 144 { 145 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 146 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; 147 struct dc *dc = clk_mgr_base->ctx->dc; 148 struct pp_smu_funcs_nv *pp_smu = NULL; 149 int display_count; 150 bool update_dppclk = false; 151 bool update_dispclk = false; 152 bool enter_display_off = false; 153 bool dpp_clock_lowered = false; 154 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu; 155 bool force_reset = false; 156 157 if (dc->work_arounds.skip_clock_update) 158 return; 159 160 if (clk_mgr_base->clks.dispclk_khz == 0 || 161 dc->debug.force_clock_mode & 0x1) { 162 //this is from resume or boot up, if forced_clock cfg option used, we bypass program dispclk and DPPCLK, but need set them for S3. 163 force_reset = true; 164 //force_clock_mode 0x1: force reset the clock even it is the same clock as long as it is in Passive level. 165 } 166 display_count = clk_mgr_helper_get_active_display_cnt(dc, context); 167 if (dc->res_pool->pp_smu) 168 pp_smu = &dc->res_pool->pp_smu->nv_funcs; 169 170 if (display_count == 0) 171 enter_display_off = true; 172 173 if (enter_display_off == safe_to_lower) { 174 if (pp_smu && pp_smu->set_display_count) 175 pp_smu->set_display_count(&pp_smu->pp_smu, display_count); 176 } 177 178 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) { 179 clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz; 180 if (pp_smu && pp_smu->set_voltage_by_freq) 181 pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PHYCLK, clk_mgr_base->clks.phyclk_khz / 1000); 182 } 183 184 185 if (dc->debug.force_min_dcfclk_mhz > 0) 186 new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ? 187 new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000); 188 189 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { 190 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; 191 if (pp_smu && pp_smu->set_hard_min_dcfclk_by_freq) 192 pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.dcfclk_khz / 1000); 193 } 194 195 if (should_set_clock(safe_to_lower, 196 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { 197 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; 198 if (pp_smu && pp_smu->set_min_deep_sleep_dcfclk) 199 pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, clk_mgr_base->clks.dcfclk_deep_sleep_khz / 1000); 200 } 201 202 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz)) { 203 clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz; 204 if (pp_smu && pp_smu->set_hard_min_socclk_by_freq) 205 pp_smu->set_hard_min_socclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.socclk_khz / 1000); 206 } 207 208 if (should_update_pstate_support(safe_to_lower, new_clocks->p_state_change_support, clk_mgr_base->clks.p_state_change_support)) { 209 clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support; 210 clk_mgr_base->clks.p_state_change_support = new_clocks->p_state_change_support; 211 if (pp_smu && pp_smu->set_pstate_handshake_support) 212 pp_smu->set_pstate_handshake_support(&pp_smu->pp_smu, clk_mgr_base->clks.p_state_change_support); 213 } 214 215 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) { 216 clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz; 217 if (pp_smu && pp_smu->set_hard_min_uclk_by_freq) 218 pp_smu->set_hard_min_uclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.dramclk_khz / 1000); 219 } 220 221 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { 222 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz) 223 dpp_clock_lowered = true; 224 clk_mgr->base.clks.dppclk_khz = new_clocks->dppclk_khz; 225 226 if (pp_smu && pp_smu->set_voltage_by_freq) 227 pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PIXELCLK, clk_mgr_base->clks.dppclk_khz / 1000); 228 229 update_dppclk = true; 230 } 231 232 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { 233 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; 234 if (pp_smu && pp_smu->set_voltage_by_freq) 235 pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_DISPCLK, clk_mgr_base->clks.dispclk_khz / 1000); 236 237 update_dispclk = true; 238 } 239 240 if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) { 241 if (dpp_clock_lowered) { 242 // if clock is being lowered, increase DTO before lowering refclk 243 dcn20_update_clocks_update_dpp_dto(clk_mgr, context); 244 dcn20_update_clocks_update_dentist(clk_mgr); 245 } else { 246 // if clock is being raised, increase refclk before lowering DTO 247 if (update_dppclk || update_dispclk) 248 dcn20_update_clocks_update_dentist(clk_mgr); 249 // always update dtos unless clock is lowered and not safe to lower 250 if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz) 251 dcn20_update_clocks_update_dpp_dto(clk_mgr, context); 252 } 253 } 254 255 if (update_dispclk && 256 dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) { 257 /*update dmcu for wait_loop count*/ 258 dmcu->funcs->set_psr_wait_loop(dmcu, 259 clk_mgr_base->clks.dispclk_khz / 1000 / 7); 260 } 261 } 262 263 void dcn2_update_clocks_fpga(struct clk_mgr *clk_mgr, 264 struct dc_state *context, 265 bool safe_to_lower) 266 { 267 struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr); 268 269 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; 270 /* Min fclk = 1.2GHz since all the extra scemi logic seems to run off of it */ 271 int fclk_adj = new_clocks->fclk_khz > 1200000 ? new_clocks->fclk_khz : 1200000; 272 273 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr->clks.phyclk_khz)) { 274 clk_mgr->clks.phyclk_khz = new_clocks->phyclk_khz; 275 } 276 277 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr->clks.dcfclk_khz)) { 278 clk_mgr->clks.dcfclk_khz = new_clocks->dcfclk_khz; 279 } 280 281 if (should_set_clock(safe_to_lower, 282 new_clocks->dcfclk_deep_sleep_khz, clk_mgr->clks.dcfclk_deep_sleep_khz)) { 283 clk_mgr->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; 284 } 285 286 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr->clks.socclk_khz)) { 287 clk_mgr->clks.socclk_khz = new_clocks->socclk_khz; 288 } 289 290 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr->clks.dramclk_khz)) { 291 clk_mgr->clks.dramclk_khz = new_clocks->dramclk_khz; 292 } 293 294 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->clks.dppclk_khz)) { 295 clk_mgr->clks.dppclk_khz = new_clocks->dppclk_khz; 296 } 297 298 if (should_set_clock(safe_to_lower, fclk_adj, clk_mgr->clks.fclk_khz)) { 299 clk_mgr->clks.fclk_khz = fclk_adj; 300 } 301 302 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr->clks.dispclk_khz)) { 303 clk_mgr->clks.dispclk_khz = new_clocks->dispclk_khz; 304 } 305 306 /* Both fclk and ref_dppclk run on the same scemi clock. 307 * So take the higher value since the DPP DTO is typically programmed 308 * such that max dppclk is 1:1 with ref_dppclk. 309 */ 310 if (clk_mgr->clks.fclk_khz > clk_mgr->clks.dppclk_khz) 311 clk_mgr->clks.dppclk_khz = clk_mgr->clks.fclk_khz; 312 if (clk_mgr->clks.dppclk_khz > clk_mgr->clks.fclk_khz) 313 clk_mgr->clks.fclk_khz = clk_mgr->clks.dppclk_khz; 314 315 // Both fclk and ref_dppclk run on the same scemi clock. 316 clk_mgr_int->dccg->ref_dppclk = clk_mgr->clks.fclk_khz; 317 318 dm_set_dcn_clocks(clk_mgr->ctx, &clk_mgr->clks); 319 } 320 321 void dcn2_init_clocks(struct clk_mgr *clk_mgr) 322 { 323 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks)); 324 // Assumption is that boot state always supports pstate 325 clk_mgr->clks.p_state_change_support = true; 326 clk_mgr->clks.prev_p_state_change_support = true; 327 } 328 329 void dcn2_enable_pme_wa(struct clk_mgr *clk_mgr_base) 330 { 331 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 332 struct pp_smu_funcs_nv *pp_smu = NULL; 333 334 if (clk_mgr->pp_smu) { 335 pp_smu = &clk_mgr->pp_smu->nv_funcs; 336 337 if (pp_smu->set_pme_wa_enable) 338 pp_smu->set_pme_wa_enable(&pp_smu->pp_smu); 339 } 340 } 341 342 void dcn2_get_clock(struct clk_mgr *clk_mgr, 343 struct dc_state *context, 344 enum dc_clock_type clock_type, 345 struct dc_clock_config *clock_cfg) 346 { 347 348 if (clock_type == DC_CLOCK_TYPE_DISPCLK) { 349 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz; 350 clock_cfg->min_clock_khz = DCN_MINIMUM_DISPCLK_Khz; 351 clock_cfg->current_clock_khz = clk_mgr->clks.dispclk_khz; 352 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dispclk_khz; 353 } 354 if (clock_type == DC_CLOCK_TYPE_DPPCLK) { 355 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz; 356 clock_cfg->min_clock_khz = DCN_MINIMUM_DPPCLK_Khz; 357 clock_cfg->current_clock_khz = clk_mgr->clks.dppclk_khz; 358 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dppclk_khz; 359 } 360 } 361 362 static bool dcn2_are_clock_states_equal(struct dc_clocks *a, 363 struct dc_clocks *b) 364 { 365 if (a->dispclk_khz != b->dispclk_khz) 366 return false; 367 else if (a->dppclk_khz != b->dppclk_khz) 368 return false; 369 else if (a->dcfclk_khz != b->dcfclk_khz) 370 return false; 371 else if (a->socclk_khz != b->socclk_khz) 372 return false; 373 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz) 374 return false; 375 else if (a->phyclk_khz != b->phyclk_khz) 376 return false; 377 else if (a->dramclk_khz != b->dramclk_khz) 378 return false; 379 else if (a->p_state_change_support != b->p_state_change_support) 380 return false; 381 382 return true; 383 } 384 385 static struct clk_mgr_funcs dcn2_funcs = { 386 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz, 387 .update_clocks = dcn2_update_clocks, 388 .init_clocks = dcn2_init_clocks, 389 .enable_pme_wa = dcn2_enable_pme_wa, 390 .get_clock = dcn2_get_clock, 391 .are_clock_states_equal = dcn2_are_clock_states_equal, 392 }; 393 394 395 void dcn20_clk_mgr_construct( 396 struct dc_context *ctx, 397 struct clk_mgr_internal *clk_mgr, 398 struct pp_smu_funcs *pp_smu, 399 struct dccg *dccg) 400 { 401 clk_mgr->base.ctx = ctx; 402 clk_mgr->pp_smu = pp_smu; 403 clk_mgr->base.funcs = &dcn2_funcs; 404 clk_mgr->regs = &clk_mgr_regs; 405 clk_mgr->clk_mgr_shift = &clk_mgr_shift; 406 clk_mgr->clk_mgr_mask = &clk_mgr_mask; 407 408 clk_mgr->dccg = dccg; 409 clk_mgr->dfs_bypass_disp_clk = 0; 410 411 clk_mgr->dprefclk_ss_percentage = 0; 412 clk_mgr->dprefclk_ss_divider = 1000; 413 clk_mgr->ss_on_dprefclk = false; 414 415 clk_mgr->base.dprefclk_khz = 700000; // 700 MHz planned if VCO is 3.85 GHz, will be retrieved 416 417 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) { 418 dcn2_funcs.update_clocks = dcn2_update_clocks_fpga; 419 clk_mgr->base.dentist_vco_freq_khz = 3850000; 420 421 } else { 422 /* DFS Slice 2 should be used for DPREFCLK */ 423 int dprefclk_did = REG_READ(CLK3_CLK2_DFS_CNTL); 424 /* Convert DPREFCLK DFS Slice DID to actual divider*/ 425 int target_div = dentist_get_divider_from_did(dprefclk_did); 426 427 /* get FbMult value */ 428 uint32_t pll_req_reg = REG_READ(CLK3_CLK_PLL_REQ); 429 struct fixed31_32 pll_req; 430 431 /* set up a fixed-point number 432 * this works because the int part is on the right edge of the register 433 * and the frac part is on the left edge 434 */ 435 436 pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int); 437 pll_req.value |= pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_frac; 438 439 /* multiply by REFCLK period */ 440 pll_req = dc_fixpt_mul_int(pll_req, 100000); 441 442 /* integer part is now VCO frequency in kHz */ 443 clk_mgr->base.dentist_vco_freq_khz = dc_fixpt_floor(pll_req); 444 445 /* in case we don't get a value from the register, use default */ 446 if (clk_mgr->base.dentist_vco_freq_khz == 0) 447 clk_mgr->base.dentist_vco_freq_khz = 3850000; 448 449 /* Calculate the DPREFCLK in kHz.*/ 450 clk_mgr->base.dprefclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR 451 * clk_mgr->base.dentist_vco_freq_khz) / target_div; 452 } 453 //Integrated_info table does not exist on dGPU projects so should not be referenced 454 //anywhere in code for dGPUs. 455 //Also there is no plan for now that DFS BYPASS will be used on NV10/12/14. 456 clk_mgr->dfs_bypass_enabled = false; 457 458 dce_clock_read_ss_info(clk_mgr); 459 } 460 461