1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dccg.h" 27 #include "clk_mgr_internal.h" 28 29 #include "dce100/dce_clk_mgr.h" 30 #include "dcn20_clk_mgr.h" 31 #include "reg_helper.h" 32 #include "core_types.h" 33 #include "dm_helpers.h" 34 35 #include "navi10_ip_offset.h" 36 #include "dcn/dcn_2_0_0_offset.h" 37 #include "dcn/dcn_2_0_0_sh_mask.h" 38 #include "clk/clk_11_0_0_offset.h" 39 #include "clk/clk_11_0_0_sh_mask.h" 40 41 #undef FN 42 #define FN(reg_name, field_name) \ 43 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name 44 45 #define REG(reg) \ 46 (clk_mgr->regs->reg) 47 48 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 49 50 #define BASE(seg) BASE_INNER(seg) 51 52 #define SR(reg_name)\ 53 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 54 mm ## reg_name 55 56 #define CLK_BASE_INNER(seg) \ 57 CLK_BASE__INST0_SEG ## seg 58 59 60 static const struct clk_mgr_registers clk_mgr_regs = { 61 CLK_REG_LIST_NV10() 62 }; 63 64 static const struct clk_mgr_shift clk_mgr_shift = { 65 CLK_MASK_SH_LIST_NV10(__SHIFT) 66 }; 67 68 static const struct clk_mgr_mask clk_mgr_mask = { 69 CLK_MASK_SH_LIST_NV10(_MASK) 70 }; 71 72 uint32_t dentist_get_did_from_divider(int divider) 73 { 74 uint32_t divider_id; 75 76 /* we want to floor here to get higher clock than required rather than lower */ 77 if (divider < DENTIST_DIVIDER_RANGE_2_START) { 78 if (divider < DENTIST_DIVIDER_RANGE_1_START) 79 divider_id = DENTIST_BASE_DID_1; 80 else 81 divider_id = DENTIST_BASE_DID_1 82 + (divider - DENTIST_DIVIDER_RANGE_1_START) 83 / DENTIST_DIVIDER_RANGE_1_STEP; 84 } else if (divider < DENTIST_DIVIDER_RANGE_3_START) { 85 divider_id = DENTIST_BASE_DID_2 86 + (divider - DENTIST_DIVIDER_RANGE_2_START) 87 / DENTIST_DIVIDER_RANGE_2_STEP; 88 } else if (divider < DENTIST_DIVIDER_RANGE_4_START) { 89 divider_id = DENTIST_BASE_DID_3 90 + (divider - DENTIST_DIVIDER_RANGE_3_START) 91 / DENTIST_DIVIDER_RANGE_3_STEP; 92 } else { 93 divider_id = DENTIST_BASE_DID_4 94 + (divider - DENTIST_DIVIDER_RANGE_4_START) 95 / DENTIST_DIVIDER_RANGE_4_STEP; 96 if (divider_id > DENTIST_MAX_DID) 97 divider_id = DENTIST_MAX_DID; 98 } 99 100 return divider_id; 101 } 102 103 void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr, 104 struct dc_state *context, bool safe_to_lower) 105 { 106 int i; 107 108 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz; 109 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { 110 int dpp_inst, dppclk_khz, prev_dppclk_khz; 111 112 /* Loop index will match dpp->inst if resource exists, 113 * and we want to avoid dependency on dpp object 114 */ 115 dpp_inst = i; 116 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz; 117 118 prev_dppclk_khz = clk_mgr->base.ctx->dc->current_state->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz; 119 120 if ((prev_dppclk_khz > dppclk_khz && safe_to_lower) || prev_dppclk_khz < dppclk_khz) { 121 clk_mgr->dccg->funcs->update_dpp_dto( 122 clk_mgr->dccg, dpp_inst, dppclk_khz); 123 } 124 } 125 } 126 127 void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr) 128 { 129 int dpp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR 130 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz; 131 int disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR 132 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz; 133 134 uint32_t dppclk_wdivider = dentist_get_did_from_divider(dpp_divider); 135 uint32_t dispclk_wdivider = dentist_get_did_from_divider(disp_divider); 136 137 REG_UPDATE(DENTIST_DISPCLK_CNTL, 138 DENTIST_DISPCLK_WDIVIDER, dispclk_wdivider); 139 // REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 5, 100); 140 REG_UPDATE(DENTIST_DISPCLK_CNTL, 141 DENTIST_DPPCLK_WDIVIDER, dppclk_wdivider); 142 REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, 1, 5, 100); 143 } 144 145 146 void dcn2_update_clocks(struct clk_mgr *clk_mgr_base, 147 struct dc_state *context, 148 bool safe_to_lower) 149 { 150 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 151 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; 152 struct dc *dc = clk_mgr_base->ctx->dc; 153 struct pp_smu_funcs_nv *pp_smu = NULL; 154 int display_count; 155 bool update_dppclk = false; 156 bool update_dispclk = false; 157 bool enter_display_off = false; 158 bool dpp_clock_lowered = false; 159 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu; 160 bool force_reset = false; 161 162 if (dc->work_arounds.skip_clock_update) 163 return; 164 165 if (clk_mgr_base->clks.dispclk_khz == 0 || 166 dc->debug.force_clock_mode & 0x1) { 167 //this is from resume or boot up, if forced_clock cfg option used, we bypass program dispclk and DPPCLK, but need set them for S3. 168 force_reset = true; 169 170 dcn2_read_clocks_from_hw_dentist(clk_mgr_base); 171 172 //force_clock_mode 0x1: force reset the clock even it is the same clock as long as it is in Passive level. 173 } 174 display_count = clk_mgr_helper_get_active_display_cnt(dc, context); 175 if (dc->res_pool->pp_smu) 176 pp_smu = &dc->res_pool->pp_smu->nv_funcs; 177 178 if (display_count == 0) 179 enter_display_off = true; 180 181 if (enter_display_off == safe_to_lower) { 182 if (pp_smu && pp_smu->set_display_count) 183 pp_smu->set_display_count(&pp_smu->pp_smu, display_count); 184 } 185 186 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) { 187 clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz; 188 if (pp_smu && pp_smu->set_voltage_by_freq) 189 pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PHYCLK, clk_mgr_base->clks.phyclk_khz / 1000); 190 } 191 192 193 if (dc->debug.force_min_dcfclk_mhz > 0) 194 new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ? 195 new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000); 196 197 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { 198 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; 199 if (pp_smu && pp_smu->set_hard_min_dcfclk_by_freq) 200 pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.dcfclk_khz / 1000); 201 } 202 203 if (should_set_clock(safe_to_lower, 204 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { 205 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; 206 if (pp_smu && pp_smu->set_min_deep_sleep_dcfclk) 207 pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, clk_mgr_base->clks.dcfclk_deep_sleep_khz / 1000); 208 } 209 210 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz)) { 211 clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz; 212 if (pp_smu && pp_smu->set_hard_min_socclk_by_freq) 213 pp_smu->set_hard_min_socclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.socclk_khz / 1000); 214 } 215 216 if (should_update_pstate_support(safe_to_lower, new_clocks->p_state_change_support, clk_mgr_base->clks.p_state_change_support)) { 217 clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support; 218 clk_mgr_base->clks.p_state_change_support = new_clocks->p_state_change_support; 219 if (pp_smu && pp_smu->set_pstate_handshake_support) 220 pp_smu->set_pstate_handshake_support(&pp_smu->pp_smu, clk_mgr_base->clks.p_state_change_support); 221 } 222 223 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) { 224 clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz; 225 if (pp_smu && pp_smu->set_hard_min_uclk_by_freq) 226 pp_smu->set_hard_min_uclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.dramclk_khz / 1000); 227 } 228 229 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { 230 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz) 231 dpp_clock_lowered = true; 232 clk_mgr->base.clks.dppclk_khz = new_clocks->dppclk_khz; 233 234 if (pp_smu && pp_smu->set_voltage_by_freq) 235 pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PIXELCLK, clk_mgr_base->clks.dppclk_khz / 1000); 236 237 update_dppclk = true; 238 } 239 240 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { 241 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; 242 if (pp_smu && pp_smu->set_voltage_by_freq) 243 pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_DISPCLK, clk_mgr_base->clks.dispclk_khz / 1000); 244 245 update_dispclk = true; 246 } 247 248 if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) { 249 if (dpp_clock_lowered) { 250 // if clock is being lowered, increase DTO before lowering refclk 251 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); 252 dcn20_update_clocks_update_dentist(clk_mgr); 253 } else { 254 // if clock is being raised, increase refclk before lowering DTO 255 if (update_dppclk || update_dispclk) 256 dcn20_update_clocks_update_dentist(clk_mgr); 257 // always update dtos unless clock is lowered and not safe to lower 258 if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz) 259 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); 260 } 261 } 262 263 if (update_dispclk && 264 dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) { 265 /*update dmcu for wait_loop count*/ 266 dmcu->funcs->set_psr_wait_loop(dmcu, 267 clk_mgr_base->clks.dispclk_khz / 1000 / 7); 268 } 269 } 270 271 void dcn2_update_clocks_fpga(struct clk_mgr *clk_mgr, 272 struct dc_state *context, 273 bool safe_to_lower) 274 { 275 struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr); 276 277 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; 278 /* Min fclk = 1.2GHz since all the extra scemi logic seems to run off of it */ 279 int fclk_adj = new_clocks->fclk_khz > 1200000 ? new_clocks->fclk_khz : 1200000; 280 281 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr->clks.phyclk_khz)) { 282 clk_mgr->clks.phyclk_khz = new_clocks->phyclk_khz; 283 } 284 285 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr->clks.dcfclk_khz)) { 286 clk_mgr->clks.dcfclk_khz = new_clocks->dcfclk_khz; 287 } 288 289 if (should_set_clock(safe_to_lower, 290 new_clocks->dcfclk_deep_sleep_khz, clk_mgr->clks.dcfclk_deep_sleep_khz)) { 291 clk_mgr->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; 292 } 293 294 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr->clks.socclk_khz)) { 295 clk_mgr->clks.socclk_khz = new_clocks->socclk_khz; 296 } 297 298 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr->clks.dramclk_khz)) { 299 clk_mgr->clks.dramclk_khz = new_clocks->dramclk_khz; 300 } 301 302 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->clks.dppclk_khz)) { 303 clk_mgr->clks.dppclk_khz = new_clocks->dppclk_khz; 304 } 305 306 if (should_set_clock(safe_to_lower, fclk_adj, clk_mgr->clks.fclk_khz)) { 307 clk_mgr->clks.fclk_khz = fclk_adj; 308 } 309 310 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr->clks.dispclk_khz)) { 311 clk_mgr->clks.dispclk_khz = new_clocks->dispclk_khz; 312 } 313 314 /* Both fclk and ref_dppclk run on the same scemi clock. 315 * So take the higher value since the DPP DTO is typically programmed 316 * such that max dppclk is 1:1 with ref_dppclk. 317 */ 318 if (clk_mgr->clks.fclk_khz > clk_mgr->clks.dppclk_khz) 319 clk_mgr->clks.dppclk_khz = clk_mgr->clks.fclk_khz; 320 if (clk_mgr->clks.dppclk_khz > clk_mgr->clks.fclk_khz) 321 clk_mgr->clks.fclk_khz = clk_mgr->clks.dppclk_khz; 322 323 // Both fclk and ref_dppclk run on the same scemi clock. 324 clk_mgr_int->dccg->ref_dppclk = clk_mgr->clks.fclk_khz; 325 326 dm_set_dcn_clocks(clk_mgr->ctx, &clk_mgr->clks); 327 } 328 329 void dcn2_init_clocks(struct clk_mgr *clk_mgr) 330 { 331 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks)); 332 // Assumption is that boot state always supports pstate 333 clk_mgr->clks.p_state_change_support = true; 334 clk_mgr->clks.prev_p_state_change_support = true; 335 } 336 337 void dcn2_enable_pme_wa(struct clk_mgr *clk_mgr_base) 338 { 339 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 340 struct pp_smu_funcs_nv *pp_smu = NULL; 341 342 if (clk_mgr->pp_smu) { 343 pp_smu = &clk_mgr->pp_smu->nv_funcs; 344 345 if (pp_smu->set_pme_wa_enable) 346 pp_smu->set_pme_wa_enable(&pp_smu->pp_smu); 347 } 348 } 349 350 351 void dcn2_read_clocks_from_hw_dentist(struct clk_mgr *clk_mgr_base) 352 { 353 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 354 uint32_t dispclk_wdivider; 355 uint32_t dppclk_wdivider; 356 int disp_divider; 357 int dpp_divider; 358 359 REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, &dispclk_wdivider); 360 REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, &dppclk_wdivider); 361 362 disp_divider = dentist_get_divider_from_did(dispclk_wdivider); 363 dpp_divider = dentist_get_divider_from_did(dispclk_wdivider); 364 365 if (disp_divider && dpp_divider) { 366 /* Calculate the current DFS clock, in kHz.*/ 367 clk_mgr_base->clks.dispclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR 368 * clk_mgr->base.dentist_vco_freq_khz) / disp_divider; 369 370 clk_mgr_base->clks.dppclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR 371 * clk_mgr->base.dentist_vco_freq_khz) / dpp_divider; 372 } 373 374 } 375 376 void dcn2_get_clock(struct clk_mgr *clk_mgr, 377 struct dc_state *context, 378 enum dc_clock_type clock_type, 379 struct dc_clock_config *clock_cfg) 380 { 381 382 if (clock_type == DC_CLOCK_TYPE_DISPCLK) { 383 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz; 384 clock_cfg->min_clock_khz = DCN_MINIMUM_DISPCLK_Khz; 385 clock_cfg->current_clock_khz = clk_mgr->clks.dispclk_khz; 386 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dispclk_khz; 387 } 388 if (clock_type == DC_CLOCK_TYPE_DPPCLK) { 389 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz; 390 clock_cfg->min_clock_khz = DCN_MINIMUM_DPPCLK_Khz; 391 clock_cfg->current_clock_khz = clk_mgr->clks.dppclk_khz; 392 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dppclk_khz; 393 } 394 } 395 396 static bool dcn2_are_clock_states_equal(struct dc_clocks *a, 397 struct dc_clocks *b) 398 { 399 if (a->dispclk_khz != b->dispclk_khz) 400 return false; 401 else if (a->dppclk_khz != b->dppclk_khz) 402 return false; 403 else if (a->dcfclk_khz != b->dcfclk_khz) 404 return false; 405 else if (a->socclk_khz != b->socclk_khz) 406 return false; 407 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz) 408 return false; 409 else if (a->phyclk_khz != b->phyclk_khz) 410 return false; 411 else if (a->dramclk_khz != b->dramclk_khz) 412 return false; 413 else if (a->p_state_change_support != b->p_state_change_support) 414 return false; 415 416 return true; 417 } 418 419 static struct clk_mgr_funcs dcn2_funcs = { 420 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz, 421 .update_clocks = dcn2_update_clocks, 422 .init_clocks = dcn2_init_clocks, 423 .enable_pme_wa = dcn2_enable_pme_wa, 424 .get_clock = dcn2_get_clock, 425 .are_clock_states_equal = dcn2_are_clock_states_equal, 426 }; 427 428 429 void dcn20_clk_mgr_construct( 430 struct dc_context *ctx, 431 struct clk_mgr_internal *clk_mgr, 432 struct pp_smu_funcs *pp_smu, 433 struct dccg *dccg) 434 { 435 clk_mgr->base.ctx = ctx; 436 clk_mgr->pp_smu = pp_smu; 437 clk_mgr->base.funcs = &dcn2_funcs; 438 clk_mgr->regs = &clk_mgr_regs; 439 clk_mgr->clk_mgr_shift = &clk_mgr_shift; 440 clk_mgr->clk_mgr_mask = &clk_mgr_mask; 441 442 clk_mgr->dccg = dccg; 443 clk_mgr->dfs_bypass_disp_clk = 0; 444 445 clk_mgr->dprefclk_ss_percentage = 0; 446 clk_mgr->dprefclk_ss_divider = 1000; 447 clk_mgr->ss_on_dprefclk = false; 448 449 clk_mgr->base.dprefclk_khz = 700000; // 700 MHz planned if VCO is 3.85 GHz, will be retrieved 450 451 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) { 452 dcn2_funcs.update_clocks = dcn2_update_clocks_fpga; 453 clk_mgr->base.dentist_vco_freq_khz = 3850000; 454 455 } else { 456 /* DFS Slice 2 should be used for DPREFCLK */ 457 int dprefclk_did = REG_READ(CLK3_CLK2_DFS_CNTL); 458 /* Convert DPREFCLK DFS Slice DID to actual divider*/ 459 int target_div = dentist_get_divider_from_did(dprefclk_did); 460 461 /* get FbMult value */ 462 uint32_t pll_req_reg = REG_READ(CLK3_CLK_PLL_REQ); 463 struct fixed31_32 pll_req; 464 465 /* set up a fixed-point number 466 * this works because the int part is on the right edge of the register 467 * and the frac part is on the left edge 468 */ 469 470 pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int); 471 pll_req.value |= pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_frac; 472 473 /* multiply by REFCLK period */ 474 pll_req = dc_fixpt_mul_int(pll_req, 100000); 475 476 /* integer part is now VCO frequency in kHz */ 477 clk_mgr->base.dentist_vco_freq_khz = dc_fixpt_floor(pll_req); 478 479 /* in case we don't get a value from the register, use default */ 480 if (clk_mgr->base.dentist_vco_freq_khz == 0) 481 clk_mgr->base.dentist_vco_freq_khz = 3850000; 482 483 /* Calculate the DPREFCLK in kHz.*/ 484 clk_mgr->base.dprefclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR 485 * clk_mgr->base.dentist_vco_freq_khz) / target_div; 486 } 487 //Integrated_info table does not exist on dGPU projects so should not be referenced 488 //anywhere in code for dGPUs. 489 //Also there is no plan for now that DFS BYPASS will be used on NV10/12/14. 490 clk_mgr->dfs_bypass_enabled = false; 491 492 dce_clock_read_ss_info(clk_mgr); 493 } 494 495