1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dccg.h" 27 #include "clk_mgr_internal.h" 28 29 30 #include "dcn20/dcn20_clk_mgr.h" 31 #include "rn_clk_mgr.h" 32 33 34 #include "dce100/dce_clk_mgr.h" 35 #include "rn_clk_mgr_vbios_smu.h" 36 #include "reg_helper.h" 37 #include "core_types.h" 38 #include "dm_helpers.h" 39 40 #include "atomfirmware.h" 41 #include "clk/clk_10_0_2_offset.h" 42 #include "clk/clk_10_0_2_sh_mask.h" 43 #include "renoir_ip_offset.h" 44 45 46 /* Constants */ 47 48 #define LPDDR_MEM_RETRAIN_LATENCY 4.977 /* Number obtained from LPDDR4 Training Counter Requirement doc */ 49 #define SMU_VER_55_51_0 0x373300 /* SMU Version that is able to set DISPCLK below 100MHz */ 50 51 /* Macros */ 52 53 #define REG(reg_name) \ 54 (CLK_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name) 55 56 57 /* TODO: evaluate how to lower or disable all dcn clocks in screen off case */ 58 static int rn_get_active_display_cnt_wa(struct dc *dc, struct dc_state *context) 59 { 60 int i, display_count; 61 bool tmds_present = false; 62 63 display_count = 0; 64 for (i = 0; i < context->stream_count; i++) { 65 const struct dc_stream_state *stream = context->streams[i]; 66 67 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A || 68 stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK || 69 stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) 70 tmds_present = true; 71 } 72 73 for (i = 0; i < dc->link_count; i++) { 74 const struct dc_link *link = dc->links[i]; 75 76 /* abusing the fact that the dig and phy are coupled to see if the phy is enabled */ 77 if (link->link_enc->funcs->is_dig_enabled && 78 link->link_enc->funcs->is_dig_enabled(link->link_enc)) 79 display_count++; 80 } 81 82 /* WA for hang on HDMI after display off back back on*/ 83 if (display_count == 0 && tmds_present) 84 display_count = 1; 85 86 return display_count; 87 } 88 89 static void rn_set_low_power_state(struct clk_mgr *clk_mgr_base) 90 { 91 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 92 93 rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_LOW_POWER); 94 /* update power state */ 95 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; 96 } 97 98 static void rn_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr, 99 struct dc_state *context, int ref_dpp_clk, bool safe_to_lower) 100 { 101 int i; 102 103 clk_mgr->dccg->ref_dppclk = ref_dpp_clk; 104 105 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { 106 int dpp_inst, dppclk_khz, prev_dppclk_khz; 107 108 /* Loop index may not match dpp->inst if some pipes disabled, 109 * so select correct inst from res_pool 110 */ 111 dpp_inst = clk_mgr->base.ctx->dc->res_pool->dpps[i]->inst; 112 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz; 113 114 prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i]; 115 116 if (safe_to_lower || prev_dppclk_khz < dppclk_khz) 117 clk_mgr->dccg->funcs->update_dpp_dto( 118 clk_mgr->dccg, dpp_inst, dppclk_khz); 119 } 120 } 121 122 123 static void rn_update_clocks(struct clk_mgr *clk_mgr_base, 124 struct dc_state *context, 125 bool safe_to_lower) 126 { 127 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 128 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; 129 struct dc *dc = clk_mgr_base->ctx->dc; 130 int display_count; 131 bool update_dppclk = false; 132 bool update_dispclk = false; 133 bool dpp_clock_lowered = false; 134 135 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu; 136 137 if (dc->work_arounds.skip_clock_update) 138 return; 139 140 /* 141 * if it is safe to lower, but we are already in the lower state, we don't have to do anything 142 * also if safe to lower is false, we just go in the higher state 143 */ 144 if (safe_to_lower && !dc->debug.disable_48mhz_pwrdwn) { 145 /* check that we're not already in lower */ 146 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { 147 148 display_count = rn_get_active_display_cnt_wa(dc, context); 149 150 /* if we can go lower, go lower */ 151 if (display_count == 0) { 152 rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_LOW_POWER); 153 /* update power state */ 154 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; 155 } 156 } 157 } else { 158 /* check that we're not already in D0 */ 159 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) { 160 rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_MISSION_MODE); 161 /* update power state */ 162 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE; 163 } 164 } 165 166 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { 167 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; 168 rn_vbios_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz); 169 } 170 171 if (should_set_clock(safe_to_lower, 172 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { 173 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; 174 rn_vbios_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz); 175 } 176 177 // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow. 178 // Do not adjust dppclk if dppclk is 0 to avoid unexpected result 179 if (new_clocks->dppclk_khz < 100000 && new_clocks->dppclk_khz > 0) 180 new_clocks->dppclk_khz = 100000; 181 182 /* 183 * Temporally ignore thew 0 cases for disp and dpp clks. 184 * We may have a new feature that requires 0 clks in the future. 185 */ 186 if (new_clocks->dppclk_khz == 0 || new_clocks->dispclk_khz == 0) { 187 new_clocks->dppclk_khz = clk_mgr_base->clks.dppclk_khz; 188 new_clocks->dispclk_khz = clk_mgr_base->clks.dispclk_khz; 189 } 190 191 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) { 192 if (clk_mgr_base->clks.dppclk_khz > new_clocks->dppclk_khz) 193 dpp_clock_lowered = true; 194 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz; 195 update_dppclk = true; 196 } 197 198 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { 199 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; 200 clk_mgr_base->clks.actual_dispclk_khz = rn_vbios_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz); 201 202 update_dispclk = true; 203 } 204 205 if (dpp_clock_lowered) { 206 // increase per DPP DTO before lowering global dppclk with requested dppclk 207 rn_update_clocks_update_dpp_dto( 208 clk_mgr, 209 context, 210 clk_mgr_base->clks.dppclk_khz, 211 safe_to_lower); 212 213 clk_mgr_base->clks.actual_dppclk_khz = 214 rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz); 215 216 //update dpp dto with actual dpp clk. 217 rn_update_clocks_update_dpp_dto( 218 clk_mgr, 219 context, 220 clk_mgr_base->clks.actual_dppclk_khz, 221 safe_to_lower); 222 223 } else { 224 // increase global DPPCLK before lowering per DPP DTO 225 if (update_dppclk || update_dispclk) 226 clk_mgr_base->clks.actual_dppclk_khz = 227 rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz); 228 229 // always update dtos unless clock is lowered and not safe to lower 230 rn_update_clocks_update_dpp_dto( 231 clk_mgr, 232 context, 233 clk_mgr_base->clks.actual_dppclk_khz, 234 safe_to_lower); 235 } 236 237 if (update_dispclk && 238 dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) { 239 /*update dmcu for wait_loop count*/ 240 dmcu->funcs->set_psr_wait_loop(dmcu, 241 clk_mgr_base->clks.dispclk_khz / 1000 / 7); 242 } 243 } 244 245 static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr) 246 { 247 /* get FbMult value */ 248 struct fixed31_32 pll_req; 249 unsigned int fbmult_frac_val = 0; 250 unsigned int fbmult_int_val = 0; 251 252 253 /* 254 * Register value of fbmult is in 8.16 format, we are converting to 31.32 255 * to leverage the fix point operations available in driver 256 */ 257 258 REG_GET(CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/ 259 REG_GET(CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */ 260 261 pll_req = dc_fixpt_from_int(fbmult_int_val); 262 263 /* 264 * since fractional part is only 16 bit in register definition but is 32 bit 265 * in our fix point definiton, need to shift left by 16 to obtain correct value 266 */ 267 pll_req.value |= fbmult_frac_val << 16; 268 269 /* multiply by REFCLK period */ 270 pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz); 271 272 /* integer part is now VCO frequency in kHz */ 273 return dc_fixpt_floor(pll_req); 274 } 275 276 static void rn_dump_clk_registers_internal(struct rn_clk_internal *internal, struct clk_mgr *clk_mgr_base) 277 { 278 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 279 280 internal->CLK1_CLK3_CURRENT_CNT = REG_READ(CLK1_CLK3_CURRENT_CNT); 281 internal->CLK1_CLK3_BYPASS_CNTL = REG_READ(CLK1_CLK3_BYPASS_CNTL); 282 283 internal->CLK1_CLK3_DS_CNTL = REG_READ(CLK1_CLK3_DS_CNTL); //dcf deep sleep divider 284 internal->CLK1_CLK3_ALLOW_DS = REG_READ(CLK1_CLK3_ALLOW_DS); 285 286 internal->CLK1_CLK1_CURRENT_CNT = REG_READ(CLK1_CLK1_CURRENT_CNT); 287 internal->CLK1_CLK1_BYPASS_CNTL = REG_READ(CLK1_CLK1_BYPASS_CNTL); 288 289 internal->CLK1_CLK2_CURRENT_CNT = REG_READ(CLK1_CLK2_CURRENT_CNT); 290 internal->CLK1_CLK2_BYPASS_CNTL = REG_READ(CLK1_CLK2_BYPASS_CNTL); 291 292 internal->CLK1_CLK0_CURRENT_CNT = REG_READ(CLK1_CLK0_CURRENT_CNT); 293 internal->CLK1_CLK0_BYPASS_CNTL = REG_READ(CLK1_CLK0_BYPASS_CNTL); 294 } 295 296 /* This function collect raw clk register values */ 297 static void rn_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass, 298 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info) 299 { 300 struct rn_clk_internal internal = {0}; 301 char *bypass_clks[5] = {"0x0 DFS", "0x1 REFCLK", "0x2 ERROR", "0x3 400 FCH", "0x4 600 FCH"}; 302 unsigned int chars_printed = 0; 303 unsigned int remaining_buffer = log_info->bufSize; 304 305 rn_dump_clk_registers_internal(&internal, clk_mgr_base); 306 307 regs_and_bypass->dcfclk = internal.CLK1_CLK3_CURRENT_CNT / 10; 308 regs_and_bypass->dcf_deep_sleep_divider = internal.CLK1_CLK3_DS_CNTL / 10; 309 regs_and_bypass->dcf_deep_sleep_allow = internal.CLK1_CLK3_ALLOW_DS; 310 regs_and_bypass->dprefclk = internal.CLK1_CLK2_CURRENT_CNT / 10; 311 regs_and_bypass->dispclk = internal.CLK1_CLK0_CURRENT_CNT / 10; 312 regs_and_bypass->dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10; 313 314 regs_and_bypass->dppclk_bypass = internal.CLK1_CLK1_BYPASS_CNTL & 0x0007; 315 if (regs_and_bypass->dppclk_bypass < 0 || regs_and_bypass->dppclk_bypass > 4) 316 regs_and_bypass->dppclk_bypass = 0; 317 regs_and_bypass->dcfclk_bypass = internal.CLK1_CLK3_BYPASS_CNTL & 0x0007; 318 if (regs_and_bypass->dcfclk_bypass < 0 || regs_and_bypass->dcfclk_bypass > 4) 319 regs_and_bypass->dcfclk_bypass = 0; 320 regs_and_bypass->dispclk_bypass = internal.CLK1_CLK0_BYPASS_CNTL & 0x0007; 321 if (regs_and_bypass->dispclk_bypass < 0 || regs_and_bypass->dispclk_bypass > 4) 322 regs_and_bypass->dispclk_bypass = 0; 323 regs_and_bypass->dprefclk_bypass = internal.CLK1_CLK2_BYPASS_CNTL & 0x0007; 324 if (regs_and_bypass->dprefclk_bypass < 0 || regs_and_bypass->dprefclk_bypass > 4) 325 regs_and_bypass->dprefclk_bypass = 0; 326 327 if (log_info->enabled) { 328 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "clk_type,clk_value,deepsleep_cntl,deepsleep_allow,bypass\n"); 329 remaining_buffer -= chars_printed; 330 *log_info->sum_chars_printed += chars_printed; 331 log_info->pBuf += chars_printed; 332 333 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dcfclk,%d,%d,%d,%s\n", 334 regs_and_bypass->dcfclk, 335 regs_and_bypass->dcf_deep_sleep_divider, 336 regs_and_bypass->dcf_deep_sleep_allow, 337 bypass_clks[(int) regs_and_bypass->dcfclk_bypass]); 338 remaining_buffer -= chars_printed; 339 *log_info->sum_chars_printed += chars_printed; 340 log_info->pBuf += chars_printed; 341 342 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dprefclk,%d,N/A,N/A,%s\n", 343 regs_and_bypass->dprefclk, 344 bypass_clks[(int) regs_and_bypass->dprefclk_bypass]); 345 remaining_buffer -= chars_printed; 346 *log_info->sum_chars_printed += chars_printed; 347 log_info->pBuf += chars_printed; 348 349 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dispclk,%d,N/A,N/A,%s\n", 350 regs_and_bypass->dispclk, 351 bypass_clks[(int) regs_and_bypass->dispclk_bypass]); 352 remaining_buffer -= chars_printed; 353 *log_info->sum_chars_printed += chars_printed; 354 log_info->pBuf += chars_printed; 355 356 //split 357 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "SPLIT\n"); 358 remaining_buffer -= chars_printed; 359 *log_info->sum_chars_printed += chars_printed; 360 log_info->pBuf += chars_printed; 361 362 // REGISTER VALUES 363 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "reg_name,value,clk_type\n"); 364 remaining_buffer -= chars_printed; 365 *log_info->sum_chars_printed += chars_printed; 366 log_info->pBuf += chars_printed; 367 368 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_CURRENT_CNT,%d,dcfclk\n", 369 internal.CLK1_CLK3_CURRENT_CNT); 370 remaining_buffer -= chars_printed; 371 *log_info->sum_chars_printed += chars_printed; 372 log_info->pBuf += chars_printed; 373 374 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_DS_CNTL,%d,dcf_deep_sleep_divider\n", 375 internal.CLK1_CLK3_DS_CNTL); 376 remaining_buffer -= chars_printed; 377 *log_info->sum_chars_printed += chars_printed; 378 log_info->pBuf += chars_printed; 379 380 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_ALLOW_DS,%d,dcf_deep_sleep_allow\n", 381 internal.CLK1_CLK3_ALLOW_DS); 382 remaining_buffer -= chars_printed; 383 *log_info->sum_chars_printed += chars_printed; 384 log_info->pBuf += chars_printed; 385 386 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK2_CURRENT_CNT,%d,dprefclk\n", 387 internal.CLK1_CLK2_CURRENT_CNT); 388 remaining_buffer -= chars_printed; 389 *log_info->sum_chars_printed += chars_printed; 390 log_info->pBuf += chars_printed; 391 392 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK0_CURRENT_CNT,%d,dispclk\n", 393 internal.CLK1_CLK0_CURRENT_CNT); 394 remaining_buffer -= chars_printed; 395 *log_info->sum_chars_printed += chars_printed; 396 log_info->pBuf += chars_printed; 397 398 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK1_CURRENT_CNT,%d,dppclk\n", 399 internal.CLK1_CLK1_CURRENT_CNT); 400 remaining_buffer -= chars_printed; 401 *log_info->sum_chars_printed += chars_printed; 402 log_info->pBuf += chars_printed; 403 404 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_BYPASS_CNTL,%d,dcfclk_bypass\n", 405 internal.CLK1_CLK3_BYPASS_CNTL); 406 remaining_buffer -= chars_printed; 407 *log_info->sum_chars_printed += chars_printed; 408 log_info->pBuf += chars_printed; 409 410 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK2_BYPASS_CNTL,%d,dprefclk_bypass\n", 411 internal.CLK1_CLK2_BYPASS_CNTL); 412 remaining_buffer -= chars_printed; 413 *log_info->sum_chars_printed += chars_printed; 414 log_info->pBuf += chars_printed; 415 416 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK0_BYPASS_CNTL,%d,dispclk_bypass\n", 417 internal.CLK1_CLK0_BYPASS_CNTL); 418 remaining_buffer -= chars_printed; 419 *log_info->sum_chars_printed += chars_printed; 420 log_info->pBuf += chars_printed; 421 422 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK1_BYPASS_CNTL,%d,dppclk_bypass\n", 423 internal.CLK1_CLK1_BYPASS_CNTL); 424 remaining_buffer -= chars_printed; 425 *log_info->sum_chars_printed += chars_printed; 426 log_info->pBuf += chars_printed; 427 } 428 } 429 430 static void rn_enable_pme_wa(struct clk_mgr *clk_mgr_base) 431 { 432 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 433 434 rn_vbios_smu_enable_pme_wa(clk_mgr); 435 } 436 437 static void rn_init_clocks(struct clk_mgr *clk_mgr) 438 { 439 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks)); 440 // Assumption is that boot state always supports pstate 441 clk_mgr->clks.p_state_change_support = true; 442 clk_mgr->clks.prev_p_state_change_support = true; 443 clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN; 444 } 445 446 static void build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_smu_wm_range_sets *ranges) 447 { 448 int i, num_valid_sets; 449 450 num_valid_sets = 0; 451 452 for (i = 0; i < WM_SET_COUNT; i++) { 453 /* skip empty entries, the smu array has no holes*/ 454 if (!bw_params->wm_table.entries[i].valid) 455 continue; 456 457 ranges->reader_wm_sets[num_valid_sets].wm_inst = bw_params->wm_table.entries[i].wm_inst; 458 ranges->reader_wm_sets[num_valid_sets].wm_type = bw_params->wm_table.entries[i].wm_type; 459 /* We will not select WM based on fclk, so leave it as unconstrained */ 460 ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 461 ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 462 /* dcfclk wil be used to select WM*/ 463 464 if (ranges->reader_wm_sets[num_valid_sets].wm_type == WM_TYPE_PSTATE_CHG) { 465 if (i == 0) 466 ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = 0; 467 else { 468 /* add 1 to make it non-overlapping with next lvl */ 469 ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; 470 } 471 ranges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; 472 473 } else { 474 /* unconstrained for memory retraining */ 475 ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 476 ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 477 478 /* Modify previous watermark range to cover up to max */ 479 ranges->reader_wm_sets[num_valid_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 480 } 481 num_valid_sets++; 482 } 483 484 ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */ 485 ranges->num_reader_wm_sets = num_valid_sets; 486 487 /* modify the min and max to make sure we cover the whole range*/ 488 ranges->reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 489 ranges->reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 490 ranges->reader_wm_sets[ranges->num_reader_wm_sets - 1].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 491 ranges->reader_wm_sets[ranges->num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 492 493 /* This is for writeback only, does not matter currently as no writeback support*/ 494 ranges->num_writer_wm_sets = 1; 495 ranges->writer_wm_sets[0].wm_inst = WM_A; 496 ranges->writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 497 ranges->writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 498 ranges->writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 499 ranges->writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 500 501 } 502 503 static void rn_notify_wm_ranges(struct clk_mgr *clk_mgr_base) 504 { 505 struct dc_debug_options *debug = &clk_mgr_base->ctx->dc->debug; 506 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 507 struct pp_smu_funcs *pp_smu = clk_mgr->pp_smu; 508 509 if (!debug->disable_pplib_wm_range) { 510 build_watermark_ranges(clk_mgr_base->bw_params, &clk_mgr_base->ranges); 511 512 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */ 513 if (pp_smu && pp_smu->rn_funcs.set_wm_ranges) 514 pp_smu->rn_funcs.set_wm_ranges(&pp_smu->rn_funcs.pp_smu, &clk_mgr_base->ranges); 515 } 516 517 } 518 519 static bool rn_are_clock_states_equal(struct dc_clocks *a, 520 struct dc_clocks *b) 521 { 522 if (a->dispclk_khz != b->dispclk_khz) 523 return false; 524 else if (a->dppclk_khz != b->dppclk_khz) 525 return false; 526 else if (a->dcfclk_khz != b->dcfclk_khz) 527 return false; 528 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz) 529 return false; 530 531 return true; 532 } 533 534 535 /* Notify clk_mgr of a change in link rate, update phyclk frequency if necessary */ 536 static void rn_notify_link_rate_change(struct clk_mgr *clk_mgr_base, struct dc_link *link) 537 { 538 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 539 unsigned int i, max_phyclk_req = 0; 540 541 clk_mgr->cur_phyclk_req_table[link->link_index] = link->cur_link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ; 542 543 for (i = 0; i < MAX_PIPES * 2; i++) { 544 if (clk_mgr->cur_phyclk_req_table[i] > max_phyclk_req) 545 max_phyclk_req = clk_mgr->cur_phyclk_req_table[i]; 546 } 547 548 if (max_phyclk_req != clk_mgr_base->clks.phyclk_khz) { 549 clk_mgr_base->clks.phyclk_khz = max_phyclk_req; 550 rn_vbios_smu_set_phyclk(clk_mgr, clk_mgr_base->clks.phyclk_khz); 551 } 552 } 553 554 static struct clk_mgr_funcs dcn21_funcs = { 555 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz, 556 .update_clocks = rn_update_clocks, 557 .init_clocks = rn_init_clocks, 558 .enable_pme_wa = rn_enable_pme_wa, 559 .are_clock_states_equal = rn_are_clock_states_equal, 560 .set_low_power_state = rn_set_low_power_state, 561 .notify_wm_ranges = rn_notify_wm_ranges, 562 .notify_link_rate_change = rn_notify_link_rate_change, 563 }; 564 565 static struct clk_bw_params rn_bw_params = { 566 .vram_type = Ddr4MemType, 567 .num_channels = 1, 568 .clk_table = { 569 .entries = { 570 { 571 .voltage = 0, 572 .dcfclk_mhz = 400, 573 .fclk_mhz = 400, 574 .memclk_mhz = 800, 575 .socclk_mhz = 0, 576 }, 577 { 578 .voltage = 0, 579 .dcfclk_mhz = 483, 580 .fclk_mhz = 800, 581 .memclk_mhz = 1600, 582 .socclk_mhz = 0, 583 }, 584 { 585 .voltage = 0, 586 .dcfclk_mhz = 602, 587 .fclk_mhz = 1067, 588 .memclk_mhz = 1067, 589 .socclk_mhz = 0, 590 }, 591 { 592 .voltage = 0, 593 .dcfclk_mhz = 738, 594 .fclk_mhz = 1333, 595 .memclk_mhz = 1600, 596 .socclk_mhz = 0, 597 }, 598 }, 599 600 .num_entries = 4, 601 }, 602 603 }; 604 605 static struct wm_table ddr4_wm_table_gs = { 606 .entries = { 607 { 608 .wm_inst = WM_A, 609 .wm_type = WM_TYPE_PSTATE_CHG, 610 .pstate_latency_us = 11.72, 611 .sr_exit_time_us = 7.09, 612 .sr_enter_plus_exit_time_us = 8.14, 613 .valid = true, 614 }, 615 { 616 .wm_inst = WM_B, 617 .wm_type = WM_TYPE_PSTATE_CHG, 618 .pstate_latency_us = 11.72, 619 .sr_exit_time_us = 10.12, 620 .sr_enter_plus_exit_time_us = 11.48, 621 .valid = true, 622 }, 623 { 624 .wm_inst = WM_C, 625 .wm_type = WM_TYPE_PSTATE_CHG, 626 .pstate_latency_us = 11.72, 627 .sr_exit_time_us = 10.12, 628 .sr_enter_plus_exit_time_us = 11.48, 629 .valid = true, 630 }, 631 { 632 .wm_inst = WM_D, 633 .wm_type = WM_TYPE_PSTATE_CHG, 634 .pstate_latency_us = 11.72, 635 .sr_exit_time_us = 10.12, 636 .sr_enter_plus_exit_time_us = 11.48, 637 .valid = true, 638 }, 639 } 640 }; 641 642 static struct wm_table lpddr4_wm_table_gs = { 643 .entries = { 644 { 645 .wm_inst = WM_A, 646 .wm_type = WM_TYPE_PSTATE_CHG, 647 .pstate_latency_us = 11.65333, 648 .sr_exit_time_us = 5.32, 649 .sr_enter_plus_exit_time_us = 6.38, 650 .valid = true, 651 }, 652 { 653 .wm_inst = WM_B, 654 .wm_type = WM_TYPE_PSTATE_CHG, 655 .pstate_latency_us = 11.65333, 656 .sr_exit_time_us = 9.82, 657 .sr_enter_plus_exit_time_us = 11.196, 658 .valid = true, 659 }, 660 { 661 .wm_inst = WM_C, 662 .wm_type = WM_TYPE_PSTATE_CHG, 663 .pstate_latency_us = 11.65333, 664 .sr_exit_time_us = 9.89, 665 .sr_enter_plus_exit_time_us = 11.24, 666 .valid = true, 667 }, 668 { 669 .wm_inst = WM_D, 670 .wm_type = WM_TYPE_PSTATE_CHG, 671 .pstate_latency_us = 11.65333, 672 .sr_exit_time_us = 9.748, 673 .sr_enter_plus_exit_time_us = 11.102, 674 .valid = true, 675 }, 676 } 677 }; 678 679 static struct wm_table lpddr4_wm_table_with_disabled_ppt = { 680 .entries = { 681 { 682 .wm_inst = WM_A, 683 .wm_type = WM_TYPE_PSTATE_CHG, 684 .pstate_latency_us = 11.65333, 685 .sr_exit_time_us = 8.32, 686 .sr_enter_plus_exit_time_us = 9.38, 687 .valid = true, 688 }, 689 { 690 .wm_inst = WM_B, 691 .wm_type = WM_TYPE_PSTATE_CHG, 692 .pstate_latency_us = 11.65333, 693 .sr_exit_time_us = 9.82, 694 .sr_enter_plus_exit_time_us = 11.196, 695 .valid = true, 696 }, 697 { 698 .wm_inst = WM_C, 699 .wm_type = WM_TYPE_PSTATE_CHG, 700 .pstate_latency_us = 11.65333, 701 .sr_exit_time_us = 9.89, 702 .sr_enter_plus_exit_time_us = 11.24, 703 .valid = true, 704 }, 705 { 706 .wm_inst = WM_D, 707 .wm_type = WM_TYPE_PSTATE_CHG, 708 .pstate_latency_us = 11.65333, 709 .sr_exit_time_us = 9.748, 710 .sr_enter_plus_exit_time_us = 11.102, 711 .valid = true, 712 }, 713 } 714 }; 715 716 static struct wm_table ddr4_wm_table_rn = { 717 .entries = { 718 { 719 .wm_inst = WM_A, 720 .wm_type = WM_TYPE_PSTATE_CHG, 721 .pstate_latency_us = 11.72, 722 .sr_exit_time_us = 11.90, 723 .sr_enter_plus_exit_time_us = 12.80, 724 .valid = true, 725 }, 726 { 727 .wm_inst = WM_B, 728 .wm_type = WM_TYPE_PSTATE_CHG, 729 .pstate_latency_us = 11.72, 730 .sr_exit_time_us = 13.18, 731 .sr_enter_plus_exit_time_us = 14.30, 732 .valid = true, 733 }, 734 { 735 .wm_inst = WM_C, 736 .wm_type = WM_TYPE_PSTATE_CHG, 737 .pstate_latency_us = 11.72, 738 .sr_exit_time_us = 13.18, 739 .sr_enter_plus_exit_time_us = 14.30, 740 .valid = true, 741 }, 742 { 743 .wm_inst = WM_D, 744 .wm_type = WM_TYPE_PSTATE_CHG, 745 .pstate_latency_us = 11.72, 746 .sr_exit_time_us = 13.18, 747 .sr_enter_plus_exit_time_us = 14.30, 748 .valid = true, 749 }, 750 } 751 }; 752 753 static struct wm_table ddr4_1R_wm_table_rn = { 754 .entries = { 755 { 756 .wm_inst = WM_A, 757 .wm_type = WM_TYPE_PSTATE_CHG, 758 .pstate_latency_us = 11.72, 759 .sr_exit_time_us = 13.90, 760 .sr_enter_plus_exit_time_us = 14.80, 761 .valid = true, 762 }, 763 { 764 .wm_inst = WM_B, 765 .wm_type = WM_TYPE_PSTATE_CHG, 766 .pstate_latency_us = 11.72, 767 .sr_exit_time_us = 13.90, 768 .sr_enter_plus_exit_time_us = 14.80, 769 .valid = true, 770 }, 771 { 772 .wm_inst = WM_C, 773 .wm_type = WM_TYPE_PSTATE_CHG, 774 .pstate_latency_us = 11.72, 775 .sr_exit_time_us = 13.90, 776 .sr_enter_plus_exit_time_us = 14.80, 777 .valid = true, 778 }, 779 { 780 .wm_inst = WM_D, 781 .wm_type = WM_TYPE_PSTATE_CHG, 782 .pstate_latency_us = 11.72, 783 .sr_exit_time_us = 13.90, 784 .sr_enter_plus_exit_time_us = 14.80, 785 .valid = true, 786 }, 787 } 788 }; 789 790 static struct wm_table lpddr4_wm_table_rn = { 791 .entries = { 792 { 793 .wm_inst = WM_A, 794 .wm_type = WM_TYPE_PSTATE_CHG, 795 .pstate_latency_us = 11.65333, 796 .sr_exit_time_us = 7.32, 797 .sr_enter_plus_exit_time_us = 8.38, 798 .valid = true, 799 }, 800 { 801 .wm_inst = WM_B, 802 .wm_type = WM_TYPE_PSTATE_CHG, 803 .pstate_latency_us = 11.65333, 804 .sr_exit_time_us = 9.82, 805 .sr_enter_plus_exit_time_us = 11.196, 806 .valid = true, 807 }, 808 { 809 .wm_inst = WM_C, 810 .wm_type = WM_TYPE_PSTATE_CHG, 811 .pstate_latency_us = 11.65333, 812 .sr_exit_time_us = 9.89, 813 .sr_enter_plus_exit_time_us = 11.24, 814 .valid = true, 815 }, 816 { 817 .wm_inst = WM_D, 818 .wm_type = WM_TYPE_PSTATE_CHG, 819 .pstate_latency_us = 11.65333, 820 .sr_exit_time_us = 9.748, 821 .sr_enter_plus_exit_time_us = 11.102, 822 .valid = true, 823 }, 824 } 825 }; 826 827 static unsigned int find_socclk_for_voltage(struct dpm_clocks *clock_table, unsigned int voltage) 828 { 829 int i; 830 831 for (i = 0; i < PP_SMU_NUM_SOCCLK_DPM_LEVELS; i++) { 832 if (clock_table->SocClocks[i].Vol == voltage) 833 return clock_table->SocClocks[i].Freq; 834 } 835 836 ASSERT(0); 837 return 0; 838 } 839 840 static unsigned int find_dcfclk_for_voltage(struct dpm_clocks *clock_table, unsigned int voltage) 841 { 842 int i; 843 844 for (i = 0; i < PP_SMU_NUM_DCFCLK_DPM_LEVELS; i++) { 845 if (clock_table->DcfClocks[i].Vol == voltage) 846 return clock_table->DcfClocks[i].Freq; 847 } 848 849 ASSERT(0); 850 return 0; 851 } 852 853 static void rn_clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params, struct dpm_clocks *clock_table, struct integrated_info *bios_info) 854 { 855 int i, j = 0; 856 857 j = -1; 858 859 ASSERT(PP_SMU_NUM_FCLK_DPM_LEVELS <= MAX_NUM_DPM_LVL); 860 861 /* Find lowest DPM, FCLK is filled in reverse order*/ 862 863 for (i = PP_SMU_NUM_FCLK_DPM_LEVELS - 1; i >= 0; i--) { 864 if (clock_table->FClocks[i].Freq != 0 && clock_table->FClocks[i].Vol != 0) { 865 j = i; 866 break; 867 } 868 } 869 870 if (j == -1) { 871 /* clock table is all 0s, just use our own hardcode */ 872 ASSERT(0); 873 return; 874 } 875 876 bw_params->clk_table.num_entries = j + 1; 877 878 for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) { 879 bw_params->clk_table.entries[i].fclk_mhz = clock_table->FClocks[j].Freq; 880 bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemClocks[j].Freq; 881 bw_params->clk_table.entries[i].voltage = clock_table->FClocks[j].Vol; 882 bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->FClocks[j].Vol); 883 bw_params->clk_table.entries[i].socclk_mhz = find_socclk_for_voltage(clock_table, 884 bw_params->clk_table.entries[i].voltage); 885 } 886 887 bw_params->vram_type = bios_info->memory_type; 888 bw_params->num_channels = bios_info->ma_channel_number; 889 890 for (i = 0; i < WM_SET_COUNT; i++) { 891 bw_params->wm_table.entries[i].wm_inst = i; 892 893 if (i >= bw_params->clk_table.num_entries) { 894 bw_params->wm_table.entries[i].valid = false; 895 continue; 896 } 897 898 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; 899 bw_params->wm_table.entries[i].valid = true; 900 } 901 902 if (bw_params->vram_type == LpDdr4MemType) { 903 /* 904 * WM set D will be re-purposed for memory retraining 905 */ 906 bw_params->wm_table.entries[WM_D].pstate_latency_us = LPDDR_MEM_RETRAIN_LATENCY; 907 bw_params->wm_table.entries[WM_D].wm_inst = WM_D; 908 bw_params->wm_table.entries[WM_D].wm_type = WM_TYPE_RETRAINING; 909 bw_params->wm_table.entries[WM_D].valid = true; 910 } 911 912 } 913 914 void rn_clk_mgr_construct( 915 struct dc_context *ctx, 916 struct clk_mgr_internal *clk_mgr, 917 struct pp_smu_funcs *pp_smu, 918 struct dccg *dccg) 919 { 920 struct dc_debug_options *debug = &ctx->dc->debug; 921 struct dpm_clocks clock_table = { 0 }; 922 enum pp_smu_status status = 0; 923 int is_green_sardine = 0; 924 925 #if defined(CONFIG_DRM_AMD_DC_DCN) 926 is_green_sardine = ASICREV_IS_GREEN_SARDINE(ctx->asic_id.hw_internal_rev); 927 #endif 928 929 clk_mgr->base.ctx = ctx; 930 clk_mgr->base.funcs = &dcn21_funcs; 931 932 clk_mgr->pp_smu = pp_smu; 933 934 clk_mgr->dccg = dccg; 935 clk_mgr->dfs_bypass_disp_clk = 0; 936 937 clk_mgr->dprefclk_ss_percentage = 0; 938 clk_mgr->dprefclk_ss_divider = 1000; 939 clk_mgr->ss_on_dprefclk = false; 940 clk_mgr->dfs_ref_freq_khz = 48000; 941 942 clk_mgr->smu_ver = rn_vbios_smu_get_smu_version(clk_mgr); 943 944 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) { 945 dcn21_funcs.update_clocks = dcn2_update_clocks_fpga; 946 clk_mgr->base.dentist_vco_freq_khz = 3600000; 947 } else { 948 struct clk_log_info log_info = {0}; 949 950 clk_mgr->periodic_retraining_disabled = rn_vbios_smu_is_periodic_retraining_disabled(clk_mgr); 951 952 /* SMU Version 55.51.0 and up no longer have an issue 953 * that needs to limit minimum dispclk */ 954 if (clk_mgr->smu_ver >= SMU_VER_55_51_0) 955 debug->min_disp_clk_khz = 0; 956 957 /* TODO: Check we get what we expect during bringup */ 958 clk_mgr->base.dentist_vco_freq_khz = get_vco_frequency_from_reg(clk_mgr); 959 960 /* in case we don't get a value from the register, use default */ 961 if (clk_mgr->base.dentist_vco_freq_khz == 0) 962 clk_mgr->base.dentist_vco_freq_khz = 3600000; 963 964 if (ctx->dc_bios->integrated_info->memory_type == LpDdr4MemType) { 965 if (clk_mgr->periodic_retraining_disabled) { 966 rn_bw_params.wm_table = lpddr4_wm_table_with_disabled_ppt; 967 } else { 968 if (is_green_sardine) 969 rn_bw_params.wm_table = lpddr4_wm_table_gs; 970 else 971 rn_bw_params.wm_table = lpddr4_wm_table_rn; 972 } 973 } else { 974 if (is_green_sardine) 975 rn_bw_params.wm_table = ddr4_wm_table_gs; 976 else { 977 if (ctx->dc->config.is_single_rank_dimm) 978 rn_bw_params.wm_table = ddr4_1R_wm_table_rn; 979 else 980 rn_bw_params.wm_table = ddr4_wm_table_rn; 981 } 982 } 983 /* Saved clocks configured at boot for debug purposes */ 984 rn_dump_clk_registers(&clk_mgr->base.boot_snapshot, &clk_mgr->base, &log_info); 985 } 986 987 clk_mgr->base.dprefclk_khz = 600000; 988 dce_clock_read_ss_info(clk_mgr); 989 990 991 clk_mgr->base.bw_params = &rn_bw_params; 992 993 if (pp_smu && pp_smu->rn_funcs.get_dpm_clock_table) { 994 status = pp_smu->rn_funcs.get_dpm_clock_table(&pp_smu->rn_funcs.pp_smu, &clock_table); 995 996 if (status == PP_SMU_RESULT_OK && 997 ctx->dc_bios && ctx->dc_bios->integrated_info) { 998 rn_clk_mgr_helper_populate_bw_params (clk_mgr->base.bw_params, &clock_table, ctx->dc_bios->integrated_info); 999 /* treat memory config as single channel if memory is asymmetrics. */ 1000 if (ctx->dc->config.is_asymmetric_memory) 1001 clk_mgr->base.bw_params->num_channels = 1; 1002 } 1003 } 1004 1005 if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment) && clk_mgr->smu_ver >= 0x00371500) { 1006 /* enable powerfeatures when displaycount goes to 0 */ 1007 rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(clk_mgr, !debug->disable_48mhz_pwrdwn); 1008 } 1009 } 1010 1011