1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dccg.h" 27 #include "clk_mgr_internal.h" 28 29 30 #include "dcn20/dcn20_clk_mgr.h" 31 #include "rn_clk_mgr.h" 32 33 34 #include "dce100/dce_clk_mgr.h" 35 #include "rn_clk_mgr_vbios_smu.h" 36 #include "reg_helper.h" 37 #include "core_types.h" 38 #include "dm_helpers.h" 39 40 #include "atomfirmware.h" 41 #include "clk/clk_10_0_2_offset.h" 42 #include "clk/clk_10_0_2_sh_mask.h" 43 #include "renoir_ip_offset.h" 44 45 46 /* Constants */ 47 48 #define LPDDR_MEM_RETRAIN_LATENCY 4.977 /* Number obtained from LPDDR4 Training Counter Requirement doc */ 49 50 /* Macros */ 51 52 #define REG(reg_name) \ 53 (CLK_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name) 54 55 56 /* TODO: evaluate how to lower or disable all dcn clocks in screen off case */ 57 int rn_get_active_display_cnt_wa( 58 struct dc *dc, 59 struct dc_state *context) 60 { 61 int i, display_count; 62 bool hdmi_present = false; 63 64 display_count = 0; 65 for (i = 0; i < context->stream_count; i++) { 66 const struct dc_stream_state *stream = context->streams[i]; 67 68 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 69 hdmi_present = true; 70 } 71 72 for (i = 0; i < dc->link_count; i++) { 73 const struct dc_link *link = dc->links[i]; 74 75 /* 76 * Only notify active stream or virtual stream. 77 * Need to notify virtual stream to work around 78 * headless case. HPD does not fire when system is in 79 * S0i2. 80 */ 81 /* abusing the fact that the dig and phy are coupled to see if the phy is enabled */ 82 if (link->connector_signal == SIGNAL_TYPE_VIRTUAL || 83 link->link_enc->funcs->is_dig_enabled(link->link_enc)) 84 display_count++; 85 } 86 87 /* WA for hang on HDMI after display off back back on*/ 88 if (display_count == 0 && hdmi_present) 89 display_count = 1; 90 91 return display_count; 92 } 93 94 void rn_update_clocks(struct clk_mgr *clk_mgr_base, 95 struct dc_state *context, 96 bool safe_to_lower) 97 { 98 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 99 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; 100 struct dc *dc = clk_mgr_base->ctx->dc; 101 int display_count; 102 bool update_dppclk = false; 103 bool update_dispclk = false; 104 bool dpp_clock_lowered = false; 105 106 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu; 107 108 if (dc->work_arounds.skip_clock_update) 109 return; 110 111 /* 112 * if it is safe to lower, but we are already in the lower state, we don't have to do anything 113 * also if safe to lower is false, we just go in the higher state 114 */ 115 if (safe_to_lower) { 116 /* check that we're not already in lower */ 117 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { 118 119 display_count = rn_get_active_display_cnt_wa(dc, context); 120 /* if we can go lower, go lower */ 121 if (display_count == 0) { 122 rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_LOW_POWER); 123 /* update power state */ 124 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; 125 } 126 } 127 } else { 128 /* check that we're not already in D0 */ 129 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) { 130 rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_MISSION_MODE); 131 /* update power state */ 132 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE; 133 } 134 } 135 136 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) { 137 clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz; 138 rn_vbios_smu_set_phyclk(clk_mgr, clk_mgr_base->clks.phyclk_khz); 139 } 140 141 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { 142 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; 143 rn_vbios_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz); 144 } 145 146 if (should_set_clock(safe_to_lower, 147 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { 148 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; 149 rn_vbios_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz); 150 } 151 152 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { 153 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz) 154 dpp_clock_lowered = true; 155 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz; 156 update_dppclk = true; 157 } 158 159 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { 160 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; 161 rn_vbios_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz); 162 163 update_dispclk = true; 164 } 165 166 if (dpp_clock_lowered) { 167 // if clock is being lowered, increase DTO before lowering refclk 168 dcn20_update_clocks_update_dpp_dto(clk_mgr, context); 169 rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz); 170 } else { 171 // if clock is being raised, increase refclk before lowering DTO 172 if (update_dppclk || update_dispclk) 173 rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz); 174 // always update dtos unless clock is lowered and not safe to lower 175 if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz) 176 dcn20_update_clocks_update_dpp_dto(clk_mgr, context); 177 } 178 179 if (update_dispclk && 180 dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) { 181 /*update dmcu for wait_loop count*/ 182 dmcu->funcs->set_psr_wait_loop(dmcu, 183 clk_mgr_base->clks.dispclk_khz / 1000 / 7); 184 } 185 } 186 187 188 static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr) 189 { 190 /* get FbMult value */ 191 struct fixed31_32 pll_req; 192 unsigned int fbmult_frac_val = 0; 193 unsigned int fbmult_int_val = 0; 194 195 196 /* 197 * Register value of fbmult is in 8.16 format, we are converting to 31.32 198 * to leverage the fix point operations available in driver 199 */ 200 201 REG_GET(CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/ 202 REG_GET(CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */ 203 204 pll_req = dc_fixpt_from_int(fbmult_int_val); 205 206 /* 207 * since fractional part is only 16 bit in register definition but is 32 bit 208 * in our fix point definiton, need to shift left by 16 to obtain correct value 209 */ 210 pll_req.value |= fbmult_frac_val << 16; 211 212 /* multiply by REFCLK period */ 213 pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz); 214 215 /* integer part is now VCO frequency in kHz */ 216 return dc_fixpt_floor(pll_req); 217 } 218 219 static void rn_dump_clk_registers_internal(struct rn_clk_internal *internal, struct clk_mgr *clk_mgr_base) 220 { 221 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 222 223 internal->CLK1_CLK3_CURRENT_CNT = REG_READ(CLK1_CLK3_CURRENT_CNT); 224 internal->CLK1_CLK3_BYPASS_CNTL = REG_READ(CLK1_CLK3_BYPASS_CNTL); 225 226 internal->CLK1_CLK3_DS_CNTL = REG_READ(CLK1_CLK3_DS_CNTL); //dcf deep sleep divider 227 internal->CLK1_CLK3_ALLOW_DS = REG_READ(CLK1_CLK3_ALLOW_DS); 228 229 internal->CLK1_CLK1_CURRENT_CNT = REG_READ(CLK1_CLK1_CURRENT_CNT); 230 internal->CLK1_CLK1_BYPASS_CNTL = REG_READ(CLK1_CLK1_BYPASS_CNTL); 231 232 internal->CLK1_CLK2_CURRENT_CNT = REG_READ(CLK1_CLK2_CURRENT_CNT); 233 internal->CLK1_CLK2_BYPASS_CNTL = REG_READ(CLK1_CLK2_BYPASS_CNTL); 234 235 internal->CLK1_CLK0_CURRENT_CNT = REG_READ(CLK1_CLK0_CURRENT_CNT); 236 internal->CLK1_CLK0_BYPASS_CNTL = REG_READ(CLK1_CLK0_BYPASS_CNTL); 237 } 238 239 /* This function collect raw clk register values */ 240 static void rn_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass, 241 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info) 242 { 243 struct rn_clk_internal internal = {0}; 244 char *bypass_clks[5] = {"0x0 DFS", "0x1 REFCLK", "0x2 ERROR", "0x3 400 FCH", "0x4 600 FCH"}; 245 unsigned int chars_printed = 0; 246 unsigned int remaining_buffer = log_info->bufSize; 247 248 rn_dump_clk_registers_internal(&internal, clk_mgr_base); 249 250 regs_and_bypass->dcfclk = internal.CLK1_CLK3_CURRENT_CNT / 10; 251 regs_and_bypass->dcf_deep_sleep_divider = internal.CLK1_CLK3_DS_CNTL / 10; 252 regs_and_bypass->dcf_deep_sleep_allow = internal.CLK1_CLK3_ALLOW_DS; 253 regs_and_bypass->dprefclk = internal.CLK1_CLK2_CURRENT_CNT / 10; 254 regs_and_bypass->dispclk = internal.CLK1_CLK0_CURRENT_CNT / 10; 255 regs_and_bypass->dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10; 256 257 regs_and_bypass->dppclk_bypass = internal.CLK1_CLK1_BYPASS_CNTL & 0x0007; 258 if (regs_and_bypass->dppclk_bypass < 0 || regs_and_bypass->dppclk_bypass > 4) 259 regs_and_bypass->dppclk_bypass = 0; 260 regs_and_bypass->dcfclk_bypass = internal.CLK1_CLK3_BYPASS_CNTL & 0x0007; 261 if (regs_and_bypass->dcfclk_bypass < 0 || regs_and_bypass->dcfclk_bypass > 4) 262 regs_and_bypass->dcfclk_bypass = 0; 263 regs_and_bypass->dispclk_bypass = internal.CLK1_CLK0_BYPASS_CNTL & 0x0007; 264 if (regs_and_bypass->dispclk_bypass < 0 || regs_and_bypass->dispclk_bypass > 4) 265 regs_and_bypass->dispclk_bypass = 0; 266 regs_and_bypass->dprefclk_bypass = internal.CLK1_CLK2_BYPASS_CNTL & 0x0007; 267 if (regs_and_bypass->dprefclk_bypass < 0 || regs_and_bypass->dprefclk_bypass > 4) 268 regs_and_bypass->dprefclk_bypass = 0; 269 270 if (log_info->enabled) { 271 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "clk_type,clk_value,deepsleep_cntl,deepsleep_allow,bypass\n"); 272 remaining_buffer -= chars_printed; 273 *log_info->sum_chars_printed += chars_printed; 274 log_info->pBuf += chars_printed; 275 276 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dcfclk,%d,%d,%d,%s\n", 277 regs_and_bypass->dcfclk, 278 regs_and_bypass->dcf_deep_sleep_divider, 279 regs_and_bypass->dcf_deep_sleep_allow, 280 bypass_clks[(int) regs_and_bypass->dcfclk_bypass]); 281 remaining_buffer -= chars_printed; 282 *log_info->sum_chars_printed += chars_printed; 283 log_info->pBuf += chars_printed; 284 285 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dprefclk,%d,N/A,N/A,%s\n", 286 regs_and_bypass->dprefclk, 287 bypass_clks[(int) regs_and_bypass->dprefclk_bypass]); 288 remaining_buffer -= chars_printed; 289 *log_info->sum_chars_printed += chars_printed; 290 log_info->pBuf += chars_printed; 291 292 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dispclk,%d,N/A,N/A,%s\n", 293 regs_and_bypass->dispclk, 294 bypass_clks[(int) regs_and_bypass->dispclk_bypass]); 295 remaining_buffer -= chars_printed; 296 *log_info->sum_chars_printed += chars_printed; 297 log_info->pBuf += chars_printed; 298 299 //split 300 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "SPLIT\n"); 301 remaining_buffer -= chars_printed; 302 *log_info->sum_chars_printed += chars_printed; 303 log_info->pBuf += chars_printed; 304 305 // REGISTER VALUES 306 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "reg_name,value,clk_type\n"); 307 remaining_buffer -= chars_printed; 308 *log_info->sum_chars_printed += chars_printed; 309 log_info->pBuf += chars_printed; 310 311 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_CURRENT_CNT,%d,dcfclk\n", 312 internal.CLK1_CLK3_CURRENT_CNT); 313 remaining_buffer -= chars_printed; 314 *log_info->sum_chars_printed += chars_printed; 315 log_info->pBuf += chars_printed; 316 317 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_DS_CNTL,%d,dcf_deep_sleep_divider\n", 318 internal.CLK1_CLK3_DS_CNTL); 319 remaining_buffer -= chars_printed; 320 *log_info->sum_chars_printed += chars_printed; 321 log_info->pBuf += chars_printed; 322 323 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_ALLOW_DS,%d,dcf_deep_sleep_allow\n", 324 internal.CLK1_CLK3_ALLOW_DS); 325 remaining_buffer -= chars_printed; 326 *log_info->sum_chars_printed += chars_printed; 327 log_info->pBuf += chars_printed; 328 329 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK2_CURRENT_CNT,%d,dprefclk\n", 330 internal.CLK1_CLK2_CURRENT_CNT); 331 remaining_buffer -= chars_printed; 332 *log_info->sum_chars_printed += chars_printed; 333 log_info->pBuf += chars_printed; 334 335 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK0_CURRENT_CNT,%d,dispclk\n", 336 internal.CLK1_CLK0_CURRENT_CNT); 337 remaining_buffer -= chars_printed; 338 *log_info->sum_chars_printed += chars_printed; 339 log_info->pBuf += chars_printed; 340 341 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK1_CURRENT_CNT,%d,dppclk\n", 342 internal.CLK1_CLK1_CURRENT_CNT); 343 remaining_buffer -= chars_printed; 344 *log_info->sum_chars_printed += chars_printed; 345 log_info->pBuf += chars_printed; 346 347 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_BYPASS_CNTL,%d,dcfclk_bypass\n", 348 internal.CLK1_CLK3_BYPASS_CNTL); 349 remaining_buffer -= chars_printed; 350 *log_info->sum_chars_printed += chars_printed; 351 log_info->pBuf += chars_printed; 352 353 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK2_BYPASS_CNTL,%d,dprefclk_bypass\n", 354 internal.CLK1_CLK2_BYPASS_CNTL); 355 remaining_buffer -= chars_printed; 356 *log_info->sum_chars_printed += chars_printed; 357 log_info->pBuf += chars_printed; 358 359 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK0_BYPASS_CNTL,%d,dispclk_bypass\n", 360 internal.CLK1_CLK0_BYPASS_CNTL); 361 remaining_buffer -= chars_printed; 362 *log_info->sum_chars_printed += chars_printed; 363 log_info->pBuf += chars_printed; 364 365 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK1_BYPASS_CNTL,%d,dppclk_bypass\n", 366 internal.CLK1_CLK1_BYPASS_CNTL); 367 remaining_buffer -= chars_printed; 368 *log_info->sum_chars_printed += chars_printed; 369 log_info->pBuf += chars_printed; 370 } 371 } 372 373 /* This function produce translated logical clk state values*/ 374 void rn_get_clk_states(struct clk_mgr *clk_mgr_base, struct clk_states *s) 375 { 376 struct clk_state_registers_and_bypass sb = { 0 }; 377 struct clk_log_info log_info = { 0 }; 378 379 rn_dump_clk_registers(&sb, clk_mgr_base, &log_info); 380 381 s->dprefclk_khz = sb.dprefclk * 1000; 382 } 383 384 void rn_enable_pme_wa(struct clk_mgr *clk_mgr_base) 385 { 386 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 387 388 rn_vbios_smu_enable_pme_wa(clk_mgr); 389 } 390 391 void rn_init_clocks(struct clk_mgr *clk_mgr) 392 { 393 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks)); 394 // Assumption is that boot state always supports pstate 395 clk_mgr->clks.p_state_change_support = true; 396 clk_mgr->clks.prev_p_state_change_support = true; 397 clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN; 398 } 399 400 void build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_smu_wm_range_sets *ranges) 401 { 402 int i, num_valid_sets; 403 404 num_valid_sets = 0; 405 406 for (i = 0; i < WM_SET_COUNT; i++) { 407 /* skip empty entries, the smu array has no holes*/ 408 if (!bw_params->wm_table.entries[i].valid) 409 continue; 410 411 ranges->reader_wm_sets[num_valid_sets].wm_inst = bw_params->wm_table.entries[i].wm_inst; 412 ranges->reader_wm_sets[num_valid_sets].wm_type = bw_params->wm_table.entries[i].wm_type;; 413 /* We will not select WM based on dcfclk, so leave it as unconstrained */ 414 ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 415 ranges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 416 /* fclk wil be used to select WM*/ 417 418 if (ranges->reader_wm_sets[num_valid_sets].wm_type == WM_TYPE_PSTATE_CHG) { 419 if (i == 0) 420 ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = 0; 421 else { 422 /* add 1 to make it non-overlapping with next lvl */ 423 ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = bw_params->clk_table.entries[i - 1].fclk_mhz + 1; 424 } 425 ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz = bw_params->clk_table.entries[i].fclk_mhz; 426 427 } else { 428 /* unconstrained for memory retraining */ 429 ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 430 ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 431 432 /* Modify previous watermark range to cover up to max */ 433 ranges->reader_wm_sets[num_valid_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 434 } 435 num_valid_sets++; 436 } 437 438 ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */ 439 ranges->num_reader_wm_sets = num_valid_sets; 440 441 /* modify the min and max to make sure we cover the whole range*/ 442 ranges->reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 443 ranges->reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 444 ranges->reader_wm_sets[ranges->num_reader_wm_sets - 1].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 445 ranges->reader_wm_sets[ranges->num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 446 447 /* This is for writeback only, does not matter currently as no writeback support*/ 448 ranges->num_writer_wm_sets = 1; 449 ranges->writer_wm_sets[0].wm_inst = WM_A; 450 ranges->writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 451 ranges->writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 452 ranges->writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 453 ranges->writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 454 455 } 456 457 static void rn_notify_wm_ranges(struct clk_mgr *clk_mgr_base) 458 { 459 struct dc_debug_options *debug = &clk_mgr_base->ctx->dc->debug; 460 struct pp_smu_wm_range_sets ranges = {0}; 461 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 462 struct pp_smu_funcs *pp_smu = clk_mgr->pp_smu; 463 464 if (!debug->disable_pplib_wm_range) { 465 build_watermark_ranges(clk_mgr_base->bw_params, &ranges); 466 467 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */ 468 if (pp_smu && pp_smu->rn_funcs.set_wm_ranges) 469 pp_smu->rn_funcs.set_wm_ranges(&pp_smu->rn_funcs.pp_smu, &ranges); 470 } 471 472 } 473 474 static bool rn_are_clock_states_equal(struct dc_clocks *a, 475 struct dc_clocks *b) 476 { 477 if (a->dispclk_khz != b->dispclk_khz) 478 return false; 479 else if (a->dppclk_khz != b->dppclk_khz) 480 return false; 481 else if (a->dcfclk_khz != b->dcfclk_khz) 482 return false; 483 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz) 484 return false; 485 486 return true; 487 } 488 489 490 static struct clk_mgr_funcs dcn21_funcs = { 491 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz, 492 .update_clocks = rn_update_clocks, 493 .init_clocks = rn_init_clocks, 494 .enable_pme_wa = rn_enable_pme_wa, 495 .are_clock_states_equal = rn_are_clock_states_equal, 496 .notify_wm_ranges = rn_notify_wm_ranges 497 }; 498 499 struct clk_bw_params rn_bw_params = { 500 .vram_type = Ddr4MemType, 501 .num_channels = 1, 502 .clk_table = { 503 .entries = { 504 { 505 .voltage = 0, 506 .dcfclk_mhz = 400, 507 .fclk_mhz = 400, 508 .memclk_mhz = 800, 509 .socclk_mhz = 0, 510 }, 511 { 512 .voltage = 0, 513 .dcfclk_mhz = 483, 514 .fclk_mhz = 800, 515 .memclk_mhz = 1600, 516 .socclk_mhz = 0, 517 }, 518 { 519 .voltage = 0, 520 .dcfclk_mhz = 602, 521 .fclk_mhz = 1067, 522 .memclk_mhz = 1067, 523 .socclk_mhz = 0, 524 }, 525 { 526 .voltage = 0, 527 .dcfclk_mhz = 738, 528 .fclk_mhz = 1333, 529 .memclk_mhz = 1600, 530 .socclk_mhz = 0, 531 }, 532 }, 533 534 .num_entries = 4, 535 }, 536 537 }; 538 539 struct wm_table ddr4_wm_table = { 540 .entries = { 541 { 542 .wm_inst = WM_A, 543 .wm_type = WM_TYPE_PSTATE_CHG, 544 .pstate_latency_us = 11.72, 545 .sr_exit_time_us = 6.09, 546 .sr_enter_plus_exit_time_us = 7.14, 547 .valid = true, 548 }, 549 { 550 .wm_inst = WM_B, 551 .wm_type = WM_TYPE_PSTATE_CHG, 552 .pstate_latency_us = 11.72, 553 .sr_exit_time_us = 10.12, 554 .sr_enter_plus_exit_time_us = 11.48, 555 .valid = true, 556 }, 557 { 558 .wm_inst = WM_C, 559 .wm_type = WM_TYPE_PSTATE_CHG, 560 .pstate_latency_us = 11.72, 561 .sr_exit_time_us = 10.12, 562 .sr_enter_plus_exit_time_us = 11.48, 563 .valid = true, 564 }, 565 { 566 .wm_inst = WM_D, 567 .wm_type = WM_TYPE_PSTATE_CHG, 568 .pstate_latency_us = 11.72, 569 .sr_exit_time_us = 10.12, 570 .sr_enter_plus_exit_time_us = 11.48, 571 .valid = true, 572 }, 573 } 574 }; 575 576 struct wm_table lpddr4_wm_table = { 577 .entries = { 578 { 579 .wm_inst = WM_A, 580 .wm_type = WM_TYPE_PSTATE_CHG, 581 .pstate_latency_us = 23.84, 582 .sr_exit_time_us = 12.5, 583 .sr_enter_plus_exit_time_us = 17.0, 584 .valid = true, 585 }, 586 { 587 .wm_inst = WM_B, 588 .wm_type = WM_TYPE_PSTATE_CHG, 589 .pstate_latency_us = 23.84, 590 .sr_exit_time_us = 12.5, 591 .sr_enter_plus_exit_time_us = 17.0, 592 .valid = true, 593 }, 594 { 595 .wm_inst = WM_C, 596 .wm_type = WM_TYPE_PSTATE_CHG, 597 .pstate_latency_us = 23.84, 598 .sr_exit_time_us = 12.5, 599 .sr_enter_plus_exit_time_us = 17.0, 600 .valid = true, 601 }, 602 { 603 .wm_inst = WM_D, 604 .wm_type = WM_TYPE_PSTATE_CHG, 605 .pstate_latency_us = 23.84, 606 .sr_exit_time_us = 12.5, 607 .sr_enter_plus_exit_time_us = 17.0, 608 .valid = true, 609 }, 610 } 611 }; 612 613 614 static unsigned int find_dcfclk_for_voltage(struct dpm_clocks *clock_table, unsigned int voltage) 615 { 616 int i; 617 618 for (i = 0; i < PP_SMU_NUM_DCFCLK_DPM_LEVELS; i++) { 619 if (clock_table->DcfClocks[i].Vol == voltage) 620 return clock_table->DcfClocks[i].Freq; 621 } 622 623 ASSERT(0); 624 return 0; 625 } 626 627 static void rn_clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params, struct dpm_clocks *clock_table, struct integrated_info *bios_info) 628 { 629 int i, j = 0; 630 631 j = -1; 632 633 ASSERT(PP_SMU_NUM_FCLK_DPM_LEVELS <= MAX_NUM_DPM_LVL); 634 635 /* Find lowest DPM, FCLK is filled in reverse order*/ 636 637 for (i = PP_SMU_NUM_FCLK_DPM_LEVELS - 1; i >= 0; i--) { 638 if (clock_table->FClocks[i].Freq != 0) { 639 j = i; 640 break; 641 } 642 } 643 644 if (j == -1) { 645 /* clock table is all 0s, just use our own hardcode */ 646 ASSERT(0); 647 return; 648 } 649 650 bw_params->clk_table.num_entries = j + 1; 651 652 for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) { 653 bw_params->clk_table.entries[i].fclk_mhz = clock_table->FClocks[j].Freq; 654 bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemClocks[j].Freq; 655 bw_params->clk_table.entries[i].voltage = clock_table->FClocks[j].Vol; 656 bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->FClocks[j].Vol); 657 } 658 659 bw_params->vram_type = bios_info->memory_type; 660 bw_params->num_channels = bios_info->ma_channel_number; 661 662 for (i = 0; i < WM_SET_COUNT; i++) { 663 bw_params->wm_table.entries[i].wm_inst = i; 664 665 if (i >= bw_params->clk_table.num_entries) { 666 bw_params->wm_table.entries[i].valid = false; 667 continue; 668 } 669 670 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; 671 bw_params->wm_table.entries[i].valid = true; 672 } 673 674 if (bw_params->vram_type == LpDdr4MemType) { 675 /* 676 * WM set D will be re-purposed for memory retraining 677 */ 678 bw_params->wm_table.entries[WM_D].pstate_latency_us = LPDDR_MEM_RETRAIN_LATENCY; 679 bw_params->wm_table.entries[WM_D].wm_inst = WM_D; 680 bw_params->wm_table.entries[WM_D].wm_type = WM_TYPE_RETRAINING; 681 bw_params->wm_table.entries[WM_D].valid = true; 682 } 683 684 } 685 686 void rn_clk_mgr_construct( 687 struct dc_context *ctx, 688 struct clk_mgr_internal *clk_mgr, 689 struct pp_smu_funcs *pp_smu, 690 struct dccg *dccg) 691 { 692 struct dc_debug_options *debug = &ctx->dc->debug; 693 struct dpm_clocks clock_table = { 0 }; 694 struct clk_state_registers_and_bypass s = { 0 }; 695 696 clk_mgr->base.ctx = ctx; 697 clk_mgr->base.funcs = &dcn21_funcs; 698 699 clk_mgr->pp_smu = pp_smu; 700 701 clk_mgr->dccg = dccg; 702 clk_mgr->dfs_bypass_disp_clk = 0; 703 704 clk_mgr->dprefclk_ss_percentage = 0; 705 clk_mgr->dprefclk_ss_divider = 1000; 706 clk_mgr->ss_on_dprefclk = false; 707 clk_mgr->dfs_ref_freq_khz = 48000; 708 709 clk_mgr->smu_ver = rn_vbios_smu_get_smu_version(clk_mgr); 710 711 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) { 712 dcn21_funcs.update_clocks = dcn2_update_clocks_fpga; 713 clk_mgr->base.dentist_vco_freq_khz = 3600000; 714 clk_mgr->base.dprefclk_khz = 600000; 715 } else { 716 struct clk_log_info log_info = {0}; 717 718 /* TODO: Check we get what we expect during bringup */ 719 clk_mgr->base.dentist_vco_freq_khz = get_vco_frequency_from_reg(clk_mgr); 720 721 /* in case we don't get a value from the register, use default */ 722 if (clk_mgr->base.dentist_vco_freq_khz == 0) 723 clk_mgr->base.dentist_vco_freq_khz = 3600000; 724 725 rn_dump_clk_registers(&s, &clk_mgr->base, &log_info); 726 /* Convert dprefclk units from MHz to KHz */ 727 /* Value already divided by 10, some resolution lost */ 728 clk_mgr->base.dprefclk_khz = s.dprefclk * 1000; 729 730 /* in case we don't get a value from the register, use default */ 731 if (clk_mgr->base.dprefclk_khz == 0) { 732 ASSERT(clk_mgr->base.dprefclk_khz == 600000); 733 clk_mgr->base.dprefclk_khz = 600000; 734 } 735 736 if (ctx->dc_bios->integrated_info->memory_type == LpDdr4MemType) { 737 rn_bw_params.wm_table = lpddr4_wm_table; 738 } else { 739 rn_bw_params.wm_table = ddr4_wm_table; 740 } 741 } 742 743 dce_clock_read_ss_info(clk_mgr); 744 745 746 clk_mgr->base.bw_params = &rn_bw_params; 747 748 if (pp_smu && pp_smu->rn_funcs.get_dpm_clock_table) { 749 pp_smu->rn_funcs.get_dpm_clock_table(&pp_smu->rn_funcs.pp_smu, &clock_table); 750 if (ctx->dc_bios && ctx->dc_bios->integrated_info) { 751 rn_clk_mgr_helper_populate_bw_params (clk_mgr->base.bw_params, &clock_table, ctx->dc_bios->integrated_info); 752 } 753 } 754 755 if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment) && clk_mgr->smu_ver >= 0x00371500) { 756 /* enable powerfeatures when displaycount goes to 0 */ 757 rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(clk_mgr, !debug->disable_48mhz_pwrdwn); 758 } 759 } 760 761