1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DCN30_CLK_MGR_H__ 27 #define __DCN30_CLK_MGR_H__ 28 29 //CLK1_CLK_PLL_REQ 30 #ifndef CLK11_CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 31 #define CLK11_CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x0 32 #define CLK11_CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc 33 #define CLK11_CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10 34 #define CLK11_CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL 35 #define CLK11_CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L 36 #define CLK11_CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L 37 //CLK1_CLK0_DFS_CNTL 38 #define CLK11_CLK1_CLK0_DFS_CNTL__CLK0_DIVIDER__SHIFT 0x0 39 #define CLK11_CLK1_CLK0_DFS_CNTL__CLK0_DIVIDER_MASK 0x0000007FL 40 /*DPREF clock related*/ 41 #define CLK0_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT 0x0 42 #define CLK0_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK 0x0000007FL 43 #define CLK1_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT 0x0 44 #define CLK1_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK 0x0000007FL 45 #define CLK2_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT 0x0 46 #define CLK2_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK 0x0000007FL 47 #define CLK3_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT 0x0 48 #define CLK3_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK 0x0000007FL 49 50 //CLK3_0_CLK3_CLK_PLL_REQ 51 #define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_int__SHIFT 0x0 52 #define CLK3_0_CLK3_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc 53 #define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10 54 #define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL 55 #define CLK3_0_CLK3_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L 56 #define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L 57 58 #define mmCLK0_CLK2_DFS_CNTL 0x16C55 59 #define mmCLK00_CLK0_CLK2_DFS_CNTL 0x16C55 60 #define mmCLK01_CLK0_CLK2_DFS_CNTL 0x16E55 61 #define mmCLK02_CLK0_CLK2_DFS_CNTL 0x17055 62 63 #define mmCLK0_CLK3_DFS_CNTL 0x16C60 64 #define mmCLK00_CLK0_CLK3_DFS_CNTL 0x16C60 65 #define mmCLK01_CLK0_CLK3_DFS_CNTL 0x16E60 66 #define mmCLK02_CLK0_CLK3_DFS_CNTL 0x17060 67 #define mmCLK03_CLK0_CLK3_DFS_CNTL 0x17260 68 69 #define mmCLK0_CLK_PLL_REQ 0x16C10 70 #define mmCLK00_CLK0_CLK_PLL_REQ 0x16C10 71 #define mmCLK01_CLK0_CLK_PLL_REQ 0x16E10 72 #define mmCLK02_CLK0_CLK_PLL_REQ 0x17010 73 #define mmCLK03_CLK0_CLK_PLL_REQ 0x17210 74 75 #define mmCLK1_CLK_PLL_REQ 0x1B00D 76 #define mmCLK10_CLK1_CLK_PLL_REQ 0x1B00D 77 #define mmCLK11_CLK1_CLK_PLL_REQ 0x1B20D 78 #define mmCLK12_CLK1_CLK_PLL_REQ 0x1B40D 79 #define mmCLK13_CLK1_CLK_PLL_REQ 0x1B60D 80 81 #define mmCLK2_CLK_PLL_REQ 0x17E0D 82 83 /*AMCLK*/ 84 85 #define mmCLK11_CLK1_CLK0_DFS_CNTL 0x1B23F 86 #define mmCLK11_CLK1_CLK_PLL_REQ 0x1B20D 87 88 #endif 89 void dcn3_init_clocks(struct clk_mgr *clk_mgr_base); 90 91 void dcn3_clk_mgr_construct(struct dc_context *ctx, 92 struct clk_mgr_internal *clk_mgr, 93 struct pp_smu_funcs *pp_smu, 94 struct dccg *dccg); 95 96 void dcn3_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr); 97 98 #endif //__DCN30_CLK_MGR_H__ 99