1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/delay.h> 27 #include "dcn30_clk_mgr_smu_msg.h" 28 29 #include "clk_mgr_internal.h" 30 #include "reg_helper.h" 31 #include "dalsmc.h" 32 #include "dcn30_smu11_driver_if.h" 33 34 #define mmDAL_MSG_REG 0x1628A 35 #define mmDAL_ARG_REG 0x16273 36 #define mmDAL_RESP_REG 0x16274 37 38 #define REG(reg_name) \ 39 mm ## reg_name 40 41 #include "logger_types.h" 42 #undef DC_LOGGER 43 #define DC_LOGGER \ 44 CTX->logger 45 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); } 46 47 48 /* 49 * Function to be used instead of REG_WAIT macro because the wait ends when 50 * the register is NOT EQUAL to zero, and because the translation in msg_if.h 51 * won't work with REG_WAIT. 52 */ 53 static uint32_t dcn30_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries) 54 { 55 uint32_t reg = 0; 56 57 do { 58 reg = REG_READ(DAL_RESP_REG); 59 if (reg) 60 break; 61 62 if (delay_us >= 1000) 63 msleep(delay_us/1000); 64 else if (delay_us > 0) 65 udelay(delay_us); 66 } while (max_retries--); 67 68 /* handle DALSMC_Result_CmdRejectedBusy? */ 69 70 /* Log? */ 71 72 return reg; 73 } 74 75 static bool dcn30_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, uint32_t msg_id, uint32_t param_in, uint32_t *param_out) 76 { 77 /* Wait for response register to be ready */ 78 dcn30_smu_wait_for_response(clk_mgr, 10, 200000); 79 80 /* Clear response register */ 81 REG_WRITE(DAL_RESP_REG, 0); 82 83 /* Set the parameter register for the SMU message */ 84 REG_WRITE(DAL_ARG_REG, param_in); 85 86 /* Trigger the message transaction by writing the message ID */ 87 REG_WRITE(DAL_MSG_REG, msg_id); 88 89 /* Wait for response */ 90 if (dcn30_smu_wait_for_response(clk_mgr, 10, 200000) == DALSMC_Result_OK) { 91 if (param_out) 92 *param_out = REG_READ(DAL_ARG_REG); 93 94 return true; 95 } 96 97 return false; 98 } 99 100 /* Test message should return input + 1 */ 101 bool dcn30_smu_test_message(struct clk_mgr_internal *clk_mgr, uint32_t input) 102 { 103 uint32_t response = 0; 104 105 smu_print("SMU Test message: %d\n", input); 106 107 if (dcn30_smu_send_msg_with_param(clk_mgr, 108 DALSMC_MSG_TestMessage, input, &response)) 109 if (response == input + 1) 110 return true; 111 112 return false; 113 } 114 115 bool dcn30_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, unsigned int *version) 116 { 117 smu_print("SMU Get SMU version\n"); 118 119 if (dcn30_smu_send_msg_with_param(clk_mgr, 120 DALSMC_MSG_GetSmuVersion, 0, version)) { 121 122 smu_print("SMU version: %d\n", *version); 123 124 return true; 125 } 126 127 return false; 128 } 129 130 /* Message output should match SMU11_DRIVER_IF_VERSION in smu11_driver_if.h */ 131 bool dcn30_smu_check_driver_if_version(struct clk_mgr_internal *clk_mgr) 132 { 133 uint32_t response = 0; 134 135 smu_print("SMU Check driver if version\n"); 136 137 if (dcn30_smu_send_msg_with_param(clk_mgr, 138 DALSMC_MSG_GetDriverIfVersion, 0, &response)) { 139 140 smu_print("SMU driver if version: %d\n", response); 141 142 if (response == SMU11_DRIVER_IF_VERSION) 143 return true; 144 } 145 146 return false; 147 } 148 149 /* Message output should match DALSMC_VERSION in dalsmc.h */ 150 bool dcn30_smu_check_msg_header_version(struct clk_mgr_internal *clk_mgr) 151 { 152 uint32_t response = 0; 153 154 smu_print("SMU Check msg header version\n"); 155 156 if (dcn30_smu_send_msg_with_param(clk_mgr, 157 DALSMC_MSG_GetMsgHeaderVersion, 0, &response)) { 158 159 smu_print("SMU msg header version: %d\n", response); 160 161 if (response == DALSMC_VERSION) 162 return true; 163 } 164 165 return false; 166 } 167 168 void dcn30_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high) 169 { 170 smu_print("SMU Set DRAM addr high: %d\n", addr_high); 171 172 dcn30_smu_send_msg_with_param(clk_mgr, 173 DALSMC_MSG_SetDalDramAddrHigh, addr_high, NULL); 174 } 175 176 void dcn30_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low) 177 { 178 smu_print("SMU Set DRAM addr low: %d\n", addr_low); 179 180 dcn30_smu_send_msg_with_param(clk_mgr, 181 DALSMC_MSG_SetDalDramAddrLow, addr_low, NULL); 182 } 183 184 void dcn30_smu_transfer_wm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr) 185 { 186 smu_print("SMU Transfer WM table SMU 2 DRAM\n"); 187 188 dcn30_smu_send_msg_with_param(clk_mgr, 189 DALSMC_MSG_TransferTableSmu2Dram, TABLE_WATERMARKS, NULL); 190 } 191 192 void dcn30_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr) 193 { 194 smu_print("SMU Transfer WM table DRAM 2 SMU\n"); 195 196 dcn30_smu_send_msg_with_param(clk_mgr, 197 DALSMC_MSG_TransferTableDram2Smu, TABLE_WATERMARKS, NULL); 198 } 199 200 /* Returns the actual frequency that was set in MHz, 0 on failure */ 201 unsigned int dcn30_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz) 202 { 203 uint32_t response = 0; 204 205 /* bits 23:16 for clock type, lower 16 bits for frequency in MHz */ 206 uint32_t param = (clk << 16) | freq_mhz; 207 208 smu_print("SMU Set hard min by freq: clk = %d, freq_mhz = %d MHz\n", clk, freq_mhz); 209 210 dcn30_smu_send_msg_with_param(clk_mgr, 211 DALSMC_MSG_SetHardMinByFreq, param, &response); 212 213 smu_print("SMU Frequency set = %d MHz\n", response); 214 215 return response; 216 } 217 218 /* Returns the actual frequency that was set in MHz, 0 on failure */ 219 unsigned int dcn30_smu_set_hard_max_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz) 220 { 221 uint32_t response = 0; 222 223 /* bits 23:16 for clock type, lower 16 bits for frequency in MHz */ 224 uint32_t param = (clk << 16) | freq_mhz; 225 226 smu_print("SMU Set hard max by freq: clk = %d, freq_mhz = %d MHz\n", clk, freq_mhz); 227 228 dcn30_smu_send_msg_with_param(clk_mgr, 229 DALSMC_MSG_SetHardMaxByFreq, param, &response); 230 231 smu_print("SMU Frequency set = %d MHz\n", response); 232 233 return response; 234 } 235 236 /* 237 * Frequency in MHz returned in lower 16 bits for valid DPM level 238 * 239 * Call with dpm_level = 0xFF to query features, return value will be: 240 * Bits 7:0 - number of DPM levels 241 * Bit 28 - 1 = auto DPM on 242 * Bit 29 - 1 = sweep DPM on 243 * Bit 30 - 1 = forced DPM on 244 * Bit 31 - 0 = discrete, 1 = fine-grained 245 * 246 * With fine-grained DPM, only min and max frequencies will be reported 247 * 248 * Returns 0 on failure 249 */ 250 unsigned int dcn30_smu_get_dpm_freq_by_index(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint8_t dpm_level) 251 { 252 uint32_t response = 0; 253 254 /* bits 23:16 for clock type, lower 8 bits for DPM level */ 255 uint32_t param = (clk << 16) | dpm_level; 256 257 smu_print("SMU Get dpm freq by index: clk = %d, dpm_level = %d\n", clk, dpm_level); 258 259 dcn30_smu_send_msg_with_param(clk_mgr, 260 DALSMC_MSG_GetDpmFreqByIndex, param, &response); 261 262 smu_print("SMU dpm freq: %d MHz\n", response); 263 264 return response; 265 } 266 267 /* Returns the max DPM frequency in DC mode in MHz, 0 on failure */ 268 unsigned int dcn30_smu_get_dc_mode_max_dpm_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk) 269 { 270 uint32_t response = 0; 271 272 /* bits 23:16 for clock type */ 273 uint32_t param = clk << 16; 274 275 smu_print("SMU Get DC mode max DPM freq: clk = %d\n", clk); 276 277 dcn30_smu_send_msg_with_param(clk_mgr, 278 DALSMC_MSG_GetDcModeMaxDpmFreq, param, &response); 279 280 smu_print("SMU DC mode max DMP freq: %d MHz\n", response); 281 282 return response; 283 } 284 285 void dcn30_smu_set_min_deep_sleep_dcef_clk(struct clk_mgr_internal *clk_mgr, uint32_t freq_mhz) 286 { 287 smu_print("SMU Set min deep sleep dcef clk: freq_mhz = %d MHz\n", freq_mhz); 288 289 dcn30_smu_send_msg_with_param(clk_mgr, 290 DALSMC_MSG_SetMinDeepSleepDcefclk, freq_mhz, NULL); 291 } 292 293 void dcn30_smu_set_num_of_displays(struct clk_mgr_internal *clk_mgr, uint32_t num_displays) 294 { 295 smu_print("SMU Set num of displays: num_displays = %d\n", num_displays); 296 297 dcn30_smu_send_msg_with_param(clk_mgr, 298 DALSMC_MSG_NumOfDisplays, num_displays, NULL); 299 } 300 301 void dcn30_smu_set_display_refresh_from_mall(struct clk_mgr_internal *clk_mgr, bool enable, uint8_t cache_timer_delay, uint8_t cache_timer_scale) 302 { 303 /* bits 8:7 for cache timer scale, bits 6:1 for cache timer delay, bit 0 = 1 for enable, = 0 for disable */ 304 uint32_t param = (cache_timer_scale << 7) | (cache_timer_delay << 1) | (enable ? 1 : 0); 305 306 dcn30_smu_send_msg_with_param(clk_mgr, 307 DALSMC_MSG_SetDisplayRefreshFromMall, param, NULL); 308 } 309 310 void dcn30_smu_set_external_client_df_cstate_allow(struct clk_mgr_internal *clk_mgr, bool enable) 311 { 312 smu_print("SMU Set external client df cstate allow: enable = %d\n", enable); 313 314 dcn30_smu_send_msg_with_param(clk_mgr, 315 DALSMC_MSG_SetExternalClientDfCstateAllow, enable ? 1 : 0, NULL); 316 } 317 318 void dcn30_smu_set_pme_workaround(struct clk_mgr_internal *clk_mgr) 319 { 320 smu_print("SMU Set PME workaround\n"); 321 322 dcn30_smu_send_msg_with_param(clk_mgr, 323 DALSMC_MSG_BacoAudioD3PME, 0, NULL); 324 } 325