1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "core_types.h" 27 #include "clk_mgr_internal.h" 28 #include "reg_helper.h" 29 #include "dm_helpers.h" 30 #include "dcn316_smu.h" 31 #include "mp/mp_13_0_8_offset.h" 32 #include "mp/mp_13_0_8_sh_mask.h" 33 34 #define MAX_INSTANCE 7 35 #define MAX_SEGMENT 6 36 37 struct IP_BASE_INSTANCE { 38 unsigned int segment[MAX_SEGMENT]; 39 }; 40 41 struct IP_BASE { 42 struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; 43 }; 44 45 static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00, 0 } }, 46 { { 0, 0, 0, 0, 0, 0 } }, 47 { { 0, 0, 0, 0, 0, 0 } }, 48 { { 0, 0, 0, 0, 0, 0 } }, 49 { { 0, 0, 0, 0, 0, 0 } }, 50 { { 0, 0, 0, 0, 0, 0 } }, 51 { { 0, 0, 0, 0, 0, 0 } } } }; 52 53 #define REG(reg_name) \ 54 (MP0_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name) 55 56 #define FN(reg_name, field) \ 57 FD(reg_name##__##field) 58 59 #include "logger_types.h" 60 #undef DC_LOGGER 61 #define DC_LOGGER \ 62 CTX->logger 63 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); } 64 65 #define VBIOSSMC_MSG_TestMessage 0x01 ///< To check if PMFW is alive and responding. Requirement specified by PMFW team 66 #define VBIOSSMC_MSG_GetPmfwVersion 0x02 ///< Get PMFW version 67 #define VBIOSSMC_MSG_Spare0 0x03 ///< Spare0 68 #define VBIOSSMC_MSG_SetDispclkFreq 0x04 ///< Set display clock frequency in MHZ 69 #define VBIOSSMC_MSG_Spare1 0x05 ///< Spare1 70 #define VBIOSSMC_MSG_SetDppclkFreq 0x06 ///< Set DPP clock frequency in MHZ 71 #define VBIOSSMC_MSG_SetHardMinDcfclkByFreq 0x07 ///< Set DCF clock frequency hard min in MHZ 72 #define VBIOSSMC_MSG_SetMinDeepSleepDcfclk 0x08 ///< Set DCF clock minimum frequency in deep sleep in MHZ 73 #define VBIOSSMC_MSG_SetPhyclkVoltageByFreq 0x09 ///< Set display phy clock frequency in MHZ in case VMIN does not support phy frequency 74 #define VBIOSSMC_MSG_GetFclkFrequency 0x0A ///< Get FCLK frequency, return frequemcy in MHZ 75 #define VBIOSSMC_MSG_SetDisplayCount 0x0B ///< Inform PMFW of number of display connected 76 #define VBIOSSMC_MSG_SPARE 0x0C ///< SPARE 77 #define VBIOSSMC_MSG_UpdatePmeRestore 0x0D ///< To ask PMFW to write into Azalia for PME wake up event 78 #define VBIOSSMC_MSG_SetVbiosDramAddrHigh 0x0E ///< Set DRAM address high 32 bits for WM table transfer 79 #define VBIOSSMC_MSG_SetVbiosDramAddrLow 0x0F ///< Set DRAM address low 32 bits for WM table transfer 80 #define VBIOSSMC_MSG_TransferTableSmu2Dram 0x10 ///< Transfer table from PMFW SRAM to system DRAM 81 #define VBIOSSMC_MSG_TransferTableDram2Smu 0x11 ///< Transfer table from system DRAM to PMFW 82 #define VBIOSSMC_MSG_SetDisplayIdleOptimizations 0x12 ///< Set Idle state optimization for display off 83 #define VBIOSSMC_MSG_GetDprefclkFreq 0x13 ///< Get DPREF clock frequency. Return in MHZ 84 #define VBIOSSMC_MSG_GetDtbclkFreq 0x14 ///< Get DPREF clock frequency. Return in MHZ 85 #define VBIOSSMC_MSG_SetDtbclkFreq 0x15 ///< Inform PMFW to turn on/off DTB clock arg = 1, turn DTB clock on 600MHz/ arg = 0 turn DTB clock off 86 #define VBIOSSMC_Message_Count 0x16 ///< Total number of VBIS and DAL messages 87 88 #define VBIOSSMC_Status_BUSY 0x0 89 #define VBIOSSMC_Result_OK 0x01 ///< Message Response OK 90 #define VBIOSSMC_Result_Failed 0xFF ///< Message Response Failed 91 #define VBIOSSMC_Result_UnknownCmd 0xFE ///< Message Response Unknown Command 92 #define VBIOSSMC_Result_CmdRejectedPrereq 0xFD ///< Message Response Command Failed Prerequisite 93 #define VBIOSSMC_Result_CmdRejectedBusy 0xFC ///< Message Response Command Rejected due to PMFW is busy. Sender should retry sending this message 94 95 /* 96 * Function to be used instead of REG_WAIT macro because the wait ends when 97 * the register is NOT EQUAL to zero, and because the translation in msg_if.h 98 * won't work with REG_WAIT. 99 */ 100 static uint32_t dcn316_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries) 101 { 102 uint32_t res_val = VBIOSSMC_Status_BUSY; 103 104 do { 105 res_val = REG_READ(MP1_SMN_C2PMSG_91); 106 if (res_val != VBIOSSMC_Status_BUSY) 107 break; 108 109 if (delay_us >= 1000) 110 msleep(delay_us/1000); 111 else if (delay_us > 0) 112 udelay(delay_us); 113 } while (max_retries--); 114 115 return res_val; 116 } 117 118 static int dcn316_smu_send_msg_with_param( 119 struct clk_mgr_internal *clk_mgr, 120 unsigned int msg_id, unsigned int param) 121 { 122 uint32_t result; 123 124 result = dcn316_smu_wait_for_response(clk_mgr, 10, 200000); 125 126 if (result != VBIOSSMC_Result_OK) 127 smu_print("SMU Response was not OK. SMU response after wait received is: %d\n", result); 128 129 if (result == VBIOSSMC_Status_BUSY) { 130 return -1; 131 } 132 133 /* First clear response register */ 134 REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Status_BUSY); 135 136 /* Set the parameter register for the SMU message, unit is Mhz */ 137 REG_WRITE(MP1_SMN_C2PMSG_83, param); 138 139 /* Trigger the message transaction by writing the message ID */ 140 REG_WRITE(MP1_SMN_C2PMSG_67, msg_id); 141 142 result = dcn316_smu_wait_for_response(clk_mgr, 10, 200000); 143 144 if (result == VBIOSSMC_Status_BUSY) { 145 ASSERT(0); 146 dm_helpers_smu_timeout(CTX, msg_id, param, 10 * 200000); 147 } 148 149 return REG_READ(MP1_SMN_C2PMSG_83); 150 } 151 152 int dcn316_smu_get_smu_version(struct clk_mgr_internal *clk_mgr) 153 { 154 return dcn316_smu_send_msg_with_param( 155 clk_mgr, 156 VBIOSSMC_MSG_GetPmfwVersion, 157 0); 158 } 159 160 161 int dcn316_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz) 162 { 163 int actual_dispclk_set_mhz = -1; 164 165 if (!clk_mgr->smu_present) 166 return requested_dispclk_khz; 167 168 /* Unit of SMU msg parameter is Mhz */ 169 actual_dispclk_set_mhz = dcn316_smu_send_msg_with_param( 170 clk_mgr, 171 VBIOSSMC_MSG_SetDispclkFreq, 172 khz_to_mhz_ceil(requested_dispclk_khz)); 173 174 return actual_dispclk_set_mhz * 1000; 175 } 176 177 int dcn316_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz) 178 { 179 int actual_dcfclk_set_mhz = -1; 180 181 if (!clk_mgr->base.ctx->dc->debug.pstate_enabled) 182 return -1; 183 184 if (!clk_mgr->smu_present) 185 return requested_dcfclk_khz; 186 187 actual_dcfclk_set_mhz = dcn316_smu_send_msg_with_param( 188 clk_mgr, 189 VBIOSSMC_MSG_SetHardMinDcfclkByFreq, 190 khz_to_mhz_ceil(requested_dcfclk_khz)); 191 192 return actual_dcfclk_set_mhz * 1000; 193 } 194 195 int dcn316_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz) 196 { 197 int actual_min_ds_dcfclk_mhz = -1; 198 199 if (!clk_mgr->base.ctx->dc->debug.pstate_enabled) 200 return -1; 201 202 if (!clk_mgr->smu_present) 203 return requested_min_ds_dcfclk_khz; 204 205 actual_min_ds_dcfclk_mhz = dcn316_smu_send_msg_with_param( 206 clk_mgr, 207 VBIOSSMC_MSG_SetMinDeepSleepDcfclk, 208 khz_to_mhz_ceil(requested_min_ds_dcfclk_khz)); 209 210 return actual_min_ds_dcfclk_mhz * 1000; 211 } 212 213 int dcn316_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz) 214 { 215 int actual_dppclk_set_mhz = -1; 216 217 if (!clk_mgr->smu_present) 218 return requested_dpp_khz; 219 220 actual_dppclk_set_mhz = dcn316_smu_send_msg_with_param( 221 clk_mgr, 222 VBIOSSMC_MSG_SetDppclkFreq, 223 khz_to_mhz_ceil(requested_dpp_khz)); 224 225 return actual_dppclk_set_mhz * 1000; 226 } 227 228 void dcn316_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info) 229 { 230 if (!clk_mgr->base.ctx->dc->debug.pstate_enabled) 231 return; 232 233 if (!clk_mgr->smu_present) 234 return; 235 236 //TODO: Work with smu team to define optimization options. 237 dcn316_smu_send_msg_with_param( 238 clk_mgr, 239 VBIOSSMC_MSG_SetDisplayIdleOptimizations, 240 idle_info); 241 } 242 243 void dcn316_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable) 244 { 245 union display_idle_optimization_u idle_info = { 0 }; 246 247 if (!clk_mgr->smu_present) 248 return; 249 250 if (enable) { 251 idle_info.idle_info.df_request_disabled = 1; 252 idle_info.idle_info.phy_ref_clk_off = 1; 253 } 254 255 dcn316_smu_send_msg_with_param( 256 clk_mgr, 257 VBIOSSMC_MSG_SetDisplayIdleOptimizations, 258 idle_info.data); 259 } 260 261 void dcn316_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high) 262 { 263 if (!clk_mgr->smu_present) 264 return; 265 266 dcn316_smu_send_msg_with_param(clk_mgr, 267 VBIOSSMC_MSG_SetVbiosDramAddrHigh, addr_high); 268 } 269 270 void dcn316_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low) 271 { 272 if (!clk_mgr->smu_present) 273 return; 274 275 dcn316_smu_send_msg_with_param(clk_mgr, 276 VBIOSSMC_MSG_SetVbiosDramAddrLow, addr_low); 277 } 278 279 void dcn316_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr) 280 { 281 if (!clk_mgr->smu_present) 282 return; 283 284 dcn316_smu_send_msg_with_param(clk_mgr, 285 VBIOSSMC_MSG_TransferTableSmu2Dram, TABLE_DPMCLOCKS); 286 } 287 288 void dcn316_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr) 289 { 290 if (!clk_mgr->smu_present) 291 return; 292 293 dcn316_smu_send_msg_with_param(clk_mgr, 294 VBIOSSMC_MSG_TransferTableDram2Smu, TABLE_WATERMARKS); 295 } 296 297 void dcn316_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr) 298 { 299 if (!clk_mgr->smu_present) 300 return; 301 302 dcn316_smu_send_msg_with_param( 303 clk_mgr, 304 VBIOSSMC_MSG_UpdatePmeRestore, 305 0); 306 } 307 308 /* Arg = 1: Turn DTB on; 0: Turn DTB CLK OFF. when it is on, it is 600MHZ */ 309 void dcn316_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable) 310 { 311 if (!clk_mgr->smu_present) 312 return; 313 314 dcn316_smu_send_msg_with_param( 315 clk_mgr, 316 VBIOSSMC_MSG_SetDtbclkFreq, 317 enable); 318 } 319 320 int dcn316_smu_get_dpref_clk(struct clk_mgr_internal *clk_mgr) 321 { 322 int dprefclk_get_mhz = -1; 323 324 if (clk_mgr->smu_present) { 325 dprefclk_get_mhz = dcn316_smu_send_msg_with_param( 326 clk_mgr, 327 VBIOSSMC_MSG_GetDprefclkFreq, 328 0); 329 } 330 return (dprefclk_get_mhz * 1000); 331 } 332 333 int dcn316_smu_get_smu_fclk(struct clk_mgr_internal *clk_mgr) 334 { 335 int fclk_get_mhz = -1; 336 337 if (clk_mgr->smu_present) { 338 fclk_get_mhz = dcn316_smu_send_msg_with_param( 339 clk_mgr, 340 VBIOSSMC_MSG_GetFclkFrequency, 341 0); 342 } 343 return (fclk_get_mhz * 1000); 344 } 345